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-rw-r--r--ArmPkg/Drivers/CpuDxe/CpuDxe.h4
-rw-r--r--ArmPkg/Drivers/CpuDxe/Mmu.c16
-rw-r--r--ArmPkg/Drivers/PL34xDmc/PL341Dmc.c256
-rw-r--r--ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c24
-rw-r--r--ArmPkg/Drivers/PL390Gic/PL390GicSec.c42
-rw-r--r--ArmPkg/Include/Drivers/PL341Dmc.h80
-rw-r--r--ArmPkg/Include/Library/L2X0CacheLib.h2
-rw-r--r--ArmPkg/Include/Protocol/VirtualUncachedPages.h2
-rw-r--r--ArmPkg/Library/ArmLib/Arm9/Arm9Support.S12
-rw-r--r--ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm4
-rw-r--r--ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm22
-rw-r--r--ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.S2
-rw-r--r--ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.asm2
-rw-r--r--ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S12
-rw-r--r--ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm12
-rw-r--r--ArmPkg/Library/ArmLib/Common/ArmLibSupport.S52
-rw-r--r--ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm52
-rw-r--r--ArmPkg/Library/ArmMPCoreMailBoxLib/ArmMPCoreMailBox.c2
-rw-r--r--ArmPkg/Library/ArmTrustZoneLib/ArmTrustZone.c4
-rwxr-xr-xArmPkg/Library/BaseMemoryLibStm/Arm/CopyMem.S120
-rwxr-xr-xArmPkg/Library/BaseMemoryLibStm/Arm/CopyMem.asm126
-rwxr-xr-xArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.S68
-rwxr-xr-xArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.asm74
-rwxr-xr-xArmPkg/Library/BaseMemoryLibVstm/Arm/CopyMem.S120
-rwxr-xr-xArmPkg/Library/BaseMemoryLibVstm/Arm/CopyMem.asm124
-rwxr-xr-xArmPkg/Library/BaseMemoryLibVstm/Arm/SetMem.S54
-rwxr-xr-xArmPkg/Library/BaseMemoryLibVstm/Arm/SetMem.asm58
-rw-r--r--ArmPkg/Library/BdsLib/BdsFilePathFs.c4
-rw-r--r--ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashldi3.S38
-rw-r--r--ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashrdi3.S38
-rw-r--r--ArmPkg/Library/CompilerIntrinsicsLib/Arm/clzsi2.S82
-rw-r--r--ArmPkg/Library/CompilerIntrinsicsLib/Arm/ctzsi2.S68
-rw-r--r--ArmPkg/Library/CompilerIntrinsicsLib/Arm/divdi3.S68
-rw-r--r--ArmPkg/Library/CompilerIntrinsicsLib/Arm/divsi3.S34
-rwxr-xr-xArmPkg/Library/CompilerIntrinsicsLib/Arm/ldivmod.S6
-rw-r--r--ArmPkg/Library/CompilerIntrinsicsLib/Arm/lshrdi3.S38
-rw-r--r--ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy.S30
-rw-r--r--ArmPkg/Library/CompilerIntrinsicsLib/Arm/memset.S36
-rw-r--r--ArmPkg/Library/CompilerIntrinsicsLib/Arm/moddi3.S60
-rw-r--r--ArmPkg/Library/CompilerIntrinsicsLib/Arm/modsi3.S22
-rw-r--r--ArmPkg/Library/CompilerIntrinsicsLib/Arm/muldi3.S80
-rw-r--r--ArmPkg/Library/CompilerIntrinsicsLib/Arm/mullu.asm4
-rw-r--r--ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch.asm18
-rw-r--r--ArmPkg/Library/CompilerIntrinsicsLib/Arm/ucmpdi2.S40
-rw-r--r--ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivdi3.S22
-rw-r--r--ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivmoddi4.S412
-rw-r--r--ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivsi3.S74
-rwxr-xr-xArmPkg/Library/CompilerIntrinsicsLib/Arm/uldiv.S6
-rw-r--r--ArmPkg/Library/CompilerIntrinsicsLib/Arm/umoddi3.S26
-rw-r--r--ArmPkg/Library/CompilerIntrinsicsLib/Arm/umodsi3.S24
-rw-r--r--ArmPkg/Universal/MmcDxe/Mmc.h12
51 files changed, 1295 insertions, 1293 deletions
diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.h b/ArmPkg/Drivers/CpuDxe/CpuDxe.h
index af2cdc60a5..e11d5d6bf4 100644
--- a/ArmPkg/Drivers/CpuDxe/CpuDxe.h
+++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.h
@@ -111,8 +111,8 @@ CpuSetMemoryAttributes (
EFI_STATUS
InitializeExceptions (
- IN EFI_CPU_ARCH_PROTOCOL *Cpu
- );
+\s\sIN EFI_CPU_ARCH_PROTOCOL *Cpu
+\s\s);
EFI_STATUS
SyncCacheConfig (
diff --git a/ArmPkg/Drivers/CpuDxe/Mmu.c b/ArmPkg/Drivers/CpuDxe/Mmu.c
index d7ea0eb551..0b86b8bc98 100644
--- a/ArmPkg/Drivers/CpuDxe/Mmu.c
+++ b/ArmPkg/Drivers/CpuDxe/Mmu.c
@@ -338,11 +338,11 @@ UpdatePageEntries (
// modify cacheability attributes
EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
if (FeaturePcdGet(PcdEfiUncachedMemoryToStronglyOrdered)) {
- // map to strongly ordered
- EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
+\s\s\s\s // map to strongly ordered
+\s\s\s\s EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
} else {
- // map to normal non-cachable
- EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
+ \s\s // map to normal non-cachable
+ \s\s EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
}
break;
@@ -486,11 +486,11 @@ UpdateSectionEntries (
// modify cacheability attributes
EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
if (FeaturePcdGet(PcdEfiUncachedMemoryToStronglyOrdered)) {
- // map to strongly ordered
- EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
+\s\s\s\s // map to strongly ordered
+\s\s\s\s EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
} else {
- // map to normal non-cachable
- EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
+ \s\s // map to normal non-cachable
+ \s\s EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
}
break;
diff --git a/ArmPkg/Drivers/PL34xDmc/PL341Dmc.c b/ArmPkg/Drivers/PL34xDmc/PL341Dmc.c
index 9c62a1a92b..6ba82e1270 100644
--- a/ArmPkg/Drivers/PL34xDmc/PL341Dmc.c
+++ b/ArmPkg/Drivers/PL34xDmc/PL341Dmc.c
@@ -64,7 +64,7 @@
#define DMC_DIRECT_CMD_MEMCMD_NOP (0x3 << 18)
#define DMC_DIRECT_CMD_MEMCMD_DPD (0x1 << 22)
#define DMC_DIRECT_CMD_BANKADDR(n) ((n & 0x3) << 16)
-#define DMC_DIRECT_CMD_CHIP_ADDR(n) ((n & 0x3) << 20)
+#define DMC_DIRECT_CMD_CHIP_ADDR(n)\s\s\s\s((n & 0x3) << 20)
//
@@ -163,25 +163,25 @@ VOID PL341DmcInit(struct pl341_dmc_config *config) {
//
if (config->has_qos) {
- // CLCD AXIID = 000
- DmcWriteReg(DMC_ID_0_CFG_REG, DMC_ID_CFG_QOS_ENABLE | DMC_ID_CFG_QOS_MIN);
-
- // Default disable QoS
- DmcWriteReg(DMC_ID_1_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
- DmcWriteReg(DMC_ID_2_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
- DmcWriteReg(DMC_ID_3_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
- DmcWriteReg(DMC_ID_4_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
- DmcWriteReg(DMC_ID_5_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
- DmcWriteReg(DMC_ID_6_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
- DmcWriteReg(DMC_ID_7_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
- DmcWriteReg(DMC_ID_8_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
- DmcWriteReg(DMC_ID_9_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
- DmcWriteReg(DMC_ID_10_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
- DmcWriteReg(DMC_ID_11_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
- DmcWriteReg(DMC_ID_12_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
- DmcWriteReg(DMC_ID_13_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
- DmcWriteReg(DMC_ID_14_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
- DmcWriteReg(DMC_ID_15_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
+\s\s// CLCD AXIID = 000
+\s\sDmcWriteReg(DMC_ID_0_CFG_REG, DMC_ID_CFG_QOS_ENABLE | DMC_ID_CFG_QOS_MIN);
+
+\s\s// Default disable QoS
+\s\sDmcWriteReg(DMC_ID_1_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
+\s\sDmcWriteReg(DMC_ID_2_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
+\s\sDmcWriteReg(DMC_ID_3_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
+\s\sDmcWriteReg(DMC_ID_4_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
+\s\sDmcWriteReg(DMC_ID_5_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
+\s\sDmcWriteReg(DMC_ID_6_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
+\s\sDmcWriteReg(DMC_ID_7_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
+\s\sDmcWriteReg(DMC_ID_8_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
+\s\sDmcWriteReg(DMC_ID_9_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
+\s\sDmcWriteReg(DMC_ID_10_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
+\s\sDmcWriteReg(DMC_ID_11_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
+\s\sDmcWriteReg(DMC_ID_12_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
+\s\sDmcWriteReg(DMC_ID_13_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
+\s\sDmcWriteReg(DMC_ID_14_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
+\s\sDmcWriteReg(DMC_ID_15_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
}
//
@@ -231,104 +231,104 @@ VOID PL341DmcInit(struct pl341_dmc_config *config) {
// |======================================
DmcWriteReg(DMC_MEMORY_CFG3_REG, config->memory_cfg3);
- // |========================================================
- // |Set Test Chip PHY Registers via PL341 User Config Reg
- // |Note that user_cfgX registers are Write Only
- // |
- // |DLL Freq set = 250MHz - 266MHz
- // |========================================================
- DmcWriteReg(DMC_USER_0_CFG_REG, 0x7C924924);
+\s\s// |========================================================
+\s\s// |Set Test Chip PHY Registers via PL341 User Config Reg
+\s\s// |Note that user_cfgX registers are Write Only
+\s\s// |
+\s\s// |DLL Freq set = 250MHz - 266MHz
+\s\s// |========================================================
+\s\sDmcWriteReg(DMC_USER_0_CFG_REG, 0x7C924924);
- // user_config2
- // ------------
- // Set defaults before calibrating the DDR2 buffer impendence
- // -Disable ODT
- // -Default drive strengths
- DmcWriteReg(DMC_USER_2_CFG_REG, 0x40000198);
+\s\s// user_config2
+\s\s// ------------
+\s\s// Set defaults before calibrating the DDR2 buffer impendence
+\s\s// -Disable ODT
+\s\s// -Default drive strengths
+\s\sDmcWriteReg(DMC_USER_2_CFG_REG, 0x40000198);
- // |=======================================================
- // |Auto calibrate the DDR2 buffers impendence
- // |=======================================================
- val32 = DmcReadReg(DMC_USER_STATUS_REG);
- while (!(val32 & 0x100)) {
- val32 = DmcReadReg(DMC_USER_STATUS_REG);
- }
-
- // Set the output driven strength
- DmcWriteReg(DMC_USER_2_CFG_REG, 0x40800000 |
- (TC_UIOLHXC_VALUE << TC_UIOLHNC_SHIFT) |
- (TC_UIOLHXC_VALUE << TC_UIOLHPC_SHIFT) |
- (0x1 << TC_UIOHOCT_SHIFT) |
- (0x1 << TC_UIOHSTOP_SHIFT));
-
- // |======================================
- // | Set PL341 Feature Control Register
- // |======================================
- // | Disable early BRESP - use to optimise CLCD performance
- DmcWriteReg(DMC_FEATURE_CRTL_REG, 0x00000001);
+\s\s// |=======================================================
+\s\s// |Auto calibrate the DDR2 buffers impendence
+\s\s// |=======================================================
+\s\sval32 = DmcReadReg(DMC_USER_STATUS_REG);
+\s\swhile (!(val32 & 0x100)) {
+\s\s val32 = DmcReadReg(DMC_USER_STATUS_REG);
+\s\s}
+
+\s\s// Set the output driven strength
+\s\sDmcWriteReg(DMC_USER_2_CFG_REG, 0x40800000 |
+\s\s\s\s (TC_UIOLHXC_VALUE << TC_UIOLHNC_SHIFT) |
+\s\s\s\s (TC_UIOLHXC_VALUE << TC_UIOLHPC_SHIFT) |
+\s\s\s\s (0x1 << TC_UIOHOCT_SHIFT) |
+\s\s\s\s (0x1 << TC_UIOHSTOP_SHIFT));
+
+\s\s// |======================================
+\s\s// | Set PL341 Feature Control Register
+\s\s// |======================================
+\s\s// | Disable early BRESP - use to optimise CLCD performance
+\s\sDmcWriteReg(DMC_FEATURE_CRTL_REG, 0x00000001);
//=================
// Config memories
//=================
for (chip = 0; chip <= config-> max_chip; chip++) {
- // send nop
- DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_NOP);
- // pre-charge all
- DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);
-
- // delay
- for (i = 0; i < 10; i++) {
- val32 = DmcReadReg(DMC_STATUS_REG);
- }
-
- // set (EMR2) extended mode register 2
- DmcWriteReg(DMC_DIRECT_CMD_REG,
- DMC_DIRECT_CMD_CHIP_ADDR(chip) |
- DMC_DIRECT_CMD_BANKADDR(2) |
- DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);
- // set (EMR3) extended mode register 3
- DmcWriteReg(DMC_DIRECT_CMD_REG,
- DMC_DIRECT_CMD_CHIP_ADDR(chip) |
- DMC_DIRECT_CMD_BANKADDR(3) |
- DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);
-
- // =================================
- // set (EMR) Extended Mode Register
- // ==================================
- // Put into OCD default state
- DmcWriteReg(DMC_DIRECT_CMD_REG,
- DMC_DIRECT_CMD_CHIP_ADDR(chip) |
- DMC_DIRECT_CMD_BANKADDR(1) |
- DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);
-
- // ===========================================================
- // set (MR) mode register - With DLL reset
- // ===========================================================
- // Burst Length = 4 (010)
- // Burst Type = Seq (0)
- // Latency = 4 (100)
- // Test mode = Off (0)
- // DLL reset = Yes (1)
- // Wr Recovery = 4 (011)
- // PD = Normal (0)
+\s\s// send nop
+\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_NOP);
+\s\s// pre-charge all
+\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);
+
+\s\s// delay
+\s\sfor (i = 0; i < 10; i++) {
+\s\s val32 = DmcReadReg(DMC_STATUS_REG);
+\s\s}
+
+\s\s// set (EMR2) extended mode register 2
+\s\sDmcWriteReg(DMC_DIRECT_CMD_REG,
+\s\s\s\s DMC_DIRECT_CMD_CHIP_ADDR(chip) |
+\s\s\s\s DMC_DIRECT_CMD_BANKADDR(2) |
+\s\s\s\s DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);
+\s\s// set (EMR3) extended mode register 3
+\s\sDmcWriteReg(DMC_DIRECT_CMD_REG,
+\s\s\s\s DMC_DIRECT_CMD_CHIP_ADDR(chip) |
+\s\s\s\s DMC_DIRECT_CMD_BANKADDR(3) |
+\s\s\s\s DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);
+
+\s\s// =================================
+\s\s// set (EMR) Extended Mode Register
+\s\s// ==================================
+\s\s// Put into OCD default state
+\s\sDmcWriteReg(DMC_DIRECT_CMD_REG,
+\s\s\s\s DMC_DIRECT_CMD_CHIP_ADDR(chip) |
+\s\s\s\s DMC_DIRECT_CMD_BANKADDR(1) |
+\s\s\s\s DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);
+
+\s\s// ===========================================================
+\s\s// set (MR) mode register - With DLL reset
+\s\s// ===========================================================
+\s\s// Burst Length = 4 (010)
+\s\s// Burst Type = Seq (0)
+\s\s// Latency = 4 (100)
+\s\s// Test mode = Off (0)
+\s\s// DLL reset = Yes (1)
+\s\s// Wr Recovery = 4 (011)
+\s\s// PD = Normal (0)
DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | 0x00080742);
- // pre-charge all
- DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);
- // auto-refresh
- DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);
- // auto-refresh
- DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);
-
- // delay
- for (i = 0; i < 10; i++) {
- val32 = DmcReadReg(DMC_STATUS_REG);
- }
-
- // ===========================================================
- // set (MR) mode register - Without DLL reset
- // ===========================================================
+\s\s// pre-charge all
+\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);
+\s\s// auto-refresh
+\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);
+\s\s// auto-refresh
+\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);
+
+\s\s// delay
+\s\sfor (i = 0; i < 10; i++) {
+\s\s val32 = DmcReadReg(DMC_STATUS_REG);
+\s\s}
+
+\s\s// ===========================================================
+\s\s// set (MR) mode register - Without DLL reset
+\s\s// ===========================================================
// auto-refresh
DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);
DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | 0x00080642);
@@ -338,26 +338,26 @@ VOID PL341DmcInit(struct pl341_dmc_config *config) {
val32 = DmcReadReg(DMC_STATUS_REG);
}
- // ======================================================
- // set (EMR) extended mode register - Enable OCD defaults
- // ======================================================
- val32 = 0; //NOP
- DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | 0x00090000 |
- (DDR_EMR_OCD_DEFAULT << DDR_EMR_OCD_SHIFT) |
- DDR_EMR_RTT_75R |
- (DDR_EMR_ODS_VAL << DDR_EMR_ODS_MASK));
-
- // delay
- for (i = 0; i < 10; i++) {
- val32 = DmcReadReg(DMC_STATUS_REG);
- }
-
- // Set (EMR) extended mode register - OCD Exit
- val32 = 0; //NOP
- DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | 0x00090000 |
- (DDR_EMR_OCD_NS << DDR_EMR_OCD_SHIFT) |
- DDR_EMR_RTT_75R |
- (DDR_EMR_ODS_VAL << DDR_EMR_ODS_MASK));
+\s\s// ======================================================
+\s\s// set (EMR) extended mode register - Enable OCD defaults
+\s\s// ======================================================
+\s\sval32 = 0; //NOP
+\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | 0x00090000 |
+\s\s\s\s (DDR_EMR_OCD_DEFAULT << DDR_EMR_OCD_SHIFT) |
+\s\s\s\s DDR_EMR_RTT_75R |
+\s\s\s\s (DDR_EMR_ODS_VAL << DDR_EMR_ODS_MASK));
+
+\s\s// delay
+\s\sfor (i = 0; i < 10; i++) {
+\s\s val32 = DmcReadReg(DMC_STATUS_REG);
+\s\s}
+
+\s\s// Set (EMR) extended mode register - OCD Exit
+\s\sval32 = 0; //NOP
+\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | 0x00090000 |
+\s\s\s\s (DDR_EMR_OCD_NS << DDR_EMR_OCD_SHIFT) |
+\s\s\s\s DDR_EMR_RTT_75R |
+\s\s\s\s (DDR_EMR_ODS_VAL << DDR_EMR_ODS_MASK));
}
diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c b/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c
index e5faa40a33..9a9006f0a3 100644
--- a/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c
+++ b/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c
@@ -21,11 +21,11 @@ EFIAPI
PL390GicEnableInterruptInterface (
IN INTN GicInterruptInterfaceBase
)
-{
- /*
- * Enable the CPU interface in Non-Secure world
- * Note: The ICCICR register is banked when Security extensions are implemented
- */
+{\s\s
+\s\s/*
+\s\s * Enable the CPU interface in Non-Secure world
+\s\s * Note: The ICCICR register is banked when Security extensions are implemented\s\s
+\s\s */
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,0x00000001);
}
@@ -50,7 +50,7 @@ PL390GicSendSgiTo (
IN INTN CPUTargetList
)
{
- MmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));
+\s\sMmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));
}
UINT32
@@ -65,9 +65,9 @@ PL390GicAcknowledgeSgiFrom (
InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
//Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
- if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
- //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
+\s\sif (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
+\s\s //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
+\s\s\s\sMmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
return 1;
} else {
return 0;
@@ -87,9 +87,9 @@ PL390GicAcknowledgeSgi2From (
InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
//Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
- if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
- //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
+\s\sif((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
+\s\s //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
+\s\s\s\sMmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
return 1;
} else {
return 0;
diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
index 46b14e0746..7bb0f3dd6f 100644
--- a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
+++ b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
@@ -34,11 +34,11 @@ PL390GicSetupNonSecure (
//Check if there are any pending interrupts
while(0 != (MmioRead32(GicDistributorBase + GIC_ICDICPR) & 0xF))
{
- //Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
- UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
+\s\s //Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
+\s\s UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
- //Write to End of interrupt signal
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
+\s\s //Write to End of interrupt signal
+\s\s MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
}
// Ensure all GIC interrupts are Non-Secure
@@ -56,19 +56,19 @@ PL390GicEnableInterruptInterface (
IN INTN GicInterruptInterfaceBase
)
{
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0x000000FF); /* Set Priority Mask to allow interrupts */
+\s\sMmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0x000000FF); /* Set Priority Mask to allow interrupts */
- /*
- * Enable CPU interface in Secure world
+\s\s/*
+\s\s * Enable CPU interface in Secure world
* Enable CPU inteface in Non-secure World
- * Signal Secure Interrupts to CPU using FIQ line *
- */
+\s\s * Signal Secure Interrupts to CPU using FIQ line *
+\s\s */
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,
- GIC_ICCICR_ENABLE_SECURE(1) |
- GIC_ICCICR_ENABLE_NS(1) |
- GIC_ICCICR_ACK_CTL(0) |
- GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(1) |
- GIC_ICCICR_USE_SBPR(0));
+ \s\s\s\sGIC_ICCICR_ENABLE_SECURE(1) |
+ \s\s\s\sGIC_ICCICR_ENABLE_NS(1) |
+ \s\s\s\sGIC_ICCICR_ACK_CTL(0) |
+ \s\s\s\sGIC_ICCICR_SIGNAL_SECURE_TO_FIQ(1) |
+ \s\s\s\sGIC_ICCICR_USE_SBPR(0));
}
VOID
@@ -88,7 +88,7 @@ PL390GicSendSgiTo (
IN INTN CPUTargetList
)
{
- MmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));
+\s\sMmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));
}
UINT32
@@ -103,9 +103,9 @@ PL390GicAcknowledgeSgiFrom (
InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
//Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
- if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
- //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
+\s\sif (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
+\s\s //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
+\s\s\s\sMmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
return 1;
} else {
return 0;
@@ -125,9 +125,9 @@ PL390GicAcknowledgeSgi2From (
InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
//Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
- if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
- //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
+\s\sif((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
+\s\s //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
+\s\s\s\sMmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
return 1;
} else {
return 0;
diff --git a/ArmPkg/Include/Drivers/PL341Dmc.h b/ArmPkg/Include/Drivers/PL341Dmc.h
index 68b8be444a..38ac70d17d 100644
--- a/ArmPkg/Include/Drivers/PL341Dmc.h
+++ b/ArmPkg/Include/Drivers/PL341Dmc.h
@@ -17,32 +17,32 @@
struct pl341_dmc_config {
- UINTN base; // base address for the controller
- UINTN has_qos; // has QoS registers
- UINTN max_chip; // number of memory chips accessible
- UINT32 refresh_prd;
- UINT32 cas_latency;
- UINT32 write_latency;
- UINT32 t_mrd;
- UINT32 t_ras;
- UINT32 t_rc;
- UINT32 t_rcd;
- UINT32 t_rfc;
- UINT32 t_rp;
- UINT32 t_rrd;
- UINT32 t_wr;
- UINT32 t_wtr;
- UINT32 t_xp;
- UINT32 t_xsr;
- UINT32 t_esr;
- UINT32 memory_cfg;
- UINT32 memory_cfg2;
- UINT32 memory_cfg3;
- UINT32 chip_cfg0;
- UINT32 chip_cfg1;
- UINT32 chip_cfg2;
- UINT32 chip_cfg3;
- UINT32 t_faw;
+ UINTN\s\sbase; // base address for the controller
+ UINTN\s\shas_qos; // has QoS registers
+ UINTN\s\smax_chip; // number of memory chips accessible
+ UINT32\s\srefresh_prd;
+ UINT32\s\scas_latency;
+ UINT32\s\swrite_latency;
+ UINT32\s\st_mrd;
+ UINT32\s\st_ras;
+ UINT32\s\st_rc;
+ UINT32\s\st_rcd;
+ UINT32\s\st_rfc;
+ UINT32\s\st_rp;
+ UINT32\s\st_rrd;
+ UINT32\s\st_wr;
+ UINT32\s\st_wtr;
+ UINT32\s\st_xp;
+ UINT32\s\st_xsr;
+ UINT32\s\st_esr;
+ UINT32\s\smemory_cfg;
+ UINT32\s\smemory_cfg2;
+ UINT32\s\smemory_cfg3;
+ UINT32\s\schip_cfg0;
+ UINT32\s\schip_cfg1;
+ UINT32\s\schip_cfg2;
+ UINT32\s\schip_cfg3;
+ UINT32\s\st_faw;
};
/* Memory config bit fields */
@@ -60,21 +60,21 @@ struct pl341_dmc_config {
#define DMC_MEMORY_CONFIG_BURST_4 (0x2 << 15)
#define DMC_MEMORY_CONFIG_BURST_8 (0x3 << 15)
#define DMC_MEMORY_CONFIG_BURST_16 (0x4 << 15)
-#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 (0x0 << 21)
-#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_2 (0x1 << 21)
-#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_3 (0x2 << 21)
-#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_4 (0x3 << 21)
+#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_1\s\s\s\s(0x0 << 21)
+#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_2\s\s\s\s(0x1 << 21)
+#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_3\s\s\s\s(0x2 << 21)
+#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_4\s\s\s\s(0x3 << 21)
-#define DMC_MEMORY_CFG2_CLK_ASYNC (0x0 << 0)
-#define DMC_MEMORY_CFG2_CLK_SYNC (0x1 << 0)
-#define DMC_MEMORY_CFG2_DQM_INIT (0x1 << 2)
-#define DMC_MEMORY_CFG2_CKE_INIT (0x1 << 3)
-#define DMC_MEMORY_CFG2_BANK_BITS_2 (0x0 << 4)
-#define DMC_MEMORY_CFG2_BANK_BITS_3 (0x3 << 4)
-#define DMC_MEMORY_CFG2_MEM_WIDTH_16 (0x0 << 6)
-#define DMC_MEMORY_CFG2_MEM_WIDTH_32 (0x1 << 6)
-#define DMC_MEMORY_CFG2_MEM_WIDTH_64 (0x2 << 6)
-#define DMC_MEMORY_CFG2_MEM_WIDTH_RESERVED (0x3 << 6)
+#define DMC_MEMORY_CFG2_CLK_ASYNC\s\s\s\s(0x0 << 0)
+#define DMC_MEMORY_CFG2_CLK_SYNC\s\s\s\s(0x1 << 0)
+#define DMC_MEMORY_CFG2_DQM_INIT\s\s\s\s(0x1 << 2)
+#define DMC_MEMORY_CFG2_CKE_INIT\s\s\s\s(0x1 << 3)
+#define DMC_MEMORY_CFG2_BANK_BITS_2\s\s\s\s(0x0 << 4)
+#define DMC_MEMORY_CFG2_BANK_BITS_3\s\s\s\s(0x3 << 4)
+#define DMC_MEMORY_CFG2_MEM_WIDTH_16\s\s\s\s(0x0 << 6)
+#define DMC_MEMORY_CFG2_MEM_WIDTH_32\s\s\s\s(0x1 << 6)
+#define DMC_MEMORY_CFG2_MEM_WIDTH_64\s\s\s\s(0x2 << 6)
+#define DMC_MEMORY_CFG2_MEM_WIDTH_RESERVED\s\s(0x3 << 6)
diff --git a/ArmPkg/Include/Library/L2X0CacheLib.h b/ArmPkg/Include/Library/L2X0CacheLib.h
index 4f95b993d0..e2c4ea29d1 100644
--- a/ArmPkg/Include/Library/L2X0CacheLib.h
+++ b/ArmPkg/Include/Library/L2X0CacheLib.h
@@ -29,7 +29,7 @@
#define L230_TAG_LATENCY 0x108
#define L230_DATA_LATENCY 0x10C
#define L2X0_INTCLEAR 0x220
-#define L2X0_CACHE_SYNC 0x730
+#define L2X0_CACHE_SYNC\s\s\s\s\s\s0x730
#define L2X0_INVWAY 0x77C
#define L2X0_CLEAN_WAY 0x7BC
#define L2X0_PFCTRL 0xF60
diff --git a/ArmPkg/Include/Protocol/VirtualUncachedPages.h b/ArmPkg/Include/Protocol/VirtualUncachedPages.h
index d0377cf7ca..866263faf1 100644
--- a/ArmPkg/Include/Protocol/VirtualUncachedPages.h
+++ b/ArmPkg/Include/Protocol/VirtualUncachedPages.h
@@ -57,4 +57,4 @@ struct _VIRTUAL_UNCACHED_PAGES_PROTOCOL {
extern EFI_GUID gVirtualUncachedPagesProtocolGuid;
-#endif
+#endif\s\s
diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9Support.S b/ArmPkg/Library/ArmLib/Arm9/Arm9Support.S
index 8e75a3d79e..badec4a72f 100644
--- a/ArmPkg/Library/ArmLib/Arm9/Arm9Support.S
+++ b/ArmPkg/Library/ArmLib/Arm9/Arm9Support.S
@@ -58,18 +58,18 @@ ASM_PFX(ArmEnableInstructionCache):
orr r0,r0,r1 @Set I bit
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
-
+\s\s
ASM_PFX(ArmDisableInstructionCache):
ldr r1,=IC_ON
mrc p15,0,r0,c1,c0,0 @Read control register configuration data
bic r0,r0,r1 @Clear I bit.
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
-
+\s\s
ASM_PFX(ArmInvalidateInstructionCache):
mov r0,#0
mcr p15,0,r0,c7,c5,0 @Invalidate entire Instruction cache.
- @Also flushes the branch target cache.
+\s\s @Also flushes the branch target cache.
mov r0,#0
mcr p15,0,r0,c7,c10,4 @Data write buffer
bx LR
@@ -99,7 +99,7 @@ ASM_PFX(ArmEnableDataCache):
orr R0,R0,R1 @Set C bit
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
-
+\s\s
ASM_PFX(ArmDisableDataCache):
ldr R1,=DC_ON
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
@@ -111,7 +111,7 @@ ASM_PFX(ArmCleanDataCache):
mrc p15,0,r15,c7,c10,3
bne ASM_PFX(ArmCleanDataCache)
mov R0,#0
- mcr p15,0,R0,c7,c10,4 @Drain write buffer
+ mcr p15,0,R0,c7,c10,4\s\s@Drain write buffer
bx LR
ASM_PFX(ArmInvalidateDataCache):
@@ -125,7 +125,7 @@ ASM_PFX(ArmCleanInvalidateDataCache):
mrc p15,0,r15,c7,c14,3
bne ASM_PFX(ArmCleanInvalidateDataCache)
mov R0,#0
- mcr p15,0,R0,c7,c10,4 @Drain write buffer
+ mcr p15,0,R0,c7,c10,4\s\s @Drain write buffer
bx LR
ASM_PFX(ArmEnableBranchPrediction):
diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm b/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm
index bc9d6d2ee0..2a147eff3a 100644
--- a/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm
+++ b/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm
@@ -112,7 +112,7 @@ ArmCleanDataCache
MRC p15,0,r15,c7,c10,3
BNE ArmCleanDataCache
MOV R0,#0
- MCR p15,0,R0,c7,c10,4 ;Drain write buffer
+ MCR p15,0,R0,c7,c10,4\s\s ;Drain write buffer
BX LR
ArmInvalidateDataCache
@@ -126,7 +126,7 @@ ArmCleanInvalidateDataCache
MRC p15,0,r15,c7,c14,3
BNE ArmCleanInvalidateDataCache
MOV R0,#0
- MCR p15,0,R0,c7,c10,4 ;Drain write buffer
+ MCR p15,0,R0,c7,c10,4\s\s ;Drain write buffer
BX LR
ArmEnableBranchPrediction
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm
index 7099ced8f4..831532f4d2 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm
@@ -70,17 +70,17 @@ ArmDisableAsynchronousAbort
ArmEnableIrq
cpsie i
isb
- bx LR
+\s\sbx LR
ArmDisableIrq
cpsid i
isb
- bx LR
+\s\sbx LR
ArmEnableFiq
cpsie f
isb
- bx LR
+\s\sbx LR
ArmDisableFiq
cpsid f
@@ -99,17 +99,17 @@ ArmDisableInterrupts
ArmGetInterruptState
mrs R0,CPSR
- tst R0,#0x80 ;Check if IRQ is enabled.
+ tst R0,#0x80\s\s ;Check if IRQ is enabled.
moveq R0,#1
movne R0,#0
- bx LR
+\s\sbx LR
ArmGetFiqState
- mrs R0,CPSR
- tst R0,#0x40 ;Check if FIQ is enabled.
- moveq R0,#1
- movne R0,#0
- bx LR
+\s\smrs R0,CPSR
+\s\stst R0,#0x40\s\s ;Check if FIQ is enabled.
+\s\smoveq R0,#1
+\s\smovne R0,#0
+\s\sbx LR
ArmInvalidateTlb
mov r0,#0
@@ -126,7 +126,7 @@ ArmSetTTBR0
ArmGetTTBR0BaseAddress
mrc p15,0,r0,c2,c0,0
- ldr r1, = 0xFFFFC000
+ ldr\s\s r1, = 0xFFFFC000
and r0, r0, r1
isb
bx lr
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.S
index 0636897b87..9d7b31efdc 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.S
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.S
@@ -31,7 +31,7 @@ ASM_PFX(ArmGetScuBaseAddress):
# the Configuration BAR as a stack is not necessary setup. The SCU is at the
# offset 0x0000 from the Private Memory Region.
mrc p15, 4, r0, c15, c0, 0
- bx lr
+ bx\s\slr
# IN None
# OUT r1 = SCU enabled (boolean)
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.asm
index 08528fc4ec..e87d231356 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.asm
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.asm
@@ -31,7 +31,7 @@ ArmGetScuBaseAddress
// the Configuration BAR as a stack is not necessary setup. The SCU is at the
// offset 0x0000 from the Private Memory Region.
mrc p15, 4, r0, c15, c0, 0
- bx lr
+ bx\s\slr
// IN None
// OUT r1 = SCU enabled (boolean)
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
index cfbb8f545c..00704164f9 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
@@ -80,21 +80,21 @@ ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
- mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line
+ mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line\s\s\s\s
dsb
isb
bx lr
ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
- mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line
+ mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line\s\s\s\s
dsb
isb
bx lr
ASM_PFX(ArmCleanDataCacheEntryBySetWay):
- mcr p15, 0, r0, c7, c10, 2 @ Clean this line
+ mcr p15, 0, r0, c7, c10, 2 @ Clean this line\s\s\s\s
dsb
isb
bx lr
@@ -119,7 +119,7 @@ ASM_PFX(ArmDisableMmu):
bic R0,R0,#1
mcr p15,0,R0,c1,c0,0 @Disable MMU
- mcr p15,0,R0,c8,c7,0 @Invalidate TLB
+\s\smcr \s\s\s\sp15,0,R0,c8,c7,0 @Invalidate TLB
mcr p15,0,R0,c7,c5,6 @Invalidate Branch predictor array
dsb
isb
@@ -309,7 +309,7 @@ ASM_PFX(ArmCallWFI):
//Note: Return 0 in Uniprocessor implementation
ASM_PFX(ArmReadCbar):
- mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register
+ mrc p15, 4, r0, c15, c0, 0\s\s//Read Configuration Base Address Register
bx lr
ASM_PFX(ArmInvalidateInstructionAndDataTlb):
@@ -318,7 +318,7 @@ ASM_PFX(ArmInvalidateInstructionAndDataTlb):
bx lr
ASM_PFX(ArmReadMpidr):
- mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
+ mrc p15, 0, r0, c0, c0, 5\s\s @ read MPIDR
bx lr
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
index 7b4ca425bd..4cd78d8a23 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
@@ -82,21 +82,21 @@ ArmCleanInvalidateDataCacheEntryByMVA
ArmInvalidateDataCacheEntryBySetWay
- mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
+ mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line\s\s\s\s
dsb
isb
bx lr
ArmCleanInvalidateDataCacheEntryBySetWay
- mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
+ mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line\s\s\s\s
dsb
isb
bx lr
ArmCleanDataCacheEntryBySetWay
- mcr p15, 0, r0, c7, c10, 2 ; Clean this line
+ mcr p15, 0, r0, c7, c10, 2 ; Clean this line\s\s\s\s
dsb
isb
bx lr
@@ -125,7 +125,7 @@ ArmDisableMmu
bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
- mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB
+ mcr \s\s p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB
mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array
dsb
isb
@@ -307,7 +307,7 @@ ArmCallWFI
//Note: Return 0 in Uniprocessor implementation
ArmReadCbar
- mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register
+ mrc p15, 4, r0, c15, c0, 0\s\s//Read Configuration Base Address Register
bx lr
ArmInvalidateInstructionAndDataTlb
@@ -316,7 +316,7 @@ ArmInvalidateInstructionAndDataTlb
bx lr
ArmReadMpidr
- mrc p15, 0, r0, c0, c0, 5 ; read MPIDR
+ mrc p15, 0, r0, c0, c0, 5\s\s\s\s; read MPIDR
bx lr
END
diff --git a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S
index 9b144c82c5..94b11a5d77 100644
--- a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S
@@ -42,48 +42,48 @@ ASM_PFX(Cp15CacheInfo):
bx LR
ASM_PFX(ArmEnableInterrupts):
- mrs R0,CPSR
- bic R0,R0,#0x80 @Enable IRQ interrupts
- msr CPSR_c,R0
- bx LR
+\s\smrs R0,CPSR
+\s\sbic R0,R0,#0x80\s\s\s\s@Enable IRQ interrupts
+\s\smsr CPSR_c,R0
+\s\sbx LR
ASM_PFX(ArmDisableInterrupts):
- mrs R0,CPSR
- orr R1,R0,#0x80 @Disable IRQ interrupts
- msr CPSR_c,R1
+\s\smrs R0,CPSR
+\s\sorr R1,R0,#0x80\s\s\s\s@Disable IRQ interrupts
+\s\smsr CPSR_c,R1
tst R0,#0x80
moveq R0,#1
movne R0,#0
- bx LR
+\s\sbx LR
ASM_PFX(ArmGetInterruptState):
- mrs R0,CPSR
- tst R0,#0x80 @Check if IRQ is enabled.
- moveq R0,#1
- movne R0,#0
- bx LR
+\s\smrs R0,CPSR
+\s\stst R0,#0x80\s\s @Check if IRQ is enabled.
+\s\smoveq R0,#1
+\s\smovne R0,#0
+\s\sbx LR
ASM_PFX(ArmEnableFiq):
- mrs R0,CPSR
- bic R0,R0,#0x40 @Enable FIQ interrupts
- msr CPSR_c,R0
- bx LR
+\s\smrs R0,CPSR
+\s\sbic R0,R0,#0x40\s\s\s\s@Enable FIQ interrupts
+\s\smsr CPSR_c,R0
+\s\sbx LR
ASM_PFX(ArmDisableFiq):
- mrs R0,CPSR
- orr R1,R0,#0x40 @Disable FIQ interrupts
- msr CPSR_c,R1
+\s\smrs R0,CPSR
+\s\sorr R1,R0,#0x40\s\s\s\s@Disable FIQ interrupts
+\s\smsr CPSR_c,R1
tst R0,#0x80
moveq R0,#1
movne R0,#0
- bx LR
+\s\sbx LR
ASM_PFX(ArmGetFiqState):
- mrs R0,CPSR
- tst R0,#0x80 @Check if FIQ is enabled.
- moveq R0,#1
- movne R0,#0
- bx LR
+\s\smrs R0,CPSR
+\s\stst R0,#0x80\s\s @Check if FIQ is enabled.
+\s\smoveq R0,#1
+\s\smovne R0,#0
+\s\sbx LR
ASM_PFX(ArmInvalidateTlb):
mov r0,#0
diff --git a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm
index cf7605f45a..0b023fed42 100644
--- a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm
+++ b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm
@@ -48,48 +48,48 @@ ArmIsMPCore
bx LR
ArmEnableInterrupts
- mrs R0,CPSR
- bic R0,R0,#0x80 ;Enable IRQ interrupts
- msr CPSR_c,R0
- bx LR
+\s\smrs R0,CPSR
+\s\sbic R0,R0,#0x80\s\s\s\s;Enable IRQ interrupts
+\s\smsr CPSR_c,R0
+\s\sbx LR
ArmDisableInterrupts
- mrs R0,CPSR
- orr R1,R0,#0x80 ;Disable IRQ interrupts
- msr CPSR_c,R1
+\s\smrs R0,CPSR
+\s\sorr R1,R0,#0x80\s\s\s\s;Disable IRQ interrupts
+\s\smsr CPSR_c,R1
tst R0,#0x80
moveq R0,#1
movne R0,#0
- bx LR
+\s\sbx LR
ArmGetInterruptState
- mrs R0,CPSR
- tst R0,#0x80 ;Check if IRQ is enabled.
- moveq R0,#1
- movne R0,#0
- bx LR
+\s\smrs R0,CPSR
+\s\stst R0,#0x80\s\s ;Check if IRQ is enabled.
+\s\smoveq R0,#1
+\s\smovne R0,#0
+\s\sbx LR
ArmEnableFiq
- mrs R0,CPSR
- bic R0,R0,#0x40 ;Enable IRQ interrupts
- msr CPSR_c,R0
- bx LR
+\s\smrs R0,CPSR
+\s\sbic R0,R0,#0x40\s\s\s\s;Enable IRQ interrupts
+\s\smsr CPSR_c,R0
+\s\sbx LR
ArmDisableFiq
- mrs R0,CPSR
- orr R1,R0,#0x40 ;Disable IRQ interrupts
- msr CPSR_c,R1
+\s\smrs R0,CPSR
+\s\sorr R1,R0,#0x40\s\s\s\s;Disable IRQ interrupts
+\s\smsr CPSR_c,R1
tst R0,#0x40
moveq R0,#1
movne R0,#0
- bx LR
+\s\sbx LR
ArmGetFiqState
- mrs R0,CPSR
- tst R0,#0x40 ;Check if IRQ is enabled.
- moveq R0,#1
- movne R0,#0
- bx LR
+\s\smrs R0,CPSR
+\s\stst R0,#0x40\s\s ;Check if IRQ is enabled.
+\s\smoveq R0,#1
+\s\smovne R0,#0
+\s\sbx LR
ArmInvalidateTlb
mov r0,#0
diff --git a/ArmPkg/Library/ArmMPCoreMailBoxLib/ArmMPCoreMailBox.c b/ArmPkg/Library/ArmMPCoreMailBoxLib/ArmMPCoreMailBox.c
index 7648780e52..98a5b6c606 100644
--- a/ArmPkg/Library/ArmMPCoreMailBoxLib/ArmMPCoreMailBox.c
+++ b/ArmPkg/Library/ArmMPCoreMailBoxLib/ArmMPCoreMailBox.c
@@ -17,7 +17,7 @@
#include <Library/IoLib.h>
VOID ArmClearMPCoreMailbox() {
- MmioWrite32(PcdGet32(PcdMPCoreMailboxClearAddress),PcdGet32(PcdMPCoreMailboxClearValue));
+\s\sMmioWrite32(PcdGet32(PcdMPCoreMailboxClearAddress),PcdGet32(PcdMPCoreMailboxClearValue));
}
UINTN ArmGetMPCoreMailbox() {
diff --git a/ArmPkg/Library/ArmTrustZoneLib/ArmTrustZone.c b/ArmPkg/Library/ArmTrustZoneLib/ArmTrustZone.c
index ed9abe37f7..1e4809bc81 100644
--- a/ArmPkg/Library/ArmTrustZoneLib/ArmTrustZone.c
+++ b/ArmPkg/Library/ArmTrustZoneLib/ArmTrustZone.c
@@ -72,8 +72,8 @@ EFI_STATUS TZASCSetRegion(UINTN TzascBase, UINTN RegionId, UINTN Enabled, UINTN
Region = (UINT32*)((UINTN)TzascBase + TZASC_REGIONS_REG + (RegionId * 0x10));
MmioWrite32((UINTN)(Region), LowAddress&0xFFFF8000);
- MmioWrite32((UINTN)(Region+1), HighAddress);
- MmioWrite32((UINTN)(Region+2), ((Security & 0xF) <<28) | ((Size & 0x3F) << 1) | (Enabled & 0x1));
+\s\sMmioWrite32((UINTN)(Region+1), HighAddress);
+\s\sMmioWrite32((UINTN)(Region+2), ((Security & 0xF) <<28) | ((Size & 0x3F) << 1) | (Enabled & 0x1));
return EFI_SUCCESS;
}
diff --git a/ArmPkg/Library/BaseMemoryLibStm/Arm/CopyMem.S b/ArmPkg/Library/BaseMemoryLibStm/Arm/CopyMem.S
index 8339a10195..fcd7199d4b 100755
--- a/ArmPkg/Library/BaseMemoryLibStm/Arm/CopyMem.S
+++ b/ArmPkg/Library/BaseMemoryLibStm/Arm/CopyMem.S
@@ -42,71 +42,71 @@ InternalMemCopyMem (
GCC_ASM_EXPORT(InternalMemCopyMem)
ASM_PFX(InternalMemCopyMem):
- stmfd sp!, {r4-r11, lr}
- tst r0, #3
- mov r11, r0
- mov r10, r0
- mov ip, r2
- mov lr, r1
- movne r0, #0
- bne L4
- tst r1, #3
- movne r3, #0
- moveq r3, #1
- cmp r2, #31
- movls r0, #0
- andhi r0, r3, #1
+\s\sstmfd\s\ssp!, {r4-r11, lr}
+\s\stst\s\sr0, #3
+\s\smov\s\sr11, r0
+\s\smov\s\sr10, r0
+\s\smov\s\sip, r2
+\s\smov\s\slr, r1
+\s\smovne\s\sr0, #0
+\s\sbne\s\sL4
+\s\stst\s\sr1, #3
+\s\smovne\s\sr3, #0
+\s\smoveq\s\sr3, #1
+\s\scmp\s\sr2, #31
+\s\smovls\s\sr0, #0
+\s\sandhi\s\sr0, r3, #1
L4:
- cmp r11, r1
- bcc L26
- bls L7
- rsb r3, r1, r11
- cmp ip, r3
- bcc L26
- cmp ip, #0
- beq L7
- add r10, r11, ip
- add lr, ip, r1
- b L16
+\s\scmp\s\sr11, r1
+\s\sbcc\s\sL26
+\s\sbls\s\sL7
+\s\srsb\s\sr3, r1, r11
+\s\scmp\s\sip, r3
+\s\sbcc\s\sL26
+\s\scmp\s\sip, #0
+\s\sbeq\s\sL7
+\s\sadd\s\sr10, r11, ip
+\s\sadd\s\slr, ip, r1
+\s\sb\s\sL16
L29:
- sub ip, ip, #8
- cmp ip, #7
- ldrd r2, [lr, #-8]!
- movls r0, #0
- cmp ip, #0
- strd r2, [r10, #-8]!
- beq L7
+\s\ssub\s\sip, ip, #8
+\s\scmp\s\sip, #7
+\s\sldrd\s\sr2, [lr, #-8]!
+\s\smovls\s\sr0, #0
+\s\scmp\s\sip, #0
+\s\sstrd\s\sr2, [r10, #-8]!
+\s\sbeq\s\sL7
L16:
- cmp r0, #0
- bne L29
- sub r3, lr, #1
- sub ip, ip, #1
- ldrb r3, [r3, #0]
- sub r2, r10, #1
- cmp ip, #0
- sub r10, r10, #1
- sub lr, lr, #1
- strb r3, [r2, #0]
- bne L16
- b L7
+\s\scmp\s\sr0, #0
+\s\sbne\s\sL29
+\s\ssub\s\sr3, lr, #1
+\s\ssub\s\sip, ip, #1
+\s\sldrb\s\sr3, [r3, #0]\s\s
+\s\ssub\s\sr2, r10, #1
+\s\scmp\s\sip, #0
+\s\ssub\s\sr10, r10, #1
+\s\ssub\s\slr, lr, #1
+\s\sstrb\s\sr3, [r2, #0]
+\s\sbne\s\sL16
+\s\sb L7
L11:
- ldrb r3, [lr], #1
- sub ip, ip, #1
- strb r3, [r10], #1
+\s\sldrb\s\sr3, [lr], #1\s\s
+\s\ssub\s\sip, ip, #1
+\s\sstrb\s\sr3, [r10], #1
L26:
- cmp ip, #0
- beq L7
+\s\scmp\s\sip, #0
+\s\sbeq\s\sL7
L30:
- cmp r0, #0
- beq L11
- sub ip, ip, #32
- cmp ip, #31
- ldmia lr!, {r2-r9}
- movls r0, #0
- cmp ip, #0
- stmia r10!, {r2-r9}
- bne L30
+\s\scmp\s\sr0, #0
+\s\sbeq\s\sL11
+\s\ssub\s\sip, ip, #32
+\s\scmp\s\sip, #31
+\s\sldmia\s\slr!, {r2-r9}
+\s\smovls\s\sr0, #0
+\s\scmp\s\sip, #0
+\s\sstmia\s\sr10!, {r2-r9}
+\s\sbne\s\sL30
L7:
- mov r0, r11
- ldmfd sp!, {r4-r11, pc}
+ mov\s\sr0, r11
+\s\sldmfd\s\ssp!, {r4-r11, pc}
diff --git a/ArmPkg/Library/BaseMemoryLibStm/Arm/CopyMem.asm b/ArmPkg/Library/BaseMemoryLibStm/Arm/CopyMem.asm
index ea6fb3225d..afb74072a0 100755
--- a/ArmPkg/Library/BaseMemoryLibStm/Arm/CopyMem.asm
+++ b/ArmPkg/Library/BaseMemoryLibStm/Arm/CopyMem.asm
@@ -37,78 +37,78 @@ InternalMemCopyMem (
IN UINTN Length
)
**/
- EXPORT InternalMemCopyMem
+\s\sEXPORT InternalMemCopyMem
- AREA AsmMemStuff, CODE, READONLY
+\s\sAREA AsmMemStuff, CODE, READONLY
InternalMemCopyMem
- stmfd sp!, {r4-r11, lr}
- tst r0, #3
- mov r11, r0
- mov r10, r0
- mov ip, r2
- mov lr, r1
- movne r0, #0
- bne L4
- tst r1, #3
- movne r3, #0
- moveq r3, #1
- cmp r2, #31
- movls r0, #0
- andhi r0, r3, #1
+\s\sstmfd\s\ssp!, {r4-r11, lr}
+\s\stst\s\sr0, #3
+\s\smov\s\sr11, r0
+\s\smov\s\sr10, r0
+\s\smov\s\sip, r2
+\s\smov\s\slr, r1
+\s\smovne\s\sr0, #0
+\s\sbne\s\sL4
+\s\stst\s\sr1, #3
+\s\smovne\s\sr3, #0
+\s\smoveq\s\sr3, #1
+\s\scmp\s\sr2, #31
+\s\smovls\s\sr0, #0
+\s\sandhi\s\sr0, r3, #1
L4
- cmp r11, r1
- bcc L26
- bls L7
- rsb r3, r1, r11
- cmp ip, r3
- bcc L26
- cmp ip, #0
- beq L7
- add r10, r11, ip
- add lr, ip, r1
- b L16
+\s\scmp\s\sr11, r1
+\s\sbcc\s\sL26
+\s\sbls\s\sL7
+\s\srsb\s\sr3, r1, r11
+\s\scmp\s\sip, r3
+\s\sbcc\s\sL26
+\s\scmp\s\sip, #0
+\s\sbeq\s\sL7
+\s\sadd\s\sr10, r11, ip
+\s\sadd\s\slr, ip, r1
+\s\sb\s\sL16
L29
- sub ip, ip, #8
- cmp ip, #7
- ldrd r2, [lr, #-8]!
- movls r0, #0
- cmp ip, #0
- strd r2, [r10, #-8]!
- beq L7
+\s\ssub\s\sip, ip, #8
+\s\scmp\s\sip, #7
+\s\sldrd\s\sr2, [lr, #-8]!
+\s\smovls\s\sr0, #0
+\s\scmp\s\sip, #0
+\s\sstrd\s\sr2, [r10, #-8]!
+\s\sbeq\s\sL7
L16
- cmp r0, #0
- bne L29
- sub r3, lr, #1
- sub ip, ip, #1
- ldrb r3, [r3, #0]
- sub r2, r10, #1
- cmp ip, #0
- sub r10, r10, #1
- sub lr, lr, #1
- strb r3, [r2, #0]
- bne L16
- b L7
+\s\scmp\s\sr0, #0
+\s\sbne\s\sL29
+\s\ssub\s\sr3, lr, #1
+\s\ssub\s\sip, ip, #1
+\s\sldrb\s\sr3, [r3, #0]\s\s
+\s\ssub\s\sr2, r10, #1
+\s\scmp\s\sip, #0
+\s\ssub\s\sr10, r10, #1
+\s\ssub\s\slr, lr, #1
+\s\sstrb\s\sr3, [r2, #0]
+\s\sbne\s\sL16
+\s\sb L7
L11
- ldrb r3, [lr], #1
- sub ip, ip, #1
- strb r3, [r10], #1
+\s\sldrb\s\sr3, [lr], #1\s\s
+\s\ssub\s\sip, ip, #1
+\s\sstrb\s\sr3, [r10], #1
L26
- cmp ip, #0
- beq L7
+\s\scmp\s\sip, #0
+\s\sbeq\s\sL7
L30
- cmp r0, #0
- beq L11
- sub ip, ip, #32
- cmp ip, #31
- ldmia lr!, {r2-r9}
- movls r0, #0
- cmp ip, #0
- stmia r10!, {r2-r9}
- bne L30
+\s\scmp\s\sr0, #0
+\s\sbeq\s\sL11
+\s\ssub\s\sip, ip, #32
+\s\scmp\s\sip, #31
+\s\sldmia\s\slr!, {r2-r9}
+\s\smovls\s\sr0, #0
+\s\scmp\s\sip, #0
+\s\sstmia\s\sr10!, {r2-r9}
+\s\sbne\s\sL30
L7
- mov r0, r11
- ldmfd sp!, {r4-r11, pc}
-
+ mov\s\sr0, r11
+\s\sldmfd\s\ssp!, {r4-r11, pc}
+\s\s
END
diff --git a/ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.S b/ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.S
index c6dbc7f2c7..db37cb47d4 100755
--- a/ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.S
+++ b/ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.S
@@ -34,49 +34,49 @@ InternalMemSetMem (
IN UINT8 Value
)
**/
-
+\s\s
.text
.align 2
GCC_ASM_EXPORT(InternalMemSetMem)
ASM_PFX(InternalMemSetMem):
- stmfd sp!, {r4-r11, lr}
- tst r0, #3
- movne r3, #0
- moveq r3, #1
- cmp r1, #31
- movls lr, #0
- andhi lr, r3, #1
- cmp lr, #0
- mov r12, r0
- bne L31
+\s\sstmfd\s\ssp!, {r4-r11, lr}
+\s\stst\s\s r0, #3
+\s\smovne\s\sr3, #0
+\s\smoveq\s\sr3, #1
+\s\scmp\s\s r1, #31
+\s\smovls lr, #0
+\s\sandhi\s\slr, r3, #1
+\s\scmp\s\s lr, #0
+\s\smov\s\s r12, r0
+\s\sbne\s\s L31
L32:
- mov r3, #0
- b L43
+\s\smov\s\s r3, #0
+\s\sb\s\s L43
L31:
and r4, r2, #0xff
orr r4, r4, r4, LSL #8
orr r4, r4, r4, LSL #16
- mov r5, r4
- mov r5, r4
- mov r6, r4
- mov r7, r4
- mov r8, r4
- mov r9, r4
- mov r10, r4
- mov r11, r4
- b L32
+\s\smov r5, r4
+\s\smov r5, r4
+\s\smov r6, r4
+\s\smov r7, r4
+\s\smov r8, r4
+\s\smov r9, r4
+\s\smov r10, r4
+\s\smov r11, r4
+\s\sb\s\s L32
L34:
- cmp lr, #0
- streqb r2, [r12], #1
- subeq r1, r1, #1
- beq L43
- sub r1, r1, #32
- cmp r1, #31
- movls lr, r3
- stmia r12!, {r4-r11}
+\s\scmp\s\s lr, #0
+\s\sstreqb\s\sr2, [r12], #1
+\s\ssubeq\s\s r1, r1, #1
+\s\sbeq\s\s L43
+\s\ssub\s\s r1, r1, #32
+\s\scmp\s\s r1, #31
+\s\smovls\s\s lr, r3
+\s\sstmia\s\s r12!, {r4-r11}
L43:
- cmp r1, #0
- bne L34
- ldmfd sp!, {r4-r11, pc}
- \ No newline at end of file
+\s\scmp\s\s r1, #0
+\s\sbne\s\s L34
+\s\sldmfd\s\s sp!, {r4-r11, pc}
+\s\s \ No newline at end of file
diff --git a/ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.asm b/ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.asm
index bed26fef6e..4a4d2380b0 100755
--- a/ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.asm
+++ b/ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.asm
@@ -33,51 +33,51 @@ InternalMemSetMem (
IN UINT8 Value
)
**/
-
- EXPORT InternalMemSetMem
-
- AREA AsmMemStuff, CODE, READONLY
+\s\s
+\s\sEXPORT InternalMemSetMem
+\s\s
+\s\sAREA AsmMemStuff, CODE, READONLY
InternalMemSetMem
- stmfd sp!, {r4-r11, lr}
- tst r0, #3
- movne r3, #0
- moveq r3, #1
- cmp r1, #31
- movls lr, #0
- andhi lr, r3, #1
- cmp lr, #0
- mov r12, r0
- bne L31
+\s\sstmfd\s\ssp!, {r4-r11, lr}
+\s\stst\s\s r0, #3
+\s\smovne\s\sr3, #0
+\s\smoveq\s\sr3, #1
+\s\scmp\s\s r1, #31
+\s\smovls lr, #0
+\s\sandhi\s\slr, r3, #1
+\s\scmp\s\s lr, #0
+\s\smov\s\s r12, r0
+\s\sbne\s\s L31
L32
- mov r3, #0
- b L43
+\s\smov\s\s r3, #0
+\s\sb\s\s L43
L31
and r4, r2, #0xff
orr r4, r4, r4, LSL #8
orr r4, r4, r4, LSL #16
- mov r5, r4
- mov r5, r4
- mov r6, r4
- mov r7, r4
- mov r8, r4
- mov r9, r4
- mov r10, r4
- mov r11, r4
- b L32
+\s\smov r5, r4
+\s\smov r5, r4
+\s\smov r6, r4
+\s\smov r7, r4
+\s\smov r8, r4
+\s\smov r9, r4
+\s\smov r10, r4
+\s\smov r11, r4
+\s\sb\s\s L32
L34
- cmp lr, #0
- streqb r2, [r12], #1
- subeq r1, r1, #1
- beq L43
- sub r1, r1, #32
- cmp r1, #31
- movls lr, r3
- stmia r12!, {r4-r11}
+\s\scmp\s\s lr, #0
+\s\sstreqb\s\sr2, [r12], #1
+\s\ssubeq\s\s r1, r1, #1
+\s\sbeq\s\s L43
+\s\ssub\s\s r1, r1, #32
+\s\scmp\s\s r1, #31
+\s\smovls\s\s lr, r3
+\s\sstmia\s\s r12!, {r4-r11}
L43
- cmp r1, #0
- bne L34
- ldmfd sp!, {r4-r11, pc}
-
+\s\scmp\s\s r1, #0
+\s\sbne\s\s L34
+\s\sldmfd\s\s sp!, {r4-r11, pc}
+\s\s
END
\ No newline at end of file
diff --git a/ArmPkg/Library/BaseMemoryLibVstm/Arm/CopyMem.S b/ArmPkg/Library/BaseMemoryLibVstm/Arm/CopyMem.S
index 239807c732..2e389b045f 100755
--- a/ArmPkg/Library/BaseMemoryLibVstm/Arm/CopyMem.S
+++ b/ArmPkg/Library/BaseMemoryLibVstm/Arm/CopyMem.S
@@ -42,73 +42,73 @@ InternalMemCopyMem (
GCC_ASM_EXPORT(InternalMemCopyMem)
ASM_PFX(InternalMemCopyMem):
- stmfd sp!, {r4, r9, lr}
- tst r0, #3
- mov r4, r0
- mov r9, r0
- mov ip, r2
- mov lr, r1
- movne r0, #0
- bne L4
- tst r1, #3
- movne r3, #0
- moveq r3, #1
- cmp r2, #127
- movls r0, #0
- andhi r0, r3, #1
+\s\sstmfd\s\ssp!, {r4, r9, lr}
+\s\stst\s\sr0, #3
+\s\smov\s\sr4, r0
+\s\smov\s\sr9, r0
+\s\smov\s\sip, r2
+\s\smov\s\slr, r1
+\s\smovne\s\sr0, #0
+\s\sbne\s\sL4
+\s\stst\s\sr1, #3
+\s\smovne\s\sr3, #0
+\s\smoveq\s\sr3, #1
+\s\scmp\s\sr2, #127
+\s\smovls\s\sr0, #0
+\s\sandhi\s\sr0, r3, #1
L4:
- cmp r4, r1
- bcc L26
- bls L7
- rsb r3, r1, r4
- cmp ip, r3
- bcc L26
- cmp ip, #0
- beq L7
- add r9, r4, ip
- add lr, ip, r1
- b L16
+\s\scmp\s\sr4, r1
+\s\sbcc\s\sL26
+\s\sbls\s\sL7
+\s\srsb\s\sr3, r1, r4
+\s\scmp\s\sip, r3
+\s\sbcc\s\sL26
+\s\scmp\s\sip, #0
+\s\sbeq\s\sL7
+\s\sadd\s\sr9, r4, ip
+\s\sadd\s\slr, ip, r1
+\s\sb\s\sL16
L29:
- sub ip, ip, #8
- cmp ip, #7
- ldrd r2, [lr, #-8]!
- movls r0, #0
- cmp ip, #0
- strd r2, [r9, #-8]!
- beq L7
+\s\ssub\s\sip, ip, #8
+\s\scmp\s\sip, #7
+\s\sldrd\s\sr2, [lr, #-8]!
+\s\smovls\s\sr0, #0
+\s\scmp\s\sip, #0
+\s\sstrd\s\sr2, [r9, #-8]!
+\s\sbeq\s\sL7
L16:
- cmp r0, #0
- bne L29
- sub r3, lr, #1
- sub ip, ip, #1
- ldrb r3, [r3, #0]
- sub r2, r9, #1
- cmp ip, #0
- sub r9, r9, #1
- sub lr, lr, #1
- strb r3, [r2, #0]
- bne L16
- b L7
+\s\scmp\s\sr0, #0
+\s\sbne\s\sL29
+\s\ssub\s\sr3, lr, #1
+\s\ssub\s\sip, ip, #1
+\s\sldrb\s\sr3, [r3, #0]\s\s
+\s\ssub\s\sr2, r9, #1
+\s\scmp\s\sip, #0
+\s\ssub\s\sr9, r9, #1
+\s\ssub\s\slr, lr, #1
+\s\sstrb\s\sr3, [r2, #0]
+\s\sbne\s\sL16
+\s\sb L7
L11:
- ldrb r3, [lr], #1
- sub ip, ip, #1
- strb r3, [r9], #1
+\s\sldrb\s\sr3, [lr], #1\s\s
+\s\ssub\s\sip, ip, #1
+\s\sstrb\s\sr3, [r9], #1
L26:
- cmp ip, #0
- beq L7
+\s\scmp\s\sip, #0
+\s\sbeq\s\sL7
L30:
- cmp r0, #0
- beq L11
- sub ip, ip, #128 // 32
- cmp ip, #127 // 31
- vldm lr!, {d0-d15}
- movls r0, #0
- cmp ip, #0
- vstm r9!, {d0-d15}
- bne L30
+\s\scmp\s\sr0, #0
+\s\sbeq\s\sL11
+\s\ssub\s\sip, ip, #128 // 32
+\s\scmp\s\sip, #127 // 31
+\s\svldm lr!, {d0-d15}
+\s\smovls\s\sr0, #0
+\s\scmp\s\sip, #0
+\s\svstm r9!, {d0-d15}
+\s\sbne\s\sL30
L7:
dsb
- mov r0, r4
- ldmfd sp!, {r4, r9, pc}
+ mov\s\sr0, r4
+\s\sldmfd\s\ssp!, {r4, r9, pc}
diff --git a/ArmPkg/Library/BaseMemoryLibVstm/Arm/CopyMem.asm b/ArmPkg/Library/BaseMemoryLibVstm/Arm/CopyMem.asm
index d9b0e9260c..a0b7596a9f 100755
--- a/ArmPkg/Library/BaseMemoryLibVstm/Arm/CopyMem.asm
+++ b/ArmPkg/Library/BaseMemoryLibVstm/Arm/CopyMem.asm
@@ -37,79 +37,79 @@ InternalMemCopyMem (
IN UINTN Length
)
**/
- EXPORT InternalMemCopyMem
+\s\sEXPORT InternalMemCopyMem
- AREA AsmMemStuff, CODE, READONLY
+\s\sAREA AsmMemStuff, CODE, READONLY
InternalMemCopyMem
- stmfd sp!, {r4, r9, lr}
- tst r0, #3
- mov r4, r0
- mov r9, r0
- mov ip, r2
- mov lr, r1
- movne r0, #0
- bne L4
- tst r1, #3
- movne r3, #0
- moveq r3, #1
- cmp r2, #127
- movls r0, #0
- andhi r0, r3, #1
+\s\sstmfd\s\ssp!, {r4, r9, lr}
+\s\stst\s\sr0, #3
+\s\smov\s\sr4, r0
+\s\smov\s\sr9, r0
+\s\smov\s\sip, r2
+\s\smov\s\slr, r1
+\s\smovne\s\sr0, #0
+\s\sbne\s\sL4
+\s\stst\s\sr1, #3
+\s\smovne\s\sr3, #0
+\s\smoveq\s\sr3, #1
+\s\scmp\s\sr2, #127
+\s\smovls\s\sr0, #0
+\s\sandhi\s\sr0, r3, #1
L4
- cmp r4, r1
- bcc L26
- bls L7
- rsb r3, r1, r4
- cmp ip, r3
- bcc L26
- cmp ip, #0
- beq L7
- add r9, r4, ip
- add lr, ip, r1
- b L16
+\s\scmp\s\sr4, r1
+\s\sbcc\s\sL26
+\s\sbls\s\sL7
+\s\srsb\s\sr3, r1, r4
+\s\scmp\s\sip, r3
+\s\sbcc\s\sL26
+\s\scmp\s\sip, #0
+\s\sbeq\s\sL7
+\s\sadd\s\sr9, r4, ip
+\s\sadd\s\slr, ip, r1
+\s\sb\s\sL16
L29
- sub ip, ip, #8
- cmp ip, #7
- ldrd r2, [lr, #-8]!
- movls r0, #0
- cmp ip, #0
- strd r2, [r9, #-8]!
- beq L7
+\s\ssub\s\sip, ip, #8
+\s\scmp\s\sip, #7
+\s\sldrd\s\sr2, [lr, #-8]!
+\s\smovls\s\sr0, #0
+\s\scmp\s\sip, #0
+\s\sstrd\s\sr2, [r9, #-8]!
+\s\sbeq\s\sL7
L16
- cmp r0, #0
- bne L29
- sub r3, lr, #1
- sub ip, ip, #1
- ldrb r3, [r3, #0]
- sub r2, r9, #1
- cmp ip, #0
- sub r9, r9, #1
- sub lr, lr, #1
- strb r3, [r2, #0]
- bne L16
- b L7
+\s\scmp\s\sr0, #0
+\s\sbne\s\sL29
+\s\ssub\s\sr3, lr, #1
+\s\ssub\s\sip, ip, #1
+\s\sldrb\s\sr3, [r3, #0]\s\s
+\s\ssub\s\sr2, r9, #1
+\s\scmp\s\sip, #0
+\s\ssub\s\sr9, r9, #1
+\s\ssub\s\slr, lr, #1
+\s\sstrb\s\sr3, [r2, #0]
+\s\sbne\s\sL16
+\s\sb L7
L11
- ldrb r3, [lr], #1
- sub ip, ip, #1
- strb r3, [r9], #1
+\s\sldrb\s\sr3, [lr], #1\s\s
+\s\ssub\s\sip, ip, #1
+\s\sstrb\s\sr3, [r9], #1
L26
- cmp ip, #0
- beq L7
+\s\scmp\s\sip, #0
+\s\sbeq\s\sL7
L30
- cmp r0, #0
- beq L11
- sub ip, ip, #128 // 32
- cmp ip, #127 // 31
- vldm lr!, {d0-d15}
- movls r0, #0
- cmp ip, #0
- vstm r9!, {d0-d15}
- bne L30
+\s\scmp\s\sr0, #0
+\s\sbeq\s\sL11
+\s\ssub\s\sip, ip, #128 // 32
+\s\scmp\s\sip, #127 // 31
+\s\svldm lr!, {d0-d15}
+\s\smovls\s\sr0, #0
+\s\scmp\s\sip, #0
+\s\svstm r9!, {d0-d15}
+\s\sbne\s\sL30
L7
dsb
- mov r0, r4
- ldmfd sp!, {r4, r9, pc}
+ mov\s\sr0, r4
+\s\sldmfd\s\ssp!, {r4, r9, pc}
END
diff --git a/ArmPkg/Library/BaseMemoryLibVstm/Arm/SetMem.S b/ArmPkg/Library/BaseMemoryLibVstm/Arm/SetMem.S
index 8120cfc1c3..24388ebba6 100755
--- a/ArmPkg/Library/BaseMemoryLibVstm/Arm/SetMem.S
+++ b/ArmPkg/Library/BaseMemoryLibVstm/Arm/SetMem.S
@@ -34,25 +34,25 @@ InternalMemSetMem (
IN UINT8 Value
)
**/
-
+\s\s
.text
.align 2
GCC_ASM_EXPORT(InternalMemSetMem)
ASM_PFX(InternalMemSetMem):
- stmfd sp!, {r4-r7, lr}
- tst r0, #3
- movne r3, #0
- moveq r3, #1
- cmp r1, #127
- movls lr, #0
- andhi lr, r3, #1
- cmp lr, #0
- mov r12, r0
- bne L31
+\s\sstmfd\s\ssp!, {r4-r7, lr}
+\s\stst\s\s r0, #3
+\s\smovne\s\sr3, #0
+\s\smoveq\s\sr3, #1
+\s\scmp\s\s r1, #127
+\s\smovls lr, #0
+\s\sandhi\s\slr, r3, #1
+\s\scmp\s\s lr, #0
+\s\smov\s\s r12, r0
+\s\sbne\s\s L31
L32:
- mov r3, #0
- b L43
+\s\smov\s\s r3, #0
+\s\sb\s\s L43
L31:
vdup.8 q0,r2
vmov q1,q0
@@ -62,19 +62,19 @@ L31:
vmov q5,q0
vmov q6,q0
vmov q7,q0
- b L32
+\s\sb\s\s L32
L34:
- cmp lr, #0
- streqb r2, [r12], #1
- subeq r1, r1, #1
- beq L43
- sub r1, r1, #128
- cmp r1, #127
- cmp r1, #31
- movls lr, r3
- vstm r12!, {d0-d15}
+\s\scmp\s\s lr, #0
+\s\sstreqb\s\sr2, [r12], #1
+\s\ssubeq\s\s r1, r1, #1
+\s\sbeq\s\s L43
+\s\ssub\s\s r1, r1, #128
+\s\scmp\s\s r1, #127
+\s\scmp\s\s r1, #31
+\s\smovls\s\s lr, r3
+\s\svstm r12!, {d0-d15}
L43:
- cmp r1, #0
- bne L34
- ldmfd sp!, {pc}
- \ No newline at end of file
+\s\scmp\s\s r1, #0
+\s\sbne\s\s L34
+\s\sldmfd\s\s sp!, {pc}
+\s\s \ No newline at end of file
diff --git a/ArmPkg/Library/BaseMemoryLibVstm/Arm/SetMem.asm b/ArmPkg/Library/BaseMemoryLibVstm/Arm/SetMem.asm
index 9fc4e4f362..b0d26d641c 100755
--- a/ArmPkg/Library/BaseMemoryLibVstm/Arm/SetMem.asm
+++ b/ArmPkg/Library/BaseMemoryLibVstm/Arm/SetMem.asm
@@ -33,25 +33,25 @@ InternalMemSetMem (
IN UINT8 Value
)
**/
-
- EXPORT InternalMemSetMem
-
- AREA AsmMemStuff, CODE, READONLY
+\s\s
+\s\sEXPORT InternalMemSetMem
+\s\s
+\s\sAREA AsmMemStuff, CODE, READONLY
InternalMemSetMem
- stmfd sp!, {lr}
- tst r0, #3
- movne r3, #0
- moveq r3, #1
- cmp r1, #127
- movls lr, #0
- andhi lr, r3, #1
- cmp lr, #0
- mov r12, r0
- bne L31
+\s\sstmfd\s\ssp!, {lr}
+\s\stst\s\s r0, #3
+\s\smovne\s\sr3, #0
+\s\smoveq\s\sr3, #1
+\s\scmp\s\s r1, #127
+\s\smovls lr, #0
+\s\sandhi\s\slr, r3, #1
+\s\scmp\s\s lr, #0
+\s\smov\s\s r12, r0
+\s\sbne\s\s L31
L32
- mov r3, #0
- b L43
+\s\smov\s\s r3, #0
+\s\sb\s\s L43
L31
vdup.8 q0,r2
vmov q1,q0
@@ -61,20 +61,20 @@ L31
vmov q5,q0
vmov q6,q0
vmov q7,q0
- b L32
+\s\sb\s\s L32
L34
- cmp lr, #0
- streqb r2, [r12], #1
- subeq r1, r1, #1
- beq L43
- sub r1, r1, #128
- cmp r1, #127
- movls lr, r3
- vstm r12!, {d0-d15}
+\s\scmp\s\s lr, #0
+\s\sstreqb\s\sr2, [r12], #1
+\s\ssubeq\s\s r1, r1, #1
+\s\sbeq\s\s L43
+\s\ssub\s\s r1, r1, #128
+\s\scmp\s\s r1, #127
+\s\smovls\s\s lr, r3
+\s\svstm r12!, {d0-d15}
L43
- cmp r1, #0
- bne L34
- ldmfd sp!, {pc}
-
+\s\scmp\s\s r1, #0
+\s\sbne\s\s L34
+\s\sldmfd\s\s sp!, {pc}
+\s\s
END
\ No newline at end of file
diff --git a/ArmPkg/Library/BdsLib/BdsFilePathFs.c b/ArmPkg/Library/BdsLib/BdsFilePathFs.c
index c92824742e..e5792b8afd 100644
--- a/ArmPkg/Library/BdsLib/BdsFilePathFs.c
+++ b/ArmPkg/Library/BdsLib/BdsFilePathFs.c
@@ -34,8 +34,8 @@ EFI_STATUS BdsLoadFileFromSimpleFileSystem(
}
//Try to Open the volume and get root directory
- Status = FsProtocol->OpenVolume(FsProtocol, &Fs);
- if (EFI_ERROR(Status)) {
+\s\sStatus = FsProtocol->OpenVolume(FsProtocol, &Fs);
+\s\sif (EFI_ERROR(Status)) {
return Status;
}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashldi3.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashldi3.S
index 101ec677e8..89beba0877 100644
--- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashldi3.S
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashldi3.S
@@ -12,24 +12,24 @@
#
#------------------------------------------------------------------------------
- .text
- .align 2
- GCC_ASM_EXPORT(__ashldi3)
-
+\s\s.text
+\s\s.align 2
+\s\sGCC_ASM_EXPORT(__ashldi3)
+\s\s
ASM_PFX(__ashldi3):
- cmp r2, #31
- bls L2
- cmp r2, #63
- subls r2, r2, #32
- movls r2, r0, asl r2
- movhi r2, #0
- mov r1, r2
- mov r0, #0
- bx lr
+\s\scmp\s\sr2, #31
+\s\sbls\s\sL2
+\s\scmp\s\sr2, #63
+\s\ssubls\s\sr2, r2, #32
+\s\smovls\s\sr2, r0, asl r2
+\s\smovhi\s\sr2, #0
+\s\smov\s\sr1, r2
+\s\smov\s\sr0, #0
+\s\sbx\s\slr
L2:
- cmp r2, #0
- rsbne r3, r2, #32
- movne r3, r0, lsr r3
- movne r0, r0, asl r2
- orrne r1, r3, r1, asl r2
- bx lr
+\s\scmp\s\sr2, #0
+\s\srsbne\s\sr3, r2, #32
+\s\smovne\s\sr3, r0, lsr r3
+\s\smovne\s\sr0, r0, asl r2
+\s\sorrne\s\sr1, r3, r1, asl r2
+\s\sbx\s\slr
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashrdi3.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashrdi3.S
index 775e288856..8c99f18e52 100644
--- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashrdi3.S
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashrdi3.S
@@ -12,25 +12,25 @@
#
#------------------------------------------------------------------------------
- .text
- .align 2
- GCC_ASM_EXPORT(__ashrdi3)
+\s\s.text
+\s\s.align 2
+\s\sGCC_ASM_EXPORT(__ashrdi3)
ASM_PFX(__ashrdi3):
- cmp r2, #31
- bls L2
- cmp r2, #63
- subls r2, r2, #32
- mov ip, r1, asr #31
- movls r2, r1, asr r2
- movhi r2, ip
- mov r0, r2
- mov r1, ip
- bx lr
+\s\scmp\s\sr2, #31
+\s\sbls\s\sL2
+\s\scmp\s\sr2, #63
+\s\ssubls\s\sr2, r2, #32
+\s\smov\s\sip, r1, asr #31
+\s\smovls\s\sr2, r1, asr r2
+\s\smovhi\s\sr2, ip
+\s\smov\s\sr0, r2
+\s\smov\s\sr1, ip
+\s\sbx\s\slr
L2:
- cmp r2, #0
- rsbne r3, r2, #32
- movne r3, r1, asl r3
- movne r1, r1, asr r2
- orrne r0, r3, r0, lsr r2
- bx lr
+\s\scmp\s\sr2, #0
+\s\srsbne\s\sr3, r2, #32
+\s\smovne\s\sr3, r1, asl r3
+\s\smovne\s\sr1, r1, asr r2
+\s\sorrne\s\sr0, r3, r0, lsr r2
+\s\sbx\s\slr
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/clzsi2.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/clzsi2.S
index 9fb6f2b3d9..ed01174bd2 100644
--- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/clzsi2.S
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/clzsi2.S
@@ -12,46 +12,46 @@
#
#------------------------------------------------------------------------------
- .text
- .align 2
- GCC_ASM_EXPORT(__clzsi2)
+\s\s.text
+\s\s.align 2
+\s\sGCC_ASM_EXPORT(__clzsi2)
ASM_PFX(__clzsi2):
- @ frame_needed = 1, uses_anonymous_args = 0
- stmfd sp!, {r7, lr}
- add r7, sp, #0
- movs r3, r0, lsr #16
- movne r3, #16
- moveq r3, #0
- movne r9, #0
- moveq r9, #16
- mov r3, r0, lsr r3
- tst r3, #65280
- movne r0, #8
- moveq r0, #0
- movne lr, #0
- moveq lr, #8
- mov r3, r3, lsr r0
- tst r3, #240
- movne r0, #4
- moveq r0, #0
- movne ip, #0
- moveq ip, #4
- mov r3, r3, lsr r0
- tst r3, #12
- movne r0, #2
- moveq r0, #0
- movne r1, #0
- moveq r1, #2
- mov r2, r3, lsr r0
- add r3, lr, r9
- add r0, r3, ip
- add r1, r0, r1
- mov r0, r2, lsr #1
- eor r0, r0, #1
- ands r0, r0, #1
- mvnne r0, #0
- rsb r3, r2, #2
- and r0, r0, r3
- add r0, r1, r0
- ldmfd sp!, {r7, pc}
+\s\s@ frame_needed = 1, uses_anonymous_args = 0
+\s\sstmfd\s\ssp!, {r7, lr}
+\s\sadd\s\sr7, sp, #0
+\s\smovs\s\sr3, r0, lsr #16
+\s\smovne\s\sr3, #16
+\s\smoveq\s\sr3, #0
+\s\smovne\s\sr9, #0
+\s\smoveq\s\sr9, #16
+\s\smov\s\sr3, r0, lsr r3
+\s\stst\s\sr3, #65280
+\s\smovne\s\sr0, #8
+\s\smoveq\s\sr0, #0
+\s\smovne\s\slr, #0
+\s\smoveq\s\slr, #8
+\s\smov\s\sr3, r3, lsr r0
+\s\stst\s\sr3, #240
+\s\smovne\s\sr0, #4
+\s\smoveq\s\sr0, #0
+\s\smovne\s\sip, #0
+\s\smoveq\s\sip, #4
+\s\smov\s\sr3, r3, lsr r0
+\s\stst\s\sr3, #12
+\s\smovne\s\sr0, #2
+\s\smoveq\s\sr0, #0
+\s\smovne\s\sr1, #0
+\s\smoveq\s\sr1, #2
+\s\smov\s\sr2, r3, lsr r0
+\s\sadd\s\sr3, lr, r9
+\s\sadd\s\sr0, r3, ip
+\s\sadd\s\sr1, r0, r1
+\s\smov\s\sr0, r2, lsr #1
+\s\seor\s\sr0, r0, #1
+\s\sands\s\sr0, r0, #1
+\s\smvnne\s\sr0, #0
+\s\srsb\s\sr3, r2, #2
+\s\sand\s\sr0, r0, r3
+\s\sadd\s\sr0, r1, r0
+\s\sldmfd\s\ssp!, {r7, pc}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ctzsi2.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ctzsi2.S
index 287ecd3ad7..3d9025ad1a 100644
--- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ctzsi2.S
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ctzsi2.S
@@ -12,38 +12,38 @@
#
#------------------------------------------------------------------------------
- .text
- .align 2
- GCC_ASM_EXPORT(__ctzsi2)
-
+\s\s.text
+\s\s.align 2
+\s\sGCC_ASM_EXPORT(__ctzsi2)
+\s\s
ASM_PFX(__ctzsi2):
- uxth r3, r0
- cmp r3, #0
- moveq ip, #16
- movne ip, #0
- @ lr needed for prologue
- mov r0, r0, lsr ip
- tst r0, #255
- movne r3, #0
- moveq r3, #8
- mov r0, r0, lsr r3
- tst r0, #15
- movne r1, #0
- moveq r1, #4
- add r3, r3, ip
- mov r0, r0, lsr r1
- tst r0, #3
- movne r2, #0
- moveq r2, #2
- add r3, r3, r1
- mov r0, r0, lsr r2
- and r0, r0, #3
- add r2, r3, r2
- eor r3, r0, #1
- mov r0, r0, lsr #1
- ands r3, r3, #1
- mvnne r3, #0
- rsb r0, r0, #2
- and r0, r3, r0
- add r0, r2, r0
- bx lr
+\s\suxth\s\sr3, r0
+\s\scmp\s\sr3, #0
+\s\smoveq\s\sip, #16
+\s\smovne\s\sip, #0
+\s\s@ lr needed for prologue
+\s\smov\s\sr0, r0, lsr ip
+\s\stst\s\sr0, #255
+\s\smovne\s\sr3, #0
+\s\smoveq\s\sr3, #8
+\s\smov\s\sr0, r0, lsr r3
+\s\stst\s\sr0, #15
+\s\smovne\s\sr1, #0
+\s\smoveq\s\sr1, #4
+\s\sadd\s\sr3, r3, ip
+\s\smov\s\sr0, r0, lsr r1
+\s\stst\s\sr0, #3
+\s\smovne\s\sr2, #0
+\s\smoveq\s\sr2, #2
+\s\sadd\s\sr3, r3, r1
+\s\smov\s\sr0, r0, lsr r2
+\s\sand\s\sr0, r0, #3
+\s\sadd\s\sr2, r3, r2
+\s\seor\s\sr3, r0, #1
+\s\smov\s\sr0, r0, lsr #1
+\s\sands\s\sr3, r3, #1
+\s\smvnne\s\sr3, #0
+\s\srsb\s\sr0, r0, #2
+\s\sand\s\sr0, r3, r0
+\s\sadd\s\sr0, r2, r0
+\s\sbx\s\slr
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divdi3.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divdi3.S
index d5f05f7eaf..080091a52f 100644
--- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divdi3.S
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divdi3.S
@@ -12,38 +12,38 @@
#
#------------------------------------------------------------------------------
- .text
- .align 2
- GCC_ASM_EXPORT(__divdi3)
-
+\s\s.text
+\s\s.align 2
+\s\sGCC_ASM_EXPORT(__divdi3)
+\s\s
ASM_PFX(__divdi3):
- @ args = 0, pretend = 0, frame = 0
- @ frame_needed = 1, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r7, lr}
- mov r4, r3, asr #31
- add r7, sp, #8
- stmfd sp!, {r10, r11}
- mov r10, r1, asr #31
- sub sp, sp, #8
- mov r11, r10
- mov r5, r4
- eor r0, r0, r10
- eor r1, r1, r10
- eor r2, r2, r4
- eor r3, r3, r4
- subs r2, r2, r4
- sbc r3, r3, r5
- mov ip, #0
- subs r0, r0, r10
- sbc r1, r1, r11
- str ip, [sp, #0]
- bl ASM_PFX(__udivmoddi4)
- eor r2, r10, r4
- eor r3, r10, r4
- eor r0, r0, r2
- eor r1, r1, r3
- subs r0, r0, r2
- sbc r1, r1, r3
- sub sp, r7, #16
- ldmfd sp!, {r10, r11}
- ldmfd sp!, {r4, r5, r7, pc}
+\s\s@ args = 0, pretend = 0, frame = 0
+\s\s@ frame_needed = 1, uses_anonymous_args = 0
+\s\sstmfd\s\ssp!, {r4, r5, r7, lr}
+\s\smov\s\sr4, r3, asr #31
+\s\sadd\s\sr7, sp, #8
+\s\sstmfd\s\ssp!, {r10, r11}
+\s\smov\s\sr10, r1, asr #31
+\s\ssub\s\ssp, sp, #8
+\s\smov\s\sr11, r10
+\s\smov\s\sr5, r4
+\s\seor\s\sr0, r0, r10
+\s\seor\s\sr1, r1, r10
+\s\seor\s\sr2, r2, r4
+\s\seor\s\sr3, r3, r4
+\s\ssubs\s\sr2, r2, r4
+\s\ssbc\s\sr3, r3, r5
+\s\smov\s\sip, #0
+\s\ssubs\s\sr0, r0, r10
+\s\ssbc\s\sr1, r1, r11
+\s\sstr\s\sip, [sp, #0]
+\s\sbl\s\sASM_PFX(__udivmoddi4)
+\s\seor\s\sr2, r10, r4
+\s\seor\s\sr3, r10, r4
+\s\seor\s\sr0, r0, r2
+\s\seor\s\sr1, r1, r3
+\s\ssubs\s\sr0, r0, r2
+\s\ssbc\s\sr1, r1, r3
+\s\ssub\s\ssp, r7, #16
+\s\sldmfd\s\ssp!, {r10, r11}
+\s\sldmfd\s\ssp!, {r4, r5, r7, pc}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divsi3.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divsi3.S
index d1a7f08747..473f1f22b9 100644
--- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divsi3.S
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divsi3.S
@@ -12,21 +12,21 @@
#
#------------------------------------------------------------------------------
- .text
- .align 2
- GCC_ASM_EXPORT(__divsi3)
-
+\s\s.text
+\s\s.align 2
+\s\sGCC_ASM_EXPORT(__divsi3)
+\s\s
ASM_PFX(__divsi3):
- eor r3, r0, r0, asr #31
- eor r2, r1, r1, asr #31
- stmfd sp!, {r4, r5, r7, lr}
- mov r5, r0, asr #31
- add r7, sp, #8
- mov r4, r1, asr #31
- sub r0, r3, r0, asr #31
- sub r1, r2, r1, asr #31
- bl ASM_PFX(__udivsi3)
- eor r1, r5, r4
- eor r0, r0, r1
- rsb r0, r1, r0
- ldmfd sp!, {r4, r5, r7, pc}
+\s\seor\s\sr3, r0, r0, asr #31
+\s\seor\s\sr2, r1, r1, asr #31
+\s\sstmfd\s\ssp!, {r4, r5, r7, lr}
+\s\smov\s\sr5, r0, asr #31
+\s\sadd\s\sr7, sp, #8
+\s\smov\s\sr4, r1, asr #31
+\s\ssub\s\sr0, r3, r0, asr #31
+\s\ssub\s\sr1, r2, r1, asr #31
+\s\sbl\s\sASM_PFX(__udivsi3)
+\s\seor\s\sr1, r5, r4
+\s\seor\s\sr0, r0, r1
+\s\srsb\s\sr0, r1, r0
+\s\sldmfd\s\ssp!, {r4, r5, r7, pc}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ldivmod.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ldivmod.S
index 97f9c6ca7c..2e7d70ab36 100755
--- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ldivmod.S
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ldivmod.S
@@ -13,9 +13,9 @@
//------------------------------------------------------------------------------
- .text
- .align 2
- GCC_ASM_EXPORT(__aeabi_ldivmod)
+\s\s.text
+\s\s.align 2
+\s\sGCC_ASM_EXPORT(__aeabi_ldivmod)
//
// A pair of (unsigned) long longs is returned in {{r0, r1}, {r2, r3}},
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/lshrdi3.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/lshrdi3.S
index 5800ae12a1..82e7cf78bb 100644
--- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/lshrdi3.S
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/lshrdi3.S
@@ -12,24 +12,24 @@
#
#------------------------------------------------------------------------------
- .text
- .align 2
- GCC_ASM_EXPORT(__lshrdi3)
-
+\s\s.text
+\s\s.align 2
+\s\sGCC_ASM_EXPORT(__lshrdi3)
+\s\s
ASM_PFX(__lshrdi3):
- cmp r2, #31
- bls L2
- cmp r2, #63
- subls r2, r2, #32
- movls r2, r1, lsr r2
- movhi r2, #0
- mov r0, r2
- mov r1, #0
- bx lr
+\s\scmp\s\sr2, #31
+\s\sbls\s\sL2
+\s\scmp\s\sr2, #63
+\s\ssubls\s\sr2, r2, #32
+\s\smovls\s\sr2, r1, lsr r2
+\s\smovhi\s\sr2, #0
+\s\smov\s\sr0, r2
+\s\smov\s\sr1, #0
+\s\sbx\s\slr
L2:
- cmp r2, #0
- rsbne r3, r2, #32
- movne r3, r1, asl r3
- movne r1, r1, lsr r2
- orrne r0, r3, r0, lsr r2
- bx lr
+\s\scmp\s\sr2, #0
+\s\srsbne\s\sr3, r2, #32
+\s\smovne\s\sr3, r1, asl r3
+\s\smovne\s\sr1, r1, lsr r2
+\s\sorrne\s\sr0, r3, r0, lsr r2
+\s\sbx\s\slr
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy.S
index 09c0e7a1c0..63d6c683d9 100644
--- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy.S
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy.S
@@ -12,23 +12,23 @@
#
#------------------------------------------------------------------------------
- .text
- .align 2
- GCC_ASM_EXPORT(memcpy)
+\s\s.text
+\s\s.align 2
+\s\sGCC_ASM_EXPORT(memcpy)
ASM_PFX(memcpy):
- stmfd sp!, {r7, lr}
- mov ip, #0
- add r7, sp, #0
- mov lr, r0
- b L4
+\s\sstmfd\s\ssp!, {r7, lr}
+\s\smov\s\sip, #0
+\s\sadd\s\sr7, sp, #0
+\s\smov\s\slr, r0
+\s\sb\s\sL4
L5:
- ldrb r3, [r1], #1 @ zero_extendqisi2
- add ip, ip, #1
- and r3, r3, #255
- strb r3, [lr], #1
+\s\sldrb\s\sr3, [r1], #1\s\s@ zero_extendqisi2
+\s\sadd\s\sip, ip, #1
+\s\sand\s\sr3, r3, #255
+\s\sstrb\s\sr3, [lr], #1
L4:
- cmp ip, r2
- bne L5
- ldmfd sp!, {r7, pc}
+\s\scmp\s\sip, r2
+\s\sbne\s\sL5
+\s\sldmfd\s\ssp!, {r7, pc}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memset.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memset.S
index 73cb1b2af3..3cd71e9f5f 100644
--- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memset.S
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memset.S
@@ -14,23 +14,25 @@
.text
- .align 2
- GCC_ASM_EXPORT (memset)
-
-ASM_PFX(memset):
- @ args = 0, pretend = 0, frame = 0
- @ frame_needed = 1, uses_anonymous_args = 0
- stmfd sp!, {r7, lr}
- mov ip, #0
- add r7, sp, #0
- mov lr, r0
- b L9
+\s\s.align 2
+\s\sGCC_ASM_EXPORT (memset)
+
+
+ASM_PFX(memset):
+
+\s\s@ args = 0, pretend = 0, frame = 0
+\s\s@ frame_needed = 1, uses_anonymous_args = 0
+\s\sstmfd\s\ssp!, {r7, lr}
+\s\smov\s\sip, #0
+\s\sadd\s\sr7, sp, #0
+\s\smov\s\slr, r0
+\s\sb\s\sL9
L10:
- and r3, r1, #255
- add ip, ip, #1
- strb r3, [lr], #1
+\s\sand\s\sr3, r1, #255
+\s\sadd\s\sip, ip, #1
+\s\sstrb\s\sr3, [lr], #1
L9:
- cmp ip, r2
- bne L10
- ldmfd sp!, {r7, pc}
+\s\scmp\s\sip, r2
+\s\sbne\s\sL10
+\s\sldmfd\s\ssp!, {r7, pc}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/moddi3.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/moddi3.S
index 4b86b83f00..c5b7ab301b 100644
--- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/moddi3.S
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/moddi3.S
@@ -12,35 +12,35 @@
#
#------------------------------------------------------------------------------
- .text
- .align 2
- GCC_ASM_EXPORT(__moddi3)
+\s\s.text
+\s\s.align 2
+\s\sGCC_ASM_EXPORT(__moddi3)
ASM_PFX(__moddi3):
- stmfd sp!, {r4, r5, r7, lr}
- mov r4, r1, asr #31
- add r7, sp, #8
- stmfd sp!, {r10, r11}
- mov r10, r3, asr #31
- sub sp, sp, #16
- mov r5, r4
- mov r11, r10
- eor r0, r0, r4
- eor r1, r1, r4
- eor r2, r2, r10
- eor r3, r3, r10
- add ip, sp, #8
- subs r0, r0, r4
- sbc r1, r1, r5
- subs r2, r2, r10
- sbc r3, r3, r11
- str ip, [sp, #0]
- bl ASM_PFX(__udivmoddi4)
- ldrd r0, [sp, #8]
- eor r0, r0, r4
- eor r1, r1, r4
- subs r0, r0, r4
- sbc r1, r1, r5
- sub sp, r7, #16
- ldmfd sp!, {r10, r11}
- ldmfd sp!, {r4, r5, r7, pc}
+\s\sstmfd\s\ssp!, {r4, r5, r7, lr}
+\s\smov\s\sr4, r1, asr #31
+\s\sadd\s\sr7, sp, #8
+\s\sstmfd\s\ssp!, {r10, r11}
+\s\smov\s\sr10, r3, asr #31
+\s\ssub\s\ssp, sp, #16
+\s\smov\s\sr5, r4
+\s\smov\s\sr11, r10
+\s\seor\s\sr0, r0, r4
+\s\seor\s\sr1, r1, r4
+\s\seor\s\sr2, r2, r10
+\s\seor\s\sr3, r3, r10
+\s\sadd\s\sip, sp, #8
+\s\ssubs\s\sr0, r0, r4
+\s\ssbc\s\sr1, r1, r5
+\s\ssubs\s\sr2, r2, r10
+\s\ssbc\s\sr3, r3, r11
+\s\sstr\s\sip, [sp, #0]
+\s\sbl\s\sASM_PFX(__udivmoddi4)
+\s\sldrd\s\sr0, [sp, #8]
+\s\seor\s\sr0, r0, r4
+\s\seor\s\sr1, r1, r4
+\s\ssubs\s\sr0, r0, r4
+\s\ssbc\s\sr1, r1, r5
+\s\ssub\s\ssp, r7, #16
+\s\sldmfd\s\ssp!, {r10, r11}
+\s\sldmfd\s\ssp!, {r4, r5, r7, pc}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/modsi3.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/modsi3.S
index 039688f44c..56b360426c 100644
--- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/modsi3.S
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/modsi3.S
@@ -12,16 +12,16 @@
#
#------------------------------------------------------------------------------
- .text
- .align 2
- GCC_ASM_EXPORT(__modsi3)
+\s\s.text
+\s\s.align 2
+\s\sGCC_ASM_EXPORT(__modsi3)
ASM_PFX(__modsi3):
- stmfd sp!, {r4, r5, r7, lr}
- add r7, sp, #8
- mov r5, r0
- mov r4, r1
- bl ___divsi3
- mul r0, r4, r0
- rsb r0, r0, r5
- ldmfd sp!, {r4, r5, r7, pc}
+\s\sstmfd\s\ssp!, {r4, r5, r7, lr}
+\s\sadd\s\sr7, sp, #8
+\s\smov\s\sr5, r0
+\s\smov\s\sr4, r1
+\s\sbl\s\s___divsi3
+\s\smul\s\sr0, r4, r0
+\s\srsb\s\sr0, r0, r5
+\s\sldmfd\s\ssp!, {r4, r5, r7, pc}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/muldi3.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/muldi3.S
index 919d6374e1..ab5d0cac2e 100644
--- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/muldi3.S
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/muldi3.S
@@ -12,47 +12,47 @@
#
#------------------------------------------------------------------------------
- .text
- .align 2
- GCC_ASM_EXPORT(__muldi3)
+\s\s.text
+\s\s.align 2
+\s\sGCC_ASM_EXPORT(__muldi3)
ASM_PFX(__muldi3):
- stmfd sp!, {r4, r5, r6, r7, lr}
- add r7, sp, #12
- stmfd sp!, {r8, r10, r11}
- ldr r11, L4
- mov r4, r0, lsr #16
- and r8, r0, r11
- and ip, r2, r11
- mul lr, ip, r8
- mul ip, r4, ip
- sub sp, sp, #8
- add r10, ip, lr, lsr #16
- and ip, r10, r11
- and lr, lr, r11
- mov r6, r2, lsr #16
- str r4, [sp, #4]
- add r4, lr, ip, asl #16
- mul ip, r8, r6
- mov r5, r10, lsr #16
- add r10, ip, r4, lsr #16
- and ip, r10, r11
- and lr, r4, r11
- add r4, lr, ip, asl #16
- mul r0, r3, r0
- add ip, r5, r10, lsr #16
- ldr r5, [sp, #4]
- mla r0, r2, r1, r0
- mla r5, r6, r5, ip
- mov r10, r4
- add r11, r0, r5
- mov r1, r11
- mov r0, r4
- sub sp, r7, #24
- ldmfd sp!, {r8, r10, r11}
- ldmfd sp!, {r4, r5, r6, r7, pc}
- .p2align 2
+\s\sstmfd\s\ssp!, {r4, r5, r6, r7, lr}
+\s\sadd\s\sr7, sp, #12
+\s\sstmfd\s\ssp!, {r8, r10, r11}
+\s\sldr\s\sr11, L4
+\s\smov\s\sr4, r0, lsr #16
+\s\sand\s\sr8, r0, r11
+\s\sand\s\sip, r2, r11
+\s\smul\s\slr, ip, r8
+\s\smul\s\sip, r4, ip
+\s\ssub\s\ssp, sp, #8
+\s\sadd\s\sr10, ip, lr, lsr #16
+\s\sand\s\sip, r10, r11
+\s\sand\s\slr, lr, r11
+\s\smov\s\sr6, r2, lsr #16
+\s\sstr\s\sr4, [sp, #4]
+\s\sadd\s\sr4, lr, ip, asl #16
+\s\smul\s\sip, r8, r6
+\s\smov\s\sr5, r10, lsr #16
+\s\sadd\s\sr10, ip, r4, lsr #16
+\s\sand\s\sip, r10, r11
+\s\sand\s\slr, r4, r11
+\s\sadd\s\sr4, lr, ip, asl #16
+\s\smul\s\sr0, r3, r0
+\s\sadd\s\sip, r5, r10, lsr #16
+\s\sldr\s\sr5, [sp, #4]
+\s\smla\s\sr0, r2, r1, r0
+\s\smla\s\sr5, r6, r5, ip
+\s\smov\s\sr10, r4
+\s\sadd\s\sr11, r0, r5
+\s\smov\s\sr1, r11
+\s\smov\s\sr0, r4
+\s\ssub\s\ssp, r7, #24
+\s\sldmfd\s\ssp!, {r8, r10, r11}
+\s\sldmfd\s\ssp!, {r4, r5, r6, r7, pc}
+\s\s.p2align 2
L5:
- .align 2
+\s\s.align 2
L4:
- .long 65535
+\s\s.long\s\s65535
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/mullu.asm b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/mullu.asm
index 20bf5155de..533912426f 100644
--- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/mullu.asm
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/mullu.asm
@@ -13,8 +13,8 @@
//------------------------------------------------------------------------------
- EXPORT __ARM_ll_mullu
- EXPORT __aeabi_lmul
+ EXPORT\s\s__ARM_ll_mullu
+ EXPORT\s\s__aeabi_lmul
AREA Math, CODE, READONLY
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch.asm b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch.asm
index c11b299c1d..7a52a039ff 100644
--- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch.asm
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch.asm
@@ -14,16 +14,16 @@
- EXPORT __ARM_switch8
+ EXPORT\s\s__ARM_switch8
- AREA ArmSwitch, CODE, READONLY
-
+ AREA\s\sArmSwitch, CODE, READONLY
+\s\s
__ARM_switch8
- LDRB r12,[lr,#-1]
- CMP r3,r12
- LDRBCC r3,[lr,r3]
- LDRBCS r3,[lr,r12]
- ADD r12,lr,r3,LSL #1
- BX r12
+\s\sLDRB\s\s r12,[lr,#-1]
+\s\sCMP\s\s\s\s r3,r12
+\s\sLDRBCC\s\sr3,[lr,r3]
+\s\sLDRBCS\s\sr3,[lr,r12]
+\s\sADD\s\s\s\s r12,lr,r3,LSL #1
+\s\sBX\s\s\s\s r12
END
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ucmpdi2.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ucmpdi2.S
index ae9a703106..ea5cf07eba 100644
--- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ucmpdi2.S
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ucmpdi2.S
@@ -12,27 +12,27 @@
#
#------------------------------------------------------------------------------
- .text
- .align 2
- GCC_ASM_EXPORT(__ucmpdi2)
-
+\s\s.text
+\s\s.align 2
+\s\sGCC_ASM_EXPORT(__ucmpdi2)
+\s\s
ASM_PFX(__ucmpdi2):
- stmfd sp!, {r4, r5, r8, lr}
- cmp r1, r3
- mov r8, r0
- mov r4, r2
- mov r5, r3
- bcc L2
- bhi L4
- cmp r0, r2
- bcc L2
- movls r0, #1
- bls L8
- b L4
+\s\sstmfd\s\ssp!, {r4, r5, r8, lr}
+\s\scmp\s\sr1, r3
+\s\smov\s\sr8, r0
+\s\smov\s\sr4, r2
+\s\smov\s\sr5, r3
+\s\sbcc\s\sL2
+\s\sbhi\s\sL4
+\s\scmp\s\sr0, r2
+\s\sbcc\s\sL2
+\s\smovls\s\sr0, #1
+\s\sbls\s\sL8
+\s\sb\s\sL4
L2:
- mov r0, #0
- b L8
+\s\smov\s\sr0, #0
+\s\sb\s\sL8
L4:
- mov r0, #2
+\s\smov\s\sr0, #2
L8:
- ldmfd sp!, {r4, r5, r8, pc}
+\s\sldmfd\s\ssp!, {r4, r5, r8, pc}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivdi3.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivdi3.S
index 7b67aeeeab..36e2a11cd7 100644
--- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivdi3.S
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivdi3.S
@@ -12,16 +12,16 @@
#
#------------------------------------------------------------------------------
- .text
- .align 2
- GCC_ASM_EXPORT(__udivdi3)
+\s\s.text
+\s\s.align 2
+\s\sGCC_ASM_EXPORT(__udivdi3)
ASM_PFX(__udivdi3):
- stmfd sp!, {r7, lr}
- add r7, sp, #0
- sub sp, sp, #8
- mov ip, #0
- str ip, [sp, #0]
- bl ASM_PFX(__udivmoddi4)
- sub sp, r7, #0
- ldmfd sp!, {r7, pc}
+\s\sstmfd\s\ssp!, {r7, lr}
+\s\sadd\s\sr7, sp, #0
+\s\ssub\s\ssp, sp, #8
+\s\smov\s\sip, #0
+\s\sstr\s\sip, [sp, #0]
+\s\sbl\s\sASM_PFX(__udivmoddi4)
+\s\ssub\s\ssp, r7, #0
+\s\sldmfd\s\ssp!, {r7, pc}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivmoddi4.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivmoddi4.S
index c6b823986c..63e25094e9 100644
--- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivmoddi4.S
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivmoddi4.S
@@ -12,231 +12,231 @@
#
#------------------------------------------------------------------------------
- .text
- .align 2
- GCC_ASM_EXPORT(__udivmoddi4)
-
+\s\s.text
+\s\s.align 2
+\s\sGCC_ASM_EXPORT(__udivmoddi4)
+\s\s
ASM_PFX(__udivmoddi4):
- stmfd sp!, {r4, r5, r6, r7, lr}
- add r7, sp, #12
- stmfd sp!, {r10, r11}
- sub sp, sp, #20
- stmia sp, {r2-r3}
- ldr r6, [sp, #48]
- orrs r2, r2, r3
- mov r10, r0
- mov r11, r1
- beq L2
- subs ip, r1, #0
- bne L4
- cmp r3, #0
- bne L6
- cmp r6, #0
- beq L8
- mov r1, r2
- bl ASM_PFX(__umodsi3)
- mov r1, #0
- stmia r6, {r0-r1}
+\s\sstmfd\s\ssp!, {r4, r5, r6, r7, lr}
+\s\sadd\s\sr7, sp, #12
+\s\sstmfd\s\ssp!, {r10, r11}
+\s\ssub\s\ssp, sp, #20
+\s\sstmia\s\ssp, {r2-r3}
+\s\sldr\s\sr6, [sp, #48]
+\s\sorrs\s\sr2, r2, r3
+\s\smov\s\sr10, r0
+\s\smov\s\sr11, r1
+\s\sbeq\s\sL2
+\s\ssubs\s\sip, r1, #0
+\s\sbne\s\sL4
+\s\scmp\s\sr3, #0
+\s\sbne\s\sL6
+\s\scmp\s\sr6, #0
+\s\sbeq\s\sL8
+\s\smov\s\sr1, r2
+\s\sbl\s\sASM_PFX(__umodsi3)
+\s\smov\s\sr1, #0
+\s\sstmia\s\sr6, {r0-r1}
L8:
- ldr r1, [sp, #0]
- mov r0, r10
- b L45
+\s\sldr\s\sr1, [sp, #0]
+\s\smov\s\sr0, r10
+\s\sb\s\sL45
L6:
- cmp r6, #0
- movne r1, #0
- stmneia r6, {r0-r1}
- b L2
+\s\scmp\s\sr6, #0
+\s\smovne\s\sr1, #0
+\s\sstmneia\s\sr6, {r0-r1}
+\s\sb\s\sL2
L4:
- ldr r1, [sp, #0]
- cmp r1, #0
- bne L12
- ldr r2, [sp, #4]
- cmp r2, #0
- bne L14
- cmp r6, #0
- beq L16
- mov r1, r2
- mov r0, r11
- bl ASM_PFX(__umodsi3)
- mov r1, #0
- stmia r6, {r0-r1}
+\s\sldr\s\sr1, [sp, #0]
+\s\scmp\s\sr1, #0
+\s\sbne\s\sL12
+\s\sldr\s\sr2, [sp, #4]
+\s\scmp\s\sr2, #0
+\s\sbne\s\sL14
+\s\scmp\s\sr6, #0
+\s\sbeq\s\sL16
+\s\smov\s\sr1, r2
+\s\smov\s\sr0, r11
+\s\sbl\s\sASM_PFX(__umodsi3)
+\s\smov\s\sr1, #0
+\s\sstmia\s\sr6, {r0-r1}
L16:
- ldr r1, [sp, #4]
- mov r0, r11
+\s\sldr\s\sr1, [sp, #4]
+\s\smov\s\sr0, r11
L45:
- bl ASM_PFX(__udivsi3)
+\s\sbl\s\sASM_PFX(__udivsi3)
L46:
- mov r10, r0
- mov r11, #0
- b L10
+\s\smov\s\sr10, r0
+\s\smov\s\sr11, #0
+\s\sb\s\sL10
L14:
- subs r1, r0, #0
- bne L18
- cmp r6, #0
- beq L16
- ldr r1, [sp, #4]
- mov r0, r11
- bl ASM_PFX(__umodsi3)
- mov r4, r10
- mov r5, r0
- stmia r6, {r4-r5}
- b L16
+\s\ssubs\s\sr1, r0, #0
+\s\sbne\s\sL18
+\s\scmp\s\sr6, #0
+\s\sbeq\s\sL16
+\s\sldr\s\sr1, [sp, #4]
+\s\smov\s\sr0, r11
+\s\sbl\s\sASM_PFX(__umodsi3)
+\s\smov\s\sr4, r10
+\s\smov\s\sr5, r0
+\s\sstmia\s\sr6, {r4-r5}
+\s\sb\s\sL16
L18:
- sub r3, r2, #1
- tst r2, r3
- bne L22
- cmp r6, #0
- movne r4, r0
- andne r5, ip, r3
- stmneia r6, {r4-r5}
+\s\ssub\s\sr3, r2, #1
+\s\stst\s\sr2, r3
+\s\sbne\s\sL22
+\s\scmp\s\sr6, #0
+\s\smovne\s\sr4, r0
+\s\sandne\s\sr5, ip, r3
+\s\sstmneia\s\sr6, {r4-r5}
L24:
- rsb r3, r2, #0
- and r3, r2, r3
- clz r3, r3
- rsb r3, r3, #31
- mov r0, ip, lsr r3
- b L46
+\s\srsb\s\sr3, r2, #0
+\s\sand\s\sr3, r2, r3
+\s\sclz\s\sr3, r3
+\s\srsb\s\sr3, r3, #31
+\s\smov\s\sr0, ip, lsr r3
+\s\sb\s\sL46
L22:
- clz r2, r2
- clz r3, ip
- rsb r3, r3, r2
- cmp r3, #30
- bhi L48
- rsb r2, r3, #31
- add lr, r3, #1
- mov r3, r1, asl r2
- str r3, [sp, #12]
- mov r3, r1, lsr lr
- ldr r0, [sp, #0]
- mov r5, ip, lsr lr
- orr r4, r3, ip, asl r2
- str r0, [sp, #8]
- b L29
+\s\sclz\s\sr2, r2
+\s\sclz\s\sr3, ip
+\s\srsb\s\sr3, r3, r2
+\s\scmp\s\sr3, #30
+\s\sbhi\s\sL48
+\s\srsb\s\sr2, r3, #31
+\s\sadd\s\slr, r3, #1
+\s\smov\s\sr3, r1, asl r2
+\s\sstr\s\sr3, [sp, #12]
+\s\smov\s\sr3, r1, lsr lr
+\s\sldr\s\sr0, [sp, #0]
+\s\smov\s\sr5, ip, lsr lr
+\s\sorr\s\sr4, r3, ip, asl r2
+\s\sstr\s\sr0, [sp, #8]
+\s\sb\s\sL29
L12:
- ldr r3, [sp, #4]
- cmp r3, #0
- bne L30
- sub r3, r1, #1
- tst r1, r3
- bne L32
- cmp r6, #0
- andne r3, r3, r0
- movne r2, r3
- movne r3, #0
- stmneia r6, {r2-r3}
+\s\sldr\s\sr3, [sp, #4]
+\s\scmp\s\sr3, #0
+\s\sbne\s\sL30
+\s\ssub\s\sr3, r1, #1
+\s\stst\s\sr1, r3
+\s\sbne\s\sL32
+\s\scmp\s\sr6, #0
+\s\sandne\s\sr3, r3, r0
+\s\smovne\s\sr2, r3
+\s\smovne\s\sr3, #0
+\s\sstmneia\s\sr6, {r2-r3}
L34:
- cmp r1, #1
- beq L10
- rsb r3, r1, #0
- and r3, r1, r3
- clz r3, r3
- rsb r0, r3, #31
- mov r1, ip, lsr r0
- rsb r3, r0, #32
- mov r0, r10, lsr r0
- orr ip, r0, ip, asl r3
- str r1, [sp, #12]
- str ip, [sp, #8]
- ldrd r10, [sp, #8]
- b L10
+\s\scmp\s\sr1, #1
+\s\sbeq\s\sL10
+\s\srsb\s\sr3, r1, #0
+\s\sand\s\sr3, r1, r3
+\s\sclz\s\sr3, r3
+\s\srsb\s\sr0, r3, #31
+\s\smov\s\sr1, ip, lsr r0
+\s\srsb\s\sr3, r0, #32
+\s\smov\s\sr0, r10, lsr r0
+\s\sorr\s\sip, r0, ip, asl r3
+\s\sstr\s\sr1, [sp, #12]
+\s\sstr\s\sip, [sp, #8]
+\s\sldrd\s\sr10, [sp, #8]
+\s\sb\s\sL10
L32:
- clz r2, r1
- clz r3, ip
- rsb r3, r3, r2
- rsb r4, r3, #31
- mov r2, r0, asl r4
- mvn r1, r3
- and r2, r2, r1, asr #31
- add lr, r3, #33
- str r2, [sp, #8]
- add r2, r3, #1
- mov r3, r3, asr #31
- and r0, r3, r0, asl r1
- mov r3, r10, lsr r2
- orr r3, r3, ip, asl r4
- and r3, r3, r1, asr #31
- orr r0, r0, r3
- mov r3, ip, lsr lr
- str r0, [sp, #12]
- mov r0, r10, lsr lr
- and r5, r3, r2, asr #31
- rsb r3, lr, #31
- mov r3, r3, asr #31
- orr r0, r0, ip, asl r1
- and r3, r3, ip, lsr r2
- and r0, r0, r2, asr #31
- orr r4, r3, r0
- b L29
+\s\sclz\s\sr2, r1
+\s\sclz\s\sr3, ip
+\s\srsb\s\sr3, r3, r2
+\s\srsb\s\sr4, r3, #31
+\s\smov\s\sr2, r0, asl r4
+\s\smvn\s\sr1, r3
+\s\sand\s\sr2, r2, r1, asr #31
+\s\sadd\s\slr, r3, #33
+\s\sstr\s\sr2, [sp, #8]
+\s\sadd\s\sr2, r3, #1
+\s\smov\s\sr3, r3, asr #31
+\s\sand\s\sr0, r3, r0, asl r1
+\s\smov\s\sr3, r10, lsr r2
+\s\sorr\s\sr3, r3, ip, asl r4
+\s\sand\s\sr3, r3, r1, asr #31
+\s\sorr\s\sr0, r0, r3
+\s\smov\s\sr3, ip, lsr lr
+\s\sstr\s\sr0, [sp, #12]
+\s\smov\s\sr0, r10, lsr lr
+\s\sand\s\sr5, r3, r2, asr #31
+\s\srsb\s\sr3, lr, #31
+\s\smov\s\sr3, r3, asr #31
+\s\sorr\s\sr0, r0, ip, asl r1
+\s\sand\s\sr3, r3, ip, lsr r2
+\s\sand\s\sr0, r0, r2, asr #31
+\s\sorr\s\sr4, r3, r0
+\s\sb\s\sL29
L30:
- clz r2, r3
- clz r3, ip
- rsb r3, r3, r2
- cmp r3, #31
- bls L37
+\s\sclz\s\sr2, r3
+\s\sclz\s\sr3, ip
+\s\srsb\s\sr3, r3, r2
+\s\scmp\s\sr3, #31
+\s\sbls\s\sL37
L48:
- cmp r6, #0
- stmneia r6, {r10-r11}
- b L2
+\s\scmp\s\sr6, #0
+\s\sstmneia\s\sr6, {r10-r11}
+\s\sb\s\sL2
L37:
- rsb r1, r3, #31
- mov r0, r0, asl r1
- add lr, r3, #1
- mov r2, #0
- str r0, [sp, #12]
- mov r0, r10, lsr lr
- str r2, [sp, #8]
- sub r2, r3, #31
- and r0, r0, r2, asr #31
- mov r3, ip, lsr lr
- orr r4, r0, ip, asl r1
- and r5, r3, r2, asr #31
+\s\srsb\s\sr1, r3, #31
+\s\smov\s\sr0, r0, asl r1
+\s\sadd\s\slr, r3, #1
+\s\smov\s\sr2, #0
+\s\sstr\s\sr0, [sp, #12]
+\s\smov\s\sr0, r10, lsr lr
+\s\sstr\s\sr2, [sp, #8]
+\s\ssub\s\sr2, r3, #31
+\s\sand\s\sr0, r0, r2, asr #31
+\s\smov\s\sr3, ip, lsr lr
+\s\sorr\s\sr4, r0, ip, asl r1
+\s\sand\s\sr5, r3, r2, asr #31
L29:
- mov ip, #0
- mov r10, ip
- b L40
+\s\smov\s\sip, #0
+\s\smov\s\sr10, ip
+\s\sb\s\sL40
L41:
- ldr r1, [sp, #12]
- ldr r2, [sp, #8]
- mov r3, r4, lsr #31
- orr r5, r3, r5, asl #1
- mov r3, r1, lsr #31
- orr r4, r3, r4, asl #1
- mov r3, r2, lsr #31
- orr r0, r3, r1, asl #1
- orr r1, ip, r2, asl #1
- ldmia sp, {r2-r3}
- str r0, [sp, #12]
- subs r2, r2, r4
- sbc r3, r3, r5
- str r1, [sp, #8]
- subs r0, r2, #1
- sbc r1, r3, #0
- mov r2, r1, asr #31
- ldmia sp, {r0-r1}
- mov r3, r2
- and ip, r2, #1
- and r3, r3, r1
- and r2, r2, r0
- subs r4, r4, r2
- sbc r5, r5, r3
- add r10, r10, #1
+\s\sldr\s\sr1, [sp, #12]
+\s\sldr\s\sr2, [sp, #8]
+\s\smov\s\sr3, r4, lsr #31
+\s\sorr\s\sr5, r3, r5, asl #1
+\s\smov\s\sr3, r1, lsr #31
+\s\sorr\s\sr4, r3, r4, asl #1
+\s\smov\s\sr3, r2, lsr #31
+\s\sorr\s\sr0, r3, r1, asl #1
+\s\sorr\s\sr1, ip, r2, asl #1
+\s\sldmia\s\ssp, {r2-r3}
+\s\sstr\s\sr0, [sp, #12]
+\s\ssubs\s\sr2, r2, r4
+\s\ssbc\s\sr3, r3, r5
+\s\sstr\s\sr1, [sp, #8]
+\s\ssubs\s\sr0, r2, #1
+\s\ssbc\s\sr1, r3, #0
+\s\smov\s\sr2, r1, asr #31
+\s\sldmia\s\ssp, {r0-r1}
+\s\smov\s\sr3, r2
+\s\sand\s\sip, r2, #1
+\s\sand\s\sr3, r3, r1
+\s\sand\s\sr2, r2, r0
+\s\ssubs\s\sr4, r4, r2
+\s\ssbc\s\sr5, r5, r3
+\s\sadd\s\sr10, r10, #1
L40:
- cmp r10, lr
- bne L41
- ldrd r0, [sp, #8]
- adds r0, r0, r0
- adc r1, r1, r1
- cmp r6, #0
- orr r10, r0, ip
- mov r11, r1
- stmneia r6, {r4-r5}
- b L10
+\s\scmp\s\sr10, lr
+\s\sbne\s\sL41
+\s\sldrd\s\sr0, [sp, #8]
+\s\sadds\s\sr0, r0, r0
+\s\sadc\s\sr1, r1, r1
+\s\scmp\s\sr6, #0
+\s\sorr\s\sr10, r0, ip
+\s\smov\s\sr11, r1
+\s\sstmneia\s\sr6, {r4-r5}
+\s\sb\s\sL10
L2:
- mov r10, #0
- mov r11, #0
+\s\smov\s\sr10, #0
+\s\smov\s\sr11, #0
L10:
- mov r0, r10
- mov r1, r11
- sub sp, r7, #20
- ldmfd sp!, {r10, r11}
- ldmfd sp!, {r4, r5, r6, r7, pc}
+\s\smov\s\sr0, r10
+\s\smov\s\sr1, r11
+\s\ssub\s\ssp, r7, #20
+\s\sldmfd\s\ssp!, {r10, r11}
+\s\sldmfd\s\ssp!, {r4, r5, r6, r7, pc}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivsi3.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivsi3.S
index 87509941f2..903d1b1a87 100644
--- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivsi3.S
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivsi3.S
@@ -12,46 +12,46 @@
#
#------------------------------------------------------------------------------
- .text
- .align 2
- GCC_ASM_EXPORT(__udivsi3)
+\s\s.text
+\s\s.align 2
+\s\sGCC_ASM_EXPORT(__udivsi3)
ASM_PFX(__udivsi3):
- cmp r1, #0
- cmpne r0, #0
- stmfd sp!, {r4, r5, r7, lr}
- add r7, sp, #8
- beq L2
- clz r2, r1
- clz r3, r0
- rsb r3, r3, r2
- cmp r3, #31
- bhi L2
- ldmeqfd sp!, {r4, r5, r7, pc}
- add r5, r3, #1
- rsb r3, r3, #31
- mov lr, #0
- mov r2, r0, asl r3
- mov ip, r0, lsr r5
- mov r4, lr
- b L8
+\s\scmp\s\sr1, #0
+\s\scmpne\s\sr0, #0
+\s\sstmfd\s\ssp!, {r4, r5, r7, lr}
+\s\sadd\s\sr7, sp, #8
+\s\sbeq\s\sL2
+\s\sclz\s\sr2, r1
+\s\sclz\s\sr3, r0
+\s\srsb\s\sr3, r3, r2
+\s\scmp\s\sr3, #31
+\s\sbhi\s\sL2
+\s\sldmeqfd\s\ssp!, {r4, r5, r7, pc}
+\s\sadd\s\sr5, r3, #1
+\s\srsb\s\sr3, r3, #31
+\s\smov\s\slr, #0
+\s\smov\s\sr2, r0, asl r3
+\s\smov\s\sip, r0, lsr r5
+\s\smov\s\sr4, lr
+\s\sb\s\sL8
L9:
- mov r0, r2, lsr #31
- orr ip, r0, ip, asl #1
- orr r2, r3, lr
- rsb r3, ip, r1
- sub r3, r3, #1
- and r0, r1, r3, asr #31
- mov lr, r3, lsr #31
- rsb ip, r0, ip
- add r4, r4, #1
+\s\smov\s\sr0, r2, lsr #31
+\s\sorr\s\sip, r0, ip, asl #1
+\s\sorr\s\sr2, r3, lr
+\s\srsb\s\sr3, ip, r1
+\s\ssub\s\sr3, r3, #1
+\s\sand\s\sr0, r1, r3, asr #31
+\s\smov\s\slr, r3, lsr #31
+\s\srsb\s\sip, r0, ip
+\s\sadd\s\sr4, r4, #1
L8:
- cmp r4, r5
- mov r3, r2, asl #1
- bne L9
- orr r0, r3, lr
- ldmfd sp!, {r4, r5, r7, pc}
+\s\scmp\s\sr4, r5
+\s\smov\s\sr3, r2, asl #1
+\s\sbne\s\sL9
+\s\sorr\s\sr0, r3, lr
+\s\sldmfd\s\ssp!, {r4, r5, r7, pc}
L2:
- mov r0, #0
- ldmfd sp!, {r4, r5, r7, pc}
+\s\smov\s\sr0, #0
+\s\sldmfd\s\ssp!, {r4, r5, r7, pc}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uldiv.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uldiv.S
index 4bde15f28d..6b309f9b0b 100755
--- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uldiv.S
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uldiv.S
@@ -14,9 +14,9 @@
- .text
- .align 2
- GCC_ASM_EXPORT(__aeabi_uldivmod)
+\s\s.text
+\s\s.align 2
+\s\sGCC_ASM_EXPORT(__aeabi_uldivmod)
//
//UINT64
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/umoddi3.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/umoddi3.S
index e4374b5789..df47e70319 100644
--- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/umoddi3.S
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/umoddi3.S
@@ -12,18 +12,18 @@
#
#------------------------------------------------------------------------------
- .text
- .align 2
- GCC_ASM_EXPORT(__umoddi3)
-
+\s\s.text
+\s\s.align 2
+\s\sGCC_ASM_EXPORT(__umoddi3)
+\s\s
ASM_PFX(__umoddi3):
- stmfd sp!, {r7, lr}
- add r7, sp, #0
- sub sp, sp, #16
- add ip, sp, #8
- str ip, [sp, #0]
- bl ASM_PFX(__udivmoddi4)
- ldrd r0, [sp, #8]
- sub sp, r7, #0
- ldmfd sp!, {r7, pc}
+\s\sstmfd\s\ssp!, {r7, lr}
+\s\sadd\s\sr7, sp, #0
+\s\ssub\s\ssp, sp, #16
+\s\sadd\s\sip, sp, #8
+\s\sstr\s\sip, [sp, #0]
+\s\sbl\s\sASM_PFX(__udivmoddi4)
+\s\sldrd\s\sr0, [sp, #8]
+\s\ssub\s\ssp, r7, #0
+\s\sldmfd\s\ssp!, {r7, pc}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/umodsi3.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/umodsi3.S
index f571a56db6..9506eedb38 100644
--- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/umodsi3.S
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/umodsi3.S
@@ -12,17 +12,17 @@
#
#------------------------------------------------------------------------------
- .text
- .align 2
- GCC_ASM_EXPORT(__umodsi3)
-
+\s\s.text
+\s\s.align 2
+\s\sGCC_ASM_EXPORT(__umodsi3)
+\s\s
ASM_PFX(__umodsi3):
- stmfd sp!, {r4, r5, r7, lr}
- add r7, sp, #8
- mov r5, r0
- mov r4, r1
- bl ASM_PFX(__udivsi3)
- mul r0, r4, r0
- rsb r0, r0, r5
- ldmfd sp!, {r4, r5, r7, pc}
+\s\sstmfd\s\ssp!, {r4, r5, r7, lr}
+\s\sadd\s\sr7, sp, #8
+\s\smov\s\sr5, r0
+\s\smov\s\sr4, r1
+\s\sbl \s\sASM_PFX(__udivsi3)
+\s\smul\s\sr0, r4, r0
+\s\srsb\s\sr0, r0, r5
+\s\sldmfd\s\ssp!, {r4, r5, r7, pc}
diff --git a/ArmPkg/Universal/MmcDxe/Mmc.h b/ArmPkg/Universal/MmcDxe/Mmc.h
index dbca991157..412e0192bc 100644
--- a/ArmPkg/Universal/MmcDxe/Mmc.h
+++ b/ArmPkg/Universal/MmcDxe/Mmc.h
@@ -30,12 +30,12 @@
#define MMC_OCR_POWERUP 0x80000000
-#define MMC_CSD_GET_CCC(Response) (Response[1] >> 20)
-#define MMC_CSD_GET_TRANSPEED(Response) (Response[0] & 0xFF)
-#define MMC_CSD_GET_READBLLEN(Response) ((Response[1] >> 16) & 0xF)
-#define MMC_CSD_GET_WRITEBLLEN(Response) ((Response[3] >> 22) & 0xF)
-#define MMC_CSD_GET_FILEFORMAT(Response) ((Response[3] >> 10) & 0x3)
-#define MMC_CSD_GET_FILEFORMATGRP(Response) ((Response[3] >> 15) & 0x1)
+#define MMC_CSD_GET_CCC(Response)\s\s\s\s(Response[1] >> 20)
+#define MMC_CSD_GET_TRANSPEED(Response)\s\s\s\s(Response[0] & 0xFF)
+#define MMC_CSD_GET_READBLLEN(Response)\s\s\s\s((Response[1] >> 16) & 0xF)
+#define MMC_CSD_GET_WRITEBLLEN(Response)\s\s((Response[3] >> 22) & 0xF)
+#define MMC_CSD_GET_FILEFORMAT(Response)\s\s((Response[3] >> 10) & 0x3)
+#define MMC_CSD_GET_FILEFORMATGRP(Response)\s\s((Response[3] >> 15) & 0x1)
#define MMC_CSD_GET_DEVICESIZE(csd) (((Response[2] >> 30) & 0x3) | ((Response[1] & 0x3FF) << 2))
#define MMC_CSD_GET_DEVICESIZEMULT(csd) ((Response[2] >> 15) & 0x7)