diff options
Diffstat (limited to 'ArmPkg/Drivers/ArmGic/GicV2')
| -rw-r--r-- | ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c | 318 | ||||
| -rw-r--r-- | ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c | 36 | ||||
| -rw-r--r-- | ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c | 42 | ||||
| -rw-r--r-- | ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2SecLib.c | 100 |
4 files changed, 0 insertions, 496 deletions
diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c deleted file mode 100644 index e649ac1bc6..0000000000 --- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c +++ /dev/null @@ -1,318 +0,0 @@ -/*++
-
-Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
-Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
-Portions copyright (c) 2011-2015, ARM Ltd. All rights reserved.<BR>
-
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-Module Name:
-
- GicV2/ArmGicV2Dxe.c
-
-Abstract:
-
- Driver implementing the GicV2 interrupt controller protocol
-
---*/
-
-#include <Library/ArmGicLib.h>
-
-#include "ArmGicDxe.h"
-
-#define ARM_GIC_DEFAULT_PRIORITY 0x80
-
-extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol;
-
-STATIC UINT32 mGicInterruptInterfaceBase;
-STATIC UINT32 mGicDistributorBase;
-
-/**
- Enable interrupt source Source.
-
- @param This Instance pointer for this protocol
- @param Source Hardware source of the interrupt
-
- @retval EFI_SUCCESS Source interrupt enabled.
- @retval EFI_UNSUPPORTED Source interrupt is not supported
-
-**/
-EFI_STATUS
-EFIAPI
-GicV2EnableInterruptSource (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source
- )
-{
- if (Source > mGicNumInterrupts) {
- ASSERT(FALSE);
- return EFI_UNSUPPORTED;
- }
-
- ArmGicEnableInterrupt (mGicDistributorBase, 0, Source);
-
- return EFI_SUCCESS;
-}
-
-/**
- Disable interrupt source Source.
-
- @param This Instance pointer for this protocol
- @param Source Hardware source of the interrupt
-
- @retval EFI_SUCCESS Source interrupt disabled.
- @retval EFI_UNSUPPORTED Source interrupt is not supported
-
-**/
-EFI_STATUS
-EFIAPI
-GicV2DisableInterruptSource (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source
- )
-{
- if (Source > mGicNumInterrupts) {
- ASSERT(FALSE);
- return EFI_UNSUPPORTED;
- }
-
- ArmGicDisableInterrupt (mGicDistributorBase, 0, Source);
-
- return EFI_SUCCESS;
-}
-
-/**
- Return current state of interrupt source Source.
-
- @param This Instance pointer for this protocol
- @param Source Hardware source of the interrupt
- @param InterruptState TRUE: source enabled, FALSE: source disabled.
-
- @retval EFI_SUCCESS InterruptState is valid
- @retval EFI_UNSUPPORTED Source interrupt is not supported
-
-**/
-EFI_STATUS
-EFIAPI
-GicV2GetInterruptSourceState (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source,
- IN BOOLEAN *InterruptState
- )
-{
- if (Source > mGicNumInterrupts) {
- ASSERT(FALSE);
- return EFI_UNSUPPORTED;
- }
-
- *InterruptState = ArmGicIsInterruptEnabled (mGicDistributorBase, 0, Source);
-
- return EFI_SUCCESS;
-}
-
-/**
- Signal to the hardware that the End Of Interrupt state
- has been reached.
-
- @param This Instance pointer for this protocol
- @param Source Hardware source of the interrupt
-
- @retval EFI_SUCCESS Source interrupt EOI'ed.
- @retval EFI_UNSUPPORTED Source interrupt is not supported
-
-**/
-EFI_STATUS
-EFIAPI
-GicV2EndOfInterrupt (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source
- )
-{
- if (Source > mGicNumInterrupts) {
- ASSERT(FALSE);
- return EFI_UNSUPPORTED;
- }
-
- ArmGicV2EndOfInterrupt (mGicInterruptInterfaceBase, Source);
- return EFI_SUCCESS;
-}
-
-/**
- EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.
-
- @param InterruptType Defines the type of interrupt or exception that
- occurred on the processor.This parameter is processor architecture specific.
- @param SystemContext A pointer to the processor context when
- the interrupt occurred on the processor.
-
- @return None
-
-**/
-VOID
-EFIAPI
-GicV2IrqInterruptHandler (
- IN EFI_EXCEPTION_TYPE InterruptType,
- IN EFI_SYSTEM_CONTEXT SystemContext
- )
-{
- UINT32 GicInterrupt;
- HARDWARE_INTERRUPT_HANDLER InterruptHandler;
-
- GicInterrupt = ArmGicV2AcknowledgeInterrupt (mGicInterruptInterfaceBase);
-
- // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the number of interrupt (ie: Spurious interrupt).
- if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) >= mGicNumInterrupts) {
- // The special interrupt do not need to be acknowledge
- return;
- }
-
- InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt];
- if (InterruptHandler != NULL) {
- // Call the registered interrupt handler.
- InterruptHandler (GicInterrupt, SystemContext);
- } else {
- DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));
- }
-
- GicV2EndOfInterrupt (&gHardwareInterruptV2Protocol, GicInterrupt);
-}
-
-//
-// The protocol instance produced by this driver
-//
-EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol = {
- RegisterInterruptSource,
- GicV2EnableInterruptSource,
- GicV2DisableInterruptSource,
- GicV2GetInterruptSourceState,
- GicV2EndOfInterrupt
-};
-
-/**
- Shutdown our hardware
-
- DXE Core will disable interrupts and turn off the timer and disable interrupts
- after all the event handlers have run.
-
- @param[in] Event The Event that is being processed
- @param[in] Context Event Context
-**/
-VOID
-EFIAPI
-GicV2ExitBootServicesEvent (
- IN EFI_EVENT Event,
- IN VOID *Context
- )
-{
- UINTN Index;
- UINT32 GicInterrupt;
-
- // Disable all the interrupts
- for (Index = 0; Index < mGicNumInterrupts; Index++) {
- GicV2DisableInterruptSource (&gHardwareInterruptV2Protocol, Index);
- }
-
- // Acknowledge all pending interrupts
- do {
- GicInterrupt = ArmGicV2AcknowledgeInterrupt (mGicInterruptInterfaceBase);
-
- if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) < mGicNumInterrupts) {
- GicV2EndOfInterrupt (&gHardwareInterruptV2Protocol, GicInterrupt);
- }
- } while (!ARM_GIC_IS_SPECIAL_INTERRUPTS (GicInterrupt));
-
- // Disable Gic Interface
- ArmGicV2DisableInterruptInterface (mGicInterruptInterfaceBase);
-
- // Disable Gic Distributor
- ArmGicDisableDistributor (mGicDistributorBase);
-}
-
-/**
- Initialize the state information for the CPU Architectural Protocol
-
- @param ImageHandle of the loaded driver
- @param SystemTable Pointer to the System Table
-
- @retval EFI_SUCCESS Protocol registered
- @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
- @retval EFI_DEVICE_ERROR Hardware problems
-
-**/
-EFI_STATUS
-GicV2DxeInitialize (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- )
-{
- EFI_STATUS Status;
- UINTN Index;
- UINT32 RegOffset;
- UINTN RegShift;
- UINT32 CpuTarget;
-
- // Make sure the Interrupt Controller Protocol is not already installed in the system.
- ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
-
- mGicInterruptInterfaceBase = PcdGet32 (PcdGicInterruptInterfaceBase);
- mGicDistributorBase = PcdGet32 (PcdGicDistributorBase);
- mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase);
-
- for (Index = 0; Index < mGicNumInterrupts; Index++) {
- GicV2DisableInterruptSource (&gHardwareInterruptV2Protocol, Index);
-
- // Set Priority
- RegOffset = Index / 4;
- RegShift = (Index % 4) * 8;
- MmioAndThenOr32 (
- mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
- ~(0xff << RegShift),
- ARM_GIC_DEFAULT_PRIORITY << RegShift
- );
- }
-
- //
- // Targets the interrupts to the Primary Cpu
- //
-
- // Only Primary CPU will run this code. We can identify our GIC CPU ID by reading
- // the GIC Distributor Target register. The 8 first GICD_ITARGETSRn are banked to each
- // connected CPU. These 8 registers hold the CPU targets fields for interrupts 0-31.
- // More Info in the GIC Specification about "Interrupt Processor Targets Registers"
- //
- // Read the first Interrupt Processor Targets Register (that corresponds to the 4
- // first SGIs)
- CpuTarget = MmioRead32 (mGicDistributorBase + ARM_GIC_ICDIPTR);
-
- // The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value
- // is 0 when we run on a uniprocessor platform.
- if (CpuTarget != 0) {
- // The 8 first Interrupt Processor Targets Registers are read-only
- for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {
- MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);
- }
- }
-
- // Set binary point reg to 0x7 (no preemption)
- MmioWrite32 (mGicInterruptInterfaceBase + ARM_GIC_ICCBPR, 0x7);
-
- // Set priority mask reg to 0xff to allow all priorities through
- MmioWrite32 (mGicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0xff);
-
- // Enable gic cpu interface
- ArmGicEnableInterruptInterface (mGicInterruptInterfaceBase);
-
- // Enable gic distributor
- ArmGicEnableDistributor (mGicDistributorBase);
-
- Status = InstallAndRegisterInterruptService (
- &gHardwareInterruptV2Protocol, GicV2IrqInterruptHandler, GicV2ExitBootServicesEvent);
-
- return Status;
-}
diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c deleted file mode 100644 index 5ac1d89ac5..0000000000 --- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c +++ /dev/null @@ -1,36 +0,0 @@ -/** @file
-*
-* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Library/ArmGicLib.h>
-#include <Library/IoLib.h>
-
-UINTN
-EFIAPI
-ArmGicV2AcknowledgeInterrupt (
- IN UINTN GicInterruptInterfaceBase
- )
-{
- // Read the Interrupt Acknowledge Register
- return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
-}
-
-VOID
-EFIAPI
-ArmGicV2EndOfInterrupt (
- IN UINTN GicInterruptInterfaceBase,
- IN UINTN Source
- )
-{
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, Source);
-}
diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c deleted file mode 100644 index 92b764f422..0000000000 --- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c +++ /dev/null @@ -1,42 +0,0 @@ -/** @file
-*
-* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Uefi.h>
-#include <Library/IoLib.h>
-#include <Library/ArmGicLib.h>
-
-
-VOID
-EFIAPI
-ArmGicV2EnableInterruptInterface (
- IN INTN GicInterruptInterfaceBase
- )
-{
- /*
- * Enable the CPU interface in Non-Secure world
- * Note: The ICCICR register is banked when Security extensions are implemented
- */
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x1);
-}
-
-VOID
-EFIAPI
-ArmGicV2DisableInterruptInterface (
- IN INTN GicInterruptInterfaceBase
- )
-{
- // Disable Gic Interface
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x0);
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x0);
-}
diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2SecLib.c b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2SecLib.c deleted file mode 100644 index ac1e0e4945..0000000000 --- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2SecLib.c +++ /dev/null @@ -1,100 +0,0 @@ -/** @file
-*
-* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Base.h>
-#include <Library/ArmLib.h>
-#include <Library/ArmPlatformLib.h>
-#include <Library/DebugLib.h>
-#include <Library/IoLib.h>
-#include <Library/ArmGicLib.h>
-
-/*
- * This function configures the all interrupts to be Non-secure.
- *
- */
-VOID
-EFIAPI
-ArmGicV2SetupNonSecure (
- IN UINTN MpId,
- IN INTN GicDistributorBase,
- IN INTN GicInterruptInterfaceBase
- )
-{
- UINTN InterruptId;
- UINTN CachedPriorityMask;
- UINTN Index;
- UINTN MaxInterrupts;
-
- CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);
-
- // Set priority Mask so that no interrupts get through to CPU
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);
-
- InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
- MaxInterrupts = ArmGicGetMaxNumInterrupts (GicDistributorBase);
-
- // Only try to clear valid interrupts. Ignore spurious interrupts.
- while ((InterruptId & 0x3FF) < MaxInterrupts) {
- // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
- ArmGicEndOfInterrupt (GicInterruptInterfaceBase, InterruptId);
-
- // Next
- InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
- }
-
- // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).
- if (ArmPlatformIsPrimaryCore (MpId)) {
- // Ensure all GIC interrupts are Non-Secure
- for (Index = 0; Index < (MaxInterrupts / 32); Index++) {
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);
- }
- } else {
- // The secondary cores only set the Non Secure bit to their banked PPIs
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);
- }
-
- // Ensure all interrupts can get through the priority mask
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);
-}
-
-VOID
-EFIAPI
-ArmGicV2EnableInterruptInterface (
- IN INTN GicInterruptInterfaceBase
- )
-{
- // Set Priority Mask to allow interrupts
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);
-
- // Enable CPU interface in Secure world
- // Enable CPU interface in Non-secure World
- // Signal Secure Interrupts to CPU using FIQ line *
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,
- ARM_GIC_ICCICR_ENABLE_SECURE |
- ARM_GIC_ICCICR_ENABLE_NS |
- ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);
-}
-
-VOID
-EFIAPI
-ArmGicV2DisableInterruptInterface (
- IN INTN GicInterruptInterfaceBase
- )
-{
- UINT32 ControlValue;
-
- // Disable CPU interface in Secure world and Non-secure World
- ControlValue = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR);
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, ControlValue & ~(ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_NS));
-}
|