diff options
Diffstat (limited to 'ArmPkg/Drivers/ArmGic')
| -rw-r--r-- | ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c | 141 | ||||
| -rw-r--r-- | ArmPkg/Drivers/ArmGic/ArmGicDxe.c | 59 | ||||
| -rw-r--r-- | ArmPkg/Drivers/ArmGic/ArmGicDxe.h | 67 | ||||
| -rw-r--r-- | ArmPkg/Drivers/ArmGic/ArmGicDxe.inf | 60 | ||||
| -rw-r--r-- | ArmPkg/Drivers/ArmGic/ArmGicLib.c | 311 | ||||
| -rw-r--r-- | ArmPkg/Drivers/ArmGic/ArmGicLib.inf | 51 | ||||
| -rw-r--r-- | ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c | 41 | ||||
| -rw-r--r-- | ArmPkg/Drivers/ArmGic/ArmGicSecLib.c | 64 | ||||
| -rw-r--r-- | ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf | 52 | ||||
| -rw-r--r-- | ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c | 318 | ||||
| -rw-r--r-- | ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c | 36 | ||||
| -rw-r--r-- | ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c | 42 | ||||
| -rw-r--r-- | ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2SecLib.c | 100 | ||||
| -rw-r--r-- | ArmPkg/Drivers/ArmGic/GicV3/AArch64/ArmGicV3.S | 124 | ||||
| -rw-r--r-- | ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S | 98 | ||||
| -rw-r--r-- | ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm | 96 | ||||
| -rw-r--r-- | ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 322 |
17 files changed, 0 insertions, 1982 deletions
diff --git a/ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c b/ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c deleted file mode 100644 index a9ccef5e1c..0000000000 --- a/ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c +++ /dev/null @@ -1,141 +0,0 @@ -/*++
-
-Copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR>
-
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
---*/
-
-#include "ArmGicDxe.h"
-
-VOID
-EFIAPI
-IrqInterruptHandler (
- IN EFI_EXCEPTION_TYPE InterruptType,
- IN EFI_SYSTEM_CONTEXT SystemContext
- );
-
-VOID
-EFIAPI
-ExitBootServicesEvent (
- IN EFI_EVENT Event,
- IN VOID *Context
- );
-
-//
-// Making this global saves a few bytes in image size
-//
-EFI_HANDLE gHardwareInterruptHandle = NULL;
-
-//
-// Notifications
-//
-EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
-
-// Maximum Number of Interrupts
-UINTN mGicNumInterrupts = 0;
-
-HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers = NULL;
-
-/**
- Register Handler for the specified interrupt source.
-
- @param This Instance pointer for this protocol
- @param Source Hardware source of the interrupt
- @param Handler Callback for interrupt. NULL to unregister
-
- @retval EFI_SUCCESS Source was updated to support Handler.
- @retval EFI_DEVICE_ERROR Hardware could not be programmed.
-
-**/
-EFI_STATUS
-EFIAPI
-RegisterInterruptSource (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source,
- IN HARDWARE_INTERRUPT_HANDLER Handler
- )
-{
- if (Source > mGicNumInterrupts) {
- ASSERT(FALSE);
- return EFI_UNSUPPORTED;
- }
-
- if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {
- return EFI_INVALID_PARAMETER;
- }
-
- if ((Handler != NULL) && (gRegisteredInterruptHandlers[Source] != NULL)) {
- return EFI_ALREADY_STARTED;
- }
-
- gRegisteredInterruptHandlers[Source] = Handler;
-
- // If the interrupt handler is unregistered then disable the interrupt
- if (NULL == Handler){
- return This->DisableInterruptSource (This, Source);
- } else {
- return This->EnableInterruptSource (This, Source);
- }
-}
-
-EFI_STATUS
-InstallAndRegisterInterruptService (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *InterruptProtocol,
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler,
- IN EFI_EVENT_NOTIFY ExitBootServicesEvent
- )
-{
- EFI_STATUS Status;
- EFI_CPU_ARCH_PROTOCOL *Cpu;
-
- // Initialize the array for the Interrupt Handlers
- gRegisteredInterruptHandlers = (HARDWARE_INTERRUPT_HANDLER*)AllocateZeroPool (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);
- if (gRegisteredInterruptHandlers == NULL) {
- return EFI_OUT_OF_RESOURCES;
- }
-
- Status = gBS->InstallMultipleProtocolInterfaces (
- &gHardwareInterruptHandle,
- &gHardwareInterruptProtocolGuid, InterruptProtocol,
- NULL
- );
- if (EFI_ERROR (Status)) {
- return Status;
- }
-
- //
- // Get the CPU protocol that this driver requires.
- //
- Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
- if (EFI_ERROR (Status)) {
- return Status;
- }
-
- //
- // Unregister the default exception handler.
- //
- Status = Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ, NULL);
- if (EFI_ERROR (Status)) {
- return Status;
- }
-
- //
- // Register to receive interrupts
- //
- Status = Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ, InterruptHandler);
- if (EFI_ERROR (Status)) {
- return Status;
- }
-
- // Register for an ExitBootServicesEvent
- Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);
-
- return Status;
-}
diff --git a/ArmPkg/Drivers/ArmGic/ArmGicDxe.c b/ArmPkg/Drivers/ArmGic/ArmGicDxe.c deleted file mode 100644 index 2bb064f89a..0000000000 --- a/ArmPkg/Drivers/ArmGic/ArmGicDxe.c +++ /dev/null @@ -1,59 +0,0 @@ -/*++
-
-Copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR>
-
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-Module Name:
-
- ArmGicDxe.c
-
-Abstract:
-
- Driver implementing the GIC interrupt controller protocol
-
---*/
-
-#include <PiDxe.h>
-
-#include "ArmGicDxe.h"
-
-/**
- Initialize the state information for the CPU Architectural Protocol
-
- @param ImageHandle of the loaded driver
- @param SystemTable Pointer to the System Table
-
- @retval EFI_SUCCESS Protocol registered
- @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
- @retval EFI_DEVICE_ERROR Hardware problems
- @retval EFI_UNSUPPORTED GIC version not supported
-
-**/
-EFI_STATUS
-InterruptDxeInitialize (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- )
-{
- EFI_STATUS Status;
- ARM_GIC_ARCH_REVISION Revision;
-
- Revision = ArmGicGetSupportedArchRevision ();
-
- if (Revision == ARM_GIC_ARCH_REVISION_2) {
- Status = GicV2DxeInitialize (ImageHandle, SystemTable);
- } else if (Revision == ARM_GIC_ARCH_REVISION_3) {
- Status = GicV3DxeInitialize (ImageHandle, SystemTable);
- } else {
- Status = EFI_UNSUPPORTED;
- }
-
- return Status;
-}
diff --git a/ArmPkg/Drivers/ArmGic/ArmGicDxe.h b/ArmPkg/Drivers/ArmGic/ArmGicDxe.h deleted file mode 100644 index af33aa90b0..0000000000 --- a/ArmPkg/Drivers/ArmGic/ArmGicDxe.h +++ /dev/null @@ -1,67 +0,0 @@ -/*++
-
-Copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR>
-
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
---*/
-
-#ifndef __ARM_GIC_DXE_H__
-#define __ARM_GIC_DXE_H__
-
-#include <Library/ArmGicLib.h>
-#include <Library/ArmLib.h>
-#include <Library/DebugLib.h>
-#include <Library/IoLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-
-#include <Protocol/Cpu.h>
-#include <Protocol/HardwareInterrupt.h>
-
-extern UINTN mGicNumInterrupts;
-extern HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers;
-
-//
-// Common API
-//
-EFI_STATUS
-InstallAndRegisterInterruptService (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *InterruptProtocol,
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler,
- IN EFI_EVENT_NOTIFY ExitBootServicesEvent
- );
-
-EFI_STATUS
-EFIAPI
-RegisterInterruptSource (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source,
- IN HARDWARE_INTERRUPT_HANDLER Handler
- );
-
-//
-// GicV2 API
-//
-EFI_STATUS
-GicV2DxeInitialize (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- );
-
-//
-// GicV3 API
-//
-EFI_STATUS
-GicV3DxeInitialize (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- );
-
-#endif
diff --git a/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf b/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf deleted file mode 100644 index e554301c4b..0000000000 --- a/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf +++ /dev/null @@ -1,60 +0,0 @@ -#/** @file
-#
-# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-# Copyright (c) 2012 - 2015, ARM Ltd. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = ArmGicDxe
- FILE_GUID = DE371F7C-DEC4-4D21-ADF1-593ABCC15882
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
-
- ENTRY_POINT = InterruptDxeInitialize
-
-[Sources.common]
- ArmGicDxe.c
- ArmGicCommonDxe.c
-
- GicV2/ArmGicV2Dxe.c
- GicV3/ArmGicV3Dxe.c
-
-[Packages]
- MdePkg/MdePkg.dec
- EmbeddedPkg/EmbeddedPkg.dec
- ArmPkg/ArmPkg.dec
-
-[LibraryClasses]
- ArmGicLib
- BaseLib
- UefiLib
- UefiBootServicesTableLib
- DebugLib
- PrintLib
- MemoryAllocationLib
- UefiDriverEntryPoint
- IoLib
- PcdLib
-
-[Protocols]
- gHardwareInterruptProtocolGuid
- gEfiCpuArchProtocolGuid
-
-[Pcd.common]
- gArmTokenSpaceGuid.PcdGicDistributorBase
- gArmTokenSpaceGuid.PcdGicRedistributorsBase
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
- gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy
-
-[Depex]
- gEfiCpuArchProtocolGuid
diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmGicLib.c deleted file mode 100644 index 248e896c4b..0000000000 --- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c +++ /dev/null @@ -1,311 +0,0 @@ -/** @file
-*
-* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Base.h>
-#include <Library/ArmGicLib.h>
-#include <Library/ArmLib.h>
-#include <Library/DebugLib.h>
-#include <Library/IoLib.h>
-#include <Library/PcdLib.h>
-
-/**
- * Return the base address of the GIC redistributor for the current CPU
- *
- * @param Revision GIC Revision. The GIC redistributor might have a different
- * granularity following the GIC revision.
- *
- * @retval Base address of the associated GIC Redistributor
- */
-STATIC
-UINTN
-GicGetCpuRedistributorBase (
- IN UINTN GicRedistributorBase,
- IN ARM_GIC_ARCH_REVISION Revision
- )
-{
- UINTN Index;
- UINTN MpId;
- UINTN CpuAffinity;
- UINTN Affinity;
- UINTN GicRedistributorGranularity;
- UINTN GicCpuRedistributorBase;
-
- MpId = ArmReadMpidr ();
- // Define CPU affinity as Affinity0[0:8], Affinity1[9:15], Affinity2[16:23], Affinity3[24:32]
- // whereas Affinity3 is defined at [32:39] in MPIDR
- CpuAffinity = (MpId & (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2)) | ((MpId & ARM_CORE_AFF3) >> 8);
-
- if (Revision == ARM_GIC_ARCH_REVISION_3) {
- // 2 x 64KB frame: Redistributor control frame + SGI Control & Generation frame
- GicRedistributorGranularity = ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_SGI_PPI_FRAME_SIZE;
- } else {
- ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
- return 0;
- }
-
- GicCpuRedistributorBase = GicRedistributorBase;
-
- for (Index = 0; Index < PcdGet32 (PcdCoreCount); Index++) {
- Affinity = MmioRead64 (GicCpuRedistributorBase + ARM_GICR_TYPER) >> 32;
- if (Affinity == CpuAffinity) {
- return GicCpuRedistributorBase;
- }
-
- // Move to the next GIC Redistributor frame
- GicRedistributorBase += GicRedistributorGranularity;
- }
-
- // The Redistributor has not been found for the current CPU
- ASSERT_EFI_ERROR (EFI_NOT_FOUND);
- return 0;
-}
-
-UINTN
-EFIAPI
-ArmGicGetInterfaceIdentification (
- IN INTN GicInterruptInterfaceBase
- )
-{
- // Read the GIC Identification Register
- return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIIDR);
-}
-
-UINTN
-EFIAPI
-ArmGicGetMaxNumInterrupts (
- IN INTN GicDistributorBase
- )
-{
- return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1);
-}
-
-VOID
-EFIAPI
-ArmGicSendSgiTo (
- IN INTN GicDistributorBase,
- IN INTN TargetListFilter,
- IN INTN CPUTargetList,
- IN INTN SgiId
- )
-{
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId);
-}
-
-/*
- * Acknowledge and return the value of the Interrupt Acknowledge Register
- *
- * InterruptId is returned separately from the register value because in
- * the GICv2 the register value contains the CpuId and InterruptId while
- * in the GICv3 the register value is only the InterruptId.
- *
- * @param GicInterruptInterfaceBase Base Address of the GIC CPU Interface
- * @param InterruptId InterruptId read from the Interrupt Acknowledge Register
- *
- * @retval value returned by the Interrupt Acknowledge Register
- *
- */
-UINTN
-EFIAPI
-ArmGicAcknowledgeInterrupt (
- IN UINTN GicInterruptInterfaceBase,
- OUT UINTN *InterruptId
- )
-{
- UINTN Value;
- ARM_GIC_ARCH_REVISION Revision;
-
- Revision = ArmGicGetSupportedArchRevision ();
- if (Revision == ARM_GIC_ARCH_REVISION_2) {
- Value = ArmGicV2AcknowledgeInterrupt (GicInterruptInterfaceBase);
- // InterruptId is required for the caller to know if a valid or spurious
- // interrupt has been read
- ASSERT (InterruptId != NULL);
- if (InterruptId != NULL) {
- *InterruptId = Value & ARM_GIC_ICCIAR_ACKINTID;
- }
- } else if (Revision == ARM_GIC_ARCH_REVISION_3) {
- Value = ArmGicV3AcknowledgeInterrupt ();
- } else {
- ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
- // Report Spurious interrupt which is what the above controllers would
- // return if no interrupt was available
- Value = 1023;
- }
-
- return Value;
-}
-
-VOID
-EFIAPI
-ArmGicEndOfInterrupt (
- IN UINTN GicInterruptInterfaceBase,
- IN UINTN Source
- )
-{
- ARM_GIC_ARCH_REVISION Revision;
-
- Revision = ArmGicGetSupportedArchRevision ();
- if (Revision == ARM_GIC_ARCH_REVISION_2) {
- ArmGicV2EndOfInterrupt (GicInterruptInterfaceBase, Source);
- } else if (Revision == ARM_GIC_ARCH_REVISION_3) {
- ArmGicV3EndOfInterrupt (Source);
- } else {
- ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
- }
-}
-
-VOID
-EFIAPI
-ArmGicEnableInterrupt (
- IN UINTN GicDistributorBase,
- IN UINTN GicRedistributorBase,
- IN UINTN Source
- )
-{
- UINT32 RegOffset;
- UINTN RegShift;
- ARM_GIC_ARCH_REVISION Revision;
- UINTN GicCpuRedistributorBase;
-
- // Calculate enable register offset and bit position
- RegOffset = Source / 32;
- RegShift = Source % 32;
-
- Revision = ArmGicGetSupportedArchRevision ();
- if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {
- // Write set-enable register
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), 1 << RegShift);
- } else {
- GicCpuRedistributorBase = GicGetCpuRedistributorBase (GicRedistributorBase, Revision);
- if (GicCpuRedistributorBase == 0) {
- ASSERT_EFI_ERROR (EFI_NOT_FOUND);
- return;
- }
-
- // Write set-enable register
- MmioWrite32 (GicCpuRedistributorBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + (4 * RegOffset), 1 << RegShift);
- }
-}
-
-VOID
-EFIAPI
-ArmGicDisableInterrupt (
- IN UINTN GicDistributorBase,
- IN UINTN GicRedistributorBase,
- IN UINTN Source
- )
-{
- UINT32 RegOffset;
- UINTN RegShift;
- ARM_GIC_ARCH_REVISION Revision;
- UINTN GicCpuRedistributorBase;
-
- // Calculate enable register offset and bit position
- RegOffset = Source / 32;
- RegShift = Source % 32;
-
- Revision = ArmGicGetSupportedArchRevision ();
- if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {
- // Write clear-enable register
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), 1 << RegShift);
- } else {
- GicCpuRedistributorBase = GicGetCpuRedistributorBase (GicRedistributorBase, Revision);
- if (GicCpuRedistributorBase == 0) {
- return;
- }
-
- // Write clear-enable register
- MmioWrite32 (GicCpuRedistributorBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ICENABLER + (4 * RegOffset), 1 << RegShift);
- }
-}
-
-BOOLEAN
-EFIAPI
-ArmGicIsInterruptEnabled (
- IN UINTN GicDistributorBase,
- IN UINTN GicRedistributorBase,
- IN UINTN Source
- )
-{
- UINT32 RegOffset;
- UINTN RegShift;
- ARM_GIC_ARCH_REVISION Revision;
- UINTN GicCpuRedistributorBase;
- UINT32 Interrupts;
-
- // Calculate enable register offset and bit position
- RegOffset = Source / 32;
- RegShift = Source % 32;
-
- Revision = ArmGicGetSupportedArchRevision ();
- if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {
- Interrupts = ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)) & (1 << RegShift)) != 0);
- } else {
- GicCpuRedistributorBase = GicGetCpuRedistributorBase (GicRedistributorBase, Revision);
- if (GicCpuRedistributorBase == 0) {
- return 0;
- }
-
- // Read set-enable register
- Interrupts = MmioRead32 (GicCpuRedistributorBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + (4 * RegOffset));
- }
-
- return ((Interrupts & (1 << RegShift)) != 0);
-}
-
-VOID
-EFIAPI
-ArmGicDisableDistributor (
- IN INTN GicDistributorBase
- )
-{
- // Disable Gic Distributor
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x0);
-}
-
-VOID
-EFIAPI
-ArmGicEnableInterruptInterface (
- IN INTN GicInterruptInterfaceBase
- )
-{
- ARM_GIC_ARCH_REVISION Revision;
-
- Revision = ArmGicGetSupportedArchRevision ();
- if (Revision == ARM_GIC_ARCH_REVISION_2) {
- ArmGicV2EnableInterruptInterface (GicInterruptInterfaceBase);
- } else if (Revision == ARM_GIC_ARCH_REVISION_3) {
- ArmGicV3EnableInterruptInterface ();
- } else {
- ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
- }
-}
-
-VOID
-EFIAPI
-ArmGicDisableInterruptInterface (
- IN INTN GicInterruptInterfaceBase
- )
-{
- ARM_GIC_ARCH_REVISION Revision;
-
- Revision = ArmGicGetSupportedArchRevision ();
- if (Revision == ARM_GIC_ARCH_REVISION_2) {
- ArmGicV2DisableInterruptInterface (GicInterruptInterfaceBase);
- } else if (Revision == ARM_GIC_ARCH_REVISION_3) {
- ArmGicV3DisableInterruptInterface ();
- } else {
- ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
- }
-}
diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.inf b/ArmPkg/Drivers/ArmGic/ArmGicLib.inf deleted file mode 100644 index 047adac85f..0000000000 --- a/ArmPkg/Drivers/ArmGic/ArmGicLib.inf +++ /dev/null @@ -1,51 +0,0 @@ -#/* @file
-# Copyright (c) 2011-2015, ARM Limited. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#*/
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = ArmGicLib
- FILE_GUID = 03d05ee4-cdeb-458c-9dfc-993f09bdf405
- MODULE_TYPE = SEC
- VERSION_STRING = 1.0
- LIBRARY_CLASS = ArmGicLib
-
-[Sources]
- ArmGicLib.c
- ArmGicNonSecLib.c
-
- GicV2/ArmGicV2Lib.c
- GicV2/ArmGicV2NonSecLib.c
-
-[Sources.ARM]
- GicV3/Arm/ArmGicV3.S | GCC
- GicV3/Arm/ArmGicV3.asm | RVCT
-
-[Sources.AARCH64]
- GicV3/AArch64/ArmGicV3.S
-
-[LibraryClasses]
- ArmLib
- DebugLib
- IoLib
- ArmGicArchLib
-
-[Packages]
- ArmPkg/ArmPkg.dec
- ArmPlatformPkg/ArmPlatformPkg.dec
- MdePkg/MdePkg.dec
-
-[Pcd]
- gArmPlatformTokenSpaceGuid.PcdCoreCount
-
-[FeaturePcd]
- gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy
diff --git a/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c b/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c deleted file mode 100644 index 31572438d9..0000000000 --- a/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c +++ /dev/null @@ -1,41 +0,0 @@ -/** @file
-*
-* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Uefi.h>
-#include <Library/IoLib.h>
-#include <Library/ArmGicLib.h>
-
-VOID
-EFIAPI
-ArmGicEnableDistributor (
- IN INTN GicDistributorBase
- )
-{
- ARM_GIC_ARCH_REVISION Revision;
-
- /*
- * Enable GIC distributor in Non-Secure world.
- * Note: The ICDDCR register is banked when Security extensions are implemented
- */
- Revision = ArmGicGetSupportedArchRevision ();
- if (Revision == ARM_GIC_ARCH_REVISION_2) {
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x1);
- } else {
- if (MmioRead32 (GicDistributorBase + ARM_GIC_ICDDCR) & ARM_GIC_ICDDCR_ARE) {
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x2);
- } else {
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x1);
- }
- }
-}
diff --git a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.c b/ArmPkg/Drivers/ArmGic/ArmGicSecLib.c deleted file mode 100644 index d64806d2f1..0000000000 --- a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.c +++ /dev/null @@ -1,64 +0,0 @@ -/** @file
-*
-* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Base.h>
-#include <Library/DebugLib.h>
-#include <Library/IoLib.h>
-#include <Library/ArmGicLib.h>
-
-/*
- * This function configures the interrupts set by the mask to be secure.
- *
- */
-VOID
-EFIAPI
-ArmGicSetSecureInterrupts (
- IN UINTN GicDistributorBase,
- IN UINTN* GicSecureInterruptMask,
- IN UINTN GicSecureInterruptMaskSize
- )
-{
- UINTN Index;
- UINT32 InterruptStatus;
-
- // We must not have more interrupts defined by the mask than the number of available interrupts
- ASSERT(GicSecureInterruptMaskSize <= (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32));
-
- // Set all the interrupts defined by the mask as Secure
- for (Index = 0; Index < GicSecureInterruptMaskSize; Index++) {
- InterruptStatus = MmioRead32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4));
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), InterruptStatus & (~GicSecureInterruptMask[Index]));
- }
-}
-
-VOID
-EFIAPI
-ArmGicEnableDistributor (
- IN INTN GicDistributorBase
- )
-{
- // Turn on the GIC distributor
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1);
-}
-
-VOID
-EFIAPI
-ArmGicSetupNonSecure (
- IN UINTN MpId,
- IN INTN GicDistributorBase,
- IN INTN GicInterruptInterfaceBase
- )
-{
- ArmGicV2SetupNonSecure (MpId, GicDistributorBase, GicInterruptInterfaceBase);
-}
diff --git a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf b/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf deleted file mode 100644 index fc2e1bc01e..0000000000 --- a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf +++ /dev/null @@ -1,52 +0,0 @@ -#/* @file
-# Copyright (c) 2011-2015, ARM Limited. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#*/
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = ArmGicSecLib
- FILE_GUID = 85f3cf80-b5f4-11df-9855-0002a5d5c51b
- MODULE_TYPE = SEC
- VERSION_STRING = 1.0
- LIBRARY_CLASS = ArmGicLib
-
-[Sources]
- ArmGicLib.c
- ArmGicSecLib.c
-
- GicV2/ArmGicV2Lib.c
- GicV2/ArmGicV2SecLib.c
-
-[Sources.ARM]
- GicV3/Arm/ArmGicV3.S | GCC
- GicV3/Arm/ArmGicV3.asm | RVCT
-
-[Sources.AARCH64]
- GicV3/AArch64/ArmGicV3.S
-
-[Packages]
- ArmPkg/ArmPkg.dec
- ArmPlatformPkg/ArmPlatformPkg.dec
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
-
-[LibraryClasses]
- ArmLib
- DebugLib
- IoLib
- ArmGicArchLib
-
-[Pcd]
- gArmPlatformTokenSpaceGuid.PcdCoreCount
-
-[FeaturePcd]
- gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy
diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c deleted file mode 100644 index e649ac1bc6..0000000000 --- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c +++ /dev/null @@ -1,318 +0,0 @@ -/*++
-
-Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
-Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
-Portions copyright (c) 2011-2015, ARM Ltd. All rights reserved.<BR>
-
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-Module Name:
-
- GicV2/ArmGicV2Dxe.c
-
-Abstract:
-
- Driver implementing the GicV2 interrupt controller protocol
-
---*/
-
-#include <Library/ArmGicLib.h>
-
-#include "ArmGicDxe.h"
-
-#define ARM_GIC_DEFAULT_PRIORITY 0x80
-
-extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol;
-
-STATIC UINT32 mGicInterruptInterfaceBase;
-STATIC UINT32 mGicDistributorBase;
-
-/**
- Enable interrupt source Source.
-
- @param This Instance pointer for this protocol
- @param Source Hardware source of the interrupt
-
- @retval EFI_SUCCESS Source interrupt enabled.
- @retval EFI_UNSUPPORTED Source interrupt is not supported
-
-**/
-EFI_STATUS
-EFIAPI
-GicV2EnableInterruptSource (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source
- )
-{
- if (Source > mGicNumInterrupts) {
- ASSERT(FALSE);
- return EFI_UNSUPPORTED;
- }
-
- ArmGicEnableInterrupt (mGicDistributorBase, 0, Source);
-
- return EFI_SUCCESS;
-}
-
-/**
- Disable interrupt source Source.
-
- @param This Instance pointer for this protocol
- @param Source Hardware source of the interrupt
-
- @retval EFI_SUCCESS Source interrupt disabled.
- @retval EFI_UNSUPPORTED Source interrupt is not supported
-
-**/
-EFI_STATUS
-EFIAPI
-GicV2DisableInterruptSource (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source
- )
-{
- if (Source > mGicNumInterrupts) {
- ASSERT(FALSE);
- return EFI_UNSUPPORTED;
- }
-
- ArmGicDisableInterrupt (mGicDistributorBase, 0, Source);
-
- return EFI_SUCCESS;
-}
-
-/**
- Return current state of interrupt source Source.
-
- @param This Instance pointer for this protocol
- @param Source Hardware source of the interrupt
- @param InterruptState TRUE: source enabled, FALSE: source disabled.
-
- @retval EFI_SUCCESS InterruptState is valid
- @retval EFI_UNSUPPORTED Source interrupt is not supported
-
-**/
-EFI_STATUS
-EFIAPI
-GicV2GetInterruptSourceState (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source,
- IN BOOLEAN *InterruptState
- )
-{
- if (Source > mGicNumInterrupts) {
- ASSERT(FALSE);
- return EFI_UNSUPPORTED;
- }
-
- *InterruptState = ArmGicIsInterruptEnabled (mGicDistributorBase, 0, Source);
-
- return EFI_SUCCESS;
-}
-
-/**
- Signal to the hardware that the End Of Interrupt state
- has been reached.
-
- @param This Instance pointer for this protocol
- @param Source Hardware source of the interrupt
-
- @retval EFI_SUCCESS Source interrupt EOI'ed.
- @retval EFI_UNSUPPORTED Source interrupt is not supported
-
-**/
-EFI_STATUS
-EFIAPI
-GicV2EndOfInterrupt (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source
- )
-{
- if (Source > mGicNumInterrupts) {
- ASSERT(FALSE);
- return EFI_UNSUPPORTED;
- }
-
- ArmGicV2EndOfInterrupt (mGicInterruptInterfaceBase, Source);
- return EFI_SUCCESS;
-}
-
-/**
- EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.
-
- @param InterruptType Defines the type of interrupt or exception that
- occurred on the processor.This parameter is processor architecture specific.
- @param SystemContext A pointer to the processor context when
- the interrupt occurred on the processor.
-
- @return None
-
-**/
-VOID
-EFIAPI
-GicV2IrqInterruptHandler (
- IN EFI_EXCEPTION_TYPE InterruptType,
- IN EFI_SYSTEM_CONTEXT SystemContext
- )
-{
- UINT32 GicInterrupt;
- HARDWARE_INTERRUPT_HANDLER InterruptHandler;
-
- GicInterrupt = ArmGicV2AcknowledgeInterrupt (mGicInterruptInterfaceBase);
-
- // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the number of interrupt (ie: Spurious interrupt).
- if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) >= mGicNumInterrupts) {
- // The special interrupt do not need to be acknowledge
- return;
- }
-
- InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt];
- if (InterruptHandler != NULL) {
- // Call the registered interrupt handler.
- InterruptHandler (GicInterrupt, SystemContext);
- } else {
- DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));
- }
-
- GicV2EndOfInterrupt (&gHardwareInterruptV2Protocol, GicInterrupt);
-}
-
-//
-// The protocol instance produced by this driver
-//
-EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol = {
- RegisterInterruptSource,
- GicV2EnableInterruptSource,
- GicV2DisableInterruptSource,
- GicV2GetInterruptSourceState,
- GicV2EndOfInterrupt
-};
-
-/**
- Shutdown our hardware
-
- DXE Core will disable interrupts and turn off the timer and disable interrupts
- after all the event handlers have run.
-
- @param[in] Event The Event that is being processed
- @param[in] Context Event Context
-**/
-VOID
-EFIAPI
-GicV2ExitBootServicesEvent (
- IN EFI_EVENT Event,
- IN VOID *Context
- )
-{
- UINTN Index;
- UINT32 GicInterrupt;
-
- // Disable all the interrupts
- for (Index = 0; Index < mGicNumInterrupts; Index++) {
- GicV2DisableInterruptSource (&gHardwareInterruptV2Protocol, Index);
- }
-
- // Acknowledge all pending interrupts
- do {
- GicInterrupt = ArmGicV2AcknowledgeInterrupt (mGicInterruptInterfaceBase);
-
- if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) < mGicNumInterrupts) {
- GicV2EndOfInterrupt (&gHardwareInterruptV2Protocol, GicInterrupt);
- }
- } while (!ARM_GIC_IS_SPECIAL_INTERRUPTS (GicInterrupt));
-
- // Disable Gic Interface
- ArmGicV2DisableInterruptInterface (mGicInterruptInterfaceBase);
-
- // Disable Gic Distributor
- ArmGicDisableDistributor (mGicDistributorBase);
-}
-
-/**
- Initialize the state information for the CPU Architectural Protocol
-
- @param ImageHandle of the loaded driver
- @param SystemTable Pointer to the System Table
-
- @retval EFI_SUCCESS Protocol registered
- @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
- @retval EFI_DEVICE_ERROR Hardware problems
-
-**/
-EFI_STATUS
-GicV2DxeInitialize (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- )
-{
- EFI_STATUS Status;
- UINTN Index;
- UINT32 RegOffset;
- UINTN RegShift;
- UINT32 CpuTarget;
-
- // Make sure the Interrupt Controller Protocol is not already installed in the system.
- ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
-
- mGicInterruptInterfaceBase = PcdGet32 (PcdGicInterruptInterfaceBase);
- mGicDistributorBase = PcdGet32 (PcdGicDistributorBase);
- mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase);
-
- for (Index = 0; Index < mGicNumInterrupts; Index++) {
- GicV2DisableInterruptSource (&gHardwareInterruptV2Protocol, Index);
-
- // Set Priority
- RegOffset = Index / 4;
- RegShift = (Index % 4) * 8;
- MmioAndThenOr32 (
- mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
- ~(0xff << RegShift),
- ARM_GIC_DEFAULT_PRIORITY << RegShift
- );
- }
-
- //
- // Targets the interrupts to the Primary Cpu
- //
-
- // Only Primary CPU will run this code. We can identify our GIC CPU ID by reading
- // the GIC Distributor Target register. The 8 first GICD_ITARGETSRn are banked to each
- // connected CPU. These 8 registers hold the CPU targets fields for interrupts 0-31.
- // More Info in the GIC Specification about "Interrupt Processor Targets Registers"
- //
- // Read the first Interrupt Processor Targets Register (that corresponds to the 4
- // first SGIs)
- CpuTarget = MmioRead32 (mGicDistributorBase + ARM_GIC_ICDIPTR);
-
- // The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value
- // is 0 when we run on a uniprocessor platform.
- if (CpuTarget != 0) {
- // The 8 first Interrupt Processor Targets Registers are read-only
- for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {
- MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);
- }
- }
-
- // Set binary point reg to 0x7 (no preemption)
- MmioWrite32 (mGicInterruptInterfaceBase + ARM_GIC_ICCBPR, 0x7);
-
- // Set priority mask reg to 0xff to allow all priorities through
- MmioWrite32 (mGicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0xff);
-
- // Enable gic cpu interface
- ArmGicEnableInterruptInterface (mGicInterruptInterfaceBase);
-
- // Enable gic distributor
- ArmGicEnableDistributor (mGicDistributorBase);
-
- Status = InstallAndRegisterInterruptService (
- &gHardwareInterruptV2Protocol, GicV2IrqInterruptHandler, GicV2ExitBootServicesEvent);
-
- return Status;
-}
diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c deleted file mode 100644 index 5ac1d89ac5..0000000000 --- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c +++ /dev/null @@ -1,36 +0,0 @@ -/** @file
-*
-* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Library/ArmGicLib.h>
-#include <Library/IoLib.h>
-
-UINTN
-EFIAPI
-ArmGicV2AcknowledgeInterrupt (
- IN UINTN GicInterruptInterfaceBase
- )
-{
- // Read the Interrupt Acknowledge Register
- return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
-}
-
-VOID
-EFIAPI
-ArmGicV2EndOfInterrupt (
- IN UINTN GicInterruptInterfaceBase,
- IN UINTN Source
- )
-{
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, Source);
-}
diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c deleted file mode 100644 index 92b764f422..0000000000 --- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c +++ /dev/null @@ -1,42 +0,0 @@ -/** @file
-*
-* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Uefi.h>
-#include <Library/IoLib.h>
-#include <Library/ArmGicLib.h>
-
-
-VOID
-EFIAPI
-ArmGicV2EnableInterruptInterface (
- IN INTN GicInterruptInterfaceBase
- )
-{
- /*
- * Enable the CPU interface in Non-Secure world
- * Note: The ICCICR register is banked when Security extensions are implemented
- */
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x1);
-}
-
-VOID
-EFIAPI
-ArmGicV2DisableInterruptInterface (
- IN INTN GicInterruptInterfaceBase
- )
-{
- // Disable Gic Interface
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x0);
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x0);
-}
diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2SecLib.c b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2SecLib.c deleted file mode 100644 index ac1e0e4945..0000000000 --- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2SecLib.c +++ /dev/null @@ -1,100 +0,0 @@ -/** @file
-*
-* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Base.h>
-#include <Library/ArmLib.h>
-#include <Library/ArmPlatformLib.h>
-#include <Library/DebugLib.h>
-#include <Library/IoLib.h>
-#include <Library/ArmGicLib.h>
-
-/*
- * This function configures the all interrupts to be Non-secure.
- *
- */
-VOID
-EFIAPI
-ArmGicV2SetupNonSecure (
- IN UINTN MpId,
- IN INTN GicDistributorBase,
- IN INTN GicInterruptInterfaceBase
- )
-{
- UINTN InterruptId;
- UINTN CachedPriorityMask;
- UINTN Index;
- UINTN MaxInterrupts;
-
- CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);
-
- // Set priority Mask so that no interrupts get through to CPU
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);
-
- InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
- MaxInterrupts = ArmGicGetMaxNumInterrupts (GicDistributorBase);
-
- // Only try to clear valid interrupts. Ignore spurious interrupts.
- while ((InterruptId & 0x3FF) < MaxInterrupts) {
- // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
- ArmGicEndOfInterrupt (GicInterruptInterfaceBase, InterruptId);
-
- // Next
- InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
- }
-
- // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).
- if (ArmPlatformIsPrimaryCore (MpId)) {
- // Ensure all GIC interrupts are Non-Secure
- for (Index = 0; Index < (MaxInterrupts / 32); Index++) {
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);
- }
- } else {
- // The secondary cores only set the Non Secure bit to their banked PPIs
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);
- }
-
- // Ensure all interrupts can get through the priority mask
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);
-}
-
-VOID
-EFIAPI
-ArmGicV2EnableInterruptInterface (
- IN INTN GicInterruptInterfaceBase
- )
-{
- // Set Priority Mask to allow interrupts
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);
-
- // Enable CPU interface in Secure world
- // Enable CPU interface in Non-secure World
- // Signal Secure Interrupts to CPU using FIQ line *
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,
- ARM_GIC_ICCICR_ENABLE_SECURE |
- ARM_GIC_ICCICR_ENABLE_NS |
- ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);
-}
-
-VOID
-EFIAPI
-ArmGicV2DisableInterruptInterface (
- IN INTN GicInterruptInterfaceBase
- )
-{
- UINT32 ControlValue;
-
- // Disable CPU interface in Secure world and Non-secure World
- ControlValue = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR);
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, ControlValue & ~(ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_NS));
-}
diff --git a/ArmPkg/Drivers/ArmGic/GicV3/AArch64/ArmGicV3.S b/ArmPkg/Drivers/ArmGic/GicV3/AArch64/ArmGicV3.S deleted file mode 100644 index f1c227f2c4..0000000000 --- a/ArmPkg/Drivers/ArmGic/GicV3/AArch64/ArmGicV3.S +++ /dev/null @@ -1,124 +0,0 @@ -#
-# Copyright (c) 2014, ARM Limited. All rights reserved.
-#
-# This program and the accompanying materials are licensed and made available
-# under the terms and conditions of the BSD License which accompanies this
-# distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#
-
-#include <AsmMacroIoLibV8.h>
-
-#if !defined(__clang__)
-
-//
-// Clang versions before v3.6 do not support the GNU extension that allows
-// system registers outside of the IMPLEMENTATION DEFINED range to be specified
-// using the generic notation below. However, clang knows these registers by
-// their architectural names, so it has no need for these aliases anyway.
-//
-#define ICC_SRE_EL1 S3_0_C12_C12_5
-#define ICC_SRE_EL2 S3_4_C12_C9_5
-#define ICC_SRE_EL3 S3_6_C12_C12_5
-#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
-#define ICC_EOIR1_EL1 S3_0_C12_C12_1
-#define ICC_IAR1_EL1 S3_0_C12_C12_0
-#define ICC_PMR_EL1 S3_0_C4_C6_0
-#define ICC_BPR1_EL1 S3_0_C12_C12_3
-
-#endif
-
-.text
-.align 2
-
-GCC_ASM_EXPORT(ArmGicV3GetControlSystemRegisterEnable)
-GCC_ASM_EXPORT(ArmGicV3SetControlSystemRegisterEnable)
-GCC_ASM_EXPORT(ArmGicV3EnableInterruptInterface)
-GCC_ASM_EXPORT(ArmGicV3DisableInterruptInterface)
-GCC_ASM_EXPORT(ArmGicV3EndOfInterrupt)
-GCC_ASM_EXPORT(ArmGicV3AcknowledgeInterrupt)
-GCC_ASM_EXPORT(ArmGicV3SetPriorityMask)
-GCC_ASM_EXPORT(ArmGicV3SetBinaryPointer)
-
-//UINT32
-//EFIAPI
-//ArmGicV3GetControlSystemRegisterEnable (
-// VOID
-// );
-ASM_PFX(ArmGicV3GetControlSystemRegisterEnable):
- EL1_OR_EL2_OR_EL3(x1)
-1: mrs x0, ICC_SRE_EL1
- b 4f
-2: mrs x0, ICC_SRE_EL2
- b 4f
-3: mrs x0, ICC_SRE_EL3
-4: ret
-
-//VOID
-//EFIAPI
-//ArmGicV3SetControlSystemRegisterEnable (
-// IN UINT32 ControlSystemRegisterEnable
-// );
-ASM_PFX(ArmGicV3SetControlSystemRegisterEnable):
- EL1_OR_EL2_OR_EL3(x1)
-1: msr ICC_SRE_EL1, x0
- b 4f
-2: msr ICC_SRE_EL2, x0
- b 4f
-3: msr ICC_SRE_EL3, x0
-4: isb
- ret
-
-//VOID
-//ArmGicV3EnableInterruptInterface (
-// VOID
-// );
-ASM_PFX(ArmGicV3EnableInterruptInterface):
- mov x0, #1
- msr ICC_IGRPEN1_EL1, x0
- ret
-
-//VOID
-//ArmGicV3DisableInterruptInterface (
-// VOID
-// );
-ASM_PFX(ArmGicV3DisableInterruptInterface):
- mov x0, #0
- msr ICC_IGRPEN1_EL1, x0
- ret
-
-//VOID
-//ArmGicV3EndOfInterrupt (
-// IN UINTN InterruptId
-// );
-ASM_PFX(ArmGicV3EndOfInterrupt):
- msr ICC_EOIR1_EL1, x0
- ret
-
-//UINTN
-//ArmGicV3AcknowledgeInterrupt (
-// VOID
-// );
-ASM_PFX(ArmGicV3AcknowledgeInterrupt):
- mrs x0, ICC_IAR1_EL1
- ret
-
-//VOID
-//ArmGicV3SetPriorityMask (
-// IN UINTN Priority
-// );
-ASM_PFX(ArmGicV3SetPriorityMask):
- msr ICC_PMR_EL1, x0
- ret
-
-//VOID
-//ArmGicV3SetBinaryPointer (
-// IN UINTN BinaryPoint
-// );
-ASM_PFX(ArmGicV3SetBinaryPointer):
- msr ICC_BPR1_EL1, x0
- ret
diff --git a/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S b/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S deleted file mode 100644 index af14b91b9c..0000000000 --- a/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S +++ /dev/null @@ -1,98 +0,0 @@ -#
-# Copyright (c) 2014, ARM Limited. All rights reserved.
-#
-# This program and the accompanying materials are licensed and made available
-# under the terms and conditions of the BSD License which accompanies this
-# distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#
-
-#include <AsmMacroIoLib.h>
-#include <Library/ArmLib.h>
-
-// For the moment we assume this will run in SVC mode on ARMv7
-
-.text
-.align 2
-
-GCC_ASM_EXPORT(ArmGicV3GetControlSystemRegisterEnable)
-GCC_ASM_EXPORT(ArmGicV3SetControlSystemRegisterEnable)
-GCC_ASM_EXPORT(ArmGicV3EnableInterruptInterface)
-GCC_ASM_EXPORT(ArmGicV3DisableInterruptInterface)
-GCC_ASM_EXPORT(ArmGicV3EndOfInterrupt)
-GCC_ASM_EXPORT(ArmGicV3AcknowledgeInterrupt)
-GCC_ASM_EXPORT(ArmGicV3SetPriorityMask)
-GCC_ASM_EXPORT(ArmGicV3SetBinaryPointer)
-
-//UINT32
-//EFIAPI
-//ArmGicGetControlSystemRegisterEnable (
-// VOID
-// );
-ASM_PFX(ArmGicV3GetControlSystemRegisterEnable):
- mrc p15, 0, r0, c12, c12, 5 // ICC_SRE
- bx lr
-
-//VOID
-//EFIAPI
-//ArmGicSetControlSystemRegisterEnable (
-// IN UINT32 ControlSystemRegisterEnable
-// );
-ASM_PFX(ArmGicV3SetControlSystemRegisterEnable):
- mcr p15, 0, r0, c12, c12, 5 // ICC_SRE
- isb
- bx lr
-
-//VOID
-//ArmGicV3EnableInterruptInterface (
-// VOID
-// );
-ASM_PFX(ArmGicV3EnableInterruptInterface):
- mov r0, #1
- mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1
- bx lr
-
-//VOID
-//ArmGicV3DisableInterruptInterface (
-// VOID
-// );
-ASM_PFX(ArmGicV3DisableInterruptInterface):
- mov r0, #0
- mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1
- bx lr
-
-//VOID
-//ArmGicV3EndOfInterrupt (
-// IN UINTN InterruptId
-// );
-ASM_PFX(ArmGicV3EndOfInterrupt):
- mcr p15, 0, r0, c12, c12, 1 //ICC_EOIR1
- bx lr
-
-//UINTN
-//ArmGicV3AcknowledgeInterrupt (
-// VOID
-// );
-ASM_PFX(ArmGicV3AcknowledgeInterrupt):
- mrc p15, 0, r0, c12, c8, 0 //ICC_IAR1
- bx lr
-
-//VOID
-//ArmGicV3SetPriorityMask (
-// IN UINTN Priority
-// );
-ASM_PFX(ArmGicV3SetPriorityMask):
- mcr p15, 0, r0, c4, c6, 0 //ICC_PMR
- bx lr
-
-//VOID
-//ArmGicV3SetBinaryPointer (
-// IN UINTN BinaryPoint
-// );
-ASM_PFX(ArmGicV3SetBinaryPointer):
- mcr p15, 0, r0, c12, c12, 3 //ICC_BPR1
- bx lr
diff --git a/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm b/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm deleted file mode 100644 index 92c3236b25..0000000000 --- a/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm +++ /dev/null @@ -1,96 +0,0 @@ -//
-// Copyright (c) 2014, ARM Limited. All rights reserved.
-//
-// This program and the accompanying materials are licensed and made available
-// under the terms and conditions of the BSD License which accompanies this
-// distribution. The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//
-
-// For the moment we assume this will run in SVC mode on ARMv7
-
- EXPORT ArmGicV3GetControlSystemRegisterEnable
- EXPORT ArmGicV3SetControlSystemRegisterEnable
- EXPORT ArmGicV3EnableInterruptInterface
- EXPORT ArmGicV3DisableInterruptInterface
- EXPORT ArmGicV3EndOfInterrupt
- EXPORT ArmGicV3AcknowledgeInterrupt
- EXPORT ArmGicV3SetPriorityMask
- EXPORT ArmGicV3SetBinaryPointer
-
- AREA ArmGicV3, CODE, READONLY
-
-//UINT32
-//EFIAPI
-//ArmGicGetControlSystemRegisterEnable (
-// VOID
-// );
-ArmGicV3GetControlSystemRegisterEnable
- mrc p15, 0, r0, c12, c12, 5 // ICC_SRE
- bx lr
-
-//VOID
-//EFIAPI
-//ArmGicSetControlSystemRegisterEnable (
-// IN UINT32 ControlSystemRegisterEnable
-// );
-ArmGicV3SetControlSystemRegisterEnable
- mcr p15, 0, r0, c12, c12, 5 // ICC_SRE
- isb
- bx lr
-
-//VOID
-//ArmGicV3EnableInterruptInterface (
-// VOID
-// );
-ArmGicV3EnableInterruptInterface
- mov r0, #1
- mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1
- bx lr
-
-//VOID
-//ArmGicV3DisableInterruptInterface (
-// VOID
-// );
-ArmGicV3DisableInterruptInterface
- mov r0, #0
- mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1
- bx lr
-
-//VOID
-//ArmGicV3EndOfInterrupt (
-// IN UINTN InterruptId
-// );
-ArmGicV3EndOfInterrupt
- mcr p15, 0, r0, c12, c12, 1 //ICC_EOIR1
- bx lr
-
-//UINTN
-//ArmGicV3AcknowledgeInterrupt (
-// VOID
-// );
-ArmGicV3AcknowledgeInterrupt
- mrc p15, 0, r0, c12, c8, 0 //ICC_IAR1
- bx lr
-
-//VOID
-//ArmGicV3SetPriorityMask (
-// IN UINTN Priority
-// );
-ArmGicV3SetPriorityMask
- mcr p15, 0, r0, c4, c6, 0 //ICC_PMR
- bx lr
-
-//VOID
-//ArmGicV3SetBinaryPointer (
-// IN UINTN BinaryPoint
-// );
-ArmGicV3SetBinaryPointer
- mcr p15, 0, r0, c12, c12, 3 //ICC_BPR1
- bx lr
-
- END
diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c deleted file mode 100644 index 4afa3d5a09..0000000000 --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c +++ /dev/null @@ -1,322 +0,0 @@ -/** @file
-*
-* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Library/ArmGicLib.h>
-
-#include "ArmGicDxe.h"
-
-#define ARM_GIC_DEFAULT_PRIORITY 0x80
-
-extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol;
-
-STATIC UINTN mGicDistributorBase;
-STATIC UINTN mGicRedistributorsBase;
-
-/**
- Enable interrupt source Source.
-
- @param This Instance pointer for this protocol
- @param Source Hardware source of the interrupt
-
- @retval EFI_SUCCESS Source interrupt enabled.
- @retval EFI_DEVICE_ERROR Hardware could not be programmed.
-
-**/
-EFI_STATUS
-EFIAPI
-GicV3EnableInterruptSource (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source
- )
-{
- if (Source > mGicNumInterrupts) {
- ASSERT(FALSE);
- return EFI_UNSUPPORTED;
- }
-
- ArmGicEnableInterrupt (mGicDistributorBase, mGicRedistributorsBase, Source);
-
- return EFI_SUCCESS;
-}
-
-/**
- Disable interrupt source Source.
-
- @param This Instance pointer for this protocol
- @param Source Hardware source of the interrupt
-
- @retval EFI_SUCCESS Source interrupt disabled.
- @retval EFI_DEVICE_ERROR Hardware could not be programmed.
-
-**/
-EFI_STATUS
-EFIAPI
-GicV3DisableInterruptSource (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source
- )
-{
- if (Source > mGicNumInterrupts) {
- ASSERT(FALSE);
- return EFI_UNSUPPORTED;
- }
-
- ArmGicDisableInterrupt (mGicDistributorBase, mGicRedistributorsBase, Source);
-
- return EFI_SUCCESS;
-}
-
-/**
- Return current state of interrupt source Source.
-
- @param This Instance pointer for this protocol
- @param Source Hardware source of the interrupt
- @param InterruptState TRUE: source enabled, FALSE: source disabled.
-
- @retval EFI_SUCCESS InterruptState is valid
- @retval EFI_DEVICE_ERROR InterruptState is not valid
-
-**/
-EFI_STATUS
-EFIAPI
-GicV3GetInterruptSourceState (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source,
- IN BOOLEAN *InterruptState
- )
-{
- if (Source > mGicNumInterrupts) {
- ASSERT(FALSE);
- return EFI_UNSUPPORTED;
- }
-
- *InterruptState = ArmGicIsInterruptEnabled (mGicDistributorBase, mGicRedistributorsBase, Source);
-
- return EFI_SUCCESS;
-}
-
-/**
- Signal to the hardware that the End Of Interrupt state
- has been reached.
-
- @param This Instance pointer for this protocol
- @param Source Hardware source of the interrupt
-
- @retval EFI_SUCCESS Source interrupt EOI'ed.
- @retval EFI_DEVICE_ERROR Hardware could not be programmed.
-
-**/
-EFI_STATUS
-EFIAPI
-GicV3EndOfInterrupt (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source
- )
-{
- if (Source > mGicNumInterrupts) {
- ASSERT(FALSE);
- return EFI_UNSUPPORTED;
- }
-
- ArmGicV3EndOfInterrupt (Source);
- return EFI_SUCCESS;
-}
-
-/**
- EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.
-
- @param InterruptType Defines the type of interrupt or exception that
- occurred on the processor.This parameter is processor architecture specific.
- @param SystemContext A pointer to the processor context when
- the interrupt occurred on the processor.
-
- @return None
-
-**/
-VOID
-EFIAPI
-GicV3IrqInterruptHandler (
- IN EFI_EXCEPTION_TYPE InterruptType,
- IN EFI_SYSTEM_CONTEXT SystemContext
- )
-{
- UINT32 GicInterrupt;
- HARDWARE_INTERRUPT_HANDLER InterruptHandler;
-
- GicInterrupt = ArmGicV3AcknowledgeInterrupt ();
-
- // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the
- // number of interrupt (ie: Spurious interrupt).
- if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) >= mGicNumInterrupts) {
- // The special interrupt do not need to be acknowledge
- return;
- }
-
- InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt];
- if (InterruptHandler != NULL) {
- // Call the registered interrupt handler.
- InterruptHandler (GicInterrupt, SystemContext);
- } else {
- DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));
- }
-
- GicV3EndOfInterrupt (&gHardwareInterruptV3Protocol, GicInterrupt);
-}
-
-//
-// The protocol instance produced by this driver
-//
-EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol = {
- RegisterInterruptSource,
- GicV3EnableInterruptSource,
- GicV3DisableInterruptSource,
- GicV3GetInterruptSourceState,
- GicV3EndOfInterrupt
-};
-
-/**
- Shutdown our hardware
-
- DXE Core will disable interrupts and turn off the timer and disable interrupts
- after all the event handlers have run.
-
- @param[in] Event The Event that is being processed
- @param[in] Context Event Context
-**/
-VOID
-EFIAPI
-GicV3ExitBootServicesEvent (
- IN EFI_EVENT Event,
- IN VOID *Context
- )
-{
- UINTN Index;
-
- // Acknowledge all pending interrupts
- for (Index = 0; Index < mGicNumInterrupts; Index++) {
- GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index);
- }
-
- for (Index = 0; Index < mGicNumInterrupts; Index++) {
- GicV3EndOfInterrupt (&gHardwareInterruptV3Protocol, Index);
- }
-
- // Disable Gic Interface
- ArmGicV3DisableInterruptInterface ();
-
- // Disable Gic Distributor
- ArmGicDisableDistributor (mGicDistributorBase);
-}
-
-/**
- Initialize the state information for the CPU Architectural Protocol
-
- @param ImageHandle of the loaded driver
- @param SystemTable Pointer to the System Table
-
- @retval EFI_SUCCESS Protocol registered
- @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
- @retval EFI_DEVICE_ERROR Hardware problems
-
-**/
-EFI_STATUS
-GicV3DxeInitialize (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- )
-{
- EFI_STATUS Status;
- UINTN Index;
- UINT32 RegOffset;
- UINTN RegShift;
- UINT64 CpuTarget;
- UINT64 MpId;
-
- // Make sure the Interrupt Controller Protocol is not already installed in the system.
- ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
-
- mGicDistributorBase = PcdGet32 (PcdGicDistributorBase);
- mGicRedistributorsBase = PcdGet32 (PcdGicRedistributorsBase);
- mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase);
-
- //
- // We will be driving this GIC in native v3 mode, i.e., with Affinity
- // Routing enabled. So ensure that the ARE bit is set.
- //
- if (!FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {
- MmioOr32 (mGicDistributorBase + ARM_GIC_ICDDCR, ARM_GIC_ICDDCR_ARE);
- }
-
- for (Index = 0; Index < mGicNumInterrupts; Index++) {
- GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index);
-
- // Set Priority
- RegOffset = Index / 4;
- RegShift = (Index % 4) * 8;
- MmioAndThenOr32 (
- mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
- ~(0xff << RegShift),
- ARM_GIC_DEFAULT_PRIORITY << RegShift
- );
- }
-
- //
- // Targets the interrupts to the Primary Cpu
- //
-
- if (FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {
- // Only Primary CPU will run this code. We can identify our GIC CPU ID by reading
- // the GIC Distributor Target register. The 8 first GICD_ITARGETSRn are banked to each
- // connected CPU. These 8 registers hold the CPU targets fields for interrupts 0-31.
- // More Info in the GIC Specification about "Interrupt Processor Targets Registers"
- //
- // Read the first Interrupt Processor Targets Register (that corresponds to the 4
- // first SGIs)
- CpuTarget = MmioRead32 (mGicDistributorBase + ARM_GIC_ICDIPTR);
-
- // The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value
- // is 0 when we run on a uniprocessor platform.
- if (CpuTarget != 0) {
- // The 8 first Interrupt Processor Targets Registers are read-only
- for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {
- MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);
- }
- }
- } else {
- MpId = ArmReadMpidr ();
- CpuTarget = MpId & (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3);
-
- // Route the SPIs to the primary CPU. SPIs start at the INTID 32
- for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) {
- MmioWrite32 (mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8), CpuTarget | ARM_GICD_IROUTER_IRM);
- }
- }
-
- // Set binary point reg to 0x7 (no preemption)
- ArmGicV3SetBinaryPointer (0x7);
-
- // Set priority mask reg to 0xff to allow all priorities through
- ArmGicV3SetPriorityMask (0xff);
-
- // Enable gic cpu interface
- ArmGicV3EnableInterruptInterface ();
-
- // Enable gic distributor
- ArmGicEnableDistributor (mGicDistributorBase);
-
- Status = InstallAndRegisterInterruptService (
- &gHardwareInterruptV3Protocol, GicV3IrqInterruptHandler, GicV3ExitBootServicesEvent);
-
- return Status;
-}
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