diff options
Diffstat (limited to 'ArmPkg/Drivers/CpuDxe')
| -rw-r--r-- | ArmPkg/Drivers/CpuDxe/CpuDxe.h | 4 | ||||
| -rw-r--r-- | ArmPkg/Drivers/CpuDxe/Mmu.c | 16 |
2 files changed, 10 insertions, 10 deletions
diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.h b/ArmPkg/Drivers/CpuDxe/CpuDxe.h index e11d5d6bf4..70f77ca059 100644 --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.h +++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.h @@ -111,8 +111,8 @@ CpuSetMemoryAttributes ( EFI_STATUS
InitializeExceptions (
-\s\sIN EFI_CPU_ARCH_PROTOCOL *Cpu
-\s\s);
+ IN EFI_CPU_ARCH_PROTOCOL *Cpu
+ );
EFI_STATUS
SyncCacheConfig (
diff --git a/ArmPkg/Drivers/CpuDxe/Mmu.c b/ArmPkg/Drivers/CpuDxe/Mmu.c index 0b86b8bc98..9ba5c83448 100644 --- a/ArmPkg/Drivers/CpuDxe/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/Mmu.c @@ -338,11 +338,11 @@ UpdatePageEntries ( // modify cacheability attributes
EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
if (FeaturePcdGet(PcdEfiUncachedMemoryToStronglyOrdered)) {
-\s\s\s\s // map to strongly ordered
-\s\s\s\s EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
+ // map to strongly ordered
+ EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
} else {
- \s\s // map to normal non-cachable
- \s\s EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
+ // map to normal non-cachable
+ EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
}
break;
@@ -486,11 +486,11 @@ UpdateSectionEntries ( // modify cacheability attributes
EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
if (FeaturePcdGet(PcdEfiUncachedMemoryToStronglyOrdered)) {
-\s\s\s\s // map to strongly ordered
-\s\s\s\s EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
+ // map to strongly ordered
+ EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
} else {
- \s\s // map to normal non-cachable
- \s\s EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
+ // map to normal non-cachable
+ EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
}
break;
|