1 files changed, 31 insertions, 4 deletions
diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
index 57ae14150e..4f10e4e512 100644
--- a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
+++ b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
@@ -12,7 +12,8 @@
 *
 **/
 
-#include <Uefi.h>
+#include <Base.h>
+#include <Library/DebugLib.h>
 #include <Library/IoLib.h>
 #include <Library/ArmGicLib.h>
 
@@ -29,6 +30,7 @@ ArmGicSetupNonSecure (
 {
   UINTN InterruptId;
   UINTN CachedPriorityMask;
+  UINTN Index;
 
   CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);
 
@@ -46,14 +48,39 @@ ArmGicSetupNonSecure (
   }
 
   // Ensure all GIC interrupts are Non-Secure
-  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);     // IRQs  0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]
-  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt
-  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)
+  for (Index = 0; Index < (PcdGet32(PcdGicNumInterrupts) / 32); Index++) {
+    MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);
+  }
 
   // Ensure all interrupts can get through the priority mask
   MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);
 }
 
+/*
+ * This function configures the interrupts set by the mask to be secure.
+ *
+ */
+VOID
+EFIAPI
+ArmGicSetSecureInterrupts (
+  IN  UINTN         GicDistributorBase,
+  IN  UINTN*        GicSecureInterruptMask,
+  IN  UINTN         GicSecureInterruptMaskSize
+  )
+{
+  UINTN  Index;
+  UINT32 InterruptStatus;
+
+  // We must not have more interrupts defined by the mask than the number of available interrupts
+  ASSERT(GicSecureInterruptMaskSize <= (PcdGet32(PcdGicNumInterrupts) / 32));
+
+  // Set all the interrupts defined by the mask as Secure
+  for (Index = 0; Index < GicSecureInterruptMaskSize; Index++) {
+    InterruptStatus = MmioRead32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4));
+    MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), InterruptStatus & (~GicSecureInterruptMask[Index]));
+  }
+}
+
 VOID
 EFIAPI
 ArmGicEnableInterruptInterface (