diff options
Diffstat (limited to 'ArmPkg/Drivers/PL390Gic/PL390GicSec.c')
| -rw-r--r-- | ArmPkg/Drivers/PL390Gic/PL390GicSec.c | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c index 46b14e0746..7bb0f3dd6f 100644 --- a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c +++ b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c @@ -34,11 +34,11 @@ PL390GicSetupNonSecure ( //Check if there are any pending interrupts
while(0 != (MmioRead32(GicDistributorBase + GIC_ICDICPR) & 0xF))
{
- //Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
- UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
+\s\s //Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
+\s\s UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
- //Write to End of interrupt signal
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
+\s\s //Write to End of interrupt signal
+\s\s MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
}
// Ensure all GIC interrupts are Non-Secure
@@ -56,19 +56,19 @@ PL390GicEnableInterruptInterface ( IN INTN GicInterruptInterfaceBase
)
{
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0x000000FF); /* Set Priority Mask to allow interrupts */
+\s\sMmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0x000000FF); /* Set Priority Mask to allow interrupts */
- /*
- * Enable CPU interface in Secure world
+\s\s/*
+\s\s * Enable CPU interface in Secure world
* Enable CPU inteface in Non-secure World
- * Signal Secure Interrupts to CPU using FIQ line *
- */
+\s\s * Signal Secure Interrupts to CPU using FIQ line *
+\s\s */
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,
- GIC_ICCICR_ENABLE_SECURE(1) |
- GIC_ICCICR_ENABLE_NS(1) |
- GIC_ICCICR_ACK_CTL(0) |
- GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(1) |
- GIC_ICCICR_USE_SBPR(0));
+ \s\s\s\sGIC_ICCICR_ENABLE_SECURE(1) |
+ \s\s\s\sGIC_ICCICR_ENABLE_NS(1) |
+ \s\s\s\sGIC_ICCICR_ACK_CTL(0) |
+ \s\s\s\sGIC_ICCICR_SIGNAL_SECURE_TO_FIQ(1) |
+ \s\s\s\sGIC_ICCICR_USE_SBPR(0));
}
VOID
@@ -88,7 +88,7 @@ PL390GicSendSgiTo ( IN INTN CPUTargetList
)
{
- MmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));
+\s\sMmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));
}
UINT32
@@ -103,9 +103,9 @@ PL390GicAcknowledgeSgiFrom ( InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
//Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
- if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
- //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
+\s\sif (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
+\s\s //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
+\s\s\s\sMmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
return 1;
} else {
return 0;
@@ -125,9 +125,9 @@ PL390GicAcknowledgeSgi2From ( InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
//Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
- if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
- //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
+\s\sif((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
+\s\s //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
+\s\s\s\sMmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
return 1;
} else {
return 0;
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