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-rw-r--r--ArmPkg/Drivers/CpuDxe/Arm/Exception.c (renamed from ArmPkg/Drivers/CpuDxe/ArmV6/Exception.c)0
-rw-r--r--ArmPkg/Drivers/CpuDxe/Arm/ExceptionSupport.S (renamed from ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.S)0
-rw-r--r--ArmPkg/Drivers/CpuDxe/Arm/ExceptionSupport.asm (renamed from ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.asm)0
-rw-r--r--ArmPkg/Drivers/CpuDxe/Arm/Mmu.c (renamed from ArmPkg/Drivers/CpuDxe/ArmV6/Mmu.c)0
-rw-r--r--ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.S191
-rw-r--r--ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.asm152
-rw-r--r--ArmPkg/Drivers/CpuDxe/CpuDxe.inf18
7 files changed, 4 insertions, 357 deletions
diff --git a/ArmPkg/Drivers/CpuDxe/ArmV6/Exception.c b/ArmPkg/Drivers/CpuDxe/Arm/Exception.c
index 4b05199db3..4b05199db3 100644
--- a/ArmPkg/Drivers/CpuDxe/ArmV6/Exception.c
+++ b/ArmPkg/Drivers/CpuDxe/Arm/Exception.c
diff --git a/ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.S b/ArmPkg/Drivers/CpuDxe/Arm/ExceptionSupport.S
index 3433b99cd4..3433b99cd4 100644
--- a/ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.S
+++ b/ArmPkg/Drivers/CpuDxe/Arm/ExceptionSupport.S
diff --git a/ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.asm b/ArmPkg/Drivers/CpuDxe/Arm/ExceptionSupport.asm
index b28ff9f7ee..b28ff9f7ee 100644
--- a/ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.asm
+++ b/ArmPkg/Drivers/CpuDxe/Arm/ExceptionSupport.asm
diff --git a/ArmPkg/Drivers/CpuDxe/ArmV6/Mmu.c b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c
index 63da8ba8cb..63da8ba8cb 100644
--- a/ArmPkg/Drivers/CpuDxe/ArmV6/Mmu.c
+++ b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c
diff --git a/ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.S b/ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.S
deleted file mode 100644
index c82618aa1b..0000000000
--- a/ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.S
+++ /dev/null
@@ -1,191 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
-
-.text
-.align 3
-
-GCC_ASM_EXPORT(ExceptionHandlersStart)
-GCC_ASM_EXPORT(ExceptionHandlersEnd)
-GCC_ASM_EXPORT(CommonExceptionEntry)
-GCC_ASM_EXPORT(AsmCommonExceptionEntry)
-GCC_ASM_EXPORT(CommonCExceptionHandler)
-
-ASM_PFX(ExceptionHandlersStart):
-
-ASM_PFX(Reset):
- b ASM_PFX(ResetEntry)
-
-ASM_PFX(UndefinedInstruction):
- b ASM_PFX(UndefinedInstructionEntry)
-
-ASM_PFX(SoftwareInterrupt):
- b ASM_PFX(SoftwareInterruptEntry)
-
-ASM_PFX(PrefetchAbort):
- b ASM_PFX(PrefetchAbortEntry)
-
-ASM_PFX(DataAbort):
- b ASM_PFX(DataAbortEntry)
-
-ASM_PFX(ReservedException):
- b ASM_PFX(ReservedExceptionEntry)
-
-ASM_PFX(Irq):
- b ASM_PFX(IrqEntry)
-
-ASM_PFX(Fiq):
- b ASM_PFX(FiqEntry)
-
-ASM_PFX(ResetEntry):
- srsdb #0x13! @ Store return state on SVC stack
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov R0,#0
- ldr R1,ASM_PFX(CommonExceptionEntry)
- bx R1
-
-ASM_PFX(UndefinedInstructionEntry):
- srsdb #0x13! @ Store return state on SVC stack
- cps #0x13 @ Switch to SVC for common stack
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov r0,#1
- ldr r1,ASM_PFX(CommonExceptionEntry)
- bx r1
-
-ASM_PFX(SoftwareInterruptEntry):
- srsdb #0x13! @ Store return state on SVC stack
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov r0,#2
- ldr r1,ASM_PFX(CommonExceptionEntry)
- bx r1
-
-ASM_PFX(PrefetchAbortEntry):
- sub LR,LR,#4
- srsdb #0x13! @ Store return state on SVC stack
- cps #0x13 @ Switch to SVC for common stack
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov r0,#3
- ldr r1,ASM_PFX(CommonExceptionEntry)
- bx r1
-
-ASM_PFX(DataAbortEntry):
- sub LR,LR,#8
- srsdb #0x13! @ Store return state on SVC stack
- cps #0x13 @ Switch to SVC for common stack
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov r0,#4
- ldr r1,ASM_PFX(CommonExceptionEntry)
- bx r1
-
-ASM_PFX(ReservedExceptionEntry):
- srsdb #0x13! @ Store return state on SVC stack
- cps #0x13 @ Switch to SVC for common stack
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov r0,#5
- ldr r1,ASM_PFX(CommonExceptionEntry)
- bx r1
-
-ASM_PFX(IrqEntry):
- sub LR,LR,#4
- srsdb #0x13! @ Store return state on SVC stack
- cps #0x13 @ Switch to SVC for common stack
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov r0,#6
- ldr r1,ASM_PFX(CommonExceptionEntry)
- bx r1
-
-ASM_PFX(FiqEntry):
- sub LR,LR,#4
- srsdb #0x13! @ Store return state on SVC stack
- cps #0x13 @ Switch to SVC for common stack
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov r0,#7
- ldr r1,ASM_PFX(CommonExceptionEntry)
- bx r1
-
-ASM_PFX(CommonExceptionEntry):
- .byte 0x12
- .byte 0x34
- .byte 0x56
- .byte 0x78
-
-ASM_PFX(ExceptionHandlersEnd):
-
-ASM_PFX(AsmCommonExceptionEntry):
- mrc p15, 0, R1, c6, c0, 2 @ Read IFAR
- str R1, [SP, #0x50] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR
-
- mrc p15, 0, R1, c5, c0, 1 @ Read IFSR
- str R1, [SP, #0x4c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR
-
- mrc p15, 0, R1, c6, c0, 0 @ Read DFAR
- str R1, [SP, #0x48] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR
-
- mrc p15, 0, R1, c5, c0, 0 @ Read DFSR
- str R1, [SP, #0x44] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR
-
- ldr R1, [SP, #0x5c] @ srsdb saved pre-exception CPSR on the stack
- str R1, [SP, #0x40] @ Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR
- and r1, r1, #0x1f @ Check to see if User or System Mode
- cmp r1, #0x1f
- cmpne r1, #0x10
- add R2, SP, #0x38 @ Store it in EFI_SYSTEM_CONTEXT_ARM.LR
- ldmneed r2, {lr}^ @ User or System mode, use unbanked register
- ldmneed r2, {lr} @ All other modes used banked register
-
- ldr R1, [SP, #0x58] @ PC is the LR pushed by srsdb
- str R1, [SP, #0x3c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.PC
-
- sub R1, SP, #0x60 @ We pused 0x60 bytes on the stack
- str R1, [SP, #0x34] @ Store it in EFI_SYSTEM_CONTEXT_ARM.SP
-
- @ R0 is exception type
- mov R1,SP @ Prepare System Context pointer as an argument for the exception handler
- blx ASM_PFX(CommonCExceptionHandler) @ Call exception handler
-
- ldr R2,[SP,#0x40] @ EFI_SYSTEM_CONTEXT_ARM.CPSR
- str R2,[SP,#0x5c] @ Store it back to srsdb stack slot so it can be restored
-
- ldr R2,[SP,#0x3c] @ EFI_SYSTEM_CONTEXT_ARM.PC
- str R2,[SP,#0x58] @ Store it back to srsdb stack slot so it can be restored
-
- ldmfd SP!,{R0-R12} @ Restore general purpose registers
- @ Exception handler can not change SP or LR as we would blow chunks
-
- add SP,SP,#0x20 @ Clear out the remaining stack space
- ldmfd SP!,{LR} @ restore the link register for this context
- rfefd SP! @ return from exception via srsdb stack slot
diff --git a/ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.asm b/ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.asm
deleted file mode 100644
index 9f09a0bc76..0000000000
--- a/ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.asm
+++ /dev/null
@@ -1,152 +0,0 @@
-//------------------------------------------------------------------------------
-//
-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-//
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution. The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//------------------------------------------------------------------------------
-
- EXPORT ExceptionHandlersStart
- EXPORT ExceptionHandlersEnd
- EXPORT CommonExceptionEntry
- EXPORT AsmCommonExceptionEntry
- IMPORT CommonCExceptionHandler
-
- PRESERVE8
- AREA DxeExceptionHandlers, CODE, READONLY
-
-ExceptionHandlersStart
-
-Reset
- b ResetEntry
-
-UndefinedInstruction
- b UndefinedInstructionEntry
-
-SoftwareInterrupt
- b SoftwareInterruptEntry
-
-PrefetchAbort
- b PrefetchAbortEntry
-
-DataAbort
- b DataAbortEntry
-
-ReservedException
- b ReservedExceptionEntry
-
-Irq
- b IrqEntry
-
-Fiq
- b FiqEntry
-
-ResetEntry
- stmfd SP!,{R0-R1}
- mov R0,#0
- ldr R1,CommonExceptionEntry
- bx R1
-
-UndefinedInstructionEntry
- stmfd SP!,{R0-R1}
- mov R0,#1
- ldr R1,CommonExceptionEntry
- bx R1
-
-SoftwareInterruptEntry
- stmfd SP!,{R0-R1}
- mov R0,#2
- ldr R1,CommonExceptionEntry
- bx R1
-
-PrefetchAbortEntry
- stmfd SP!,{R0-R1}
- mov R0,#3
- SUB LR,LR,#4
- ldr R1,CommonExceptionEntry
- bx R1
-
-DataAbortEntry
- stmfd SP!,{R0-R1}
- mov R0,#4
- SUB LR,LR,#8
- ldr R1,CommonExceptionEntry
- bx R1
-
-ReservedExceptionEntry
- stmfd SP!,{R0-R1}
- mov R0,#5
- ldr R1,CommonExceptionEntry
- bx R1
-
-IrqEntry
- stmfd SP!,{R0-R1}
- mov R0,#6
- SUB LR,LR,#4
- ldr R1,CommonExceptionEntry
- bx R1
-
-FiqEntry
- stmfd SP!,{R0-R1}
- mov R0,#7
- SUB LR,LR,#4
- ldr R1,CommonExceptionEntry
- bx R1
-
-CommonExceptionEntry
- dcd 0x12345678
-
-ExceptionHandlersEnd
-
-AsmCommonExceptionEntry
- mrc p15, 0, r1, c6, c0, 2 ; Read IFAR
- stmfd SP!,{R1} ; Store the IFAR
-
- mrc p15, 0, r1, c5, c0, 1 ; Read IFSR
- stmfd SP!,{R1} ; Store the IFSR
-
- mrc p15, 0, r1, c6, c0, 0 ; Read DFAR
- stmfd SP!,{R1} ; Store the DFAR
-
- mrc p15, 0, r1, c5, c0, 0 ; Read DFSR
- stmfd SP!,{R1} ; Store the DFSR
-
- mrs R1,SPSR ; Read SPSR (which is the pre-exception CPSR)
- stmfd SP!,{R1} ; Store the SPSR
-
- stmfd SP!,{LR} ; Store the link register (which is the pre-exception PC)
- stmfd SP,{SP,LR}^ ; Store user/system mode stack pointer and link register
- nop ; Required by ARM architecture
- SUB SP,SP,#0x08 ; Adjust stack pointer
- stmfd SP!,{R2-R12} ; Store general purpose registers
-
- ldr R3,[SP,#0x50] ; Read saved R1 from the stack (it was saved by the exception entry routine)
- ldr R2,[SP,#0x4C] ; Read saved R0 from the stack (it was saved by the exception entry routine)
- stmfd SP!,{R2-R3} ; Store general purpose registers R0 and R1
-
- mov R1,SP ; Prepare System Context pointer as an argument for the exception handler
-
- sub SP,SP,#4 ; Adjust SP to preserve 8-byte alignment
- blx CommonCExceptionHandler ; Call exception handler
- add SP,SP,#4 ; Adjust SP back to where we were
-
- ldr R2,[SP,#0x40] ; Load CPSR from context, in case it has changed
- MSR SPSR_cxsf,R2 ; Store it back to the SPSR to be restored when exiting this handler
-
- ldmfd SP!,{R0-R12} ; Restore general purpose registers
- ldm SP,{SP,LR}^ ; Restore user/system mode stack pointer and link register
- nop ; Required by ARM architecture
- add SP,SP,#0x08 ; Adjust stack pointer
- ldmfd SP!,{LR} ; Restore the link register (which is the pre-exception PC)
- add SP,SP,#0x1C ; Clear out the remaining stack space
- movs PC,LR ; Return from exception
-
- END
-
-
diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.inf b/ArmPkg/Drivers/CpuDxe/CpuDxe.inf
index 01f65a3655..9ad242a42e 100644
--- a/ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.inf
@@ -30,21 +30,11 @@
CpuMpCore.c
CpuMmuCommon.c
-#
-# Prior to ARMv6 we have multiple stacks, one per mode
-#
-# ArmV4/ExceptionSupport.asm | RVCT
-# ArmV4/ExceptionSupport.S | GCC
-
-#
-# ARMv6 or later uses a single stack via srs/stm instructions
-#
-
[Sources.ARM]
- ArmV6/Mmu.c
- ArmV6/Exception.c
- ArmV6/ExceptionSupport.asm | RVCT
- ArmV6/ExceptionSupport.S | GCC
+ Arm/Mmu.c
+ Arm/Exception.c
+ Arm/ExceptionSupport.asm | RVCT
+ Arm/ExceptionSupport.S | GCC
[Sources.AARCH64]
AArch64/Mmu.c
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 08:25:03 +0000