diff options
Diffstat (limited to 'ArmPkg/Drivers')
4 files changed, 275 insertions, 0 deletions
diff --git a/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Helper.S b/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Helper.S new file mode 100644 index 0000000000..96acde19e8 --- /dev/null +++ b/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Helper.S @@ -0,0 +1,67 @@ +//
+// Copyright (c) 2011, ARM Limited. All rights reserved.
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
+
+#include <Library/ArmCpuLib.h>
+
+.text
+.align 3
+
+GCC_ASM_EXPORT(ArmCpuSynchronizeWait)
+GCC_ASM_IMPORT(CArmCpuSynchronizeWait)
+
+// VOID
+// ArmCpuSynchronizeWait (
+// IN ARM_CPU_SYNCHRONIZE_EVENT Event
+// );
+ASM_PFX(ArmCpuSynchronizeWait):
+ cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
+ // The SCU enabled is the event to tell us the Init Boot Memory is initialized
+ bx lr
+ b CArmCpuSynchronizeWait
+
+
+#if 0
+GCC_ASM_EXPORT(ArmCpuSynchronizeWait)
+GCC_ASM_EXPORT(ArmGetScuBaseAddress)
+GCC_ASM_IMPORT(CArmCpuSynchronizeWait)
+
+// VOID
+// ArmCpuSynchronizeWait (
+// IN ARM_CPU_SYNCHRONIZE_EVENT Event
+// );
+ASM_PFX(ArmCpuSynchronizeWait):
+ cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
+ // The SCU enabled is the event to tell us the Init Boot Memory is initialized
+ beq ArmWaitScuEnabled
+ b CArmCpuSynchronizeWait
+
+// IN None
+// OUT r0 = SCU Base Address
+ASM_PFX(ArmGetScuBaseAddress):
+ // Read Configuration Base Address Register. ArmCBar cannot be called to get
+ // the Configuration BAR as a stack is not necessary setup. The SCU is at the
+ // offset 0x0000 from the Private Memory Region.
+ mrc p15, 4, r0, c15, c0, 0
+ bx lr
+
+ASM_PFX(ArmWaitScuEnabled):
+ // Read Configuration Base Address Register. ArmCBar cannot be called to get
+ // the Configuration BAR as a stack is not necessary setup. The SCU is at the
+ // offset 0x0000 from the Private Memory Region.
+ mrc p15, 4, r0, c15, c0, 0
+ add r0, r0, #A9_SCU_CONTROL_OFFSET
+ ldr r0, [r0]
+ cmp r0, #1
+ bne ArmWaitScuEnabled
+ bx lr
+#endif
diff --git a/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Helper.asm b/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Helper.asm new file mode 100644 index 0000000000..d0fc2b5a8a --- /dev/null +++ b/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Helper.asm @@ -0,0 +1,54 @@ +//
+// Copyright (c) 2011, ARM Limited. All rights reserved.
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
+
+#include <Library/ArmCpuLib.h>
+#include <Chipset/ArmCortexA9.h>
+
+ EXPORT ArmCpuSynchronizeWait
+ EXPORT ArmGetScuBaseAddress
+ IMPORT CArmCpuSynchronizeWait
+
+ PRESERVE8
+ AREA ArmCortexA9Helper, CODE, READONLY
+
+// VOID
+// ArmCpuSynchronizeWait (
+// IN ARM_CPU_SYNCHRONIZE_EVENT Event
+// );
+ArmCpuSynchronizeWait
+ cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
+ // The SCU enabled is the event to tell us the Init Boot Memory is initialized
+ beq ArmWaitScuEnabled
+ b CArmCpuSynchronizeWait
+
+// IN None
+// OUT r0 = SCU Base Address
+ArmGetScuBaseAddress
+ // Read Configuration Base Address Register. ArmCBar cannot be called to get
+ // the Configuration BAR as a stack is not necessary setup. The SCU is at the
+ // offset 0x0000 from the Private Memory Region.
+ mrc p15, 4, r0, c15, c0, 0
+ bx lr
+
+ArmWaitScuEnabled
+ // Read Configuration Base Address Register. ArmCBar cannot be called to get
+ // the Configuration BAR as a stack is not necessary setup. The SCU is at the
+ // offset 0x0000 from the Private Memory Region.
+ mrc p15, 4, r0, c15, c0, 0
+ add r0, r0, #A9_SCU_CONTROL_OFFSET
+ ldr r0, [r0]
+ cmp r0, #1
+ bne ArmWaitScuEnabled
+ bx lr
+
+ END
diff --git a/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Lib.c b/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Lib.c new file mode 100644 index 0000000000..2e285d54c7 --- /dev/null +++ b/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Lib.c @@ -0,0 +1,112 @@ +/** @file
+
+ Copyright (c) 2011, ARM Limited. All rights reserved.
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Library/ArmLib.h>
+#include <Library/ArmCpuLib.h>
+#include <Library/ArmGicLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+
+VOID
+ArmCpuSynchronizeSignal (
+ IN ARM_CPU_SYNCHRONIZE_EVENT Event
+ )
+{
+ if (Event == ARM_CPU_EVENT_BOOT_MEM_INIT) {
+ // Do nothing, Cortex A9 secondary cores are waiting for the SCU to be
+ // enabled (done by ArmCpuSetup()) as a way to know when the Init Boot
+ // Mem as been initialized
+ } else {
+ // Send SGI to all Secondary core to wake them up from WFI state.
+ ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
+ }
+}
+
+VOID
+CArmCpuSynchronizeWait (
+ IN ARM_CPU_SYNCHRONIZE_EVENT Event
+ )
+{
+ // Waiting for the SGI from the primary core
+ ArmCallWFI ();
+
+ // Acknowledge the interrupt and send End of Interrupt signal.
+ ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
+}
+
+#if 0
+VOID
+ArmEnableScu (
+ VOID
+ )
+{
+ INTN ScuBase;
+
+ ScuBase = ArmGetScuBaseAddress();
+
+ // Invalidate all: write -1 to SCU Invalidate All register
+ MmioWrite32(ScuBase + A9_SCU_INVALL_OFFSET, 0xffffffff);
+ // Enable SCU
+ MmioWrite32(ScuBase + A9_SCU_CONTROL_OFFSET, 0x1);
+}
+#endif
+
+VOID
+ArmCpuSetup (
+ IN UINTN MpId
+ )
+{
+ /*AMP mode and SMP mode
+
+ By default, the processor is in AMP mode (bit 5 reset to 0). To prevent coherent data corruption the sequence to turn on MP11 CPUs in SMP mode is:
+
+ 1.Write the SCU register to change CPU mode.
+ 2.Disable interrupts.
+ 3.Clean and invalidate all the D-cache.
+ 4.Write SMP/nAMP bit as 1.
+ 5.Enable interrupts.
+
+ Source: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360e/BIHHFGEC.html
+ */
+
+ // If MPCore then Enable the SCU
+ if (ArmIsMpCore()) {
+ //ArmEnableScu ();
+ }
+}
+
+
+VOID
+ArmCpuSetupSmpNonSecure (
+ IN UINTN MpId
+ )
+{
+#if 0
+ INTN ScuBase;
+
+ ArmSetAuxCrBit (A9_FEATURE_SMP);
+
+ // Make the SCU accessible in Non Secure world
+ if (IS_PRIMARY_CORE(MpId)) {
+ ScuBase = ArmGetScuBaseAddress();
+
+ // Allow NS access to SCU register
+ MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);
+ // Allow NS access to Private Peripherals
+ MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);
+ }
+#endif
+}
+
diff --git a/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11MpCoreLib.inf b/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11MpCoreLib.inf new file mode 100644 index 0000000000..2b9621c6ec --- /dev/null +++ b/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11MpCoreLib.inf @@ -0,0 +1,42 @@ +#/* @file
+# Copyright (c) 2011, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = Arm11MpCoreLib
+ FILE_GUID = dc8a69e0-6be0-469c-94d3-5e6d71aa9808
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmCpuLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ArmPkg/ArmPkg.dec
+
+[LibraryClasses]
+ ArmLib
+ ArmGicSecLib
+ IoLib
+ PcdLib
+
+[Sources.common]
+ Arm11Lib.c
+ Arm11Helper.asm | RVCT
+ Arm11Helper.S | GCC
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
|