diff options
Diffstat (limited to 'ArmPkg/Drivers')
-rw-r--r-- | ArmPkg/Drivers/PL390Gic/PL390Gic.c | 71 | ||||
-rw-r--r-- | ArmPkg/Drivers/PL390Gic/PL390GicDxe.c | 46 | ||||
-rw-r--r-- | ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf | 4 | ||||
-rw-r--r-- | ArmPkg/Drivers/PL390Gic/PL390GicLib.inf (renamed from ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf) | 7 | ||||
-rw-r--r-- | ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c | 64 | ||||
-rw-r--r-- | ArmPkg/Drivers/PL390Gic/PL390GicSec.c | 95 | ||||
-rw-r--r-- | ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf (renamed from ArmPkg/Drivers/PL390Gic/PL390GicSec.inf) | 7 |
7 files changed, 125 insertions, 169 deletions
diff --git a/ArmPkg/Drivers/PL390Gic/PL390Gic.c b/ArmPkg/Drivers/PL390Gic/PL390Gic.c new file mode 100644 index 0000000000..9da5cc4b59 --- /dev/null +++ b/ArmPkg/Drivers/PL390Gic/PL390Gic.c @@ -0,0 +1,71 @@ +/** @file
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/ArmGicLib.h>
+
+VOID
+EFIAPI
+ArmGicSendSgiTo (
+ IN INTN GicDistributorBase,
+ IN INTN TargetListFilter,
+ IN INTN CPUTargetList
+ )
+{
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));
+}
+
+UINT32
+EFIAPI
+ArmGicAcknowledgeSgiFrom (
+ IN INTN GicInterruptInterfaceBase,
+ IN INTN CoreId
+ )
+{
+ INTN InterruptId;
+
+ InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
+
+ // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
+ if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
+ // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+UINT32
+EFIAPI
+ArmGicAcknowledgeSgi2From (
+ IN INTN GicInterruptInterfaceBase,
+ IN INTN CoreId,
+ IN INTN SgiId
+ )
+{
+ INTN InterruptId;
+
+ InterruptId = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
+
+ // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
+ if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
+ // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);
+ return 1;
+ } else {
+ return 0;
+ }
+}
diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c b/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c index 02853a2f31..d352dcaee0 100644 --- a/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c +++ b/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c @@ -29,25 +29,24 @@ Abstract: #include <Library/UefiLib.h> #include <Library/PcdLib.h> #include <Library/IoLib.h> +#include <Library/ArmGicLib.h> #include <Protocol/Cpu.h> #include <Protocol/HardwareInterrupt.h> -#include <Drivers/PL390Gic.h> - // number of 32-bit registers needed to represent those interrupts as a bit // (used for enable set, enable clear, pending set, pending clear, and active regs) -#define GIC_NUM_REG_PER_INT_BITS (PcdGet32(PcdGicNumInterrupts) / 32) +#define ARM_GIC_NUM_REG_PER_INT_BITS (PcdGet32(PcdGicNumInterrupts) / 32) // number of 32-bit registers needed to represent those interrupts as two bits // (used for configuration reg) -#define GIC_NUM_REG_PER_INT_CFG (PcdGet32(PcdGicNumInterrupts) / 16) +#define ARM_GIC_NUM_REG_PER_INT_CFG (PcdGet32(PcdGicNumInterrupts) / 16) // number of 32-bit registers needed to represent interrupts as 8-bit priority field // (used for priority regs) -#define GIC_NUM_REG_PER_INT_BYTES (PcdGet32(PcdGicNumInterrupts) / 4) +#define ARM_GIC_NUM_REG_PER_INT_BYTES (PcdGet32(PcdGicNumInterrupts) / 4) -#define GIC_DEFAULT_PRIORITY 0x80 +#define ARM_GIC_DEFAULT_PRIORITY 0x80 extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol; @@ -130,7 +129,7 @@ EnableInterruptSource ( RegShift = Source % 32; // write set-enable register - MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDISER + (4*RegOffset), 1 << RegShift); + MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset), 1 << RegShift); return EFI_SUCCESS; } @@ -165,7 +164,7 @@ DisableInterruptSource ( RegShift = Source % 32; // Write set-enable register - MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDICER + (4*RegOffset), 1 << RegShift); + MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDICER + (4*RegOffset), 1 << RegShift); return EFI_SUCCESS; } @@ -201,7 +200,7 @@ GetInterruptSourceState ( RegOffset = Source / 32; RegShift = Source % 32; - if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDISER + (4*RegOffset)) & (1<<RegShift)) == 0) { + if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset)) & (1<<RegShift)) == 0) { *InterruptState = FALSE; } else { *InterruptState = TRUE; @@ -233,7 +232,7 @@ EndOfInterrupt ( return EFI_UNSUPPORTED; } - MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCEIOR, Source); + MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCEIOR, Source); return EFI_SUCCESS; } @@ -258,9 +257,10 @@ IrqInterruptHandler ( UINT32 GicInterrupt; HARDWARE_INTERRUPT_HANDLER InterruptHandler; - GicInterrupt = MmioRead32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCIAR); + GicInterrupt = MmioRead32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCIAR); + //TODO: Comment me if (GicInterrupt >= PcdGet32(PcdGicNumInterrupts)) { - MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCEIOR, GicInterrupt); + MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCEIOR, GicInterrupt); return; } @@ -323,11 +323,11 @@ ExitBootServicesEvent ( } // Disable Gic Interface - MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCICR, 0x0); - MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCPMR, 0x0); + MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x0); + MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0x0); // Disable Gic Distributor - MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDDCR, 0x0); + MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x0); } /** @@ -363,28 +363,28 @@ InterruptDxeInitialize ( RegOffset = Index / 4; RegShift = (Index % 4) * 8; MmioAndThenOr32 ( - PcdGet32(PcdGicDistributorBase) + GIC_ICDIPR + (4*RegOffset), + PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPR + (4*RegOffset), ~(0xff << RegShift), - GIC_DEFAULT_PRIORITY << RegShift + ARM_GIC_DEFAULT_PRIORITY << RegShift ); } // Configure interrupts for cpu 0 - for (Index = 0; Index < GIC_NUM_REG_PER_INT_BYTES; Index++) { - MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDIPTR + (Index*4), 0x01010101); + for (Index = 0; Index < ARM_GIC_NUM_REG_PER_INT_BYTES; Index++) { + MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index*4), 0x01010101); } // Set binary point reg to 0x7 (no preemption) - MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCBPR, 0x7); + MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCBPR, 0x7); // Set priority mask reg to 0xff to allow all priorities through - MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCPMR, 0xff); + MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0xff); // Enable gic cpu interface - MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCICR, 0x1); + MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x1); // Enable gic distributor - MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDDCR, 0x1); + MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x1); ZeroMem (&gRegisteredInterruptHandlers, sizeof (gRegisteredInterruptHandlers)); diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf b/ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf index 3baa902a63..48ae8ba82d 100644 --- a/ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf +++ b/ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf @@ -24,7 +24,6 @@ [Sources.common] PL390GicDxe.c - [Packages] MdePkg/MdePkg.dec EmbeddedPkg/EmbeddedPkg.dec @@ -39,9 +38,6 @@ UefiDriverEntryPoint IoLib -[Guids] - - [Protocols] gHardwareInterruptProtocolGuid gEfiCpuArchProtocolGuid diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf b/ArmPkg/Drivers/PL390Gic/PL390GicLib.inf index f5ffd7febb..cae5c2b24c 100644 --- a/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf +++ b/ArmPkg/Drivers/PL390Gic/PL390GicLib.inf @@ -13,17 +13,16 @@ [Defines]
INF_VERSION = 0x00010005
- BASE_NAME = PL390GicNonSec
+ BASE_NAME = PL390GicLib
FILE_GUID = 03d05ee4-cdeb-458c-9dfc-993f09bdf405
MODULE_TYPE = SEC
VERSION_STRING = 1.0
- LIBRARY_CLASS = PL390GicNonSecLib
+ LIBRARY_CLASS = ArmGicLib
[Sources]
+ PL390Gic.c
PL390GicNonSec.c
[Packages]
ArmPkg/ArmPkg.dec
MdePkg/MdePkg.dec
-
-[FixedPcd]
diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c b/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c index c2089fe846..09ef00b85f 100644 --- a/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c +++ b/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c @@ -14,12 +14,12 @@ #include <Uefi.h>
#include <Library/IoLib.h>
-#include <Drivers/PL390Gic.h>
+#include <Library/ArmGicLib.h>
VOID
EFIAPI
-PL390GicEnableInterruptInterface (
+ArmGicEnableInterruptInterface (
IN INTN GicInterruptInterfaceBase
)
{
@@ -27,12 +27,12 @@ PL390GicEnableInterruptInterface ( * Enable the CPU interface in Non-Secure world
* Note: The ICCICR register is banked when Security extensions are implemented
*/
- MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCICR,0x00000001);
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,0x00000001);
}
VOID
EFIAPI
-PL390GicEnableDistributor (
+ArmGicEnableDistributor (
IN INTN GicDistributorBase
)
{
@@ -40,59 +40,5 @@ PL390GicEnableDistributor ( * Enable GIC distributor in Non-Secure world.
* Note: The ICDDCR register is banked when Security extensions are implemented
*/
- MmioWrite32 (GicDistributorBase + GIC_ICDDCR, 0x00000001);
-}
-
-VOID
-EFIAPI
-PL390GicSendSgiTo (
- IN INTN GicDistributorBase,
- IN INTN TargetListFilter,
- IN INTN CPUTargetList
- )
-{
- MmioWrite32 (GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));
-}
-
-UINT32
-EFIAPI
-PL390GicAcknowledgeSgiFrom (
- IN INTN GicInterruptInterfaceBase,
- IN INTN CoreId
- )
-{
- INTN InterruptId;
-
- InterruptId = MmioRead32 (GicInterruptInterfaceBase + GIC_ICCIAR);
-
- // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
- if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
- // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
- MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
- return 1;
- } else {
- return 0;
- }
-}
-
-UINT32
-EFIAPI
-PL390GicAcknowledgeSgi2From (
- IN INTN GicInterruptInterfaceBase,
- IN INTN CoreId,
- IN INTN SgiId
- )
-{
- INTN InterruptId;
-
- InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
-
- // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
- if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
- // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
- MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
- return 1;
- } else {
- return 0;
- }
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x00000001);
}
diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c index bf4c010b70..244f9ecf2a 100644 --- a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c +++ b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c @@ -14,7 +14,7 @@ #include <Uefi.h>
#include <Library/IoLib.h>
-#include <Drivers/PL390Gic.h>
+#include <Library/ArmGicLib.h>
/*
* This function configures the all interrupts to be Non-secure.
@@ -22,114 +22,59 @@ */
VOID
EFIAPI
-PL390GicSetupNonSecure (
+ArmGicSetupNonSecure (
IN INTN GicDistributorBase,
IN INTN GicInterruptInterfaceBase
)
{
- UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + GIC_ICCPMR);
+ UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR);
// Set priority Mask so that no interrupts get through to CPU
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0);
+ MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);
// Check if there are any pending interrupts
- while(0 != (MmioRead32(GicDistributorBase + GIC_ICDICPR) & 0xF)) {
+ //TODO: could be extended to take Peripheral interrupts into consideration, but at the moment only SGI's are taken into consideration.
+ while(0 != (MmioRead32(GicDistributorBase + ARM_GIC_ICDICPR) & 0xF)) {
// Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
- UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
+ UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
// Write to End of interrupt signal
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
+ MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);
}
// Ensure all GIC interrupts are Non-Secure
- MmioWrite32(GicDistributorBase + GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]
- MmioWrite32(GicDistributorBase + GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt
- MmioWrite32(GicDistributorBase + GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)
+ MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]
+ MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt
+ MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)
// Ensure all interrupts can get through the priority mask
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, CachedPriorityMask);
+ MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);
}
VOID
EFIAPI
-PL390GicEnableInterruptInterface (
+ArmGicEnableInterruptInterface (
IN INTN GicInterruptInterfaceBase
)
{
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0x000000FF); /* Set Priority Mask to allow interrupts */
+ MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF); /* Set Priority Mask to allow interrupts */
/*
* Enable CPU interface in Secure world
* Enable CPU inteface in Non-secure World
* Signal Secure Interrupts to CPU using FIQ line *
*/
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,
- GIC_ICCICR_ENABLE_SECURE(1) |
- GIC_ICCICR_ENABLE_NS(1) |
- GIC_ICCICR_ACK_CTL(0) |
- GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(1) |
- GIC_ICCICR_USE_SBPR(0));
+ MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCICR,
+ ARM_GIC_ICCICR_ENABLE_SECURE |
+ ARM_GIC_ICCICR_ENABLE_NS |
+ ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);
}
VOID
EFIAPI
-PL390GicEnableDistributor (
+ArmGicEnableDistributor (
IN INTN GicDistributorBase
)
{
- MmioWrite32(GicDistributorBase + GIC_ICDDCR, 1); // turn on the GIC distributor
-}
-
-VOID
-EFIAPI
-PL390GicSendSgiTo (
- IN INTN GicDistributorBase,
- IN INTN TargetListFilter,
- IN INTN CPUTargetList
- )
-{
- MmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));
-}
-
-UINT32
-EFIAPI
-PL390GicAcknowledgeSgiFrom (
- IN INTN GicInterruptInterfaceBase,
- IN INTN CoreId
- )
-{
- INTN InterruptId;
-
- InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
-
- // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
- if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
- // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
- return 1;
- } else {
- return 0;
- }
-}
-
-UINT32
-EFIAPI
-PL390GicAcknowledgeSgi2From (
- IN INTN GicInterruptInterfaceBase,
- IN INTN CoreId,
- IN INTN SgiId
- )
-{
- INTN InterruptId;
-
- InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
-
- // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
- if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
- // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
- return 1;
- } else {
- return 0;
- }
+ MmioWrite32(GicDistributorBase + ARM_GIC_ICDDCR, 1); // turn on the GIC distributor
}
diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicSec.inf b/ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf index 9cbdb6e8b3..fdec5c68d3 100644 --- a/ArmPkg/Drivers/PL390Gic/PL390GicSec.inf +++ b/ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf @@ -13,17 +13,16 @@ [Defines]
INF_VERSION = 0x00010005
- BASE_NAME = PL390GicSec
+ BASE_NAME = PL390GicSecLib
FILE_GUID = 85f3cf80-b5f4-11df-9855-0002a5d5c51b
MODULE_TYPE = SEC
VERSION_STRING = 1.0
- LIBRARY_CLASS = PL390GicSecLib
+ LIBRARY_CLASS = ArmGicSecLib
[Sources]
+ PL390Gic.c
PL390GicSec.c
[Packages]
ArmPkg/ArmPkg.dec
MdePkg/MdePkg.dec
-
-[FixedPcd]
|