diff options
Diffstat (limited to 'ArmPkg/Include/Drivers/PL341Dmc.h')
| -rw-r--r-- | ArmPkg/Include/Drivers/PL341Dmc.h | 80 |
1 files changed, 40 insertions, 40 deletions
diff --git a/ArmPkg/Include/Drivers/PL341Dmc.h b/ArmPkg/Include/Drivers/PL341Dmc.h index 38ac70d17d..6ccc8482b5 100644 --- a/ArmPkg/Include/Drivers/PL341Dmc.h +++ b/ArmPkg/Include/Drivers/PL341Dmc.h @@ -17,32 +17,32 @@ struct pl341_dmc_config { - UINTN\s\sbase; // base address for the controller - UINTN\s\shas_qos; // has QoS registers - UINTN\s\smax_chip; // number of memory chips accessible - UINT32\s\srefresh_prd; - UINT32\s\scas_latency; - UINT32\s\swrite_latency; - UINT32\s\st_mrd; - UINT32\s\st_ras; - UINT32\s\st_rc; - UINT32\s\st_rcd; - UINT32\s\st_rfc; - UINT32\s\st_rp; - UINT32\s\st_rrd; - UINT32\s\st_wr; - UINT32\s\st_wtr; - UINT32\s\st_xp; - UINT32\s\st_xsr; - UINT32\s\st_esr; - UINT32\s\smemory_cfg; - UINT32\s\smemory_cfg2; - UINT32\s\smemory_cfg3; - UINT32\s\schip_cfg0; - UINT32\s\schip_cfg1; - UINT32\s\schip_cfg2; - UINT32\s\schip_cfg3; - UINT32\s\st_faw; + UINTN base; // base address for the controller + UINTN has_qos; // has QoS registers + UINTN max_chip; // number of memory chips accessible + UINT32 refresh_prd; + UINT32 cas_latency; + UINT32 write_latency; + UINT32 t_mrd; + UINT32 t_ras; + UINT32 t_rc; + UINT32 t_rcd; + UINT32 t_rfc; + UINT32 t_rp; + UINT32 t_rrd; + UINT32 t_wr; + UINT32 t_wtr; + UINT32 t_xp; + UINT32 t_xsr; + UINT32 t_esr; + UINT32 memory_cfg; + UINT32 memory_cfg2; + UINT32 memory_cfg3; + UINT32 chip_cfg0; + UINT32 chip_cfg1; + UINT32 chip_cfg2; + UINT32 chip_cfg3; + UINT32 t_faw; }; /* Memory config bit fields */ @@ -60,21 +60,21 @@ struct pl341_dmc_config { #define DMC_MEMORY_CONFIG_BURST_4 (0x2 << 15) #define DMC_MEMORY_CONFIG_BURST_8 (0x3 << 15) #define DMC_MEMORY_CONFIG_BURST_16 (0x4 << 15) -#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_1\s\s\s\s(0x0 << 21) -#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_2\s\s\s\s(0x1 << 21) -#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_3\s\s\s\s(0x2 << 21) -#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_4\s\s\s\s(0x3 << 21) +#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 (0x0 << 21) +#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_2 (0x1 << 21) +#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_3 (0x2 << 21) +#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_4 (0x3 << 21) -#define DMC_MEMORY_CFG2_CLK_ASYNC\s\s\s\s(0x0 << 0) -#define DMC_MEMORY_CFG2_CLK_SYNC\s\s\s\s(0x1 << 0) -#define DMC_MEMORY_CFG2_DQM_INIT\s\s\s\s(0x1 << 2) -#define DMC_MEMORY_CFG2_CKE_INIT\s\s\s\s(0x1 << 3) -#define DMC_MEMORY_CFG2_BANK_BITS_2\s\s\s\s(0x0 << 4) -#define DMC_MEMORY_CFG2_BANK_BITS_3\s\s\s\s(0x3 << 4) -#define DMC_MEMORY_CFG2_MEM_WIDTH_16\s\s\s\s(0x0 << 6) -#define DMC_MEMORY_CFG2_MEM_WIDTH_32\s\s\s\s(0x1 << 6) -#define DMC_MEMORY_CFG2_MEM_WIDTH_64\s\s\s\s(0x2 << 6) -#define DMC_MEMORY_CFG2_MEM_WIDTH_RESERVED\s\s(0x3 << 6) +#define DMC_MEMORY_CFG2_CLK_ASYNC (0x0 << 0) +#define DMC_MEMORY_CFG2_CLK_SYNC (0x1 << 0) +#define DMC_MEMORY_CFG2_DQM_INIT (0x1 << 2) +#define DMC_MEMORY_CFG2_CKE_INIT (0x1 << 3) +#define DMC_MEMORY_CFG2_BANK_BITS_2 (0x0 << 4) +#define DMC_MEMORY_CFG2_BANK_BITS_3 (0x3 << 4) +#define DMC_MEMORY_CFG2_MEM_WIDTH_16 (0x0 << 6) +#define DMC_MEMORY_CFG2_MEM_WIDTH_32 (0x1 << 6) +#define DMC_MEMORY_CFG2_MEM_WIDTH_64 (0x2 << 6) +#define DMC_MEMORY_CFG2_MEM_WIDTH_RESERVED (0x3 << 6) |