diff options
Diffstat (limited to 'ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm')
-rw-r--r-- | ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm | 96 |
1 files changed, 50 insertions, 46 deletions
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm index 7a6c3083a3..3ce5f2ecd8 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm @@ -32,7 +32,6 @@ DC_ON EQU ( 0x1:SHL:2 ) IC_ON EQU ( 0x1:SHL:12 ) -XP_ON EQU ( 0x1:SHL:23 ) AREA ArmCacheLib, CODE, READONLY @@ -40,17 +39,13 @@ XP_ON EQU ( 0x1:SHL:23 ) ArmInvalidateDataCacheEntryByMVA - DSB - ISB - MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line + MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line DSB ISB BX lr ArmCleanDataCacheEntryByMVA - DSB - ISB MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line DSB ISB @@ -58,8 +53,6 @@ ArmCleanDataCacheEntryByMVA ArmCleanInvalidateDataCacheEntryByMVA - DSB - ISB MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line DSB ISB @@ -67,8 +60,6 @@ ArmCleanInvalidateDataCacheEntryByMVA ArmInvalidateDataCacheEntryBySetWay - DSB - ISB mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line DSB ISB @@ -76,8 +67,6 @@ ArmInvalidateDataCacheEntryBySetWay ArmCleanInvalidateDataCacheEntryBySetWay - DSB - ISB mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line DSB ISB @@ -85,8 +74,6 @@ ArmCleanInvalidateDataCacheEntryBySetWay ArmCleanDataCacheEntryBySetWay - DSB - ISB mcr p15, 0, r0, c7, c10, 2 ; Clean this line DSB ISB @@ -94,8 +81,6 @@ ArmCleanDataCacheEntryBySetWay ArmDrainWriteBuffer - DSB - ISB mcr p15, 0, r0, c7, c10, 4 ; Drain write buffer for sync DSB ISB @@ -103,8 +88,6 @@ ArmDrainWriteBuffer ArmInvalidateInstructionCache - DSB - ISB MOV R0,#0 MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache MOV R0,#0 @@ -114,8 +97,6 @@ ArmInvalidateInstructionCache BX LR ArmEnableMmu - DSB - ISB mrc p15,0,R0,c1,c0,0 orr R0,R0,#1 mcr p15,0,R0,c1,c0,0 @@ -124,33 +105,22 @@ ArmEnableMmu bx LR ArmMmuEnabled - DSB - ISB mrc p15,0,R0,c1,c0,0 and R0,R0,#1 - DSB ISB bx LR ArmDisableMmu - DSB - ISB mov R0,#0 mcr p15,0,R0,c13,c0,0 ;FCSE PID register must be cleared before disabling MMU mrc p15,0,R0,c1,c0,0 bic R0,R0,#1 mcr p15,0,R0,c1,c0,0 ;Disable MMU - mov R0,#0 - mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier - mov R0,#0 - mcr p15,0,R0,c7,c5,4 ;Instruction synchronization barrier DSB ISB bx LR ArmEnableDataCache - DSB - ISB LDR R1,=DC_ON MRC p15,0,R0,c1,c0,0 ;Read control register configuration data ORR R0,R0,R1 ;Set C bit @@ -160,56 +130,90 @@ ArmEnableDataCache BX LR ArmDisableDataCache - DSB - ISB LDR R1,=DC_ON MRC p15,0,R0,c1,c0,0 ;Read control register configuration data BIC R0,R0,R1 ;Clear C bit MCR p15,0,r0,c1,c0,0 ;Write control register configuration data - DSB ISB BX LR ArmEnableInstructionCache - DSB - ISB LDR R1,=IC_ON MRC p15,0,R0,c1,c0,0 ;Read control register configuration data ORR R0,R0,R1 ;Set I bit MCR p15,0,r0,c1,c0,0 ;Write control register configuration data - DSB ISB BX LR ArmDisableInstructionCache - DSB - ISB LDR R1,=IC_ON MRC p15,0,R0,c1,c0,0 ;Read control register configuration data BIC R0,R0,R1 ;Clear I bit. MCR p15,0,r0,c1,c0,0 ;Write control register configuration data - DSB ISB BX LR ArmEnableBranchPrediction - DSB - ISB mrc p15, 0, r0, c1, c0, 0 orr r0, r0, #0x00000800 mcr p15, 0, r0, c1, c0, 0 - DSB ISB bx LR ArmDisableBranchPrediction - DSB - ISB mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x00000800 mcr p15, 0, r0, c1, c0, 0 - DSB ISB bx LR + +ArmV7AllDataCachesOperation + STMFD SP!,{r4-r12, LR} + MOV R1, R0 ; Save Function call in R1 + MRC p15, 1, R6, c0, c0, 1 ; Read CLIDR + ANDS R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC) + MOV R3, R3, LSR #23 ; Cache level value (naturally aligned) + BEQ Finished + MOV R10, #0 + +Loop1 + ADD R2, R10, R10, LSR #1 ; Work out 3xcachelevel + MOV R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level + AND R12, R12, #7 ; get those 3 bits alone + CMP R12, #2 + BLT Skip ; no cache or only instruction cache at this level + MCR p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction + ISB ; ISB to sync the change to the CacheSizeID reg + MRC p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR) + AND R2, R12, #&7 ; extract the line length field + ADD R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes) + LDR R4, =0x3FF + ANDS R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned) + CLZ R5, R4 ; R5 is the bit position of the way size increment + LDR R7, =0x00007FFF + ANDS R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned) + +Loop2 + MOV R9, R4 ; R9 working copy of the max way size (right aligned) + +Loop3 + ORR R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11 + ORR R0, R0, R7, LSL R2 ; factor in the index number + + BLX R1 + + SUBS R9, R9, #1 ; decrement the way number + BGE Loop3 + SUBS R7, R7, #1 ; decrement the index + BGE Loop2 +Skip + ADD R10, R10, #2 ; increment the cache number + CMP R3, R10 + BGT Loop1 + +Finished + LDMFD SP!, {r4-r12, lr} + BX LR + END |