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-rw-r--r--ArmPkg/ArmPkg.dec18
-rw-r--r--ArmPkg/Include/Chipset/AArch64.h14
-rw-r--r--ArmPkg/Include/Chipset/ArmV7.h14
-rw-r--r--ArmPkg/Include/Library/ArmLib.h12
-rw-r--r--ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S12
-rw-r--r--ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm16
-rw-r--r--ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S6
-rw-r--r--ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S10
-rw-r--r--ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm10
9 files changed, 54 insertions, 58 deletions
diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
index 3326e7b584..39f264251b 100644
--- a/ArmPkg/ArmPkg.dec
+++ b/ArmPkg/ArmPkg.dec
@@ -128,15 +128,7 @@
# - BIT9 : SIF - Secure Instruction Fetch
# 0x31 = NS | EA | FW
gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038
-
- # Non Secure Access Control Register
- # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality
- # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31
- # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable
- # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable
- # 0xC00 = cp10 | cp11
- gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039
-
+
# System Memory (DRAM): These PCDs define the region of in-built system memory
# Some platforms can get DRAM extensions, these additional regions will be declared
# to UEFI by ArmPLatformPlib
@@ -182,6 +174,14 @@
# The FDT blob must be loaded at a 64bit aligned address.
gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x8|UINT32|0x00000026
+ # Non Secure Access Control Register
+ # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality
+ # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31
+ # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable
+ # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable
+ # 0xC00 = cp10 | cp11
+ gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039
+
[PcdsFixedAtBuild.AARCH64]
# By default we do transition to EL2 non-secure mode with Stack for EL2.
# Mode Description Bits
diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArch64.h
index 7f1f44ccc3..8b64786004 100644
--- a/ArmPkg/Include/Chipset/AArch64.h
+++ b/ArmPkg/Include/Chipset/AArch64.h
@@ -34,15 +34,6 @@
// ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions
#define AARCH64_PFR0_FP (0xF << 16)
-// NSACR - Non-Secure Access Control Register definitions
-#define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF)
-#define NSACR_NSD32DIS (1 << 14)
-#define NSACR_NSASEDIS (1 << 15)
-#define NSACR_PLE (1 << 16)
-#define NSACR_TL (1 << 17)
-#define NSACR_NS_SMP (1 << 18)
-#define NSACR_RFR (1 << 19)
-
// SCR - Secure Configuration Register definitions
#define SCR_NS (1 << 0)
#define SCR_IRQ (1 << 1)
@@ -176,4 +167,9 @@ GcdAttributeToPageAttribute (
IN UINT64 GcdAttributes
);
+UINTN
+ArmWriteCptr (
+ IN UINT64 Cptr
+ );
+
#endif // __AARCH64_H__
diff --git a/ArmPkg/Include/Chipset/ArmV7.h b/ArmPkg/Include/Chipset/ArmV7.h
index 479e8d05e1..29922eca19 100644
--- a/ArmPkg/Include/Chipset/ArmV7.h
+++ b/ArmPkg/Include/Chipset/ArmV7.h
@@ -112,5 +112,17 @@ EFIAPI
ArmReadIdPfr1 (
VOID
);
-
+
+UINT32
+EFIAPI
+ArmReadNsacr (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteNsacr (
+ IN UINT32 Nsacr
+ );
+
#endif // __ARM_V7_H__
diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 1f1fd9e515..bd1bbc40b4 100644
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -537,18 +537,6 @@ ArmEnableVFP (
UINT32
EFIAPI
-ArmReadNsacr (
- VOID
- );
-
-VOID
-EFIAPI
-ArmWriteNsacr (
- IN UINT32 SetWayFormat
- );
-
-UINT32
-EFIAPI
ArmReadScr (
VOID
);
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S
index 9595f224c5..5ee8b25675 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S
@@ -1,7 +1,7 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-# Copyright (c) 2011, ARM Limited. All rights reserved.
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -29,6 +29,8 @@ GCC_ASM_EXPORT(ArmEnableInterrupts)
GCC_ASM_EXPORT(ArmDisableInterrupts)
GCC_ASM_EXPORT(ReadCCSIDR)
GCC_ASM_EXPORT(ReadCLIDR)
+GCC_ASM_EXPORT(ArmReadNsacr)
+GCC_ASM_EXPORT(ArmWriteNsacr)
#------------------------------------------------------------------------------
@@ -98,4 +100,12 @@ ASM_PFX(ReadCLIDR):
mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
bx lr
+ASM_PFX(ArmReadNsacr):
+ mrc p15, 0, r0, c1, c1, 2
+ bx lr
+
+ASM_PFX(ArmWriteNsacr):
+ mcr p15, 0, r0, c1, c1, 2
+ bx lr
+
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm
index a5ff6b2610..6af662bda5 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm
@@ -1,7 +1,7 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-// Copyright (c) 2011, ARM Limited. All rights reserved.
+// Copyright (c) 2011-2013, ARM Limited. All rights reserved.
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
@@ -25,7 +25,9 @@
EXPORT ArmDisableInterrupts
EXPORT ReadCCSIDR
EXPORT ReadCLIDR
-
+ EXPORT ArmReadNsacr
+ EXPORT ArmWriteNsacr
+
AREA ArmLibSupportV7, CODE, READONLY
@@ -96,5 +98,13 @@ ReadCCSIDR
ReadCLIDR
mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
bx lr
-
+
+ArmReadNsacr
+ mrc p15, 0, r0, c1, c1, 2
+ bx lr
+
+ArmWriteNsacr
+ mcr p15, 0, r0, c1, c1, 2
+ bx lr
+
END
diff --git a/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S
index 2db812616a..cf2ec76be9 100644
--- a/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S
@@ -32,7 +32,7 @@ GCC_ASM_EXPORT (ArmWriteAuxCr)
GCC_ASM_EXPORT (ArmReadAuxCr)
GCC_ASM_EXPORT (ArmInvalidateTlb)
GCC_ASM_EXPORT (ArmUpdateTranslationTableEntry)
-GCC_ASM_EXPORT (ArmWriteNsacr)
+GCC_ASM_EXPORT (ArmWriteCptr)
GCC_ASM_EXPORT (ArmWriteScr)
GCC_ASM_EXPORT (ArmWriteMVBar)
GCC_ASM_EXPORT (ArmCallWFE)
@@ -176,9 +176,9 @@ ASM_PFX(ArmInvalidateTlb):
isb
ret
-ASM_PFX(ArmWriteNsacr):
+ASM_PFX(ArmWriteCptr):
msr cptr_el3, x0 // EL3 Coprocessor Trap Reg (CPTR)
- ret // Non-Secure Access Control Reg (NSACR) in ARMv7
+ ret
ASM_PFX(ArmWriteScr):
msr scr_el3, x0 // Secure configuration register EL3
diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
index 71aee43073..4c95565e8f 100644
--- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
@@ -38,8 +38,6 @@ GCC_ASM_EXPORT(ArmWriteAuxCr)
GCC_ASM_EXPORT(ArmReadAuxCr)
GCC_ASM_EXPORT(ArmInvalidateTlb)
GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
-GCC_ASM_EXPORT(ArmReadNsacr)
-GCC_ASM_EXPORT(ArmWriteNsacr)
GCC_ASM_EXPORT(ArmReadScr)
GCC_ASM_EXPORT(ArmWriteScr)
GCC_ASM_EXPORT(ArmReadMVBar)
@@ -147,14 +145,6 @@ ASM_PFX(ArmInvalidateTlb):
isb
bx lr
-ASM_PFX(ArmReadNsacr):
- mrc p15, 0, r0, c1, c1, 2
- bx lr
-
-ASM_PFX(ArmWriteNsacr):
- mcr p15, 0, r0, c1, c1, 2
- bx lr
-
ASM_PFX(ArmReadScr):
mrc p15, 0, r0, c1, c1, 0
bx lr
diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
index 1636010e0f..f4b22943ff 100644
--- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
+++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
@@ -38,8 +38,6 @@
EXPORT ArmReadAuxCr
EXPORT ArmInvalidateTlb
EXPORT ArmUpdateTranslationTableEntry
- EXPORT ArmReadNsacr
- EXPORT ArmWriteNsacr
EXPORT ArmReadScr
EXPORT ArmWriteScr
EXPORT ArmReadMVBar
@@ -147,14 +145,6 @@ ArmInvalidateTlb
isb
bx lr
-ArmReadNsacr
- mrc p15, 0, r0, c1, c1, 2
- bx lr
-
-ArmWriteNsacr
- mcr p15, 0, r0, c1, c1, 2
- bx lr
-
ArmReadScr
mrc p15, 0, r0, c1, c1, 0
bx lr
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 13:45:37 +0000