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-rw-r--r--ArmPkg/Include/Chipset/AArch64.h5
-rw-r--r--ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c42
2 files changed, 0 insertions, 47 deletions
diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArch64.h
index 47993ec9fc..f6a8901289 100644
--- a/ArmPkg/Include/Chipset/AArch64.h
+++ b/ArmPkg/Include/Chipset/AArch64.h
@@ -178,11 +178,6 @@ PageAttributeToGcdAttribute (
IN UINT64 PageAttributes
);
-UINT64
-GcdAttributeToPageAttribute (
- IN UINT64 GcdAttributes
- );
-
UINTN
ArmWriteCptr (
IN UINT64 Cptr
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
index 8829c6286b..c8b3d4a121 100644
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
@@ -96,48 +96,6 @@ PageAttributeToGcdAttribute (
return GcdAttributes;
}
-UINT64
-GcdAttributeToPageAttribute (
- IN UINT64 GcdAttributes
- )
-{
- UINT64 PageAttributes;
-
- switch (GcdAttributes & 0xFF) {
- case EFI_MEMORY_UC:
- PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY;
- break;
- case EFI_MEMORY_WC:
- PageAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
- break;
- case EFI_MEMORY_WT:
- PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH;
- break;
- case EFI_MEMORY_WB:
- PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK;
- break;
- default:
- DEBUG ((EFI_D_ERROR, "GcdAttributeToPageAttribute: 0x%X attributes is not supported.\n", GcdAttributes));
- ASSERT (0);
- // If no match has been found then we mark the memory as device memory.
- // The only side effect of using device memory should be a slow down in the performance.
- PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY;
- }
-
- // Determine protection attributes
- if (GcdAttributes & EFI_MEMORY_WP) {
- // Read only cases map to write-protect
- PageAttributes |= TT_AP_RO_RO;
- }
-
- // Process eXecute Never attribute
- if (GcdAttributes & EFI_MEMORY_XP) {
- PageAttributes |= (TT_PXN_MASK | TT_UXN_MASK);
- }
-
- return PageAttributes;
-}
-
ARM_MEMORY_REGION_ATTRIBUTES
GcdAttributeToArmAttribute (
IN UINT64 GcdAttributes