diff options
Diffstat (limited to 'ArmPkg')
| -rw-r--r-- | ArmPkg/Drivers/CpuDxe/CpuDxe.c | 2 | ||||
| -rw-r--r-- | ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c | 4 | ||||
| -rw-r--r-- | ArmPkg/Drivers/PL390Gic/PL390GicSec.c | 37 |
3 files changed, 23 insertions, 20 deletions
diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.c b/ArmPkg/Drivers/CpuDxe/CpuDxe.c index f14a676383..337ab7cfb5 100644 --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.c +++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.c @@ -259,7 +259,7 @@ CpuDxeInitialize ( // If the platform is a MPCore system then install the Configuration Table describing the
// secondary core states
- if (ArmIsMPCore()) {
+ if (ArmIsMpCore()) {
PublishArmProcessorTable();
}
diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c b/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c index 09ef00b85f..55ff56e797 100644 --- a/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c +++ b/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c @@ -27,7 +27,7 @@ ArmGicEnableInterruptInterface ( * Enable the CPU interface in Non-Secure world
* Note: The ICCICR register is banked when Security extensions are implemented
*/
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,0x00000001);
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x1);
}
VOID
@@ -40,5 +40,5 @@ ArmGicEnableDistributor ( * Enable GIC distributor in Non-Secure world.
* Note: The ICDDCR register is banked when Security extensions are implemented
*/
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x00000001);
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x1);
}
diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c index 244f9ecf2a..57ae14150e 100644 --- a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c +++ b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c @@ -27,28 +27,31 @@ ArmGicSetupNonSecure ( IN INTN GicInterruptInterfaceBase
)
{
- UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR);
+ UINTN InterruptId;
+ UINTN CachedPriorityMask;
+
+ CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);
// Set priority Mask so that no interrupts get through to CPU
- MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);
// Check if there are any pending interrupts
//TODO: could be extended to take Peripheral interrupts into consideration, but at the moment only SGI's are taken into consideration.
- while(0 != (MmioRead32(GicDistributorBase + ARM_GIC_ICDICPR) & 0xF)) {
+ while(0 != (MmioRead32 (GicDistributorBase + ARM_GIC_ICDICPR) & 0xF)) {
// Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
- UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
+ InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
// Write to End of interrupt signal
- MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);
}
// Ensure all GIC interrupts are Non-Secure
- MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]
- MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt
- MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)
// Ensure all interrupts can get through the priority mask
- MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);
}
VOID
@@ -57,14 +60,13 @@ ArmGicEnableInterruptInterface ( IN INTN GicInterruptInterfaceBase
)
{
- MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF); /* Set Priority Mask to allow interrupts */
+ // Set Priority Mask to allow interrupts
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);
- /*
- * Enable CPU interface in Secure world
- * Enable CPU inteface in Non-secure World
- * Signal Secure Interrupts to CPU using FIQ line *
- */
- MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCICR,
+ // Enable CPU interface in Secure world
+ // Enable CPU inteface in Non-secure World
+ // Signal Secure Interrupts to CPU using FIQ line *
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,
ARM_GIC_ICCICR_ENABLE_SECURE |
ARM_GIC_ICCICR_ENABLE_NS |
ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);
@@ -76,5 +78,6 @@ ArmGicEnableDistributor ( IN INTN GicDistributorBase
)
{
- MmioWrite32(GicDistributorBase + ARM_GIC_ICDDCR, 1); // turn on the GIC distributor
+ // Turn on the GIC distributor
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1);
}
|