1 files changed, 25 insertions, 8 deletions
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/RTSMSec.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/RTSMSec.c
index bce834eea9..4c018f7672 100644
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/RTSMSec.c
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/RTSMSec.c
@@ -1,18 +1,19 @@
 /** @file
 *
-*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
-*  
-*  This program and the accompanying materials                          
-*  are licensed and made available under the terms and conditions of the BSD License         
-*  which accompanies this distribution.  The full text of the license may be found at        
-*  http://opensource.org/licenses/bsd-license.php                                            
+*  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
 *
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 *
 **/
 
 #include <Library/IoLib.h>
+#include <Library/ArmGicLib.h>
 #include <Library/ArmPlatformLib.h>
 #include <Library/DebugLib.h>
 #include <Library/PcdLib.h>
@@ -22,6 +23,12 @@
 
 #include <ArmPlatform.h>
 
+// Initialize GICv3 to expose it as a GICv2 as UEFI does not support GICv3 yet
+VOID
+InitializeGicV3 (
+  VOID
+  );
+
 /**
   Initialize the Secure peripherals and memory regions
 
@@ -49,6 +56,8 @@ ArmPlatformSecInitialize (
   IN  UINTN                     MpId
   )
 {
+  UINT32  Identification;
+
   // If it is not the primary core then there is nothing to do
   if (!ArmPlatformIsPrimaryCore (MpId)) {
     return RETURN_SUCCESS;
@@ -63,6 +72,14 @@ ArmPlatformSecInitialize (
   // Configure SP810 to use 1MHz clock and disable
   MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
 
+  // Read the GIC Identification Register
+  Identification = MmioRead32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCIDR);
+
+  // Check if we are GICv3
+  if (ARM_GIC_ICCIDR_GET_ARCH_VERSION(Identification) >= 0x3) {
+    InitializeGicV3 ();
+  }
+
   return RETURN_SUCCESS;
 }