diff options
Diffstat (limited to 'ArmPlatformPkg/Sec')
| -rw-r--r-- | ArmPlatformPkg/Sec/Sec.inf | 3 | ||||
| -rw-r--r-- | ArmPlatformPkg/Sec/SecEntryPoint.S | 133 | ||||
| -rw-r--r-- | ArmPlatformPkg/Sec/SecEntryPoint.asm | 57 |
3 files changed, 119 insertions, 74 deletions
diff --git a/ArmPlatformPkg/Sec/Sec.inf b/ArmPlatformPkg/Sec/Sec.inf index 7b116c7fd9..d2c5083c21 100644 --- a/ArmPlatformPkg/Sec/Sec.inf +++ b/ArmPlatformPkg/Sec/Sec.inf @@ -59,7 +59,8 @@ gArmTokenSpaceGuid.PcdNormalFvBaseAddress gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase - gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize diff --git a/ArmPlatformPkg/Sec/SecEntryPoint.S b/ArmPlatformPkg/Sec/SecEntryPoint.S index 5d83bf1ee7..7f13057f6b 100644 --- a/ArmPlatformPkg/Sec/SecEntryPoint.S +++ b/ArmPlatformPkg/Sec/SecEntryPoint.S @@ -1,34 +1,27 @@ -#------------------------------------------------------------------------------
-#
-# ARM VE Entry point. Reset vector in FV header will brach to
-# _ModuleEntryPoint.
-#
-# Copyright (c) 2011, ARM Limited. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
+//
+// Copyright (c) 2011, ARM Limited. All rights reserved.
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
+#include <AutoGen.h>
#include <AsmMacroIoLib.h>
#include <Base.h>
#include <Library/PcdLib.h>
#include <Library/ArmPlatformLib.h>
-#include <AutoGen.h>
-#Start of Code section
.text
.align 3
-#make _ModuleEntryPoint as global
GCC_ASM_EXPORT(_ModuleEntryPoint)
-#global functions referenced by this module
GCC_ASM_IMPORT(CEntryPoint)
GCC_ASM_IMPORT(ArmPlatformSecBootAction)
GCC_ASM_IMPORT(ArmPlatformInitializeBootMemory)
@@ -42,75 +35,99 @@ GCC_ASM_IMPORT(SecVectorTable) GCC_ASM_IMPORT(ArmIsScuEnable)
#endif
-StartupAddr: .word ASM_PFX(CEntryPoint)
-SecVectorTableAddr: .word ASM_PFX(SecVectorTable)
+StartupAddr: .word ASM_PFX(CEntryPoint)
+SecVectorTableAddr: .word ASM_PFX(SecVectorTable)
ASM_PFX(_ModuleEntryPoint):
- # First ensure all interrupts are disabled
- bl ASM_PFX(ArmDisableInterrupts)
+ // First ensure all interrupts are disabled
+ bl ASM_PFX(ArmDisableInterrupts)
- # Ensure that the MMU and caches are off
- bl ASM_PFX(ArmDisableCachesAndMmu)
+ // Ensure that the MMU and caches are off
+ bl ASM_PFX(ArmDisableCachesAndMmu)
- # Jump to Platform Specific Boot Action function
+ // Jump to Platform Specific Boot Action function
blx ASM_PFX(ArmPlatformSecBootAction)
- # Set VBAR to the start of the exception vectors in Secure Mode
+ // Set VBAR to the start of the exception vectors in Secure Mode
ldr r0, =SecVectorTable
bl ASM_PFX(ArmWriteVBar)
-_IdentifyCpu:
- # Identify CPU ID
+_IdentifyCpu:
+ // Identify CPU ID
bl ASM_PFX(ArmReadMpidr)
// Get ID of this CPU in Multicore system
LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)
and r5, r0, r1
- #get ID of this CPU in Multicore system
+ // Is it the Primary Core ?
LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r1)
cmp r5, r1
- # Only the primary core initialize the memory (SMC)
+ // Only the primary core initialize the memory (SMC)
beq _InitMem
#if (FixedPcdGet32(PcdMPCoreSupport))
- # ... The secondary cores wait for SCU to be enabled
+ // ... The secondary cores wait for SCU to be enabled
_WaitForEnabledScu:
bl ASM_PFX(ArmIsScuEnable)
tst r1, #1
beq _WaitForEnabledScu
- b _SetupStack
+ b _SetupSecondaryCoreStack
#endif
_InitMem:
// Initialize Init Boot Memory
bl ASM_PFX(ArmPlatformInitializeBootMemory)
-
- # Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
- mov r5, #0
-
-_SetupStack:
- # Setup Stack for the 4 CPU cores
- #Read Stack Base address from PCD
+
+ // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)
+
+_SetupPrimaryCoreStack:
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r2)
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r3)
+ // Calculate the Top of the Stack
+ add r2, r2, r3
+ LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r3)
+
+ // The reserved space for global variable must be 8-bytes aligned for pushing
+ // 64-bit variable on the stack
+ SetPrimaryStack (r2, r3, r1)
+
+ // Set all the SEC global variables to 0
+ mov r3, sp
+ mov r1, #0x0
+_InitGlobals:
+ str r1, [r3], #4
+ cmp r3, r2
+ blt _InitGlobals
+
+ b _PrepareArguments
+
+_SetupSecondaryCoreStack:
+ // Get the Core Position (ClusterId * 4) + CoreId
+ GetCorePositionInStack(r0, r5, r1)
+ // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack
+ add r0, r0, #1
+
+ // Get the base of the stack for the secondary cores
LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)
+ add r1, r1, r2
- #read Stack size from PCD
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecStackSize), r2)
+ // StackOffset = CorePos * StackSize
+ mul r0, r0, r2
+ // SP = StackBase + StackOffset
+ add sp, r1, r0
- #calcuate Stack Pointer reg value using Stack size and CPU ID.
- mov r3,r5 @ r3 = core_id
- mul r3,r3,r2 @ r3 = core_id * stack_size = offset from the stack base
- add r3,r3,r1 @ r3 ldr= stack_base + offset
- mov sp, r3
-
- # move sec startup address into a data register
- # ensure we're jumping to FV version of the code (not boot remapped alias)
+
+_PrepareArguments:
+ // Move sec startup address into a data register
+ // Ensure we're jumping to FV version of the code (not boot remapped alias)
ldr r3, StartupAddr
- # Move the CoreId in r0 to be the first argument of the SEC Entry Point
+ // Jump to SEC C code
+ // r0 = mp_id
mov r0, r5
-
- # jump to SEC C code
- # r0 = core_id
- blx r3
-
-
+ blx r3
+
+_NeverReturn:
+ b _NeverReturn
diff --git a/ArmPlatformPkg/Sec/SecEntryPoint.asm b/ArmPlatformPkg/Sec/SecEntryPoint.asm index e85d6ce609..c39b80a85f 100644 --- a/ArmPlatformPkg/Sec/SecEntryPoint.asm +++ b/ArmPlatformPkg/Sec/SecEntryPoint.asm @@ -71,32 +71,57 @@ _WaitForEnabledScu bl ArmIsScuEnable tst r1, #1 beq _WaitForEnabledScu - b _SetupStack + b _SetupSecondaryCoreStack #endif _InitMem // Initialize Init Boot Memory bl ArmPlatformInitializeBootMemory - + // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack) - mov r5, #0 + LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5) + +_SetupPrimaryCoreStack + LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r2) + LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r3) + // Calculate the Top of the Stack + add r2, r2, r3 + LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r3) + + // The reserved space for global variable must be 8-bytes aligned for pushing + // 64-bit variable on the stack + SetPrimaryStack (r2, r3, r1) + + // Set all the SEC global variables to 0 + mov r3, sp + mov r1, #0x0 +_InitGlobals + str r1, [r3], #4 + cmp r3, r2 + blt _InitGlobals -_SetupStack - // Setup Stack for the 4 CPU cores - //Read Stack Base address from PCD + b _PrepareArguments + +_SetupSecondaryCoreStack + // Get the Core Position (ClusterId * 4) + CoreId + GetCorePositionInStack(r0, r5, r1) + // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack + add r0, r0, #1 + + // Get the base of the stack for the secondary cores LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1) + LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2) + add r1, r1, r2 - // Read Stack size from PCD - LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecStackSize), r2) + // StackOffset = CorePos * StackSize + mul r0, r0, r2 + // SP = StackBase + StackOffset + add sp, r1, r0 - // Calcuate Stack Pointer reg value using Stack size and CPU ID. - mov r3,r5 // r3 = core_id - mul r3,r3,r2 // r3 = core_id * stack_size = offset from the stack base - add r3,r3,r1 // r3 = stack_base + offset - mov sp, r3 - + +_PrepareArguments // Move sec startup address into a data register - // ensure we're jumping to FV version of the code (not boot remapped alias) + // Ensure we're jumping to FV version of the code (not boot remapped alias) ldr r3, StartupAddr // Jump to SEC C code @@ -104,4 +129,6 @@ _SetupStack mov r0, r5 blx r3 +_NeverReturn + b _NeverReturn END |