diff options
Diffstat (limited to 'ArmPlatformPkg')
24 files changed, 537 insertions, 411 deletions
diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec index 3eb3608954..898dcc105d 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dec +++ b/ArmPlatformPkg/ArmPlatformPkg.dec @@ -41,11 +41,15 @@ [PcdsFeatureFlag.common] # Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0. gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012 + + gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE|BOOLEAN|0x00000001 + gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|FALSE|BOOLEAN|0x00000002 + gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004 + [PcdsFixedAtBuild.common] # These PCDs should be FeaturePcds. But we used these PCDs as an '#if' in an ASM file. # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor. - gArmPlatformTokenSpaceGuid.PcdStandalone|0|UINT32|0x00000001 gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|0|UINT32|0x00000003 # Stack for CPU Cores in Secure Mode diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc index 2ac5203404..0002d1a17c 100644 --- a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc +++ b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc @@ -123,6 +123,8 @@ [LibraryClasses.common.SEC]
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf
ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbSecLib.inf
+ DebugSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf
+
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
# 1/123 faster than Stm or Vstm version
@@ -261,7 +263,8 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
!if $(EDK2_SKIP_PEICORE) == 1
- gArmTokenSpaceGuid.PcdSkipPeiCore|TRUE
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
+ gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE
!endif
## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
@@ -341,8 +344,6 @@ #
gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x00000000
- gArmPlatformTokenSpaceGuid.PcdStandalone|1
-
# Stack for CPU Cores in Secure Mode
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x4B000000 # Top of SEC Stack for Secure World
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize|0x2000 # Size of SEC Stack for Secure World
@@ -445,7 +446,10 @@ ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf
}
!else
- ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+ ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf {
+ <LibraryClasses>
+ PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf
+ }
MdeModulePkg/Core/Pei/PeiMain.inf
MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
<LibraryClasses>
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc index aca849d972..69e724bcbb 100644 --- a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc +++ b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc @@ -114,6 +114,8 @@ # ARM PL011 UART Driver PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf + # ARM PL390 General Interrupt Driver in Secure and Non-secure + PL390GicNonSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf @@ -124,6 +126,8 @@ [LibraryClasses.common.SEC] ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibSec.inf ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbSecLib.inf + DebugSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf # 1/123 faster than Stm or Vstm version @@ -134,9 +138,8 @@ # L2 Cache Driver L2X0CacheLib|ArmPlatformPkg/Library/L2X0CacheLibNull/L2X0CacheLibNull.inf - # ARM PL390 General Interrupt Driver in Secure and Non-secure + # ARM PL390 General Interrupt Driver in Secure PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSec.inf - PL390GicNonSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf !if $(EDK2_SKIP_PEICORE) == 1 PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf @@ -263,7 +266,8 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE !if $(EDK2_SKIP_PEICORE) == 1 - gArmTokenSpaceGuid.PcdSkipPeiCore|TRUE + gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE + gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE !endif ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. @@ -343,7 +347,6 @@ # gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x00000000 - gArmPlatformTokenSpaceGuid.PcdStandalone|1 gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|1 # Stacks for MPCores in Secure World @@ -446,13 +449,16 @@ # PEI Phase modules # !if $(EDK2_SKIP_PEICORE) == 1 - ArmPlatformPkg/PrePi/PeiMPCore.inf{ + ArmPlatformPkg/PrePi/PeiMPCore.inf { <LibraryClasses> ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf } !else - ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf { + <LibraryClasses> + PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf + } MdeModulePkg/Core/Pei/PeiMain.inf MdeModulePkg/Universal/PCD/Pei/Pcd.inf { <LibraryClasses> diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf index e375709a0f..0cd0c8eec7 100644 --- a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf +++ b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf @@ -37,10 +37,5 @@ ArmRealViewEbHelper.asm | RVCT ArmRealViewEbHelper.S | GCC -[Protocols] - [FeaturePcd] gEmbeddedTokenSpaceGuid.PcdCacheEnable - -[FixedPcd] - gArmPlatformTokenSpaceGuid.PcdStandalone diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbSecLib.inf b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbSecLib.inf index d4a603718b..60b40074e5 100644 --- a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbSecLib.inf +++ b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbSecLib.inf @@ -13,7 +13,7 @@ [Defines]
INF_VERSION = 0x00010005
- BASE_NAME = ArmRealViewEbLib
+ BASE_NAME = ArmRealViewEbSecLib
FILE_GUID = 6e02ebe0-1d96-11e0-b9cb-0002a5d5c51b
MODULE_TYPE = BASE
VERSION_STRING = 1.0
@@ -37,10 +37,5 @@ ArmRealViewEbBoot.asm | RVCT
ArmRealViewEbBoot.S | GCC
-[Protocols]
-
[FeaturePcd]
gEmbeddedTokenSpaceGuid.PcdCacheEnable
-
-[FixedPcd]
- gArmPlatformTokenSpaceGuid.PcdStandalone
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Library/GdbSerialLib/GdbSerialLib.c b/ArmPlatformPkg/ArmRealViewEbPkg/Library/GdbSerialLib/GdbSerialLib.c index 1ad0e17877..bce88837a9 100644 --- a/ArmPlatformPkg/ArmRealViewEbPkg/Library/GdbSerialLib/GdbSerialLib.c +++ b/ArmPlatformPkg/ArmRealViewEbPkg/Library/GdbSerialLib/GdbSerialLib.c @@ -1,51 +1,51 @@ -/** @file - Basic serial IO abstaction for GDB - - Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> - - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include <Uefi.h> -#include <Library/GdbSerialLib.h> -#include <Library/PcdLib.h> -#include <Library/IoLib.h> -#include <Drivers/PL011Uart.h> - -RETURN_STATUS -EFIAPI -GdbSerialLibConstructor ( - VOID - ) -{ - return GdbSerialInit (115200, 0, 8, 1); -} - -RETURN_STATUS -EFIAPI -GdbSerialInit ( - IN UINT64 BaudRate, - IN UINT8 Parity, - IN UINT8 DataBits, - IN UINT8 StopBits - ) -{ - if ((Parity != 0) || (DataBits != 8) || (StopBits != 1)) { - return RETURN_UNSUPPORTED; - } - - if (BaudRate != 115200) { - // Could add support for different Baud rates.... - return RETURN_UNSUPPORTED; - } - +/** @file
+ Basic serial IO abstaction for GDB
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Uefi.h>
+#include <Library/GdbSerialLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Drivers/PL011Uart.h>
+
+RETURN_STATUS
+EFIAPI
+GdbSerialLibConstructor (
+ VOID
+ )
+{
+ return GdbSerialInit (115200, 0, 8, 1);
+}
+
+RETURN_STATUS
+EFIAPI
+GdbSerialInit (
+ IN UINT64 BaudRate,
+ IN UINT8 Parity,
+ IN UINT8 DataBits,
+ IN UINT8 StopBits
+ )
+{
+ if ((Parity != 0) || (DataBits != 8) || (StopBits != 1)) {
+ return RETURN_UNSUPPORTED;
+ }
+
+ if (BaudRate != 115200) {
+ // Could add support for different Baud rates....
+ return RETURN_UNSUPPORTED;
+ }
+
UINT32 Base = PcdGet32 (PcdGdbUartBase);
// initialize baud rate generator to 115200 based on EB clock REFCLK24MHZ
@@ -62,14 +62,14 @@ GdbSerialInit ( MmioWrite32 (Base + UARTCR, 0x301);
return RETURN_SUCCESS;
-} - -BOOLEAN -EFIAPI -GdbIsCharAvailable ( - VOID - ) -{ +}
+
+BOOLEAN
+EFIAPI
+GdbIsCharAvailable (
+ VOID
+ )
+{
UINT32 FR = PcdGet32 (PcdGdbUartBase) + UARTFR;
if ((MmioRead32 (FR) & UART_RX_EMPTY_FLAG_MASK) == 0) {
@@ -77,42 +77,42 @@ GdbIsCharAvailable ( } else {
return FALSE;
}
-} - -CHAR8 -EFIAPI -GdbGetChar ( - VOID - ) -{ +}
+
+CHAR8
+EFIAPI
+GdbGetChar (
+ VOID
+ )
+{
UINT32 FR = PcdGet32 (PcdGdbUartBase) + UARTFR;
UINT32 DR = PcdGet32 (PcdGdbUartBase) + UARTDR;
while ((MmioRead32 (FR) & UART_RX_EMPTY_FLAG_MASK) == 0);
return MmioRead8 (DR);
-} - -VOID -EFIAPI -GdbPutChar ( - IN CHAR8 Char - ) -{ +}
+
+VOID
+EFIAPI
+GdbPutChar (
+ IN CHAR8 Char
+ )
+{
UINT32 FR = PcdGet32 (PcdGdbUartBase) + UARTFR;
UINT32 DR = PcdGet32 (PcdGdbUartBase) + UARTDR;
while ((MmioRead32 (FR) & UART_TX_EMPTY_FLAG_MASK) != 0);
MmioWrite8 (DR, Char);
- return; -} - -VOID -GdbPutString ( - IN CHAR8 *String - ) -{ - while (*String != '\0') { - GdbPutChar (*String); - String++; - } -} + return;
+}
+
+VOID
+GdbPutString (
+ IN CHAR8 *String
+ )
+{
+ while (*String != '\0') {
+ GdbPutChar (*String);
+ String++;
+ }
+}
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc index fc158234a9..34e3d9929d 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc @@ -136,6 +136,7 @@ [LibraryClasses.common.SEC] ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibSec.inf ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressSecLib.inf + DebugSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf @@ -284,10 +285,18 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE -!if $(EDK2_SKIP_PEICORE) == 1 - gArmTokenSpaceGuid.PcdSkipPeiCore|TRUE +!if $(EDK2_ARMVE_STANDALONE) == 1 + gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE +!else + gArmPlatformTokenSpaceGuid.PcdStandalone|FALSE + gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE + gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE !endif +!if $(EDK2_SKIP_PEICORE) == 1 + gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE + gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE +!endif ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. # It could be set FALSE to save size. @@ -377,10 +386,6 @@ gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|1 gArmTokenSpaceGuid.PcdVFPEnabled|1 -!if $(EDK2_ARMVE_STANDALONE) == 1 - gArmPlatformTokenSpaceGuid.PcdStandalone|1 -!endif - # Stacks for MPCores in Secure World gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x49E00000 # Top of SEC Stack for Secure World gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize|0x2000 # Stack for each of the 4 CPU cores @@ -493,7 +498,10 @@ ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf } !else - ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf { + <LibraryClasses> + PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf + } MdeModulePkg/Core/Pei/PeiMain.inf MdeModulePkg/Universal/PCD/Pei/Pcd.inf { <LibraryClasses> diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf index f160622d78..d3867ae931 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf @@ -42,15 +42,11 @@ CTA9x4Helper.asm | RVCT CTA9x4Helper.S | GCC -[Protocols] - [FeaturePcd] gEmbeddedTokenSpaceGuid.PcdCacheEnable gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping [FixedPcd] - gArmPlatformTokenSpaceGuid.PcdStandalone - gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressSecLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressSecLib.inf index 3f08784ff5..8674f7923b 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressSecLib.inf +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressSecLib.inf @@ -30,6 +30,7 @@ ArmLib
ArmTrustZoneLib
ArmPlatformSysConfigLib
+ DebugSecExtraActionLib
IoLib
L2X0CacheLib
PL301AxiLib
@@ -45,13 +46,9 @@ CTA9x4Boot.asm | RVCT
CTA9x4Boot.S | GCC
-[Protocols]
-
[FeaturePcd]
gEmbeddedTokenSpaceGuid.PcdCacheEnable
gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
[FixedPcd]
- gArmPlatformTokenSpaceGuid.PcdStandalone
-
gArmTokenSpaceGuid.PcdL2x0ControllerBase
diff --git a/ArmPlatformPkg/Bds/BootMenu.c b/ArmPlatformPkg/Bds/BootMenu.c index 1e25c1e72e..91550df9d4 100644 --- a/ArmPlatformPkg/Bds/BootMenu.c +++ b/ArmPlatformPkg/Bds/BootMenu.c @@ -405,7 +405,7 @@ BootMenuMain ( BootOption = NULL;
BootMainEntryCount = sizeof(BootMainEntries) / sizeof(struct BOOT_MAIN_ENTRY);
- +
// Get Boot#### list
BootOptionList (&BootOptionsList);
diff --git a/ArmPlatformPkg/Include/Library/ArmPlatformLib.h b/ArmPlatformPkg/Include/Library/ArmPlatformLib.h index ba0f8520b7..c49812560e 100644 --- a/ArmPlatformPkg/Include/Library/ArmPlatformLib.h +++ b/ArmPlatformPkg/Include/Library/ArmPlatformLib.h @@ -95,6 +95,19 @@ ArmPlatformSecInitialize ( ); /** + Call before jumping to Normal World + + This function allows the firmware platform to do extra actions before + jumping to the Normal World + +**/ +VOID +ArmPlatformSecExtraAction ( + IN UINTN CoreId, + OUT UINTN* JumpAddress + ); + +/** Initialize controllers that must setup in the normal world This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei diff --git a/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c b/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c new file mode 100755 index 0000000000..2d9595f885 --- /dev/null +++ b/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c @@ -0,0 +1,103 @@ +/** @file
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <PiPei.h>
+
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PrintLib.h>
+#include <Library/SerialPortLib.h>
+
+#include <Drivers/PL390Gic.h>
+
+#define ARM_PRIMARY_CORE 0
+
+// When the firmware is built as not Standalone, the secondary cores need to wait the firmware
+// entirely written into DRAM. It is the firmware from DRAM which will wake up the secondary cores.
+VOID
+NonSecureWaitForFirmware (
+ VOID
+ )
+{
+ VOID (*secondary_start)(VOID);
+
+ // The secondary cores will execute the firmware once wake from WFI.
+ secondary_start = (VOID (*)())PcdGet32(PcdNormalFvBaseAddress);
+
+ ArmCallWFI();
+
+ // Acknowledge the interrupt and send End of Interrupt signal.
+ PL390GicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), ARM_PRIMARY_CORE);
+
+ // Jump to secondary core entry point.
+ secondary_start ();
+
+ // PEI Core should always load and never return
+ ASSERT (FALSE);
+}
+
+/**
+ Call before jumping to Normal World
+
+ This function allows the firmware platform to do extra actions before
+ jumping to the Normal World
+
+**/
+VOID
+ArmPlatformSecExtraAction (
+ IN UINTN CoreId,
+ OUT UINTN* JumpAddress
+ )
+{
+ CHAR8 Buffer[100];
+ UINTN CharCount;
+
+ if (FeaturePcdGet (PcdStandalone) == FALSE) {
+ if (CoreId == ARM_PRIMARY_CORE) {
+ UINTN* StartAddress = (UINTN*)PcdGet32(PcdNormalFvBaseAddress);
+
+ // Patch the DRAM to make an infinite loop at the start address
+ *StartAddress = 0xEAFFFFFE; // opcode for while(1)
+
+ CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Waiting for firmware at 0x%08X ...\n\r",StartAddress);
+ SerialPortWrite ((UINT8 *) Buffer, CharCount);
+
+ *JumpAddress = PcdGet32(PcdNormalFvBaseAddress);
+ } else {
+ // When the primary core is stopped by the hardware debugger to copy the firmware
+ // into DRAM. The secondary cores are still running. As soon as the first bytes of
+ // the firmware are written into DRAM, the secondary cores will start to execute the
+ // code even if the firmware is not entirely written into the memory.
+ // That's why the secondary cores need to be parked in WFI and wake up once the
+ // firmware is ready.
+
+ *JumpAddress = (UINTN)NonSecureWaitForFirmware;
+ }
+ } else if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) {
+ if (CoreId == ARM_PRIMARY_CORE) {
+ // Signal the secondary cores they can jump to PEI phase
+ PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
+
+ // To enter into Non Secure state, we need to make a return from exception
+ *JumpAddress = PcdGet32(PcdNormalFvBaseAddress);
+ } else {
+ // We wait for the primary core to finish to initialize the System Memory. Otherwise the secondary
+ // cores would make crash the system by setting their stacks in DRAM before the primary core has not
+ // finished to initialize the system memory.
+ *JumpAddress = (UINTN)NonSecureWaitForFirmware;
+ }
+ } else {
+ *JumpAddress = PcdGet32(PcdNormalFvBaseAddress);
+ }
+}
diff --git a/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf b/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf new file mode 100755 index 0000000000..4b5df2887c --- /dev/null +++ b/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf @@ -0,0 +1,51 @@ +#/* @file +# Copyright (c) 2011, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#*/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = DebugSecExtraActionLib + FILE_GUID = 8fff7a60-a6f8-11e0-990a-0002a5d5c51b + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = DebugSecExtraActionLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = ARM +# + +[Sources.common] + DebugSecExtraActionLib.c + +[Packages] + MdePkg/MdePkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + +[LibraryClasses] + DebugLib + PcdLib + PL390GicSecLib + PrintLib + SerialPortLib + +[FeaturePcd] + gArmPlatformTokenSpaceGuid.PcdStandalone + gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec + +[FixedPcd] + gArmTokenSpaceGuid.PcdNormalFvBaseAddress + + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase diff --git a/ArmPlatformPkg/PrePeiCore/Exception.S b/ArmPlatformPkg/PrePeiCore/Exception.S index 159a4d0578..abce21d0a5 100644 --- a/ArmPlatformPkg/PrePeiCore/Exception.S +++ b/ArmPlatformPkg/PrePeiCore/Exception.S @@ -1,102 +1,102 @@ -// -// Copyright (c) 2011, ARM Limited. All rights reserved. -// -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -# - -#include <AsmMacroIoLib.h> -#include <Base.h> -#include <AutoGen.h> - -#start of the code section -.text +//
+// Copyright (c) 2011, ARM Limited. All rights reserved.
+//
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+#include <AsmMacroIoLib.h>
+#include <Base.h>
+#include <AutoGen.h>
+
+#start of the code section
+.text
.align 5
-# IMPORT -GCC_ASM_IMPORT(PeiCommonExceptionEntry) - -# EXPORT -GCC_ASM_EXPORT(PeiVectorTable) +# IMPORT
+GCC_ASM_IMPORT(PeiCommonExceptionEntry)
+
+# EXPORT
+GCC_ASM_EXPORT(PeiVectorTable)
+
+//============================================================
+//Default Exception Handlers
+//============================================================
+
+
+ASM_PFX(PeiVectorTable):
+ b _DefaultResetHandler
+ b _DefaultUndefined
+ b _DefaultSWI
+ b _DefaultPrefetchAbort
+ b _DefaultDataAbort
+ b _DefaultReserved
+ b _DefaultIrq
+ b _DefaultFiq
+
+//
+// Default Exception handlers: There is no plan to return from any of these exceptions.
+// No context saving at all.
+//
+_DefaultResetHandler:
+ mov r1, lr
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #0
+ blx ASM_PFX(PeiCommonExceptionEntry)
+
+_DefaultUndefined:
+ sub r1, LR, #4
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #1
+ blx ASM_PFX(PeiCommonExceptionEntry)
+
+_DefaultSWI:
+ sub r1, LR, #4
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #2
+ blx ASM_PFX(PeiCommonExceptionEntry)
+
+_DefaultPrefetchAbort:
+ sub r1, LR, #4
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #3
+ blx ASM_PFX(PeiCommonExceptionEntry)
+
+_DefaultDataAbort:
+ sub r1, LR, #8
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #4
+ blx ASM_PFX(PeiCommonExceptionEntry)
+
+_DefaultReserved:
+ mov r1, lr
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #5
+ blx ASM_PFX(PeiCommonExceptionEntry)
+
+_DefaultIrq:
+ sub r1, LR, #4
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #6
+ blx ASM_PFX(PeiCommonExceptionEntry)
-//============================================================ -//Default Exception Handlers -//============================================================ - - -ASM_PFX(PeiVectorTable): - b _DefaultResetHandler - b _DefaultUndefined - b _DefaultSWI - b _DefaultPrefetchAbort - b _DefaultDataAbort - b _DefaultReserved - b _DefaultIrq - b _DefaultFiq - -// -// Default Exception handlers: There is no plan to return from any of these exceptions. -// No context saving at all. -// -_DefaultResetHandler: - mov r1, lr - # Switch to SVC for common stack - cps #0x13 - mov r0, #0 - blx ASM_PFX(PeiCommonExceptionEntry) - -_DefaultUndefined: - sub r1, LR, #4 - # Switch to SVC for common stack - cps #0x13 - mov r0, #1 - blx ASM_PFX(PeiCommonExceptionEntry) - -_DefaultSWI: - sub r1, LR, #4 - # Switch to SVC for common stack - cps #0x13 - mov r0, #2 - blx ASM_PFX(PeiCommonExceptionEntry) - -_DefaultPrefetchAbort: - sub r1, LR, #4 - # Switch to SVC for common stack - cps #0x13 - mov r0, #3 - blx ASM_PFX(PeiCommonExceptionEntry) - -_DefaultDataAbort: - sub r1, LR, #8 - # Switch to SVC for common stack - cps #0x13 - mov r0, #4 - blx ASM_PFX(PeiCommonExceptionEntry) - -_DefaultReserved: - mov r1, lr - # Switch to SVC for common stack - cps #0x13 - mov r0, #5 - blx ASM_PFX(PeiCommonExceptionEntry) - -_DefaultIrq: - sub r1, LR, #4 - # Switch to SVC for common stack - cps #0x13 - mov r0, #6 - blx ASM_PFX(PeiCommonExceptionEntry) - -_DefaultFiq: - sub r1, LR, #4 - # Switch to SVC for common stack - cps #0x13 - mov r0, #7 - blx ASM_PFX(PeiCommonExceptionEntry) +_DefaultFiq:
+ sub r1, LR, #4
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #7
+ blx ASM_PFX(PeiCommonExceptionEntry)
diff --git a/ArmPlatformPkg/PrePeiCore/Exception.asm b/ArmPlatformPkg/PrePeiCore/Exception.asm index 16e0d9d14c..55bd4af1dd 100644 --- a/ArmPlatformPkg/PrePeiCore/Exception.asm +++ b/ArmPlatformPkg/PrePeiCore/Exception.asm @@ -21,71 +21,71 @@ PRESERVE8
AREA PrePeiCoreException, CODE, READONLY, CODEALIGN, ALIGN=5
-//============================================================ -//Default Exception Handlers -//============================================================ - - -PeiVectorTable - b _DefaultResetHandler - b _DefaultUndefined - b _DefaultSWI - b _DefaultPrefetchAbort - b _DefaultDataAbort - b _DefaultReserved - b _DefaultIrq - b _DefaultFiq - +//============================================================
+//Default Exception Handlers
+//============================================================
+
+
+PeiVectorTable
+ b _DefaultResetHandler
+ b _DefaultUndefined
+ b _DefaultSWI
+ b _DefaultPrefetchAbort
+ b _DefaultDataAbort
+ b _DefaultReserved
+ b _DefaultIrq
+ b _DefaultFiq
+
//
// Default Exception handlers: There is no plan to return from any of these exceptions.
-// No context saving at all. +// No context saving at all.
//
-_DefaultResetHandler +_DefaultResetHandler
mov r1, lr
- cps #0x13 ; Switch to SVC for common stack - mov r0, #0 - blx PeiCommonExceptionEntry - -_DefaultUndefined + cps #0x13 ; Switch to SVC for common stack
+ mov r0, #0
+ blx PeiCommonExceptionEntry
+
+_DefaultUndefined
sub r1, LR, #4
- cps #0x13 ; Switch to SVC for common stack - mov r0, #1 - blx PeiCommonExceptionEntry - -_DefaultSWI + cps #0x13 ; Switch to SVC for common stack
+ mov r0, #1
+ blx PeiCommonExceptionEntry
+
+_DefaultSWI
sub r1, LR, #4
- cps #0x13 ; Switch to SVC for common stack - mov r0, #2 - blx PeiCommonExceptionEntry - -_DefaultPrefetchAbort + cps #0x13 ; Switch to SVC for common stack
+ mov r0, #2
+ blx PeiCommonExceptionEntry
+
+_DefaultPrefetchAbort
sub r1, LR, #4
- cps #0x13 ; Switch to SVC for common stack - mov r0, #3 - blx PeiCommonExceptionEntry - -_DefaultDataAbort + cps #0x13 ; Switch to SVC for common stack
+ mov r0, #3
+ blx PeiCommonExceptionEntry
+
+_DefaultDataAbort
sub r1, LR, #8
- cps #0x13 ; Switch to SVC for common stack - mov r0, #4 - blx PeiCommonExceptionEntry - -_DefaultReserved + cps #0x13 ; Switch to SVC for common stack
+ mov r0, #4
+ blx PeiCommonExceptionEntry
+
+_DefaultReserved
mov r1, lr
- cps #0x13 ; Switch to SVC for common stack - mov r0, #5 - blx PeiCommonExceptionEntry - -_DefaultIrq + cps #0x13 ; Switch to SVC for common stack
+ mov r0, #5
+ blx PeiCommonExceptionEntry
+
+_DefaultIrq
sub r1, LR, #4
- cps #0x13 ; Switch to SVC for common stack - mov r0, #6 - blx PeiCommonExceptionEntry - -_DefaultFiq + cps #0x13 ; Switch to SVC for common stack
+ mov r0, #6
+ blx PeiCommonExceptionEntry
+
+_DefaultFiq
sub r1, LR, #4
- cps #0x13 ; Switch to SVC for common stack - mov r0, #7 - blx PeiCommonExceptionEntry + cps #0x13 ; Switch to SVC for common stack
+ mov r0, #7
+ blx PeiCommonExceptionEntry
END
diff --git a/ArmPlatformPkg/PrePeiCore/MainMPCore.c b/ArmPlatformPkg/PrePeiCore/MainMPCore.c index 17a0002dee..35c41540f4 100644 --- a/ArmPlatformPkg/PrePeiCore/MainMPCore.c +++ b/ArmPlatformPkg/PrePeiCore/MainMPCore.c @@ -69,7 +69,7 @@ PrimaryMain ( PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));
// If ArmVe has not been built as Standalone then we need to wake up the secondary cores
- if (!PcdGet32(PcdStandalone)) {
+ if (FeaturePcdGet(PcdSendSgiToBringUpSecondaryCores)) {
// Sending SGI to all the Secondary CPU interfaces
PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
}
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c index ccf0e7d3d4..0b7f973d53 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c @@ -16,6 +16,7 @@ #include <Library/IoLib.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
+#include <Library/DebugAgentLib.h>
#include <Library/PrintLib.h>
#include <Library/ArmLib.h>
#include <Library/SerialPortLib.h>
@@ -62,7 +63,11 @@ CEntryPoint ( //If not primary Jump to Secondary Main
if(0 == CoreId) {
- //Goto primary Main.
+ // Initialize the Debug Agent for Source Level Debugging
+ InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
+ SaveAndSetDebugTimerInterrupt (TRUE);
+
+ // Goto primary Main.
PrimaryMain (PeiCoreEntryPoint);
} else {
SecondaryMain (CoreId);
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf index bcde6c4b10..8c255443af 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf @@ -42,6 +42,7 @@ ArmMPCoreMailBoxLib
BaseLib
DebugLib
+ DebugAgentLib
IoLib
PL390GicNonSecLib
PrintLib
@@ -50,9 +51,10 @@ [Ppis]
gEfiTemporaryRamSupportPpiGuid
-[FixedPcd]
- gArmPlatformTokenSpaceGuid.PcdStandalone
+[FeaturePcd]
+ gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores
+[FixedPcd]
gArmTokenSpaceGuid.PcdNormalFvBaseAddress
gArmTokenSpaceGuid.PcdNormalFvSize
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf b/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf index 5b0886d0dd..f37bcb0751 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf @@ -41,16 +41,17 @@ ArmPlatformLib
BaseLib
DebugLib
+ DebugAgentLib
IoLib
PrintLib
- SerialPortLib
[Ppis]
gEfiTemporaryRamSupportPpiGuid
-[FixedPcd]
- gArmPlatformTokenSpaceGuid.PcdStandalone
+[FeaturePcd]
+ gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores
+[FixedPcd]
gArmTokenSpaceGuid.PcdNormalFvBaseAddress
gArmTokenSpaceGuid.PcdNormalFvSize
diff --git a/ArmPlatformPkg/PrePi/PeiMPCore.inf b/ArmPlatformPkg/PrePi/PeiMPCore.inf index 256fcafee9..c7d18d4394 100755 --- a/ArmPlatformPkg/PrePi/PeiMPCore.inf +++ b/ArmPlatformPkg/PrePi/PeiMPCore.inf @@ -59,9 +59,9 @@ [FeaturePcd] gEmbeddedTokenSpaceGuid.PcdCacheEnable gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob + gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores [FixedPcd] - gArmPlatformTokenSpaceGuid.PcdStandalone gArmTokenSpaceGuid.PcdVFPEnabled gArmTokenSpaceGuid.PcdNormalFdBaseAddress diff --git a/ArmPlatformPkg/PrePi/PeiUniCore.inf b/ArmPlatformPkg/PrePi/PeiUniCore.inf index c28fe3c6cb..3af265576e 100755 --- a/ArmPlatformPkg/PrePi/PeiUniCore.inf +++ b/ArmPlatformPkg/PrePi/PeiUniCore.inf @@ -57,9 +57,9 @@ [FeaturePcd] gEmbeddedTokenSpaceGuid.PcdCacheEnable gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob + gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores [FixedPcd] - gArmPlatformTokenSpaceGuid.PcdStandalone gArmTokenSpaceGuid.PcdVFPEnabled gArmTokenSpaceGuid.PcdNormalFdBaseAddress diff --git a/ArmPlatformPkg/Sec/Exception.asm b/ArmPlatformPkg/Sec/Exception.asm index ef8629a897..cf3825bc6a 100644 --- a/ArmPlatformPkg/Sec/Exception.asm +++ b/ArmPlatformPkg/Sec/Exception.asm @@ -21,71 +21,71 @@ PRESERVE8
AREA SecException, CODE, READONLY, CODEALIGN, ALIGN=5
-//============================================================ -//Default Exception Handlers -//============================================================ - - -SecVectorTable - b _DefaultResetHandler - b _DefaultUndefined - b _DefaultSWI - b _DefaultPrefetchAbort - b _DefaultDataAbort - b _DefaultReserved - b _DefaultIrq - b _DefaultFiq +//============================================================
+//Default Exception Handlers
+//============================================================
+
+
+SecVectorTable
+ b _DefaultResetHandler
+ b _DefaultUndefined
+ b _DefaultSWI
+ b _DefaultPrefetchAbort
+ b _DefaultDataAbort
+ b _DefaultReserved
+ b _DefaultIrq
+ b _DefaultFiq
-// +//
// Default Exception handlers: There is no plan to return from any of these exceptions.
// No context saving at all.
-// -_DefaultResetHandler +//
+_DefaultResetHandler
mov r1, lr
- cps #0x13 ; Switch to SVC for common stack - mov r0, #0 - blx SecCommonExceptionEntry - -_DefaultUndefined + cps #0x13 ; Switch to SVC for common stack
+ mov r0, #0
+ blx SecCommonExceptionEntry
+
+_DefaultUndefined
sub r1, LR
- cps #0x13 ; Switch to SVC for common stack - mov r0, #1 - blx SecCommonExceptionEntry - -_DefaultSWI + cps #0x13 ; Switch to SVC for common stack
+ mov r0, #1
+ blx SecCommonExceptionEntry
+
+_DefaultSWI
sub r1, LR, #4
- cps #0x13 ; Switch to SVC for common stack - mov r0, #2 - blx SecCommonExceptionEntry - -_DefaultPrefetchAbort + cps #0x13 ; Switch to SVC for common stack
+ mov r0, #2
+ blx SecCommonExceptionEntry
+
+_DefaultPrefetchAbort
sub r1, LR, #4
- cps #0x13 ; Switch to SVC for common stack - mov r0, #3 - blx SecCommonExceptionEntry - -_DefaultDataAbort + cps #0x13 ; Switch to SVC for common stack
+ mov r0, #3
+ blx SecCommonExceptionEntry
+
+_DefaultDataAbort
sub r1, LR, #8
- cps #0x13 ; Switch to SVC for common stack - mov r0, #4 - blx SecCommonExceptionEntry - -_DefaultReserved + cps #0x13 ; Switch to SVC for common stack
+ mov r0, #4
+ blx SecCommonExceptionEntry
+
+_DefaultReserved
mov r1, lr
- cps #0x13 ; Switch to SVC for common stack - mov r0, #5 - blx SecCommonExceptionEntry - -_DefaultIrq + cps #0x13 ; Switch to SVC for common stack
+ mov r0, #5
+ blx SecCommonExceptionEntry
+
+_DefaultIrq
sub r1, LR, #4
- cps #0x13 ; Switch to SVC for common stack - mov r0, #6 - blx SecCommonExceptionEntry - -_DefaultFiq + cps #0x13 ; Switch to SVC for common stack
+ mov r0, #6
+ blx SecCommonExceptionEntry
+
+_DefaultFiq
sub r1, LR, #4
- cps #0x13 ; Switch to SVC for common stack - mov r0, #7 - blx SecCommonExceptionEntry + cps #0x13 ; Switch to SVC for common stack
+ mov r0, #7
+ blx SecCommonExceptionEntry
END
diff --git a/ArmPlatformPkg/Sec/Sec.c b/ArmPlatformPkg/Sec/Sec.c index 8ddc654c24..42df66ea20 100644 --- a/ArmPlatformPkg/Sec/Sec.c +++ b/ArmPlatformPkg/Sec/Sec.c @@ -14,6 +14,7 @@ **/ #include <Library/DebugLib.h> +#include <Library/DebugAgentLib.h> #include <Library/PcdLib.h> #include <Library/PrintLib.h> #include <Library/BaseLib.h> @@ -70,6 +71,7 @@ CEntryPoint ( { CHAR8 Buffer[100]; UINTN CharCount; + UINTN JumpAddress; // Primary CPU clears out the SCU tag RAMs, secondaries wait if (CoreId == ARM_PRIMARY_CORE) { @@ -85,6 +87,10 @@ CEntryPoint ( CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware built at %a on %a\n\r",__TIME__, __DATE__); SerialPortWrite ((UINT8 *) Buffer, CharCount); + // Initialize the Debug Agent for Source Level Debugging + InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL); + SaveAndSetDebugTimerInterrupt (TRUE); + // Now we've got UART, make the check: // - The Vector table must be 32-byte aligned ASSERT(((UINT32)SecVectorTable & ((1 << 5)-1)) == 0); @@ -119,7 +125,7 @@ CEntryPoint ( // If we skip the PEI Core we could want to initialize the DRAM in the SEC phase. // If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM - if (FeaturePcdGet(PcdSkipPeiCore) || !PcdGet32(PcdStandalone)) { + if (FeaturePcdGet(PcdSystemMemoryInitializeInSec)) { // Initialize system memory (DRAM) ArmPlatformInitializeSystemMemory (); } @@ -155,7 +161,7 @@ CEntryPoint ( // PL390GicEnableDistributor (PcdGet32(PcdGicDistributorBase)); - PL390GicEnableInterruptInterface(PcdGet32(PcdGicInterruptInterfaceBase)); + PL390GicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase)); // Send SGI to all Secondary core to wake them up from WFI state. PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E); @@ -170,11 +176,11 @@ CEntryPoint ( ArmCallWFI(); // Acknowledge the interrupt and send End of Interrupt signal. - PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase), ARM_PRIMARY_CORE); + PL390GicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), ARM_PRIMARY_CORE); } // Transfer the interrupt to Non-secure World - PL390GicSetupNonSecure(PcdGet32(PcdGicDistributorBase),PcdGet32(PcdGicInterruptInterfaceBase)); + PL390GicSetupNonSecure (PcdGet32(PcdGicDistributorBase),PcdGet32(PcdGicInterruptInterfaceBase)); // Write to CP15 Non-secure Access Control Register : // - Enable CP10 and CP11 accesses in NS World @@ -195,84 +201,24 @@ CEntryPoint ( if (CoreId == ARM_PRIMARY_CORE) { PL390GicEnableDistributor (PcdGet32(PcdGicDistributorBase)); } - PL390GicEnableInterruptInterface(PcdGet32(PcdGicInterruptInterfaceBase)); + PL390GicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase)); // With Trustzone support the transition from Sec to Normal world is done by return_from_exception(). // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program // Status Register as the the current one (CPSR). - copy_cpsr_into_spsr(); + copy_cpsr_into_spsr (); } - // If ArmVe has not been built as Standalone then we need to patch the DRAM to add an infinite loop at the start address - if (!PcdGet32(PcdStandalone)) { - if (CoreId == ARM_PRIMARY_CORE) { - UINTN* StartAddress = (UINTN*)PcdGet32(PcdNormalFvBaseAddress); - - // Patch the DRAM to make an infinite loop at the start address - *StartAddress = 0xEAFFFFFE; // opcode for while(1) - - CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Waiting for firmware at 0x%08X ...\n\r",StartAddress); - SerialPortWrite ((UINT8 *) Buffer, CharCount); - - // To enter into Non Secure state, we need to make a return from exception - return_from_exception(PcdGet32(PcdNormalFvBaseAddress)); - } else { - // When the primary core is stopped by the hardware debugger to copy the firmware - // into DRAM. The secondary cores are still running. As soon as the first bytes of - // the firmware are written into DRAM, the secondary cores will start to execute the - // code even if the firmware is not entirely written into the memory. - // That's why the secondary cores need to be parked in WFI and wake up once the - // firmware is ready. - - // Enter Secondary Cores into non Secure State. To enter into Non Secure state, we need to make a return from exception - return_from_exception((UINTN)NonSecureWaitForFirmware); - } - } else if (FeaturePcdGet(PcdSkipPeiCore)) { - if (CoreId == ARM_PRIMARY_CORE) { - // Signal the secondary cores they can jump to PEI phase - PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E); + JumpAddress = PcdGet32 (PcdNormalFvBaseAddress); + ArmPlatformSecExtraAction (CoreId, &JumpAddress); - // To enter into Non Secure state, we need to make a return from exception - return_from_exception(PcdGet32(PcdNormalFvBaseAddress)); - } else { - // We wait for the primary core to finish to initialize the System Memory. When we skip PEI Core, we could set the stack in DRAM - // Without this synchronization the secondary cores will complete the SEC before the primary core has finished to intitialize the DRAM. - return_from_exception((UINTN)NonSecureWaitForFirmware); - } - } else { - // To enter into Non Secure state, we need to make a return from exception - return_from_exception(PcdGet32(PcdNormalFvBaseAddress)); - } + return_from_exception (JumpAddress); //-------------------- Non Secure Mode --------------------- // PEI Core should always load and never return ASSERT (FALSE); } -// When the firmware is built as not Standalone, the secondary cores need to wait the firmware -// entirely written into DRAM. It is the firmware from DRAM which will wake up the secondary cores. -VOID -NonSecureWaitForFirmware ( - VOID - ) -{ - VOID (*secondary_start)(VOID); - - // The secondary cores will execute the firmware once wake from WFI. - secondary_start = (VOID (*)())PcdGet32(PcdNormalFvBaseAddress); - - ArmCallWFI(); - - // Acknowledge the interrupt and send End of Interrupt signal. - PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),ARM_PRIMARY_CORE); - - // Jump to secondary core entry point. - secondary_start(); - - // PEI Core should always load and never return - ASSERT (FALSE); -} - VOID SecCommonExceptionEntry ( IN UINT32 Entry, diff --git a/ArmPlatformPkg/Sec/Sec.inf b/ArmPlatformPkg/Sec/Sec.inf index 974c31a2fb..23dee117d3 100644 --- a/ArmPlatformPkg/Sec/Sec.inf +++ b/ArmPlatformPkg/Sec/Sec.inf @@ -40,16 +40,16 @@ ArmPlatformLib BaseLib DebugLib + DebugAgentLib IoLib PL390GicSecLib PrintLib SerialPortLib [FeaturePcd] - gArmTokenSpaceGuid.PcdSkipPeiCore + gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec [FixedPcd] - gArmPlatformTokenSpaceGuid.PcdStandalone gArmTokenSpaceGuid.PcdVFPEnabled gArmPlatformTokenSpaceGuid.PcdMPCoreSupport |