diff options
Diffstat (limited to 'BraswellPlatformPkg/Common/Silicon')
7 files changed, 1238 insertions, 0 deletions
diff --git a/BraswellPlatformPkg/Common/Silicon/WinbondSio/Wpce791/LpcDriver.c b/BraswellPlatformPkg/Common/Silicon/WinbondSio/Wpce791/LpcDriver.c new file mode 100644 index 0000000000..2722524b6c --- /dev/null +++ b/BraswellPlatformPkg/Common/Silicon/WinbondSio/Wpce791/LpcDriver.c @@ -0,0 +1,333 @@ +/** @file
+ EFI Lpc Driver for a Generic PC Platform.
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "LpcDriver.h"
+#include "IndustryStandard/Pci22.h"
+
+//
+// This driver is for ACPI(PNP0A03,0)/PCI(0x1f,0)
+//
+
+//
+// Lpc Driver Global Variables
+//
+
+EFI_DRIVER_BINDING_PROTOCOL gLpcDriver = {
+ LpcDriverSupported,
+ LpcDriverStart,
+ LpcDriverStop,
+ 0x10,
+ NULL,
+ NULL
+};
+
+LPC_DEV mLpc = {
+ LPC_DEV_SIGNATURE,
+ NULL,
+ {
+ IsaDeviceEnumerate,
+ IsaDeviceSetPower,
+ IsaGetCurrentResource,
+ IsaGetPossibleResource,
+ IsaSetResource,
+ IsaEnableDevice,
+ IsaInitDevice,
+ LpcInterfaceInit
+ },
+ NULL
+};
+
+BOOLEAN InitExecuted = FALSE;
+
+/**
+ The entry point of the Lpc driver.
+
+**/
+EFI_STATUS
+EFIAPI
+LpcDriverEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ return EfiLibInstallDriverBinding (ImageHandle, SystemTable, &gLpcDriver, ImageHandle);
+}
+
+/**
+ ControllerDriver Protocol Method.
+
+**/
+EFI_STATUS
+EFIAPI
+LpcDriverSupported (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ )
+{
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_DEVICE_PATH_PROTOCOL *IsaBridgeDevicePath;
+ ACPI_HID_DEVICE_PATH *AcpiNode;
+ PCI_DEVICE_PATH *PciNode;
+ PCI_TYPE00 Pci;
+
+ //
+ // Get the ISA bridge's Device Path and test it
+ // the following code is specific
+ //
+ Status = gBS->OpenProtocol (
+ Controller,
+ &gEfiDevicePathProtocolGuid,
+ (VOID **) &IsaBridgeDevicePath,
+ This->DriverBindingHandle,
+ Controller,
+ EFI_OPEN_PROTOCOL_BY_DRIVER
+ );
+
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = EFI_SUCCESS;
+ AcpiNode = (ACPI_HID_DEVICE_PATH *) IsaBridgeDevicePath;
+ if (AcpiNode->Header.Type != ACPI_DEVICE_PATH ||
+ AcpiNode->Header.SubType != ACPI_DP ||
+ DevicePathNodeLength (&AcpiNode->Header) != sizeof (ACPI_HID_DEVICE_PATH) ||
+ AcpiNode -> HID != EISA_PNP_ID(0x0A03) ||
+ AcpiNode -> UID != 0 ) {
+ Status = EFI_UNSUPPORTED;
+ } else {
+ //
+ // Get the next node
+ //
+ IsaBridgeDevicePath = NextDevicePathNode (IsaBridgeDevicePath);
+ PciNode = (PCI_DEVICE_PATH *) IsaBridgeDevicePath;
+ if (PciNode->Header.Type != HARDWARE_DEVICE_PATH ||
+ PciNode->Header.SubType != HW_PCI_DP ||
+ DevicePathNodeLength (&PciNode->Header) != sizeof (PCI_DEVICE_PATH) ||
+ PciNode -> Function != 0x00 ||
+ PciNode -> Device != 0x1f ) {
+ Status = EFI_UNSUPPORTED;
+ }
+ }
+
+ gBS->CloseProtocol (
+ Controller,
+ &gEfiDevicePathProtocolGuid,
+ This->DriverBindingHandle,
+ Controller
+ );
+
+ if (EFI_ERROR (Status)) {
+ return EFI_UNSUPPORTED;
+ }
+
+ //
+ // Get PciIo protocol instance
+ //
+ Status = gBS->OpenProtocol (
+ Controller,
+ &gEfiPciIoProtocolGuid,
+ (VOID **) &PciIo,
+ This->DriverBindingHandle,
+ Controller,
+ EFI_OPEN_PROTOCOL_BY_DRIVER
+ );
+
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint32,
+ 0,
+ sizeof (Pci) / sizeof (UINT32),
+ &Pci
+ );
+
+ if (!EFI_ERROR (Status)) {
+ Status = EFI_SUCCESS; //TODO: force return success as temp solution EFI_UNSUPPORTED;
+ if ((Pci.Hdr.Command & 0x03) == 0x03) {
+ if (Pci.Hdr.ClassCode[2] == PCI_CLASS_BRIDGE) {
+ //
+ // See if this is a standard PCI to ISA Bridge from the Base Code
+ // and Class Code
+ //
+ if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA) {
+ Status = EFI_SUCCESS;
+ } else {
+ }
+
+ //
+ // See if this is an Intel PCI to ISA bridge in Positive Decode Mode
+ //
+ if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA_PDECODE &&
+ Pci.Hdr.VendorId == 0x8086 &&
+ Pci.Hdr.DeviceId == 0x7110) {
+ Status = EFI_SUCCESS;
+ } else {
+ }
+ } else {
+ }
+ }
+ else {
+ }
+ }
+
+ gBS->CloseProtocol (
+ Controller,
+ &gEfiPciIoProtocolGuid,
+ This->DriverBindingHandle,
+ Controller
+ );
+
+ return Status;
+}
+
+/**
+ Install EFI_ISA_ACPI_PROTOCOL
+
+**/
+EFI_STATUS
+EFIAPI
+LpcDriverStart (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ )
+{
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ LPC_DEV *LpcDev;
+
+ LpcDev = NULL;
+
+ //
+ // Get Pci IO
+ //
+ Status = gBS->OpenProtocol (
+ Controller,
+ &gEfiPciIoProtocolGuid,
+ (VOID **) &PciIo,
+ This->DriverBindingHandle,
+ Controller,
+ EFI_OPEN_PROTOCOL_BY_DRIVER
+ );
+
+ if (EFI_ERROR (Status) && Status != EFI_ALREADY_STARTED) {
+ return Status;
+ }
+
+ mLpc.PciIo = PciIo;
+
+ //
+ // Install IsaAcpi interface, the Sio interface is not installed!
+ //
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Controller,
+ &gEfiIsaAcpiProtocolGuid,
+ &mLpc.IsaAcpi,
+ NULL
+ );
+
+ return Status;
+}
+
+EFI_STATUS
+EFIAPI
+LpcDriverStop (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
+ )
+{
+ EFI_STATUS Status;
+ EFI_ISA_ACPI_PROTOCOL *IsaAcpi;
+ LPC_DEV *LpcDev;
+
+ //
+ // Get EFI_ISA_ACPI_PROTOCOL interface
+ //
+ Status = gBS->OpenProtocol (
+ Controller,
+ &gEfiIsaAcpiProtocolGuid,
+ (VOID **) &IsaAcpi,
+ This->DriverBindingHandle,
+ Controller,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ LpcDev = LPC_ISA_ACPI_FROM_THIS (IsaAcpi);
+
+ //
+ // Uninstall protocol interface: EFI_ISA_ACPI_PROTOCOL
+ //
+ Status = gBS->UninstallProtocolInterface (
+ Controller,
+ &gEfiIsaAcpiProtocolGuid,
+ &LpcDev->IsaAcpi
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ gBS->CloseProtocol (
+ Controller,
+ &gEfiPciIoProtocolGuid,
+ This->DriverBindingHandle,
+ Controller
+ );
+
+ return EFI_SUCCESS;
+}
+
+VOID
+LpcIoRead8 (
+ IN UINT16 Port,
+ OUT UINT8 *Data
+ )
+{
+ mLpc.PciIo->Io.Read(
+ mLpc.PciIo,
+ EfiPciWidthUint8,
+ EFI_PCI_IO_PASS_THROUGH_BAR,
+ Port,
+ 1,
+ Data
+ );
+}
+
+VOID
+LpcIoWrite8 (
+ IN UINT16 Port,
+ IN UINT8 Data
+ )
+{
+ mLpc.PciIo->Io.Write(
+ mLpc.PciIo,
+ EfiPciWidthUint8,
+ EFI_PCI_IO_PASS_THROUGH_BAR,
+ Port,
+ 1,
+ &Data
+ );
+}
+
diff --git a/BraswellPlatformPkg/Common/Silicon/WinbondSio/Wpce791/LpcDriver.h b/BraswellPlatformPkg/Common/Silicon/WinbondSio/Wpce791/LpcDriver.h new file mode 100644 index 0000000000..199fb97b69 --- /dev/null +++ b/BraswellPlatformPkg/Common/Silicon/WinbondSio/Wpce791/LpcDriver.h @@ -0,0 +1,118 @@ +/** @file
+ EFI Lpc Driver for a Generic PC Platform.
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _LPC_DRIVER_H
+#define _LPC_DRIVER_H
+
+#include "LpcSio.h"
+#include "LpcIsaAcpi.h"
+#include "Protocol/IsaAcpi.h"
+#include "Protocol/PciIo.h"
+#include "Protocol/DriverBinding.h"
+#include "Library/UefiBootServicesTableLib.h"
+#include "IsaAcpiDxe/PcatIsaAcpi.h"
+#include "IndustryStandard/Pci22.h"
+#include "Protocol/LpcWpce791Policy.h"
+#include <PchRegs.h>
+#include <PlatformBaseAddresses.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+
+#define ICH_LPC_BRIDGE_BUS_DEV_FUNC 0x1F0000
+
+//
+// LPC device private data structure
+//
+#define LPC_DEV_SIGNATURE SIGNATURE_32('X', '7', '8', 'W') //'W87X'
+#define EFI_WPCE791_PS2_KEYBOARD_ENABLE 0x01
+#define EFI_WPCE791_PS2_KEYBOARD_DISABLE 0x00
+
+#define EFI_WPCE791_PS2_MOUSE_ENABLE 0x01
+#define EFI_WPCE791_PS2_MOUSE_DISABLE 0x00
+
+#define PCI_IDX 0xCF8
+#define PCI_DAT 0xCFC
+
+#define PCI_LPC_BASE (0x8000F800)
+#define PCI_LPC_REG(x) (PCI_LPC_BASE + (x))
+
+#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ4 BIT4 // UART IRQ4 Enable
+
+typedef struct {
+ UINTN Signature;
+ EFI_HANDLE Handle;
+ EFI_ISA_ACPI_PROTOCOL IsaAcpi;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+
+} LPC_DEV;
+
+#define LPC_ISA_ACPI_FROM_THIS(a) BASE_CR (a, LPC_DEV, IsaAcpi)
+
+//
+// Driver entry point
+//
+EFI_STATUS
+EFIAPI
+LpcDriverEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+//
+// Prototypes for Driver model protocol interface
+//
+EFI_STATUS
+EFIAPI
+LpcDriverSupported (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ );
+
+EFI_STATUS
+EFIAPI
+LpcDriverStart (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ );
+
+EFI_STATUS
+EFIAPI
+LpcDriverStop (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
+ );
+
+VOID
+LpcIoRead8 (
+ IN UINT16 Port,
+ OUT UINT8 *Data
+ );
+
+VOID
+LpcIoWrite8 (
+ IN UINT16 Port,
+ IN UINT8 Data
+ );
+
+VOID
+EnableInternalUartDevice (
+ VOID
+ );
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Silicon/WinbondSio/Wpce791/LpcIsaAcpi.c b/BraswellPlatformPkg/Common/Silicon/WinbondSio/Wpce791/LpcIsaAcpi.c new file mode 100644 index 0000000000..6892d07d26 --- /dev/null +++ b/BraswellPlatformPkg/Common/Silicon/WinbondSio/Wpce791/LpcIsaAcpi.c @@ -0,0 +1,407 @@ +/** @file
+ IsaAcpi driver implementation.
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "LpcDriver.h"
+
+//
+// PS/2 Keyboard Controller
+//
+static EFI_ISA_ACPI_RESOURCE mLpcWpce791Ps2KeyboardDeviceResources[] = {
+ {EfiIsaAcpiResourceIo, 0, 0x60, 0x64},
+ {EfiIsaAcpiResourceInterrupt, 0, 1, 0},
+ {EfiIsaAcpiResourceEndOfList, 0, 0, 0}
+};
+
+//
+// PS/2 Mouse Controller
+//
+static EFI_ISA_ACPI_RESOURCE mLpcWpce791Ps2MouseDeviceResources[] = {
+ {EfiIsaAcpiResourceIo, 0, 0x60, 0x64},
+ {EfiIsaAcpiResourceInterrupt, 0, 12, 0},
+ {EfiIsaAcpiResourceEndOfList, 0, 0, 0}
+};
+
+//
+// COM
+//
+static EFI_ISA_ACPI_RESOURCE mLpcWpce791ComDeviceResources[] = {
+ {EfiIsaAcpiResourceIo, 0, 0x3f8, 0x3ff},
+ {EfiIsaAcpiResourceInterrupt, 0, 4, 0},
+ {EfiIsaAcpiResourceEndOfList, 0, 0, 0}
+};
+
+//
+// Table of ISA Controllers
+//
+EFI_ISA_ACPI_RESOURCE_LIST mLpcWpce791DeviceList[] = {
+ {{EISA_PNP_ID(0x303), 0}, mLpcWpce791Ps2KeyboardDeviceResources }, // PS/2 Keyboard Controller
+ {{EISA_PNP_ID(0xF03), 0}, mLpcWpce791Ps2MouseDeviceResources }, // PS/2 Mouse Controller
+ {{EISA_PNP_ID(0x501), 0}, mLpcWpce791ComDeviceResources }, // COM
+ {{0, 0}, NULL } // End
+};
+
+static ICH_DMA_INIT mIchDmaInitTable [] = {
+//
+// Register OFFSET, Value
+//
+
+ 0x0D8, 0x000, // Reset DMA Controller 2
+ 0x0D0, 0x000, // Enable DMA controller 2
+ 0x00C, 0x000, // Reset DMA Controller 1
+ 0x008, 0x000, // Enable DMA controller 1
+
+ //
+ // Channel 4
+ //
+ 0x0D6, 0x0c0, // DMA contr. 2 Cascade mode, addr. increment, disable auto init.
+ 0x0D2, 0x000, // Clear write request register
+ 0x0d4, 0x000, // Enable DREQs for channel
+
+ //
+ // Channel 0
+ //
+ 0x00B, 0x040, // DMA contr. 1 single mode, addr. increment, disable auto init.
+ 0x009, 0x000, // Clear write request register
+ 0x00A, 0x000, // Enable DREQs for channel
+
+ //
+ // Channel 1
+ //
+ 0x00B, 0x041, // DMA contr. 1 single mode, addr. increment, disable auto init.
+ 0x009, 0x001, // Clear write request register
+ 0x00A, 0x001, // Enable DREQs for channel
+
+ //
+ // Channel 2
+ //
+ 0x00B, 0x042, // DMA contr. 1 single mode, addr. increment, disable auto init.
+ 0x009, 0x002, // Clear write request register
+ 0x00A, 0x002, // Enable DREQs for channel
+
+ //
+ // Channel 3
+ //
+ 0x00B, 0x043, // DMA contr. 1 single mode, addr. increment, disable auto init.
+ 0x009, 0x003, // Clear write request register
+ 0x00A, 0x003, // Enable DREQs for channel
+
+ //
+ // Channel 5
+ //
+ 0x0D6, 0x041, // DMA contr. 2 single mode, addr. increment, disable auto init.
+ 0x0D2, 0x001, // Clear write request register
+ 0x0D4, 0x001, // Enable DREQs for channel
+
+ //
+ // Channel 6
+ //
+ 0x0D6, 0x042, // DMA contr. 2 single mode, addr. increment, disable auto init.
+ 0x0D2, 0x002, // Clear write request register
+ 0x0D4, 0x002, // Enable DREQs for channel
+
+ //
+ // Channel 7
+ //
+ 0x0D6, 0x043, // DMA contr. 2 single mode, addr. increment, disable auto init.
+ 0x0D2, 0x003, // Clear write request register
+ 0x0D4, 0x003 // Enable DREQs for channel
+
+};
+
+//
+// ISA ACPI Protocol Functions
+//
+/**
+ Enumerate the ISA devices on the ISA bus.
+
+**/
+VOID
+IsaDeviceLookup (
+ IN EFI_ISA_ACPI_DEVICE_ID *Device,
+ OUT EFI_ISA_ACPI_RESOURCE_LIST **IsaAcpiDevice,
+ OUT EFI_ISA_ACPI_RESOURCE_LIST **NextIsaAcpiDevice
+ )
+{
+ UINTN Index;
+
+ *IsaAcpiDevice = NULL;
+
+ if (NextIsaAcpiDevice != NULL) {
+ *NextIsaAcpiDevice = NULL;
+ }
+ if (Device == NULL) {
+ Index = 0;
+ } else {
+ for (Index = 0; mLpcWpce791DeviceList[Index].Device.HID != 0; Index++) {
+ if (Device->HID == mLpcWpce791DeviceList[Index].Device.HID &&
+ Device->UID == mLpcWpce791DeviceList[Index].Device.UID) {
+ break;
+ }
+ }
+ if (mLpcWpce791DeviceList[Index].Device.HID == 0) {
+ return;
+ }
+ *IsaAcpiDevice = &(mLpcWpce791DeviceList[Index]);
+ Index++;
+ }
+ if (NextIsaAcpiDevice != NULL && mLpcWpce791DeviceList[Index].Device.HID != 0) {
+ *NextIsaAcpiDevice = &(mLpcWpce791DeviceList[Index]);
+ }
+}
+
+/**
+ Enumerate the ISA devices on the ISA bus
+ It is hard code now and future it will get from ACPI table
+
+**/
+EFI_STATUS
+EFIAPI
+IsaDeviceEnumerate (
+ IN EFI_ISA_ACPI_PROTOCOL *This,
+ OUT EFI_ISA_ACPI_DEVICE_ID **Device
+ )
+{
+ EFI_ISA_ACPI_RESOURCE_LIST *IsaAcpiDevice;
+ EFI_ISA_ACPI_RESOURCE_LIST *NextIsaAcpiDevice;
+
+ IsaDeviceLookup (*Device, &IsaAcpiDevice, &NextIsaAcpiDevice);
+ if (NextIsaAcpiDevice == NULL) {
+ return EFI_NOT_FOUND;
+ }
+ *Device = &(NextIsaAcpiDevice->Device);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Set ISA device power use sio
+
+**/
+EFI_STATUS
+EFIAPI
+IsaDeviceSetPower (
+ IN EFI_ISA_ACPI_PROTOCOL *This,
+ IN EFI_ISA_ACPI_DEVICE_ID *Device,
+ IN BOOLEAN OnOff
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Get current Resource of the specific ISA device
+ It is hardcode now and future will get from ACPI table
+
+**/
+EFI_STATUS
+EFIAPI
+IsaGetCurrentResource (
+ IN EFI_ISA_ACPI_PROTOCOL *This,
+ IN EFI_ISA_ACPI_DEVICE_ID *Device,
+ OUT EFI_ISA_ACPI_RESOURCE_LIST **ResourceList
+ )
+{
+ IsaDeviceLookup (Device, ResourceList, NULL);
+ if (*ResourceList == NULL || (*ResourceList)->ResourceItem == NULL) {
+ return EFI_NOT_FOUND;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+IsaGetPossibleResource (
+ IN EFI_ISA_ACPI_PROTOCOL *This,
+ IN EFI_ISA_ACPI_DEVICE_ID *Device,
+ OUT EFI_ISA_ACPI_RESOURCE_LIST **ResourceList
+ )
+{
+ //
+ // Not supported yet
+ //
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+EFIAPI
+IsaSetResource (
+ IN EFI_ISA_ACPI_PROTOCOL *This,
+ IN EFI_ISA_ACPI_DEVICE_ID *Device,
+ IN EFI_ISA_ACPI_RESOURCE_LIST *ResourceList
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+EFIAPI
+IsaEnableDevice (
+ IN EFI_ISA_ACPI_PROTOCOL *This,
+ IN EFI_ISA_ACPI_DEVICE_ID *Device,
+ IN BOOLEAN Enable
+ )
+{
+
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Clear out Resource List if device is set to disable by platform policy
+
+**/
+VOID
+EmptyResourceList (
+ IN UINT32 DeviceHid
+ )
+{
+ UINT8 Index;
+
+ for (Index = 0; mLpcWpce791DeviceList[Index].Device.HID != 0; Index++) {
+ if (DeviceHid == mLpcWpce791DeviceList[Index].Device.HID) {
+ mLpcWpce791DeviceList[Index].ResourceItem = NULL;
+ }
+ }
+
+ return;
+}
+
+/**
+ Clear out Resource List if device is set to disable by platform policy
+
+**/
+VOID
+EmptyResourceListHidUid (
+ IN UINT32 DeviceHid,
+ IN UINT32 DeviceUid
+ )
+{
+ UINT8 Index;
+
+ for (Index = 0; mLpcWpce791DeviceList[Index].Device.HID != 0; Index++) {
+ if ((DeviceHid == mLpcWpce791DeviceList[Index].Device.HID) &&
+ (DeviceUid == mLpcWpce791DeviceList[Index].Device.UID)) {
+ mLpcWpce791DeviceList[Index].ResourceItem = NULL;
+ }
+ }
+
+ return;
+}
+
+EFI_STATUS
+EFIAPI
+IsaInitDevice (
+ IN EFI_ISA_ACPI_PROTOCOL *This,
+ IN EFI_ISA_ACPI_DEVICE_ID *Device
+ )
+{
+ EFI_WPCE791_POLICY_PROTOCOL *LpcWpce791Policy;
+ EFI_STATUS Status;
+
+ //
+ // Disable configuration according to platform protocol
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiLpcWpce791PolicyProtocolGuid,
+ NULL,
+ (VOID **) &LpcWpce791Policy
+ );
+ if (!EFI_ERROR (Status)) {
+ if (LpcWpce791Policy->DeviceEnables.Ps2Keyboard == EFI_WPCE791_PS2_KEYBOARD_DISABLE) {
+ EmptyResourceList (EISA_PNP_ID (0x303));
+ DisableLogicalDevice (SIO_KEYBOARD);
+ EmptyResourceList (EISA_PNP_ID (0xF03));
+ DisableLogicalDevice (SIO_KEYBOARD);
+ }
+ if (LpcWpce791Policy->DeviceEnables.Ps2Mouse == EFI_WPCE791_PS2_MOUSE_DISABLE) {
+ EmptyResourceList (EISA_PNP_ID (0xF03));
+ DisableLogicalDevice (SIO_MOUSE);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+VOID
+EnableInternalUartDevice (
+ VOID
+ )
+{
+ //
+ // Program and enable PMC Base.
+ //
+ IoWrite32 (PCI_IDX, PCI_LPC_REG(R_PCH_LPC_PMC_BASE));
+ IoWrite32 (PCI_DAT, (PMC_BASE_ADDRESS | B_PCH_LPC_PMC_BASE_EN));
+
+ //
+ // Program and enable iLB Base.
+ //
+ IoWrite32 (PCI_IDX, PCI_LPC_REG(R_PCH_LPC_ILB_BASE));
+ IoWrite32 (PCI_DAT, (ILB_BASE_ADDRESS | B_PCH_LPC_ILB_BASE_EN));
+ //
+ // Enable internal UART interrupt.
+ //
+ MmioOr32 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT32) (B_PCH_ILB_IRQE_UARTIRQEN_IRQ4));
+ //
+ // GPIO: N67(HV_DDI2_DDC_SCL) - Setting Mode 3
+ // UART0_TXD
+ //
+ MmioWrite32 ((UINTN) (IO_BASE_ADDRESS + 0xD438), (UINT32) 0x00930300);
+ //
+ // GPIO: N62(HV_DDI2_DDC_SDA) - Setting Mode 3
+ // UART0_RXD
+ //
+ MmioWrite32 ((UINTN) (IO_BASE_ADDRESS + 0xD410), (UINT32) 0x00930300);
+ MmioOr32 ((UINTN)(PcdGet64 (PcdPciExpressBaseAddress) + (31 << 15)) + R_PCH_LPC_UART_CTRL, (UINT32) B_PCH_LPC_UART_CTRL_COM1_EN);
+}
+
+EFI_STATUS
+EFIAPI
+LpcInterfaceInit (
+ IN EFI_ISA_ACPI_PROTOCOL *This
+ )
+{
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINTN Index;
+
+ PciIo = (LPC_ISA_ACPI_FROM_THIS (This))->PciIo;
+
+ //
+ // DMA controller initialize
+ //
+ for (Index=0; Index < (sizeof (mIchDmaInitTable) / sizeof (ICH_DMA_INIT)); Index++) {
+ PciIo->Io.Write (
+ PciIo,
+ EfiPciIoWidthUint8,
+ EFI_PCI_IO_PASS_THROUGH_BAR,
+ mIchDmaInitTable[Index].Register,
+ 1,
+ &mIchDmaInitTable[Index].Value
+ );
+ }
+
+ if (!PcdGetBool (PcdWpce791UartSerialIoEnable)) {
+ EmptyResourceList (EISA_PNP_ID (0x501));
+ }
+ else {
+ //
+ // Initialize Serial Port.
+ //
+ EnableInternalUartDevice ();
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/BraswellPlatformPkg/Common/Silicon/WinbondSio/Wpce791/LpcIsaAcpi.h b/BraswellPlatformPkg/Common/Silicon/WinbondSio/Wpce791/LpcIsaAcpi.h new file mode 100644 index 0000000000..405b309e15 --- /dev/null +++ b/BraswellPlatformPkg/Common/Silicon/WinbondSio/Wpce791/LpcIsaAcpi.h @@ -0,0 +1,95 @@ +/** @file
+ Isa Acpi interface.
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _LPC_ISA_ACPI_H
+#define _LPC_ISA_ACPI_H
+
+#include "Protocol/IsaAcpi.h"
+#include "Library/DevicePathLib.h"
+
+typedef struct {
+ UINT8 Register;
+ UINT8 Value;
+} ICH_DMA_INIT;
+
+//
+// Prototypes for the ISA ACPI protocol interface
+//
+EFI_STATUS
+EFIAPI
+IsaDeviceEnumerate (
+ IN EFI_ISA_ACPI_PROTOCOL *This,
+ OUT EFI_ISA_ACPI_DEVICE_ID **Device
+ );
+
+EFI_STATUS
+EFIAPI
+IsaDeviceSetPower (
+ IN EFI_ISA_ACPI_PROTOCOL *This,
+ IN EFI_ISA_ACPI_DEVICE_ID *Device,
+ IN BOOLEAN OnOff
+ );
+
+EFI_STATUS
+EFIAPI
+IsaGetCurrentResource (
+ IN EFI_ISA_ACPI_PROTOCOL *This,
+ IN EFI_ISA_ACPI_DEVICE_ID *Device,
+ OUT EFI_ISA_ACPI_RESOURCE_LIST **ResourceList
+ );
+
+EFI_STATUS
+EFIAPI
+IsaGetPossibleResource (
+ IN EFI_ISA_ACPI_PROTOCOL *This,
+ IN EFI_ISA_ACPI_DEVICE_ID *Device,
+ OUT EFI_ISA_ACPI_RESOURCE_LIST **ResourceList
+ );
+
+EFI_STATUS
+EFIAPI
+IsaSetResource (
+ IN EFI_ISA_ACPI_PROTOCOL *This,
+ IN EFI_ISA_ACPI_DEVICE_ID *Device,
+ IN EFI_ISA_ACPI_RESOURCE_LIST *ResourceList
+ );
+
+EFI_STATUS
+EFIAPI
+IsaEnableDevice (
+ IN EFI_ISA_ACPI_PROTOCOL *This,
+ IN EFI_ISA_ACPI_DEVICE_ID *Device,
+ IN BOOLEAN Enable
+ );
+
+EFI_STATUS
+EFIAPI
+IsaInitDevice (
+ IN EFI_ISA_ACPI_PROTOCOL *This,
+ IN EFI_ISA_ACPI_DEVICE_ID *Device
+ );
+
+EFI_STATUS
+EFIAPI
+LpcInterfaceInit (
+ IN EFI_ISA_ACPI_PROTOCOL *This
+);
+
+VOID
+EmptyResourceList (
+ IN UINT32 DeviceHid
+);
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Silicon/WinbondSio/Wpce791/LpcSio.c b/BraswellPlatformPkg/Common/Silicon/WinbondSio/Wpce791/LpcSio.c new file mode 100644 index 0000000000..0032c0bf66 --- /dev/null +++ b/BraswellPlatformPkg/Common/Silicon/WinbondSio/Wpce791/LpcSio.c @@ -0,0 +1,120 @@ +/** @file
+ Sio implementation.
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "LpcDriver.h"
+#include <Library/S3BootScriptLib.h>
+
+VOID
+WriteRegister (
+ IN UINT8 Index,
+ IN UINT8 Data
+ );
+
+typedef struct {
+ UINT8 Register;
+ UINT8 Value;
+} EFI_SIO_TABLE;
+
+EFI_SIO_TABLE mSioTable[] = {
+ //
+ // Init keyboard controller
+ //
+ { REG_LOGICAL_DEVICE, SIO_KEYBOARD },
+ { BASE_ADDRESS_HIGH, 0x00 },
+ { BASE_ADDRESS_LOW, 0x60 },
+ { BASE_ADDRESS_HIGH2, 0x00 },
+ { BASE_ADDRESS_LOW2, 0x64 },
+ { PRIMARY_INTERRUPT_SELECT, 0x01 },
+ { ACTIVATE, 0x1 },
+
+ //
+ // Init Mouse controller
+ //
+ { REG_LOGICAL_DEVICE, SIO_MOUSE },
+ { BASE_ADDRESS_HIGH, 0x00 },
+ { BASE_ADDRESS_LOW, 0x60 },
+ { BASE_ADDRESS_HIGH2, 0x00 },
+ { BASE_ADDRESS_LOW2, 0x64 },
+ { PRIMARY_INTERRUPT_SELECT, 0x0c },
+ { ACTIVATE, 0x1 },
+
+ { REG_LOGICAL_DEVICE, SIO_COM },
+ { BASE_ADDRESS_HIGH, 0x03 },
+ { BASE_ADDRESS_LOW, 0xf8 },
+ { PRIMARY_INTERRUPT_SELECT, 0x04 },
+ { ACTIVATE, 0x1 },
+
+};
+
+VOID
+LPCWPCE791SetDefault ()
+{
+ UINT8 Index;
+
+ for (Index = 0; Index < sizeof (mSioTable) / sizeof (EFI_SIO_TABLE); Index++) {
+ WriteRegisterAndSaveToScript (mSioTable[Index].Register, mSioTable[Index].Value);
+ }
+
+ return;
+}
+
+VOID
+DisableLogicalDevice (
+ UINT8 DeviceId
+ )
+{
+ WriteRegisterAndSaveToScript (REG_LOGICAL_DEVICE, DeviceId);
+ WriteRegisterAndSaveToScript (ACTIVATE, 0);
+ WriteRegisterAndSaveToScript (BASE_ADDRESS_HIGH, 0);
+ WriteRegisterAndSaveToScript (BASE_ADDRESS_LOW, 0);
+
+ return;
+}
+
+VOID
+WriteRegister (
+ IN UINT8 Index,
+ IN UINT8 Data
+ )
+{
+ LpcIoWrite8 (CONFIG_PORT, Index);
+ LpcIoWrite8 (DATA_PORT, Data);
+
+ return;
+}
+
+VOID
+WriteRegisterAndSaveToScript (
+ IN UINT8 Index,
+ IN UINT8 Data
+ )
+{
+ UINT8 Buffer[2];
+
+ LpcIoWrite8 (CONFIG_PORT, Index);
+ LpcIoWrite8 (DATA_PORT, Data);
+
+ Buffer[0] = Index;
+ Buffer[1] = Data;
+ S3BootScriptSaveIoWrite (
+ EfiBootScriptWidthUint8,
+ INDEX_PORT,
+ 2,
+ Buffer
+ );
+
+ return;
+}
+
diff --git a/BraswellPlatformPkg/Common/Silicon/WinbondSio/Wpce791/LpcSio.h b/BraswellPlatformPkg/Common/Silicon/WinbondSio/Wpce791/LpcSio.h new file mode 100644 index 0000000000..ad0a7c8bf0 --- /dev/null +++ b/BraswellPlatformPkg/Common/Silicon/WinbondSio/Wpce791/LpcSio.h @@ -0,0 +1,96 @@ +/** @file
+ Lpc driver's sio interface.
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _LPC_SIO_H
+#define _LPC_SIO_H
+
+#include "Protocol/PciRootBridgeIo.h"
+
+#define VARSIOINSTALLED L"VarSIOProcotolInstalled"
+
+//
+// Port address
+//
+#define CONFIG_PORT 0x04E
+#define INDEX_PORT 0x04E
+#define DATA_PORT INDEX_PORT + 1
+
+//
+// Logical Device
+//
+#define SIO_COM 0x3
+#define SIO_MSWC 0x4
+#define SIO_MOUSE 0x5
+#define SIO_KEYBOARD 0x6
+#define SIO_SHM 0xF
+#define SIO_PM1 0x11
+#define SIO_PM2 0x12
+#define SIO_PM3 0x17
+#define SIO_ESHM 0x1D
+
+//
+// Global register
+//
+#define REG_LOGICAL_DEVICE 0x07
+#define REG_DEVICE_ID 0x20
+#define SIO_CONFIG_1 0x21
+#define REG_CHIP_REV 0x24
+#define SIO_CONFIG_5 0x25
+#define SIO_CONFIG_6 0x26
+#define REG_DEVICE_REV 0x27
+#define SIO_CONFIG_9 0x29
+#define SIO_CONFIG_D 0x2D
+
+#define ACTIVATE 0x30
+#define BASE_ADDRESS_HIGH 0x60
+#define BASE_ADDRESS_LOW 0x61
+#define BASE_ADDRESS_HIGH2 0x62
+#define BASE_ADDRESS_LOW2 0x63
+#define PRIMARY_INTERRUPT_SELECT 0x70
+#define DMA_CHANNEL_SELECT 0x74
+
+EFI_STATUS
+InitializeLpcSio (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *RootBridgeIo
+ );
+
+//
+// Prototypes for the sio internal function
+//
+//
+// Internal function
+//
+VOID
+LPCWPCE791SetDefault (
+ VOID
+ );
+
+VOID
+WriteRegisterAndSaveToScript (
+ IN UINT8 Index,
+ IN UINT8 Data
+ );
+
+VOID
+FloppyWriteProtect (
+ VOID
+ );
+
+VOID
+DisableLogicalDevice (
+ UINT8 DeviceId
+ );
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Silicon/WinbondSio/Wpce791/Wpce791.inf b/BraswellPlatformPkg/Common/Silicon/WinbondSio/Wpce791/Wpce791.inf new file mode 100644 index 0000000000..e2ddfd6bf1 --- /dev/null +++ b/BraswellPlatformPkg/Common/Silicon/WinbondSio/Wpce791/Wpce791.inf @@ -0,0 +1,69 @@ +## @file
+# Component description file for SIO791 module.
+#
+# This module provides support for Wpce791 Super IO.
+#
+# Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SIO791
+ FILE_GUID = FAB62520-454C-4A0C-B5F2-BFF4F2401F3A
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = LpcDriverEntryPoint
+
+[Sources]
+ LpcIsaAcpi.h
+ LpcSio.h
+ LpcDriver.h
+ LpcIsaAcpi.c
+ LpcSio.c
+ LpcDriver.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ BraswellPlatformPkg/BraswellPlatformPkg.dec
+ IntelFrameworkPkg/IntelFrameworkPkg.dec
+ IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
+ PcAtChipsetPkg/PcAtChipsetPkg.dec
+ ChvRefCodePkg/ChvRefCodePkg.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ UefiBootServicesTableLib
+ DevicePathLib
+ UefiLib
+ S3BootScriptLib
+ DebugLib
+ IoLib
+
+[Protocols]
+ ## CONSUMES
+ gEfiPciIoProtocolGuid
+
+ ## PRODUCES
+ gEfiIsaAcpiProtocolGuid
+
+ ## SOMETIMES_CONSUMES
+ gEfiLpcWpce791PolicyProtocolGuid
+
+[Pcd]
+ gPlatformModuleTokenSpaceGuid.PcdWpce791UartSerialIoEnable ## CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+
+[Guids]
+
+[Depex]
+ TRUE
+
|