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-rw-r--r--Core/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf46
-rw-r--r--Core/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni22
-rw-r--r--Core/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.S73
-rw-r--r--Core/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.asm79
-rw-r--r--Core/UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.S57
-rw-r--r--Core/UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.asm62
6 files changed, 339 insertions, 0 deletions
diff --git a/Core/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf b/Core/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
new file mode 100644
index 0000000000..7cf7d8ca80
--- /dev/null
+++ b/Core/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
@@ -0,0 +1,46 @@
+## @file
+# This library defines some routines that are generic for IA32 family CPU.
+#
+# The library routines are UEFI specification compliant.
+#
+# Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BaseUefiCpuLib
+ MODULE_UNI_FILE = BaseUefiCpuLib.uni
+ FILE_GUID = 34C24FD7-7A90-45c2-89FD-946473D9CE98
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = UefiCpuLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[Sources.IA32]
+ Ia32/InitializeFpu.asm
+ Ia32/InitializeFpu.S
+
+[Sources.X64]
+ X64/InitializeFpu.asm
+ X64/InitializeFpu.S
+
+[Packages]
+ MdePkg/MdePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+ UefiCpuLib
+
diff --git a/Core/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni b/Core/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni
new file mode 100644
index 0000000000..1a1c0d2411
--- /dev/null
+++ b/Core/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni
@@ -0,0 +1,22 @@
+// /** @file
+// This library defines some routines that are generic for IA32 family CPU.
+//
+// The library routines are UEFI specification compliant.
+//
+// Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "Defines generic routines for IA32 family CPUs."
+
+#string STR_MODULE_DESCRIPTION #language en-US "The library routines comply with the UEFI Specification."
+
diff --git a/Core/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.S b/Core/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.S
new file mode 100644
index 0000000000..4972bc2e7f
--- /dev/null
+++ b/Core/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.S
@@ -0,0 +1,73 @@
+#------------------------------------------------------------------------------
+#*
+#* Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
+#* This program and the accompanying materials
+#* are licensed and made available under the terms and conditions of the BSD License
+#* which accompanies this distribution. The full text of the license may be found at
+#* http://opensource.org/licenses/bsd-license.php
+#*
+#* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#*
+#*
+#------------------------------------------------------------------------------
+
+#
+# Float control word initial value:
+# all exceptions masked, double-precision, round-to-nearest
+#
+ASM_PFX(mFpuControlWord): .word 0x027F
+#
+# Multimedia-extensions control word:
+# all exceptions masked, round-to-nearest, flush to zero for masked underflow
+#
+ASM_PFX(mMmxControlWord): .long 0x01F80
+
+#
+# Initializes floating point units for requirement of UEFI specification.
+#
+# This function initializes floating-point control word to 0x027F (all exceptions
+# masked,double-precision, round-to-nearest) and multimedia-extensions control word
+# (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
+# for masked underflow).
+#
+ASM_GLOBAL ASM_PFX(InitializeFloatingPointUnits)
+ASM_PFX(InitializeFloatingPointUnits):
+
+ pushl %ebx
+
+ #
+ # Initialize floating point units
+ #
+ finit
+ fldcw ASM_PFX(mFpuControlWord)
+
+ #
+ # Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
+ # whether the processor supports SSE instruction.
+ #
+ movl $1, %eax
+ cpuid
+ btl $25, %edx
+ jnc Done
+
+ #
+ # Set OSFXSR bit 9 in CR4
+ #
+ movl %cr4, %eax
+ or $0x200, %eax
+ movl %eax, %cr4
+
+ #
+ # The processor should support SSE instruction and we can use
+ # ldmxcsr instruction
+ #
+ ldmxcsr ASM_PFX(mMmxControlWord)
+
+Done:
+ popl %ebx
+
+ ret
+
+#END
+
diff --git a/Core/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.asm b/Core/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.asm
new file mode 100644
index 0000000000..3c31da98f6
--- /dev/null
+++ b/Core/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.asm
@@ -0,0 +1,79 @@
+;------------------------------------------------------------------------------
+;*
+;* Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
+;* This program and the accompanying materials
+;* are licensed and made available under the terms and conditions of the BSD License
+;* which accompanies this distribution. The full text of the license may be found at
+;* http://opensource.org/licenses/bsd-license.php
+;*
+;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;*
+;*
+;------------------------------------------------------------------------------
+
+
+ .686
+ .model flat,C
+ .const
+;
+; Float control word initial value:
+; all exceptions masked, double-precision, round-to-nearest
+;
+mFpuControlWord DW 027Fh
+;
+; Multimedia-extensions control word:
+; all exceptions masked, round-to-nearest, flush to zero for masked underflow
+;
+mMmxControlWord DD 01F80h
+
+ .xmm
+ .code
+
+;
+; Initializes floating point units for requirement of UEFI specification.
+;
+; This function initializes floating-point control word to 0x027F (all exceptions
+; masked,double-precision, round-to-nearest) and multimedia-extensions control word
+; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
+; for masked underflow).
+;
+InitializeFloatingPointUnits PROC PUBLIC
+
+ push ebx
+
+ ;
+ ; Initialize floating point units
+ ;
+ finit
+ fldcw mFpuControlWord
+
+ ;
+ ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
+ ; whether the processor supports SSE instruction.
+ ;
+ mov eax, 1
+ cpuid
+ bt edx, 25
+ jnc Done
+
+ ;
+ ; Set OSFXSR bit 9 in CR4
+ ;
+ mov eax, cr4
+ or eax, BIT9
+ mov cr4, eax
+
+ ;
+ ; The processor should support SSE instruction and we can use
+ ; ldmxcsr instruction
+ ;
+ ldmxcsr mMmxControlWord
+Done:
+ pop ebx
+
+ ret
+
+InitializeFloatingPointUnits ENDP
+
+END
diff --git a/Core/UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.S b/Core/UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.S
new file mode 100644
index 0000000000..97d9f72338
--- /dev/null
+++ b/Core/UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.S
@@ -0,0 +1,57 @@
+#------------------------------------------------------------------------------
+#*
+#* Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>
+#* This program and the accompanying materials
+#* are licensed and made available under the terms and conditions of the BSD License
+#* which accompanies this distribution. The full text of the license may be found at
+#* http://opensource.org/licenses/bsd-license.php
+#*
+#* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#*
+#*
+#------------------------------------------------------------------------------
+
+#
+# Initializes floating point units for requirement of UEFI specification.
+#
+# This function initializes floating-point control word to 0x037F (all exceptions
+# masked,double-extended-precision, round-to-nearest) and multimedia-extensions control word
+# (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
+# for masked underflow).
+#
+ASM_GLOBAL ASM_PFX(InitializeFloatingPointUnits)
+ASM_PFX(InitializeFloatingPointUnits):
+
+ #
+ # Initialize floating point units
+ #
+ finit
+
+ #
+ # Float control word initial value:
+ # all exceptions masked, double-precision, round-to-nearest
+ #
+ pushq $0x037F
+ lea (%rsp), %rax
+ fldcw (%rax)
+ popq %rax
+
+ #
+ # Set OSFXSR bit 9 in CR4
+ #
+ movq %cr4, %rax
+ or $0x200, %rax
+ movq %rax, %cr4
+
+ #
+ # Multimedia-extensions control word:
+ # all exceptions masked, round-to-nearest, flush to zero for masked underflow
+ #
+ pushq $0x01F80
+ lea (%rsp), %rax
+ ldmxcsr (%rax)
+ popq %rax
+
+ ret
+
diff --git a/Core/UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.asm b/Core/UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.asm
new file mode 100644
index 0000000000..331af15cc6
--- /dev/null
+++ b/Core/UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.asm
@@ -0,0 +1,62 @@
+;------------------------------------------------------------------------------
+;*
+;* Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>
+;* This program and the accompanying materials
+;* are licensed and made available under the terms and conditions of the BSD License
+;* which accompanies this distribution. The full text of the license may be found at
+;* http://opensource.org/licenses/bsd-license.php
+;*
+;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;*
+;*
+;------------------------------------------------------------------------------
+
+
+.const
+;
+; Float control word initial value:
+; all exceptions masked, double-extended-precision, round-to-nearest
+;
+mFpuControlWord DW 037Fh
+;
+; Multimedia-extensions control word:
+; all exceptions masked, round-to-nearest, flush to zero for masked underflow
+;
+mMmxControlWord DD 01F80h
+
+.code
+
+
+;
+; Initializes floating point units for requirement of UEFI specification.
+;
+; This function initializes floating-point control word to 0x027F (all exceptions
+; masked,double-precision, round-to-nearest) and multimedia-extensions control word
+; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
+; for masked underflow).
+;
+InitializeFloatingPointUnits PROC PUBLIC
+
+ ;
+ ; Initialize floating point units
+ ;
+ ; The following opcodes stand for instruction 'finit'
+ ; to be supported by some 64-bit assemblers
+ ;
+ DB 9Bh, 0DBh, 0E3h
+ fldcw mFpuControlWord
+
+ ;
+ ; Set OSFXSR bit 9 in CR4
+ ;
+ mov rax, cr4
+ or rax, BIT9
+ mov cr4, rax
+
+ ldmxcsr mMmxControlWord
+
+ ret
+InitializeFloatingPointUnits ENDP
+
+END
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-06 01:32:32 +0000