1 files changed, 73 insertions, 0 deletions
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/SdramSpd.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/SdramSpd.h
new file mode 100644
index 0000000000..f8ca8485d4
--- /dev/null
+++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/SdramSpd.h
@@ -0,0 +1,73 @@
+/*++
+
+Copyright (c) 2007, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name: 
+
+  SdramSpd.h
+
+Abstract:
+
+  This file contains definitions for the SPD fields on an SDRAM.
+ 
+--*/
+
+#ifndef _SDRAM_SPD_H
+#define _SDRAM_SPD_H
+
+//
+// SDRAM SPD field definitions
+//
+#define SPD_MEMORY_TYPE                 2
+#define SPD_SDRAM_ROW_ADDR              3
+#define SPD_SDRAM_COL_ADDR              4
+#define SPD_SDRAM_MODULE_ROWS           5
+#define SPD_SDRAM_MODULE_DATA_WIDTH_LSB 6
+#define SPD_SDRAM_MODULE_DATA_WIDTH_MSB 7
+#define SPD_SDRAM_ECC_SUPPORT           11
+#define SPD_SDRAM_REFRESH               12
+#define SPD_SDRAM_WIDTH                 13
+#define SPD_SDRAM_ERROR_WIDTH           14
+#define SPD_SDRAM_BURST_LENGTH          16
+#define SPD_SDRAM_NO_OF_BANKS           17
+#define SPD_SDRAM_CAS_LATENCY           18
+#define SPD_SDRAM_MODULE_ATTR           21
+
+#define SPD_SDRAM_TCLK1_PULSE           9   // cycle time for highest cas latency
+#define SPD_SDRAM_TAC1_PULSE            10  // access time for highest cas latency
+#define SPD_SDRAM_TCLK2_PULSE           23  // cycle time for 2nd highest cas latency
+#define SPD_SDRAM_TAC2_PULSE            24  // access time for 2nd highest cas latency
+#define SPD_SDRAM_TCLK3_PULSE           25  // cycle time for 3rd highest cas latency
+#define SPD_SDRAM_TAC3_PULSE            26  // access time for 3rd highest cas latency
+#define SPD_SDRAM_MIN_PRECHARGE         27
+#define SPD_SDRAM_ACTIVE_MIN            28
+#define SPD_SDRAM_RAS_CAS               29
+#define SPD_SDRAM_RAS_PULSE             30
+#define SPD_SDRAM_DENSITY               31
+
+//
+// Memory Type Definitions
+//
+#define SPD_VAL_SDR_TYPE  4 // SDR SDRAM memory
+#define SPD_VAL_DDR_TYPE  7 // DDR SDRAM memory
+#define SPD_VAL_DDR2_TYPE 8 // DDR2 SDRAM memory
+//
+// ECC Type Definitions
+//
+#define SPD_ECC_TYPE_NONE   0x00  // No error checking
+#define SPD_ECC_TYPE_PARITY 0x01  // No error checking
+#define SPD_ECC_TYPE_ECC    0x02  // Error checking only
+//
+// Module Attributes (Bit positions)
+//
+#define SPD_BUFFERED    0x01
+#define SPD_REGISTERED  0x02
+
+#endif