diff options
Diffstat (limited to 'EdkModulePkg/Bus/Pci/PciBus/Dxe/PciLib.h')
| -rw-r--r-- | EdkModulePkg/Bus/Pci/PciBus/Dxe/PciLib.h | 126 |
1 files changed, 117 insertions, 9 deletions
diff --git a/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciLib.h b/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciLib.h index f8e88375d7..17e3587cb0 100644 --- a/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciLib.h +++ b/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciLib.h @@ -1,18 +1,18 @@ /*++
-Copyright (c) 2006, Intel Corporation
-All rights reserved. This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
PciLib.h
-
+
Abstract:
PCI Bus Driver Lib header file.
@@ -26,6 +26,15 @@ Revision History #ifndef _EFI_PCI_LIB_H
#define _EFI_PCI_LIB_H
+//
+// Mask definistions for PCD PcdPciIncompatibleDeviceSupportMask
+//
+#define PCI_INCOMPATIBLE_ACPI_RESOURCE_SUPPORT 0x01
+#define PCI_INCOMPATIBLE_READ_SUPPORT 0x02
+#define PCI_INCOMPATIBLE_WRITE_SUPPORT 0x04
+#define PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT 0x08
+#define PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT 0x0a
+
VOID
InstallHotPlugRequestProtocol (
IN EFI_STATUS *Status
@@ -274,4 +283,103 @@ Returns: --*/
;
+/**
+ Read PCI configuration space through EFI_PCI_IO_PROTOCOL.
+
+ @param PciIo A pointer to the EFI_PCI_O_PROTOCOL.
+ @param Width Signifies the width of the memory operations.
+ @Param Address The address within the PCI configuration space for the PCI controller.
+ @param Buffer For read operations, the destination buffer to store the results. For
+ write operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+PciIoRead (
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT32 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ );
+
+/**
+ Write PCI configuration space through EFI_PCI_IO_PROTOCOL.
+
+ @param PciIo A pointer to the EFI_PCI_O_PROTOCOL.
+ @param Width Signifies the width of the memory operations.
+ @Param Address The address within the PCI configuration space for the PCI controller.
+ @param Buffer For read operations, the destination buffer to store the results. For
+ write operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+PciIoWrite (
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT32 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ );
+
+/**
+ Write PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+
+ @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param Pci A pointer to PCI_TYPE00.
+ @param Width Signifies the width of the memory operations.
+ @Param Address The address within the PCI configuration space for the PCI controller.
+ @param Buffer For read operations, the destination buffer to store the results. For
+ write operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+PciRootBridgeIoWrite (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
+ IN PCI_TYPE00 *Pci,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ );
+
+/**
+ Read PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+
+ @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param Pci A pointer to PCI_TYPE00.
+ @param Width Signifies the width of the memory operations.
+ @Param Address The address within the PCI configuration space for the PCI controller.
+ @param Buffer For read operations, the destination buffer to store the results. For
+ write operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+PciRootBridgeIoRead (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
+ IN PCI_TYPE00 *Pci,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ );
#endif
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