diff options
Diffstat (limited to 'IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.c')
| -rw-r--r-- | IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.c | 956 |
1 files changed, 32 insertions, 924 deletions
diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.c b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.c index 615bbaa4dc..16c0cce99a 100644 --- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.c +++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.c @@ -37,50 +37,50 @@ GetBackPcCardBar ( //
if (!gFullEnumeration) {
Address = 0;
- PciIoRead (
- &(PciIoDevice->PciIo),
- EfiPciIoWidthUint32,
- PCI_CARD_MEMORY_BASE_0,
- 1,
- &Address
- );
+ PciIoDevice->PciIo.Pci.Read (
+ &(PciIoDevice->PciIo),
+ EfiPciIoWidthUint32,
+ PCI_CARD_MEMORY_BASE_0,
+ 1,
+ &Address
+ );
(PciIoDevice->PciBar)[P2C_MEM_1].BaseAddress = (UINT64) (Address);
(PciIoDevice->PciBar)[P2C_MEM_1].Length = 0x2000000;
(PciIoDevice->PciBar)[P2C_MEM_1].BarType = PciBarTypeMem32;
Address = 0;
- PciIoRead (
- &(PciIoDevice->PciIo),
- EfiPciIoWidthUint32,
- PCI_CARD_MEMORY_BASE_1,
- 1,
- &Address
- );
+ PciIoDevice->PciIo.Pci.Read (
+ &(PciIoDevice->PciIo),
+ EfiPciIoWidthUint32,
+ PCI_CARD_MEMORY_BASE_1,
+ 1,
+ &Address
+ );
(PciIoDevice->PciBar)[P2C_MEM_2].BaseAddress = (UINT64) (Address);
(PciIoDevice->PciBar)[P2C_MEM_2].Length = 0x2000000;
(PciIoDevice->PciBar)[P2C_MEM_2].BarType = PciBarTypePMem32;
Address = 0;
- PciIoRead (
- &(PciIoDevice->PciIo),
- EfiPciIoWidthUint32,
- PCI_CARD_IO_BASE_0_LOWER,
- 1,
- &Address
- );
+ PciIoDevice->PciIo.Pci.Read (
+ &(PciIoDevice->PciIo),
+ EfiPciIoWidthUint32,
+ PCI_CARD_IO_BASE_0_LOWER,
+ 1,
+ &Address
+ );
(PciIoDevice->PciBar)[P2C_IO_1].BaseAddress = (UINT64) (Address);
(PciIoDevice->PciBar)[P2C_IO_1].Length = 0x100;
(PciIoDevice->PciBar)[P2C_IO_1].BarType = PciBarTypeIo16;
Address = 0;
- PciIoRead (
- &(PciIoDevice->PciIo),
- EfiPciIoWidthUint32,
- PCI_CARD_IO_BASE_1_LOWER,
- 1,
- &Address
- );
+ PciIoDevice->PciIo.Pci.Read (
+ &(PciIoDevice->PciIo),
+ EfiPciIoWidthUint32,
+ PCI_CARD_IO_BASE_1_LOWER,
+ 1,
+ &Address
+ );
(PciIoDevice->PciBar)[P2C_IO_2].BaseAddress = (UINT64) (Address);
(PciIoDevice->PciBar)[P2C_IO_2].Length = 0x100;
(PciIoDevice->PciBar)[P2C_IO_2].BarType = PciBarTypeIo16;
@@ -891,9 +891,8 @@ PciScanBus ( Register = (UINT16) ((SecondBus << 8) | (UINT16) StartBusNumber);
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET);
- Status = PciRootBridgeIoWrite (
+ Status = PciRootBridgeIo->Pci.Write (
PciRootBridgeIo,
- &Pci,
EfiPciWidthUint16,
Address,
1,
@@ -912,9 +911,8 @@ PciScanBus ( //
Register = 0xFF;
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);
- Status = PciRootBridgeIoWrite (
+ Status = PciRootBridgeIo->Pci.Write (
PciRootBridgeIo,
- &Pci,
EfiPciWidthUint8,
Address,
1,
@@ -962,9 +960,8 @@ PciScanBus ( //
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);
- Status = PciRootBridgeIoWrite (
+ Status = PciRootBridgeIo->Pci.Write (
PciRootBridgeIo,
- &Pci,
EfiPciWidthUint8,
Address,
1,
@@ -1117,7 +1114,7 @@ PciHostBridgeP2CProcess ( **/
EFI_STATUS
PciHostBridgeEnumerator (
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
)
{
EFI_HANDLE RootBridgeHandle;
@@ -1331,892 +1328,3 @@ PciHostBridgeEnumerator ( return EFI_SUCCESS;
}
-
-/**
- Read PCI device configuration register by specified address.
-
- This function check the incompatiblilites on PCI device. Return the register
- value.
-
- @param PciRootBridgeIo PCI root bridge io protocol instance.
- @param PciIo PCI IO protocol instance.
- @param PciDeviceInfo PCI device information.
- @param Width Signifies the width of the memory operations.
- @param Offset The offset within the PCI configuration space for the PCI controller.
- @param Buffer For read operations, the destination buffer to store the results. For
- write operations, the source buffer to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
- @retval EFI_UNSUPPORTED Width is invalid for this PCI root bridge.
- @retval other Some error occurred when reading PCI device configuration space
- or checking incompatibility.
-
-**/
-EFI_STATUS
-ReadConfigData (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL
- IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL
- IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,
- IN UINT64 Width,
- IN UINT64 Offset,
- IN OUT VOID *Buffer
- )
-{
- EFI_STATUS Status;
- UINT64 AccessWidth;
- EFI_PCI_REGISTER_ACCESS_DATA *PciRegisterAccessData;
- UINT64 AccessAddress;
- UINTN Stride;
- UINT64 TempBuffer;
- UINT8 *Pointer;
-
- ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));
- ASSERT (Buffer != NULL);
-
- if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT) != 0) {
- //
- // Check access compatibility at first time
- //
- Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_READ, Offset & 0xff, Width, &PciRegisterAccessData);
-
- if (Status == EFI_SUCCESS) {
- //
- // There exists incompatibility on this operation
- //
- AccessWidth = Width;
-
- if (PciRegisterAccessData->Width != VALUE_NOCARE) {
- AccessWidth = PciRegisterAccessData->Width;
- }
-
- AccessAddress = Offset & ~((1 << AccessWidth) - 1);
-
- TempBuffer = 0;
- Stride = 0;
- Pointer = (UINT8 *) &TempBuffer;
-
- while (TRUE) {
-
- if (PciRootBridgeIo != NULL) {
- Status = PciRootBridgeIo->Pci.Read (
- PciRootBridgeIo,
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) AccessWidth,
- AccessAddress,
- 1,
- Pointer
- );
- } else if (PciIo != NULL) {
- Status = PciIo->Pci.Read (
- PciIo,
- (EFI_PCI_IO_PROTOCOL_WIDTH) AccessWidth,
- (UINT32) AccessAddress,
- 1,
- Pointer
- );
- }
-
- if (Status != EFI_SUCCESS) {
- return Status;
- }
-
- Stride = (UINTN)1 << AccessWidth;
- AccessAddress += Stride;
- if (AccessAddress >= (Offset + LShiftU64 (1ULL, (UINTN)Width))) {
- //
- // If all datas have been read, exit
- //
- break;
- }
-
- Pointer += Stride;
-
- if ((AccessAddress & 0xff) < PciRegisterAccessData->EndOffset) {
- //
- // If current offset doesn't reach the end
- //
- continue;
- }
-
- //
- // Continue checking access incompatibility
- //
- Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_READ, AccessAddress & 0xff, AccessWidth, &PciRegisterAccessData);
- if (Status == EFI_SUCCESS) {
- if (PciRegisterAccessData->Width != VALUE_NOCARE) {
- AccessWidth = PciRegisterAccessData->Width;
- }
- }
- }
-
- switch (Width) {
- case EfiPciWidthUint8:
- * (UINT8 *) Buffer = (UINT8) TempBuffer;
- break;
- case EfiPciWidthUint16:
- * (UINT16 *) Buffer = (UINT16) TempBuffer;
- break;
- case EfiPciWidthUint32:
- * (UINT32 *) Buffer = (UINT32) TempBuffer;
- break;
- default:
- return EFI_UNSUPPORTED;
- }
-
- return Status;
- }
- }
- //
- // AccessWidth incompatible check not supportted
- // or, there doesn't exist incompatibility on this operation
- //
- if (PciRootBridgeIo != NULL) {
- Status = PciRootBridgeIo->Pci.Read (
- PciRootBridgeIo,
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
- Offset,
- 1,
- Buffer
- );
-
- } else {
- Status = PciIo->Pci.Read (
- PciIo,
- (EFI_PCI_IO_PROTOCOL_WIDTH) Width,
- (UINT32) Offset,
- 1,
- Buffer
- );
- }
-
- return Status;
-}
-
-/**
- Update register value by checking PCI device incompatibility.
-
- This function check register value incompatibilites on PCI device. Return the register
- value.
-
- @param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.
- @param AccessType Access type, READ or WRITE.
- @param Width Signifies the width of the memory operations.
- @param Offset The offset within the PCI configuration space.
- @param Buffer Store the register data.
-
- @retval EFI_SUCCESS The data has been updated.
- @retval EFI_UNSUPPORTED Width is invalid for this PCI root bridge.
- @retval other Some error occurred when checking incompatibility.
-
-**/
-EFI_STATUS
-UpdateConfigData (
- IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,
- IN UINT64 AccessType,
- IN UINT64 Width,
- IN UINT64 Offset,
- IN OUT VOID *Buffer
-)
-{
- EFI_STATUS Status;
- EFI_PCI_REGISTER_VALUE_DATA *PciRegisterData;
- UINT32 AndValue;
- UINT32 OrValue;
- UINT32 TempValue;
-
- ASSERT (Buffer != NULL);
-
- //
- // Check register value incompatibility
- //
- Status = PciRegisterUpdateCheck (PciDeviceInfo, AccessType, Offset & 0xff, &PciRegisterData);
- if (Status == EFI_SUCCESS) {
-
- AndValue = ((UINT32) PciRegisterData->AndValue) >> (((UINT8) Offset & 0x3) * 8);
- OrValue = ((UINT32) PciRegisterData->OrValue) >> (((UINT8) Offset & 0x3) * 8);
-
- TempValue = * (UINT32 *) Buffer;
- if (PciRegisterData->AndValue != VALUE_NOCARE) {
- TempValue &= AndValue;
- }
- if (PciRegisterData->OrValue != VALUE_NOCARE) {
- TempValue |= OrValue;
- }
-
- switch (Width) {
- case EfiPciWidthUint8:
- *(UINT8 *)Buffer = (UINT8) TempValue;
- break;
-
- case EfiPciWidthUint16:
- *(UINT16 *)Buffer = (UINT16) TempValue;
- break;
- case EfiPciWidthUint32:
- *(UINT32 *)Buffer = TempValue;
- break;
-
- default:
- return EFI_UNSUPPORTED;
- }
- }
-
- return Status;
-}
-
-/**
- Write PCI device configuration register by specified address.
-
- This function check the incompatiblilites on PCI device, and write date
- into register.
-
- @param PciRootBridgeIo PCI root bridge io instance.
- @param PciIo PCI IO protocol instance.
- @param PciDeviceInfo PCI device information.
- @param Width Signifies the width of the memory operations.
- @param Offset The offset within the PCI configuration space for the PCI controller.
- @param Buffer For read operations, the destination buffer to store the results. For
- write operations, the source buffer to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
- @retval other Some error occurred when writing PCI device information
- or checking incompatibility.
-
-**/
-EFI_STATUS
-WriteConfigData (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL
- IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL
- IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,
- IN UINT64 Width,
- IN UINT64 Offset,
- IN VOID *Buffer
- )
-{
- EFI_STATUS Status;
- UINT64 AccessWidth;
- EFI_PCI_REGISTER_ACCESS_DATA *PciRegisterAccessData;
- UINT64 AccessAddress;
- UINTN Stride;
- UINT8 *Pointer;
- UINT64 Data;
- UINTN Shift;
-
- ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));
- ASSERT (Buffer != NULL);
-
- if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT) != 0) {
- //
- // Check access compatibility at first time
- //
- Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_WRITE, Offset & 0xff, Width, &PciRegisterAccessData);
-
- if (Status == EFI_SUCCESS) {
- //
- // There exists incompatibility on this operation
- //
- AccessWidth = Width;
-
- if (PciRegisterAccessData->Width != VALUE_NOCARE) {
- AccessWidth = PciRegisterAccessData->Width;
- }
-
- AccessAddress = Offset & ~((1 << AccessWidth) - 1);
-
- Stride = 0;
- Pointer = (UINT8 *) &Buffer;
- Data = * (UINT64 *) Buffer;
-
- while (TRUE) {
-
- if (AccessWidth > Width) {
- //
- // If actual access width is larger than orignal one, additional data need to be read back firstly
- //
- Status = ReadConfigData (PciRootBridgeIo, PciIo, PciDeviceInfo, AccessWidth, AccessAddress, &Data);
- if (Status != EFI_SUCCESS) {
- return Status;
- }
-
- //
- // Check data read incompatibility
- //
- UpdateConfigData (PciDeviceInfo, PCI_REGISTER_READ, AccessWidth, AccessAddress & 0xff, &Data);
-
- Shift = (UINTN)(Offset - AccessAddress) * 8;
- switch (Width) {
- case EfiPciWidthUint8:
- Data = (* (UINT8 *) Buffer) << Shift | (Data & ~(0xff << Shift));
- break;
-
- case EfiPciWidthUint16:
- Data = (* (UINT16 *) Buffer) << Shift | (Data & ~(0xffff << Shift));
- break;
- }
-
- //
- // Check data write incompatibility
- //
- UpdateConfigData (PciDeviceInfo, PCI_REGISTER_WRITE, AccessWidth, MultU64x32 (AccessAddress, 0xff), &Data);
- }
-
- if (PciRootBridgeIo != NULL) {
- Status = PciRootBridgeIo->Pci.Write (
- PciRootBridgeIo,
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) AccessWidth,
- AccessAddress,
- 1,
- &Data
- );
- } else {
- Status = PciIo->Pci.Write (
- PciIo,
- (EFI_PCI_IO_PROTOCOL_WIDTH) AccessWidth,
- (UINT32) AccessAddress,
- 1,
- &Data
- );
- }
-
- if (Status != EFI_SUCCESS) {
- return Status;
- }
-
- Data = RShiftU64 (Data, ((1 << AccessWidth) * 8));
-
- Stride = (UINTN)1 << AccessWidth;
- AccessAddress += Stride;
- if (AccessAddress >= (Offset + LShiftU64 (1ULL, (UINTN)Width))) {
- //
- // If all datas have been written, exit
- //
- break;
- }
-
- Pointer += Stride;
-
- if ((AccessAddress & 0xff) < PciRegisterAccessData->EndOffset) {
- //
- // If current offset doesn't reach the end
- //
- continue;
- }
-
- //
- // Continue checking access incompatibility
- //
- Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_WRITE, AccessAddress & 0xff, AccessWidth, &PciRegisterAccessData);
- if (Status == EFI_SUCCESS) {
- if (PciRegisterAccessData->Width != VALUE_NOCARE) {
- AccessWidth = PciRegisterAccessData->Width;
- }
- }
- };
-
- return Status;
- }
-
- }
- //
- // AccessWidth incompatible check not supportted
- // or, there doesn't exist incompatibility on this operation
- //
- if (PciRootBridgeIo != NULL) {
- Status = PciRootBridgeIo->Pci.Write (
- PciRootBridgeIo,
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
- Offset,
- 1,
- Buffer
- );
- } else {
- Status = PciIo->Pci.Write (
- PciIo,
- (EFI_PCI_IO_PROTOCOL_WIDTH) Width,
- (UINT32) Offset,
- 1,
- Buffer
- );
- }
-
- return Status;
-}
-
-/**
- Abstract PCI device device information.
-
- @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param PciIo A pointer to EFI_PCI_PROTOCOL.
- @param Pci PCI device configuration space.
- @param Offset The offset within the PCI configuration space for the PCI controller.
- @param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.
-
- @retval EFI_SUCCESS Pci device device information has been abstracted.
- @retval EFI_NOT_FOUND Cannot found the specified PCI device.
- @retval other Some error occurred when reading PCI device information.
-
-**/
-EFI_STATUS
-GetPciDeviceDeviceInfo (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL
- IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL
- IN PCI_TYPE00 *Pci, OPTIONAL
- IN UINT64 Offset, OPTIONAL
- OUT EFI_PCI_DEVICE_INFO *PciDeviceInfo
-)
-{
- EFI_STATUS Status;
- UINT64 PciAddress;
- UINT32 PciConfigData;
- PCI_IO_DEVICE *PciIoDevice;
-
- ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));
- ASSERT (PciDeviceInfo != NULL);
-
- if (PciIo != NULL) {
- PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo);
-
- //
- // Get pointer to PCI_TYPE00 from PciIoDevice
- //
- Pci = &PciIoDevice->Pci;
- }
-
- if (Pci == NULL) {
- //
- // While PCI_TYPE00 hasn't been gotten, read PCI device device information directly
- //
- PciAddress = Offset & 0xffffffffffffff00ULL;
- Status = PciRootBridgeIo->Pci.Read (
- PciRootBridgeIo,
- EfiPciWidthUint32,
- PciAddress,
- 1,
- &PciConfigData
- );
-
- if (EFI_ERROR (Status)) {
- return Status;
- }
-
- if ((PciConfigData & 0xffff) == 0xffff) {
- return EFI_NOT_FOUND;
- }
-
- PciDeviceInfo->VendorID = PciConfigData & 0xffff;
- PciDeviceInfo->DeviceID = PciConfigData >> 16;
-
- Status = PciRootBridgeIo->Pci.Read (
- PciRootBridgeIo,
- EfiPciWidthUint32,
- PciAddress + 8,
- 1,
- &PciConfigData
- );
- if (EFI_ERROR (Status)) {
- return Status;
- }
-
- PciDeviceInfo->RevisionID = PciConfigData & 0xf;
-
- Status = PciRootBridgeIo->Pci.Read (
- PciRootBridgeIo,
- EfiPciWidthUint32,
- PciAddress + 0x2c,
- 1,
- &PciConfigData
- );
-
- if (EFI_ERROR (Status)) {
- return Status;
- }
-
- PciDeviceInfo->SubsystemVendorID = PciConfigData & 0xffff;
- PciDeviceInfo->SubsystemID = PciConfigData >> 16;
-
- } else {
- PciDeviceInfo->VendorID = Pci->Hdr.VendorId;
- PciDeviceInfo->DeviceID = Pci->Hdr.DeviceId;
- PciDeviceInfo->RevisionID = Pci->Hdr.RevisionID;
- PciDeviceInfo->SubsystemVendorID = Pci->Device.SubsystemVendorID;
- PciDeviceInfo->SubsystemID = Pci->Device.SubsystemID;
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Read PCI configuration space with incompatibility check.
-
- @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param PciIo A pointer to the EFI_PCI_IO_PROTOCOL.
- @param Pci A pointer to PCI_TYPE00.
- @param Width Signifies the width of the memory operations.
- @param Offset The offset within the PCI configuration space for the PCI controller.
- @param Count The number of unit to be read.
- @param Buffer For read operations, the destination buffer to store the results. For
- write operations, the source buffer to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
- @retval EFI_UNSUPPORTED Buffer is NULL.
- @retval other Some error occurred when reading PCI configuration space.
-
-**/
-EFI_STATUS
-PciIncompatibilityCheckRead (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL
- IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL
- IN PCI_TYPE00 *Pci, OPTIONAL
- IN UINTN Width,
- IN UINT64 Offset,
- IN UINTN Count,
- IN OUT VOID *Buffer
- )
-{
- EFI_STATUS Status;
- EFI_PCI_DEVICE_INFO PciDeviceInfo;
- UINT32 Stride;
-
- ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));
- if (Buffer == NULL) {
- return EFI_UNSUPPORTED;
- }
-
- //
- // get PCI device device information
- //
- Status = GetPciDeviceDeviceInfo (PciRootBridgeIo, PciIo, Pci, Offset, &PciDeviceInfo);
- if (Status != EFI_SUCCESS) {
- return Status;
- }
-
- Stride = 1 << Width;
-
- for (; Count > 0; Count--, Offset += Stride, Buffer = (UINT8 *)Buffer + Stride) {
-
- //
- // read configuration register
- //
- Status = ReadConfigData (PciRootBridgeIo, PciIo, &PciDeviceInfo, (UINT64) Width, Offset, Buffer);
-
- if (Status != EFI_SUCCESS) {
- return Status;
- }
-
- //
- // update the data read from configuration register
- //
- if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT) != 0) {
- UpdateConfigData (&PciDeviceInfo, PCI_REGISTER_READ, Width, Offset & 0xff, Buffer);
- }
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Write PCI configuration space with incompatibility check.
-
- @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param PciIo A pointer to the EFI_PCI_IO_PROTOCOL.
- @param Pci A pointer to PCI_TYPE00.
- @param Width Signifies the width of the memory operations.
- @param Offset The offset within the PCI configuration space for the PCI controller.
- @param Count The number of unit to be write.
- @param Buffer For read operations, the destination buffer to store the results. For
- write operations, the source buffer to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
- @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
- valid for the PCI configuration header of the PCI controller.
- Buffer is NULL.
- @retval other Some error occurred when writing PCI configuration space.
-
-**/
-EFI_STATUS
-PciIncompatibilityCheckWrite (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL
- IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL
- IN PCI_TYPE00 *Pci, OPTIONAL
- IN UINTN Width,
- IN UINT64 Offset,
- IN UINTN Count,
- IN OUT VOID *Buffer
- )
-{
- EFI_STATUS Status;
- EFI_PCI_DEVICE_INFO PciDeviceInfo;
- UINT32 Stride;
- UINT64 Data;
-
- ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));
- if (Buffer == NULL) {
- return EFI_UNSUPPORTED;
- }
-
- //
- // Get PCI device device information
- //
- Status = GetPciDeviceDeviceInfo (PciRootBridgeIo, PciIo, Pci, Offset, &PciDeviceInfo);
- if (Status != EFI_SUCCESS) {
- return Status;
- }
-
- Stride = 1 << Width;
-
- for (; Count > 0; Count--, Offset += Stride, Buffer = (UINT8 *) Buffer + Stride) {
-
- Data = 0;
-
- switch (Width) {
- case EfiPciWidthUint8:
- Data = * (UINT8 *) Buffer;
- break;
- case EfiPciWidthUint16:
- Data = * (UINT16 *) Buffer;
- break;
-
- case EfiPciWidthUint32:
- Data = * (UINT32 *) Buffer;
- break;
-
- default:
- return EFI_UNSUPPORTED;
- }
-
- //
- // Update the data writen into configuration register
- //
- if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT) != 0) {
- UpdateConfigData (&PciDeviceInfo, PCI_REGISTER_WRITE, Width, Offset & 0xff, &Data);
- }
-
- //
- // Write configuration register
- //
- Status = WriteConfigData (PciRootBridgeIo, PciIo, &PciDeviceInfo, Width, Offset, &Data);
-
- if (Status != EFI_SUCCESS) {
- return Status;
- }
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Read PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param Pci A pointer to PCI_TYPE00.
- @param Width Signifies the width of the memory operations.
- @param Offset The offset within the PCI configuration space for the PCI controller.
- @param Count The number of unit to be read.
- @param Buffer For read operations, the destination buffer to store the results. For
- write operations, the source buffer to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
- @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
-
-**/
-EFI_STATUS
-PciRootBridgeIoRead (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
- IN PCI_TYPE00 *Pci, OPTIONAL
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Offset,
- IN UINTN Count,
- IN OUT VOID *Buffer
- )
-{
- EFI_STATUS Status;
-
- if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_READ_SUPPORT) != 0) {
- //
- // If PCI incompatibility check enabled
- //
- Status = PciIncompatibilityCheckRead (
- PciRootBridgeIo,
- NULL,
- Pci,
- (UINTN) Width,
- Offset,
- Count,
- Buffer
- );
- if (Status == EFI_UNSUPPORTED) {
- return EFI_INVALID_PARAMETER;
- } else {
- return Status;
- }
- } else {
- return PciRootBridgeIo->Pci.Read (
- PciRootBridgeIo,
- Width,
- Offset,
- Count,
- Buffer
- );
- }
-}
-
-/**
- Write PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param Pci A pointer to PCI_TYPE00.
- @param Width Signifies the width of the memory operations.
- @param Offset The offset within the PCI configuration space for the PCI controller.
- @param Count The number of unit to be read.
- @param Buffer For read operations, the destination buffer to store the results. For
- write operations, the source buffer to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
- @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
-
-**/
-EFI_STATUS
-PciRootBridgeIoWrite (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
- IN PCI_TYPE00 *Pci,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Offset,
- IN UINTN Count,
- IN OUT VOID *Buffer
- )
-{
- EFI_STATUS Status;
-
- if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_WRITE_SUPPORT) != 0) {
- //
- // If PCI incompatibility check enabled
- //
- Status = PciIncompatibilityCheckWrite (
- PciRootBridgeIo,
- NULL,
- Pci,
- Width,
- Offset,
- Count,
- Buffer
- );
- if (Status == EFI_UNSUPPORTED) {
- return EFI_INVALID_PARAMETER;
- } else {
- return Status;
- }
-
- } else {
- return PciRootBridgeIo->Pci.Write (
- PciRootBridgeIo,
- Width,
- Offset,
- Count,
- Buffer
- );
- }
-}
-
-/**
- Read PCI configuration space through EFI_PCI_IO_PROTOCOL.
-
- @param PciIo A pointer to the EFI_PCI_O_PROTOCOL.
- @param Width Signifies the width of the memory operations.
- @param Offset The offset within the PCI configuration space for the PCI controller.
- @param Count The number of unit to be read.
- @param Buffer For read operations, the destination buffer to store the results. For
- write operations, the source buffer to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI controller.
- @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
- valid for the PCI configuration header of the PCI controller.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
- @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
-
-**/
-EFI_STATUS
-PciIoRead (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
- IN UINT32 Offset,
- IN UINTN Count,
- IN OUT VOID *Buffer
- )
-{
- if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_READ_SUPPORT) != 0) {
- //
- // If PCI incompatibility check enabled
- //
- return PciIncompatibilityCheckRead (
- NULL,
- PciIo,
- NULL,
- (UINTN) Width,
- Offset,
- Count,
- Buffer
- );
- } else {
- return PciIo->Pci.Read (
- PciIo,
- Width,
- Offset,
- Count,
- Buffer
- );
- }
-}
-
-/**
- Write PCI configuration space through EFI_PCI_IO_PROTOCOL.
-
- If PCI incompatibility check is enabled, do incompatibility check.
-
- @param PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.
- @param Width Signifies the width of the memory operations.
- @param Offset The offset within the PCI configuration space for the PCI controller.
- @param Count The number of PCI configuration operations to perform.
- @param Buffer For read operations, the destination buffer to store the results. For write
- operations, the source buffer to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI controller.
- @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
- valid for the PCI configuration header of the PCI controller.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
- @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
-
-**/
-EFI_STATUS
-PciIoWrite (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
- IN UINT32 Offset,
- IN UINTN Count,
- IN OUT VOID *Buffer
- )
-{
- if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_WRITE_SUPPORT) != 0) {
- //
- // If PCI incompatibility check enabled
- //
- return PciIncompatibilityCheckWrite (
- NULL,
- PciIo,
- NULL,
- Width,
- Offset,
- Count,
- Buffer
- );
-
- } else {
- return PciIo->Pci.Write (
- PciIo,
- Width,
- Offset,
- Count,
- Buffer
- );
- }
-}
-
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