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-rw-r--r--MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c22
-rw-r--r--MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h2
2 files changed, 23 insertions, 1 deletions
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
index 4798bea860..1058f03030 100644
--- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
@@ -125,7 +125,7 @@ XhcGetCapability (
Xhc = XHC_FROM_THIS (This);
*MaxSpeed = EFI_USB_SPEED_SUPER;
*PortNumber = (UINT8) (Xhc->HcSParams1.Data.MaxPorts);
- *Is64BitCapable = (UINT8) (Xhc->HcCParams.Data.Ac64);
+ *Is64BitCapable = (UINT8) Xhc->Support64BitDma;
DEBUG ((EFI_D_INFO, "XhcGetCapability: %d ports, 64 bit %d\n", *PortNumber, *Is64BitCapable));
gBS->RestoreTPL (OldTpl);
@@ -2020,6 +2020,26 @@ XhcDriverBindingStart (
return EFI_OUT_OF_RESOURCES;
}
+ //
+ // Enable 64-bit DMA support in the PCI layer if this controller
+ // supports it.
+ //
+ if (Xhc->HcCParams.Data.Ac64 != 0) {
+ Status = PciIo->Attributes (
+ PciIo,
+ EfiPciIoAttributeOperationEnable,
+ EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE,
+ NULL
+ );
+ if (!EFI_ERROR (Status)) {
+ Xhc->Support64BitDma = TRUE;
+ } else {
+ DEBUG ((EFI_D_WARN,
+ "%a: failed to enable 64-bit DMA on 64-bit capable controller @ %p (%r)\n",
+ __FUNCTION__, Controller, Status));
+ }
+ }
+
XhcSetBiosOwnership (Xhc);
XhcResetHC (Xhc, XHC_RESET_TIMEOUT);
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h
index 7999151b3f..0f53bb0eff 100644
--- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h
@@ -256,6 +256,8 @@ struct _USB_XHCI_INSTANCE {
// The array supports up to 255 devices, entry 0 is reserved and should not be used.
//
USB_DEV_CONTEXT UsbDevContext[256];
+
+ BOOLEAN Support64BitDma; // Whether 64 bit DMA may be used with this device
};