diff options
Diffstat (limited to 'MdePkg/Library')
16 files changed, 5148 insertions, 13 deletions
diff --git a/MdePkg/Library/DxePcdLib/DxePcdLib.inf b/MdePkg/Library/DxePcdLib/DxePcdLib.inf index 2958ed0a7c..78b1a7b34a 100644 --- a/MdePkg/Library/DxePcdLib/DxePcdLib.inf +++ b/MdePkg/Library/DxePcdLib/DxePcdLib.inf @@ -31,7 +31,7 @@ FILE_GUID = af97eb89-4cc6-45f8-a514-ca025b346480
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = PcdLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
+ LIBRARY_CLASS = PcdLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER SMM_CORE UEFI_APPLICATION UEFI_DRIVER
CONSTRUCTOR = PcdLibConstructor
#
diff --git a/MdePkg/Library/SmmIoLibCpuIo/IoHighLevel.c b/MdePkg/Library/SmmIoLibCpuIo/IoHighLevel.c new file mode 100644 index 0000000000..72ea425663 --- /dev/null +++ b/MdePkg/Library/SmmIoLibCpuIo/IoHighLevel.c @@ -0,0 +1,2275 @@ +/** @file
+ High-level Io/Mmio functions.
+
+ All assertions for bit field operations are handled bit field functions in the
+ Base Library.
+
+ Copyright (c) 2009, Intel Corporation<BR>
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Module Name: IoHighLevel.c
+
+ The following IoLib instances share the same version of this file:
+
+ BaseIoLibIntrinsic
+ DxeIoLibCpuIo
+ PeiIoLibCpuIo
+ SmmIoLibCpuIo
+**/
+
+
+#include "SmmCpuIoLibInternal.h"
+
+/**
+ Reads an 8-bit I/O port, performs a bitwise OR, and writes the
+ result back to the 8-bit I/O port.
+
+ Reads the 8-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 8-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT8
+EFIAPI
+IoOr8 (
+ IN UINTN Port,
+ IN UINT8 OrData
+ )
+{
+ return IoWrite8 (Port, (UINT8) (IoRead8 (Port) | OrData));
+}
+
+/**
+ Reads an 8-bit I/O port, performs a bitwise AND, and writes the result back
+ to the 8-bit I/O port.
+
+ Reads the 8-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 8-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT8
+EFIAPI
+IoAnd8 (
+ IN UINTN Port,
+ IN UINT8 AndData
+ )
+{
+ return IoWrite8 (Port, (UINT8) (IoRead8 (Port) & AndData));
+}
+
+/**
+ Reads an 8-bit I/O port, performs a bitwise AND followed by a bitwise
+ inclusive OR, and writes the result back to the 8-bit I/O port.
+
+ Reads the 8-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, performs a bitwise OR
+ between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 8-bit I/O port specified by Port. The value
+ written to the I/O port is returned. This function must guarantee that all
+ I/O read and write operations are serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param AndData The value to AND with the read value from the I/O port.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT8
+EFIAPI
+IoAndThenOr8 (
+ IN UINTN Port,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return IoWrite8 (Port, (UINT8) ((IoRead8 (Port) & AndData) | OrData));
+}
+
+/**
+ Reads a bit field of an I/O register.
+
+ Reads the bit field in an 8-bit I/O register. The bit field is specified by
+ the StartBit and the EndBit. The value of the bit field is returned.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+IoBitFieldRead8 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead8 (IoRead8 (Port), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to an I/O register.
+
+ Writes Value to the bit field of the I/O register. The bit field is specified
+ by the StartBit and the EndBit. All other bits in the destination I/O
+ register are preserved. The value written to the I/O port is returned. Extra
+ left bits in Value are stripped.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param Value New value of the bit field.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT8
+EFIAPI
+IoBitFieldWrite8 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
+ )
+{
+ return IoWrite8 (
+ Port,
+ BitFieldWrite8 (IoRead8 (Port), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise OR, and writes the
+ result back to the bit field in the 8-bit port.
+
+ Reads the 8-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 8-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized. Extra left bits in OrData are stripped.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT8
+EFIAPI
+IoBitFieldOr8 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
+ )
+{
+ return IoWrite8 (
+ Port,
+ BitFieldOr8 (IoRead8 (Port), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise AND, and writes the
+ result back to the bit field in the 8-bit port.
+
+ Reads the 8-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 8-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized. Extra left bits in AndData are stripped.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT8
+EFIAPI
+IoBitFieldAnd8 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
+ )
+{
+ return IoWrite8 (
+ Port,
+ BitFieldAnd8 (IoRead8 (Port), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 8-bit port.
+
+ Reads the 8-bit I/O port specified by Port, performs a bitwise AND followed
+ by a bitwise OR between the read result and the value specified by
+ AndData, and writes the result to the 8-bit I/O port specified by Port. The
+ value written to the I/O port is returned. This function must guarantee that
+ all I/O read and write operations are serialized. Extra left bits in both
+ AndData and OrData are stripped.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the read value from the I/O port.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT8
+EFIAPI
+IoBitFieldAndThenOr8 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return IoWrite8 (
+ Port,
+ BitFieldAndThenOr8 (IoRead8 (Port), StartBit, EndBit, AndData, OrData)
+ );
+}
+
+/**
+ Reads a 16-bit I/O port, performs a bitwise OR, and writes the
+ result back to the 16-bit I/O port.
+
+ Reads the 16-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 16-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT16
+EFIAPI
+IoOr16 (
+ IN UINTN Port,
+ IN UINT16 OrData
+ )
+{
+ return IoWrite16 (Port, (UINT16) (IoRead16 (Port) | OrData));
+}
+
+/**
+ Reads a 16-bit I/O port, performs a bitwise AND, and writes the result back
+ to the 16-bit I/O port.
+
+ Reads the 16-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 16-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT16
+EFIAPI
+IoAnd16 (
+ IN UINTN Port,
+ IN UINT16 AndData
+ )
+{
+ return IoWrite16 (Port, (UINT16) (IoRead16 (Port) & AndData));
+}
+
+/**
+ Reads a 16-bit I/O port, performs a bitwise AND followed by a bitwise
+ inclusive OR, and writes the result back to the 16-bit I/O port.
+
+ Reads the 16-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, performs a bitwise OR
+ between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 16-bit I/O port specified by Port. The value
+ written to the I/O port is returned. This function must guarantee that all
+ I/O read and write operations are serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param AndData The value to AND with the read value from the I/O port.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT16
+EFIAPI
+IoAndThenOr16 (
+ IN UINTN Port,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ return IoWrite16 (Port, (UINT16) ((IoRead16 (Port) & AndData) | OrData));
+}
+
+/**
+ Reads a bit field of an I/O register.
+
+ Reads the bit field in a 16-bit I/O register. The bit field is specified by
+ the StartBit and the EndBit. The value of the bit field is returned.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+IoBitFieldRead16 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead16 (IoRead16 (Port), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to an I/O register.
+
+ Writes Value to the bit field of the I/O register. The bit field is specified
+ by the StartBit and the EndBit. All other bits in the destination I/O
+ register are preserved. The value written to the I/O port is returned. Extra
+ left bits in Value are stripped.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param Value New value of the bit field.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT16
+EFIAPI
+IoBitFieldWrite16 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
+ )
+{
+ return IoWrite16 (
+ Port,
+ BitFieldWrite16 (IoRead16 (Port), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise OR, and writes the
+ result back to the bit field in the 16-bit port.
+
+ Reads the 16-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 16-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized. Extra left bits in OrData are stripped.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT16
+EFIAPI
+IoBitFieldOr16 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
+ )
+{
+ return IoWrite16 (
+ Port,
+ BitFieldOr16 (IoRead16 (Port), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise AND, and writes the
+ result back to the bit field in the 16-bit port.
+
+ Reads the 16-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 16-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized. Extra left bits in AndData are stripped.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT16
+EFIAPI
+IoBitFieldAnd16 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
+ )
+{
+ return IoWrite16 (
+ Port,
+ BitFieldAnd16 (IoRead16 (Port), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 16-bit port.
+
+ Reads the 16-bit I/O port specified by Port, performs a bitwise AND followed
+ by a bitwise OR between the read result and the value specified by
+ AndData, and writes the result to the 16-bit I/O port specified by Port. The
+ value written to the I/O port is returned. This function must guarantee that
+ all I/O read and write operations are serialized. Extra left bits in both
+ AndData and OrData are stripped.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the read value from the I/O port.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT16
+EFIAPI
+IoBitFieldAndThenOr16 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ return IoWrite16 (
+ Port,
+ BitFieldAndThenOr16 (IoRead16 (Port), StartBit, EndBit, AndData, OrData)
+ );
+}
+
+/**
+ Reads a 32-bit I/O port, performs a bitwise OR, and writes the
+ result back to the 32-bit I/O port.
+
+ Reads the 32-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 32-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT32
+EFIAPI
+IoOr32 (
+ IN UINTN Port,
+ IN UINT32 OrData
+ )
+{
+ return IoWrite32 (Port, IoRead32 (Port) | OrData);
+}
+
+/**
+ Reads a 32-bit I/O port, performs a bitwise AND, and writes the result back
+ to the 32-bit I/O port.
+
+ Reads the 32-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 32-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT32
+EFIAPI
+IoAnd32 (
+ IN UINTN Port,
+ IN UINT32 AndData
+ )
+{
+ return IoWrite32 (Port, IoRead32 (Port) & AndData);
+}
+
+/**
+ Reads a 32-bit I/O port, performs a bitwise AND followed by a bitwise
+ inclusive OR, and writes the result back to the 32-bit I/O port.
+
+ Reads the 32-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, performs a bitwise OR
+ between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 32-bit I/O port specified by Port. The value
+ written to the I/O port is returned. This function must guarantee that all
+ I/O read and write operations are serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param AndData The value to AND with the read value from the I/O port.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT32
+EFIAPI
+IoAndThenOr32 (
+ IN UINTN Port,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return IoWrite32 (Port, (IoRead32 (Port) & AndData) | OrData);
+}
+
+/**
+ Reads a bit field of an I/O register.
+
+ Reads the bit field in a 32-bit I/O register. The bit field is specified by
+ the StartBit and the EndBit. The value of the bit field is returned.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+IoBitFieldRead32 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead32 (IoRead32 (Port), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to an I/O register.
+
+ Writes Value to the bit field of the I/O register. The bit field is specified
+ by the StartBit and the EndBit. All other bits in the destination I/O
+ register are preserved. The value written to the I/O port is returned. Extra
+ left bits in Value are stripped.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param Value New value of the bit field.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT32
+EFIAPI
+IoBitFieldWrite32 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ )
+{
+ return IoWrite32 (
+ Port,
+ BitFieldWrite32 (IoRead32 (Port), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise OR, and writes the
+ result back to the bit field in the 32-bit port.
+
+ Reads the 32-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 32-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized. Extra left bits in OrData are stripped.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT32
+EFIAPI
+IoBitFieldOr32 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ )
+{
+ return IoWrite32 (
+ Port,
+ BitFieldOr32 (IoRead32 (Port), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise AND, and writes the
+ result back to the bit field in the 32-bit port.
+
+ Reads the 32-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 32-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized. Extra left bits in AndData are stripped.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT32
+EFIAPI
+IoBitFieldAnd32 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ )
+{
+ return IoWrite32 (
+ Port,
+ BitFieldAnd32 (IoRead32 (Port), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 32-bit port.
+
+ Reads the 32-bit I/O port specified by Port, performs a bitwise AND followed
+ by a bitwise OR between the read result and the value specified by
+ AndData, and writes the result to the 32-bit I/O port specified by Port. The
+ value written to the I/O port is returned. This function must guarantee that
+ all I/O read and write operations are serialized. Extra left bits in both
+ AndData and OrData are stripped.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the read value from the I/O port.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT32
+EFIAPI
+IoBitFieldAndThenOr32 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return IoWrite32 (
+ Port,
+ BitFieldAndThenOr32 (IoRead32 (Port), StartBit, EndBit, AndData, OrData)
+ );
+}
+
+/**
+ Reads a 64-bit I/O port, performs a bitwise OR, and writes the
+ result back to the 64-bit I/O port.
+
+ Reads the 64-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 64-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT64
+EFIAPI
+IoOr64 (
+ IN UINTN Port,
+ IN UINT64 OrData
+ )
+{
+ return IoWrite64 (Port, IoRead64 (Port) | OrData);
+}
+
+/**
+ Reads a 64-bit I/O port, performs a bitwise AND, and writes the result back
+ to the 64-bit I/O port.
+
+ Reads the 64-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 64-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT64
+EFIAPI
+IoAnd64 (
+ IN UINTN Port,
+ IN UINT64 AndData
+ )
+{
+ return IoWrite64 (Port, IoRead64 (Port) & AndData);
+}
+
+/**
+ Reads a 64-bit I/O port, performs a bitwise AND followed by a bitwise
+ inclusive OR, and writes the result back to the 64-bit I/O port.
+
+ Reads the 64-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, performs a bitwise OR
+ between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 64-bit I/O port specified by Port. The value
+ written to the I/O port is returned. This function must guarantee that all
+ I/O read and write operations are serialized.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param AndData The value to AND with the read value from the I/O port.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT64
+EFIAPI
+IoAndThenOr64 (
+ IN UINTN Port,
+ IN UINT64 AndData,
+ IN UINT64 OrData
+ )
+{
+ return IoWrite64 (Port, (IoRead64 (Port) & AndData) | OrData);
+}
+
+/**
+ Reads a bit field of an I/O register.
+
+ Reads the bit field in a 64-bit I/O register. The bit field is specified by
+ the StartBit and the EndBit. The value of the bit field is returned.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+
+ @return The value read.
+
+**/
+UINT64
+EFIAPI
+IoBitFieldRead64 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead64 (IoRead64 (Port), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to an I/O register.
+
+ Writes Value to the bit field of the I/O register. The bit field is specified
+ by the StartBit and the EndBit. All other bits in the destination I/O
+ register are preserved. The value written to the I/O port is returned. Extra
+ left bits in Value are stripped.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param Value New value of the bit field.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT64
+EFIAPI
+IoBitFieldWrite64 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 Value
+ )
+{
+ return IoWrite64 (
+ Port,
+ BitFieldWrite64 (IoRead64 (Port), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads a bit field in a 64-bit port, performs a bitwise OR, and writes the
+ result back to the bit field in the 64-bit port.
+
+ Reads the 64-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 64-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized. Extra left bits in OrData are stripped.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT64
+EFIAPI
+IoBitFieldOr64 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 OrData
+ )
+{
+ return IoWrite64 (
+ Port,
+ BitFieldOr64 (IoRead64 (Port), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in a 64-bit port, performs a bitwise AND, and writes the
+ result back to the bit field in the 64-bit port.
+
+ Reads the 64-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 64-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized. Extra left bits in AndData are stripped.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT64
+EFIAPI
+IoBitFieldAnd64 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData
+ )
+{
+ return IoWrite64 (
+ Port,
+ BitFieldAnd64 (IoRead64 (Port), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in a 64-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 64-bit port.
+
+ Reads the 64-bit I/O port specified by Port, performs a bitwise AND followed
+ by a bitwise OR between the read result and the value specified by
+ AndData, and writes the result to the 64-bit I/O port specified by Port. The
+ value written to the I/O port is returned. This function must guarantee that
+ all I/O read and write operations are serialized. Extra left bits in both
+ AndData and OrData are stripped.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param AndData The value to AND with the read value from the I/O port.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT64
+EFIAPI
+IoBitFieldAndThenOr64 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData,
+ IN UINT64 OrData
+ )
+{
+ return IoWrite64 (
+ Port,
+ BitFieldAndThenOr64 (IoRead64 (Port), StartBit, EndBit, AndData, OrData)
+ );
+}
+
+/**
+ Reads an 8-bit MMIO register, performs a bitwise OR, and writes the
+ result back to the 8-bit MMIO register.
+
+ Reads the 8-bit MMIO register specified by Address, performs a bitwise
+ inclusive OR between the read result and the value specified by OrData, and
+ writes the result to the 8-bit MMIO register specified by Address. The value
+ written to the MMIO register is returned. This function must guarantee that
+ all MMIO read and write operations are serialized.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+MmioOr8 (
+ IN UINTN Address,
+ IN UINT8 OrData
+ )
+{
+ return MmioWrite8 (Address, (UINT8) (MmioRead8 (Address) | OrData));
+}
+
+/**
+ Reads an 8-bit MMIO register, performs a bitwise AND, and writes the result
+ back to the 8-bit MMIO register.
+
+ Reads the 8-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, and writes the
+ result to the 8-bit MMIO register specified by Address. The value written to
+ the MMIO register is returned. This function must guarantee that all MMIO
+ read and write operations are serialized.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+MmioAnd8 (
+ IN UINTN Address,
+ IN UINT8 AndData
+ )
+{
+ return MmioWrite8 (Address, (UINT8) (MmioRead8 (Address) & AndData));
+}
+
+/**
+ Reads an 8-bit MMIO register, performs a bitwise AND followed by a bitwise
+ inclusive OR, and writes the result back to the 8-bit MMIO register.
+
+ Reads the 8-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, performs a
+ bitwise OR between the result of the AND operation and the value specified by
+ OrData, and writes the result to the 8-bit MMIO register specified by
+ Address. The value written to the MMIO register is returned. This function
+ must guarantee that all MMIO read and write operations are serialized.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+MmioAndThenOr8 (
+ IN UINTN Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return MmioWrite8 (Address, (UINT8) ((MmioRead8 (Address) & AndData) | OrData));
+}
+
+/**
+ Reads a bit field of a MMIO register.
+
+ Reads the bit field in an 8-bit MMIO register. The bit field is specified by
+ the StartBit and the EndBit. The value of the bit field is returned.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address MMIO register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+MmioBitFieldRead8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead8 (MmioRead8 (Address), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a MMIO register.
+
+ Writes Value to the bit field of the MMIO register. The bit field is
+ specified by the StartBit and the EndBit. All other bits in the destination
+ MMIO register are preserved. The new value of the 8-bit register is returned.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param Value New value of the bit field.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+MmioBitFieldWrite8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
+ )
+{
+ return MmioWrite8 (
+ Address,
+ BitFieldWrite8 (MmioRead8 (Address), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit MMIO register, performs a bitwise OR, and
+ writes the result back to the bit field in the 8-bit MMIO register.
+
+ Reads the 8-bit MMIO register specified by Address, performs a bitwise
+ inclusive OR between the read result and the value specified by OrData, and
+ writes the result to the 8-bit MMIO register specified by Address. The value
+ written to the MMIO register is returned. This function must guarantee that
+ all MMIO read and write operations are serialized. Extra left bits in OrData
+ are stripped.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param OrData The value to OR with read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+MmioBitFieldOr8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
+ )
+{
+ return MmioWrite8 (
+ Address,
+ BitFieldOr8 (MmioRead8 (Address), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit MMIO register, performs a bitwise AND, and
+ writes the result back to the bit field in the 8-bit MMIO register.
+
+ Reads the 8-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, and writes the
+ result to the 8-bit MMIO register specified by Address. The value written to
+ the MMIO register is returned. This function must guarantee that all MMIO
+ read and write operations are serialized. Extra left bits in AndData are
+ stripped.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+MmioBitFieldAnd8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
+ )
+{
+ return MmioWrite8 (
+ Address,
+ BitFieldAnd8 (MmioRead8 (Address), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit MMIO register, performs a bitwise AND followed
+ by a bitwise OR, and writes the result back to the bit field in the
+ 8-bit MMIO register.
+
+ Reads the 8-bit MMIO register specified by Address, performs a bitwise AND
+ followed by a bitwise OR between the read result and the value
+ specified by AndData, and writes the result to the 8-bit MMIO register
+ specified by Address. The value written to the MMIO register is returned.
+ This function must guarantee that all MMIO read and write operations are
+ serialized. Extra left bits in both AndData and OrData are stripped.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+MmioBitFieldAndThenOr8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return MmioWrite8 (
+ Address,
+ BitFieldAndThenOr8 (MmioRead8 (Address), StartBit, EndBit, AndData, OrData)
+ );
+}
+
+/**
+ Reads a 16-bit MMIO register, performs a bitwise OR, and writes the
+ result back to the 16-bit MMIO register.
+
+ Reads the 16-bit MMIO register specified by Address, performs a bitwise
+ inclusive OR between the read result and the value specified by OrData, and
+ writes the result to the 16-bit MMIO register specified by Address. The value
+ written to the MMIO register is returned. This function must guarantee that
+ all MMIO read and write operations are serialized.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+MmioOr16 (
+ IN UINTN Address,
+ IN UINT16 OrData
+ )
+{
+ return MmioWrite16 (Address, (UINT16) (MmioRead16 (Address) | OrData));
+}
+
+/**
+ Reads a 16-bit MMIO register, performs a bitwise AND, and writes the result
+ back to the 16-bit MMIO register.
+
+ Reads the 16-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, and writes the
+ result to the 16-bit MMIO register specified by Address. The value written to
+ the MMIO register is returned. This function must guarantee that all MMIO
+ read and write operations are serialized.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+MmioAnd16 (
+ IN UINTN Address,
+ IN UINT16 AndData
+ )
+{
+ return MmioWrite16 (Address, (UINT16) (MmioRead16 (Address) & AndData));
+}
+
+/**
+ Reads a 16-bit MMIO register, performs a bitwise AND followed by a bitwise
+ inclusive OR, and writes the result back to the 16-bit MMIO register.
+
+ Reads the 16-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, performs a
+ bitwise OR between the result of the AND operation and the value specified by
+ OrData, and writes the result to the 16-bit MMIO register specified by
+ Address. The value written to the MMIO register is returned. This function
+ must guarantee that all MMIO read and write operations are serialized.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+MmioAndThenOr16 (
+ IN UINTN Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ return MmioWrite16 (Address, (UINT16) ((MmioRead16 (Address) & AndData) | OrData));
+}
+
+/**
+ Reads a bit field of a MMIO register.
+
+ Reads the bit field in a 16-bit MMIO register. The bit field is specified by
+ the StartBit and the EndBit. The value of the bit field is returned.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address MMIO register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+MmioBitFieldRead16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead16 (MmioRead16 (Address), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a MMIO register.
+
+ Writes Value to the bit field of the MMIO register. The bit field is
+ specified by the StartBit and the EndBit. All other bits in the destination
+ MMIO register are preserved. The new value of the 16-bit register is returned.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param Value New value of the bit field.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+MmioBitFieldWrite16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
+ )
+{
+ return MmioWrite16 (
+ Address,
+ BitFieldWrite16 (MmioRead16 (Address), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads a bit field in a 16-bit MMIO register, performs a bitwise OR, and
+ writes the result back to the bit field in the 16-bit MMIO register.
+
+ Reads the 16-bit MMIO register specified by Address, performs a bitwise
+ inclusive OR between the read result and the value specified by OrData, and
+ writes the result to the 16-bit MMIO register specified by Address. The value
+ written to the MMIO register is returned. This function must guarantee that
+ all MMIO read and write operations are serialized. Extra left bits in OrData
+ are stripped.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param OrData The value to OR with read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+MmioBitFieldOr16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
+ )
+{
+ return MmioWrite16 (
+ Address,
+ BitFieldOr16 (MmioRead16 (Address), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in a 16-bit MMIO register, performs a bitwise AND, and
+ writes the result back to the bit field in the 16-bit MMIO register.
+
+ Reads the 16-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, and writes the
+ result to the 16-bit MMIO register specified by Address. The value written to
+ the MMIO register is returned. This function must guarantee that all MMIO
+ read and write operations are serialized. Extra left bits in AndData are
+ stripped.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+MmioBitFieldAnd16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
+ )
+{
+ return MmioWrite16 (
+ Address,
+ BitFieldAnd16 (MmioRead16 (Address), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in a 16-bit MMIO register, performs a bitwise AND followed
+ by a bitwise OR, and writes the result back to the bit field in the
+ 16-bit MMIO register.
+
+ Reads the 16-bit MMIO register specified by Address, performs a bitwise AND
+ followed by a bitwise OR between the read result and the value
+ specified by AndData, and writes the result to the 16-bit MMIO register
+ specified by Address. The value written to the MMIO register is returned.
+ This function must guarantee that all MMIO read and write operations are
+ serialized. Extra left bits in both AndData and OrData are stripped.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+MmioBitFieldAndThenOr16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ return MmioWrite16 (
+ Address,
+ BitFieldAndThenOr16 (MmioRead16 (Address), StartBit, EndBit, AndData, OrData)
+ );
+}
+
+/**
+ Reads a 32-bit MMIO register, performs a bitwise OR, and writes the
+ result back to the 32-bit MMIO register.
+
+ Reads the 32-bit MMIO register specified by Address, performs a bitwise
+ inclusive OR between the read result and the value specified by OrData, and
+ writes the result to the 32-bit MMIO register specified by Address. The value
+ written to the MMIO register is returned. This function must guarantee that
+ all MMIO read and write operations are serialized.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+MmioOr32 (
+ IN UINTN Address,
+ IN UINT32 OrData
+ )
+{
+ return MmioWrite32 (Address, MmioRead32 (Address) | OrData);
+}
+
+/**
+ Reads a 32-bit MMIO register, performs a bitwise AND, and writes the result
+ back to the 32-bit MMIO register.
+
+ Reads the 32-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, and writes the
+ result to the 32-bit MMIO register specified by Address. The value written to
+ the MMIO register is returned. This function must guarantee that all MMIO
+ read and write operations are serialized.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+MmioAnd32 (
+ IN UINTN Address,
+ IN UINT32 AndData
+ )
+{
+ return MmioWrite32 (Address, MmioRead32 (Address) & AndData);
+}
+
+/**
+ Reads a 32-bit MMIO register, performs a bitwise AND followed by a bitwise
+ inclusive OR, and writes the result back to the 32-bit MMIO register.
+
+ Reads the 32-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, performs a
+ bitwise OR between the result of the AND operation and the value specified by
+ OrData, and writes the result to the 32-bit MMIO register specified by
+ Address. The value written to the MMIO register is returned. This function
+ must guarantee that all MMIO read and write operations are serialized.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+MmioAndThenOr32 (
+ IN UINTN Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return MmioWrite32 (Address, (MmioRead32 (Address) & AndData) | OrData);
+}
+
+/**
+ Reads a bit field of a MMIO register.
+
+ Reads the bit field in a 32-bit MMIO register. The bit field is specified by
+ the StartBit and the EndBit. The value of the bit field is returned.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address MMIO register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+MmioBitFieldRead32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead32 (MmioRead32 (Address), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a MMIO register.
+
+ Writes Value to the bit field of the MMIO register. The bit field is
+ specified by the StartBit and the EndBit. All other bits in the destination
+ MMIO register are preserved. The new value of the 32-bit register is returned.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param Value New value of the bit field.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+MmioBitFieldWrite32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ )
+{
+ return MmioWrite32 (
+ Address,
+ BitFieldWrite32 (MmioRead32 (Address), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit MMIO register, performs a bitwise OR, and
+ writes the result back to the bit field in the 32-bit MMIO register.
+
+ Reads the 32-bit MMIO register specified by Address, performs a bitwise
+ inclusive OR between the read result and the value specified by OrData, and
+ writes the result to the 32-bit MMIO register specified by Address. The value
+ written to the MMIO register is returned. This function must guarantee that
+ all MMIO read and write operations are serialized. Extra left bits in OrData
+ are stripped.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param OrData The value to OR with read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+MmioBitFieldOr32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ )
+{
+ return MmioWrite32 (
+ Address,
+ BitFieldOr32 (MmioRead32 (Address), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit MMIO register, performs a bitwise AND, and
+ writes the result back to the bit field in the 32-bit MMIO register.
+
+ Reads the 32-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, and writes the
+ result to the 32-bit MMIO register specified by Address. The value written to
+ the MMIO register is returned. This function must guarantee that all MMIO
+ read and write operations are serialized. Extra left bits in AndData are
+ stripped.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+MmioBitFieldAnd32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ )
+{
+ return MmioWrite32 (
+ Address,
+ BitFieldAnd32 (MmioRead32 (Address), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit MMIO register, performs a bitwise AND followed
+ by a bitwise OR, and writes the result back to the bit field in the
+ 32-bit MMIO register.
+
+ Reads the 32-bit MMIO register specified by Address, performs a bitwise AND
+ followed by a bitwise OR between the read result and the value
+ specified by AndData, and writes the result to the 32-bit MMIO register
+ specified by Address. The value written to the MMIO register is returned.
+ This function must guarantee that all MMIO read and write operations are
+ serialized. Extra left bits in both AndData and OrData are stripped.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+MmioBitFieldAndThenOr32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return MmioWrite32 (
+ Address,
+ BitFieldAndThenOr32 (MmioRead32 (Address), StartBit, EndBit, AndData, OrData)
+ );
+}
+
+/**
+ Reads a 64-bit MMIO register, performs a bitwise OR, and writes the
+ result back to the 64-bit MMIO register.
+
+ Reads the 64-bit MMIO register specified by Address, performs a bitwise
+ inclusive OR between the read result and the value specified by OrData, and
+ writes the result to the 64-bit MMIO register specified by Address. The value
+ written to the MMIO register is returned. This function must guarantee that
+ all MMIO read and write operations are serialized.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+MmioOr64 (
+ IN UINTN Address,
+ IN UINT64 OrData
+ )
+{
+ return MmioWrite64 (Address, MmioRead64 (Address) | OrData);
+}
+
+/**
+ Reads a 64-bit MMIO register, performs a bitwise AND, and writes the result
+ back to the 64-bit MMIO register.
+
+ Reads the 64-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, and writes the
+ result to the 64-bit MMIO register specified by Address. The value written to
+ the MMIO register is returned. This function must guarantee that all MMIO
+ read and write operations are serialized.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+MmioAnd64 (
+ IN UINTN Address,
+ IN UINT64 AndData
+ )
+{
+ return MmioWrite64 (Address, MmioRead64 (Address) & AndData);
+}
+
+/**
+ Reads a 64-bit MMIO register, performs a bitwise AND followed by a bitwise
+ inclusive OR, and writes the result back to the 64-bit MMIO register.
+
+ Reads the 64-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, performs a
+ bitwise OR between the result of the AND operation and the value specified by
+ OrData, and writes the result to the 64-bit MMIO register specified by
+ Address. The value written to the MMIO register is returned. This function
+ must guarantee that all MMIO read and write operations are serialized.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+MmioAndThenOr64 (
+ IN UINTN Address,
+ IN UINT64 AndData,
+ IN UINT64 OrData
+ )
+{
+ return MmioWrite64 (Address, (MmioRead64 (Address) & AndData) | OrData);
+}
+
+/**
+ Reads a bit field of a MMIO register.
+
+ Reads the bit field in a 64-bit MMIO register. The bit field is specified by
+ the StartBit and the EndBit. The value of the bit field is returned.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address MMIO register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+
+ @return The value read.
+
+**/
+UINT64
+EFIAPI
+MmioBitFieldRead64 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead64 (MmioRead64 (Address), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a MMIO register.
+
+ Writes Value to the bit field of the MMIO register. The bit field is
+ specified by the StartBit and the EndBit. All other bits in the destination
+ MMIO register are preserved. The new value of the 64-bit register is returned.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param Value New value of the bit field.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+MmioBitFieldWrite64 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 Value
+ )
+{
+ return MmioWrite64 (
+ Address,
+ BitFieldWrite64 (MmioRead64 (Address), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads a bit field in a 64-bit MMIO register, performs a bitwise OR, and
+ writes the result back to the bit field in the 64-bit MMIO register.
+
+ Reads the 64-bit MMIO register specified by Address, performs a bitwise
+ inclusive OR between the read result and the value specified by OrData, and
+ writes the result to the 64-bit MMIO register specified by Address. The value
+ written to the MMIO register is returned. This function must guarantee that
+ all MMIO read and write operations are serialized. Extra left bits in OrData
+ are stripped.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param OrData The value to OR with read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+MmioBitFieldOr64 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 OrData
+ )
+{
+ return MmioWrite64 (
+ Address,
+ BitFieldOr64 (MmioRead64 (Address), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in a 64-bit MMIO register, performs a bitwise AND, and
+ writes the result back to the bit field in the 64-bit MMIO register.
+
+ Reads the 64-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, and writes the
+ result to the 64-bit MMIO register specified by Address. The value written to
+ the MMIO register is returned. This function must guarantee that all MMIO
+ read and write operations are serialized. Extra left bits in AndData are
+ stripped.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param AndData The value to AND with read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+MmioBitFieldAnd64 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData
+ )
+{
+ return MmioWrite64 (
+ Address,
+ BitFieldAnd64 (MmioRead64 (Address), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in a 64-bit MMIO register, performs a bitwise AND followed
+ by a bitwise OR, and writes the result back to the bit field in the
+ 64-bit MMIO register.
+
+ Reads the 64-bit MMIO register specified by Address, performs a bitwise AND
+ followed by a bitwise OR between the read result and the value
+ specified by AndData, and writes the result to the 64-bit MMIO register
+ specified by Address. The value written to the MMIO register is returned.
+ This function must guarantee that all MMIO read and write operations are
+ serialized. Extra left bits in both AndData and OrData are stripped.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param AndData The value to AND with read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+MmioBitFieldAndThenOr64 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData,
+ IN UINT64 OrData
+ )
+{
+ return MmioWrite64 (
+ Address,
+ BitFieldAndThenOr64 (MmioRead64 (Address), StartBit, EndBit, AndData, OrData)
+ );
+}
diff --git a/MdePkg/Library/SmmIoLibCpuIo/IoLib.c b/MdePkg/Library/SmmIoLibCpuIo/IoLib.c new file mode 100644 index 0000000000..4b74e9c222 --- /dev/null +++ b/MdePkg/Library/SmmIoLibCpuIo/IoLib.c @@ -0,0 +1,642 @@ +/** @file
+ I/O Library.
+ The implementation of I/O operation for this library instance
+ are based on EFI_CPU_IO_PROTOCOL.
+
+ Copyright (c) 2009, Intel Corporation<BR>
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Module Name: IoLib.c
+
+**/
+
+
+#include "SmmCpuIoLibInternal.h"
+
+//
+// Globle varible to cache pointer to CpuIo protocol.
+//
+EFI_SMM_CPU_IO_PROTOCOL *mCpuIo = NULL;
+EFI_SMM_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo = NULL;
+
+/**
+ The constructor function caches the pointer to CpuIo protocol.
+
+ The constructor function locates CpuIo protocol from protocol database.
+ It will ASSERT() if that operation fails and it will always return EFI_SUCCESS.
+
+ @param ImageHandle The firmware allocated handle for the EFI image.
+ @param SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
+
+**/
+EFI_STATUS
+EFIAPI
+IoLibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ Status = gSmst->SmmLocateProtocol (&gEfiSmmPciRootBridgeIoProtocolGuid, NULL, (VOID **) &mPciRootBridgeIo);
+ if (EFI_ERROR (Status)) {
+ Status = gSmst->SmmLocateProtocol (&gEfiSmmCpuIoProtocolGuid, NULL, (VOID **) &mCpuIo);
+ }
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+/**
+ Reads registers in the EFI CPU I/O space.
+
+ Reads the I/O port specified by Port with registers width specified by Width.
+ The read value is returned. If such operations are not supported, then ASSERT().
+ This function must guarantee that all I/O read and write operations are serialized.
+
+ @param Port The base address of the I/O operation.
+ The caller is responsible for aligning the Address if required.
+ @param Width The width of the I/O operation.
+
+ @return Data read from registers in the EFI CPU I/O space.
+
+**/
+UINT64
+EFIAPI
+IoReadWorker (
+ IN UINTN Port,
+ IN EFI_SMM_IO_WIDTH Width
+ )
+{
+ EFI_STATUS Status;
+ UINT64 Data;
+
+ if (mPciRootBridgeIo != NULL) {
+ Status = mPciRootBridgeIo->Io.Read (mPciRootBridgeIo, (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, Port, 1, &Data);
+ } else {
+ Status = mCpuIo->Io.Read (mCpuIo, Width, Port, 1, &Data);
+ }
+ ASSERT_EFI_ERROR (Status);
+
+ return Data;
+}
+
+/**
+ Writes registers in the EFI CPU I/O space.
+
+ Writes the I/O port specified by Port with registers width and value specified by Width
+ and Data respectively. Data is returned. If such operations are not supported, then ASSERT().
+ This function must guarantee that all I/O read and write operations are serialized.
+
+ @param Port The base address of the I/O operation.
+ The caller is responsible for aligning the Address if required.
+ @param Width The width of the I/O operation.
+ @param Data The value to write to the I/O port.
+
+ @return The paramter of Data.
+
+**/
+UINT64
+EFIAPI
+IoWriteWorker (
+ IN UINTN Port,
+ IN EFI_SMM_IO_WIDTH Width,
+ IN UINT64 Data
+ )
+{
+ EFI_STATUS Status;
+
+ if (mPciRootBridgeIo != NULL) {
+ Status = mPciRootBridgeIo->Io.Write (mPciRootBridgeIo, (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, Port, 1, &Data);
+ } else {
+ Status = mCpuIo->Io.Write (mCpuIo, Width, Port, 1, &Data);
+ }
+ ASSERT_EFI_ERROR (Status);
+
+ return Data;
+}
+
+/**
+ Reads memory-mapped registers in the EFI system memory space.
+
+ Reads the MMIO registers specified by Address with registers width specified by Width.
+ The read value is returned. If such operations are not supported, then ASSERT().
+ This function must guarantee that all MMIO read and write operations are serialized.
+
+ @param Address The MMIO register to read.
+ The caller is responsible for aligning the Address if required.
+ @param Width The width of the I/O operation.
+
+ @return Data read from registers in the EFI system memory space.
+
+**/
+UINT64
+EFIAPI
+MmioReadWorker (
+ IN UINTN Address,
+ IN EFI_SMM_IO_WIDTH Width
+ )
+{
+ EFI_STATUS Status;
+ UINT64 Data;
+
+ if (mPciRootBridgeIo != NULL) {
+ Status = mPciRootBridgeIo->Mem.Read (mPciRootBridgeIo, (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, Address, 1, &Data);
+ } else {
+ Status = mCpuIo->Mem.Read (mCpuIo, Width, Address, 1, &Data);
+ }
+ ASSERT_EFI_ERROR (Status);
+
+ return Data;
+}
+
+/**
+ Writes memory-mapped registers in the EFI system memory space.
+
+ Writes the MMIO registers specified by Address with registers width and value specified by Width
+ and Data respectively. Data is returned. If such operations are not supported, then ASSERT().
+ This function must guarantee that all MMIO read and write operations are serialized.
+
+ @param Address The MMIO register to read.
+ The caller is responsible for aligning the Address if required.
+ @param Width The width of the I/O operation.
+ @param Data The value to write to the I/O port.
+
+ @return Data read from registers in the EFI system memory space.
+
+**/
+UINT64
+EFIAPI
+MmioWriteWorker (
+ IN UINTN Address,
+ IN EFI_SMM_IO_WIDTH Width,
+ IN UINT64 Data
+ )
+{
+ EFI_STATUS Status;
+
+ if (mPciRootBridgeIo != NULL) {
+ Status = mPciRootBridgeIo->Mem.Write (mPciRootBridgeIo, (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, Address, 1, &Data);
+ } else {
+ Status = mCpuIo->Mem.Write (mCpuIo, Width, Address, 1, &Data);
+ }
+ ASSERT_EFI_ERROR (Status);
+
+ return Data;
+}
+
+/**
+ Reads an 8-bit I/O port.
+
+ Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+IoRead8 (
+ IN UINTN Port
+ )
+{
+ return (UINT8)IoReadWorker (Port, SMM_IO_UINT8);
+}
+
+/**
+ Writes an 8-bit I/O port.
+
+ Writes the 8-bit I/O port specified by Port with the value specified by Value
+ and returns Value. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written the I/O port.
+
+**/
+UINT8
+EFIAPI
+IoWrite8 (
+ IN UINTN Port,
+ IN UINT8 Value
+ )
+{
+ return (UINT8)IoWriteWorker (Port, SMM_IO_UINT8, Value);
+}
+
+/**
+ Reads a 16-bit I/O port.
+
+ Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If Port is not aligned on a 16-bit boundary, then ASSERT().
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+IoRead16 (
+ IN UINTN Port
+ )
+{
+ //
+ // Make sure Port is aligned on a 16-bit boundary.
+ //
+ ASSERT ((Port & 1) == 0);
+ return (UINT16)IoReadWorker (Port, SMM_IO_UINT16);
+}
+
+/**
+ Writes a 16-bit I/O port.
+
+ Writes the 16-bit I/O port specified by Port with the value specified by Value
+ and returns Value. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If Port is not aligned on a 16-bit boundary, then ASSERT().
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written the I/O port.
+
+**/
+UINT16
+EFIAPI
+IoWrite16 (
+ IN UINTN Port,
+ IN UINT16 Value
+ )
+{
+ //
+ // Make sure Port is aligned on a 16-bit boundary.
+ //
+ ASSERT ((Port & 1) == 0);
+ return (UINT16)IoWriteWorker (Port, SMM_IO_UINT16, Value);
+}
+
+/**
+ Reads a 32-bit I/O port.
+
+ Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If Port is not aligned on a 32-bit boundary, then ASSERT().
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+IoRead32 (
+ IN UINTN Port
+ )
+{
+ //
+ // Make sure Port is aligned on a 32-bit boundary.
+ //
+ ASSERT ((Port & 3) == 0);
+ return (UINT32)IoReadWorker (Port, SMM_IO_UINT32);
+}
+
+/**
+ Writes a 32-bit I/O port.
+
+ Writes the 32-bit I/O port specified by Port with the value specified by Value
+ and returns Value. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If Port is not aligned on a 32-bit boundary, then ASSERT().
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written the I/O port.
+
+**/
+UINT32
+EFIAPI
+IoWrite32 (
+ IN UINTN Port,
+ IN UINT32 Value
+ )
+{
+ //
+ // Make sure Port is aligned on a 32-bit boundary.
+ //
+ ASSERT ((Port & 3) == 0);
+ return (UINT32)IoWriteWorker (Port, SMM_IO_UINT32, Value);
+}
+
+/**
+ Reads a 64-bit I/O port.
+
+ Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If Port is not aligned on a 64-bit boundary, then ASSERT().
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT64
+EFIAPI
+IoRead64 (
+ IN UINTN Port
+ )
+{
+ //
+ // Make sure Port is aligned on a 64-bit boundary.
+ //
+ ASSERT ((Port & 7) == 0);
+ return IoReadWorker (Port, SMM_IO_UINT64);
+}
+
+/**
+ Writes a 64-bit I/O port.
+
+ Writes the 64-bit I/O port specified by Port with the value specified by Value
+ and returns Value. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If Port is not aligned on a 64-bit boundary, then ASSERT().
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written the I/O port.
+
+**/
+UINT64
+EFIAPI
+IoWrite64 (
+ IN UINTN Port,
+ IN UINT64 Value
+ )
+{
+ //
+ // Make sure Port is aligned on a 64-bit boundary.
+ //
+ ASSERT ((Port & 7) == 0);
+ return IoWriteWorker (Port, SMM_IO_UINT64, Value);
+}
+
+/**
+ Reads an 8-bit MMIO register.
+
+ Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
+ returned. This function must guarantee that all MMIO read and write
+ operations are serialized.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+MmioRead8 (
+ IN UINTN Address
+ )
+{
+ return (UINT8)MmioReadWorker (Address, SMM_IO_UINT8);
+}
+
+/**
+ Writes an 8-bit MMIO register.
+
+ Writes the 8-bit MMIO register specified by Address with the value specified
+ by Value and returns Value. This function must guarantee that all MMIO read
+ and write operations are serialized.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+MmioWrite8 (
+ IN UINTN Address,
+ IN UINT8 Value
+ )
+{
+ return (UINT8)MmioWriteWorker (Address, SMM_IO_UINT8, Value);
+}
+
+/**
+ Reads a 16-bit MMIO register.
+
+ Reads the 16-bit MMIO register specified by Address. The 16-bit read value is
+ returned. This function must guarantee that all MMIO read and write
+ operations are serialized.
+
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+MmioRead16 (
+ IN UINTN Address
+ )
+{
+ //
+ // Make sure Address is aligned on a 16-bit boundary.
+ //
+ ASSERT ((Address & 1) == 0);
+ return (UINT16)MmioReadWorker (Address, SMM_IO_UINT16);
+}
+
+/**
+ Writes a 16-bit MMIO register.
+
+ Writes the 16-bit MMIO register specified by Address with the value specified
+ by Value and returns Value. This function must guarantee that all MMIO read
+ and write operations are serialized.
+
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+MmioWrite16 (
+ IN UINTN Address,
+ IN UINT16 Value
+ )
+{
+ //
+ // Make sure Address is aligned on a 16-bit boundary.
+ //
+ ASSERT ((Address & 1) == 0);
+ return (UINT16)MmioWriteWorker (Address, SMM_IO_UINT16, Value);
+}
+
+/**
+ Reads a 32-bit MMIO register.
+
+ Reads the 32-bit MMIO register specified by Address. The 32-bit read value is
+ returned. This function must guarantee that all MMIO read and write
+ operations are serialized.
+
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+MmioRead32 (
+ IN UINTN Address
+ )
+{
+ //
+ // Make sure Address is aligned on a 32-bit boundary.
+ //
+ ASSERT ((Address & 3) == 0);
+ return (UINT32)MmioReadWorker (Address, SMM_IO_UINT32);
+}
+
+/**
+ Writes a 32-bit MMIO register.
+
+ Writes the 32-bit MMIO register specified by Address with the value specified
+ by Value and returns Value. This function must guarantee that all MMIO read
+ and write operations are serialized.
+
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+MmioWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ )
+{
+ //
+ // Make sure Address is aligned on a 32-bit boundary.
+ //
+ ASSERT ((Address & 3) == 0);
+ return (UINT32)MmioWriteWorker (Address, SMM_IO_UINT32, Value);
+}
+
+/**
+ Reads a 64-bit MMIO register.
+
+ Reads the 64-bit MMIO register specified by Address. The 64-bit read value is
+ returned. This function must guarantee that all MMIO read and write
+ operations are serialized.
+
+ If Address is not aligned on a 64-bit boundary, then ASSERT().
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT64
+EFIAPI
+MmioRead64 (
+ IN UINTN Address
+ )
+{
+ //
+ // Make sure Address is aligned on a 64-bit boundary.
+ //
+ ASSERT ((Address & 7) == 0);
+ return (UINT64)MmioReadWorker (Address, SMM_IO_UINT64);
+}
+
+/**
+ Writes a 64-bit MMIO register.
+
+ Writes the 64-bit MMIO register specified by Address with the value specified
+ by Value and returns Value. This function must guarantee that all MMIO read
+ and write operations are serialized.
+
+ If Address is not aligned on a 64-bit boundary, then ASSERT().
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+MmioWrite64 (
+ IN UINTN Address,
+ IN UINT64 Value
+ )
+{
+ //
+ // Make sure Address is aligned on a 64-bit boundary.
+ //
+ ASSERT ((Address & 7) == 0);
+ return (UINT64)MmioWriteWorker (Address, SMM_IO_UINT64, Value);
+}
diff --git a/MdePkg/Library/SmmIoLibCpuIo/IoLibMmioBuffer.c b/MdePkg/Library/SmmIoLibCpuIo/IoLibMmioBuffer.c new file mode 100644 index 0000000000..e4effa9602 --- /dev/null +++ b/MdePkg/Library/SmmIoLibCpuIo/IoLibMmioBuffer.c @@ -0,0 +1,416 @@ +/** @file
+ I/O Library MMIO Buffer Functions.
+
+ Copyright (c) 2009, Intel Corporation<BR>
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Module Name: IoLibMmioBuffer.c
+
+**/
+
+
+#include "SmmCpuIoLibInternal.h"
+
+/**
+ Copy data from MMIO region to system memory by using 8-bit access.
+
+ Copy data from MMIO region specified by starting address StartAddress
+ to system memory specified by Buffer by using 8-bit access. The total
+ number of byte to be copied is specified by Length. Buffer is returned.
+
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+
+ @param StartAddress Starting address for the MMIO region to be copied from.
+ @param Length Size in bytes of the copy.
+ @param Buffer Pointer to a system memory buffer receiving the data read.
+
+ @return Buffer
+
+**/
+UINT8 *
+EFIAPI
+MmioReadBuffer8 (
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ OUT UINT8 *Buffer
+ )
+{
+ UINT8 *ReturnBuffer;
+
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
+
+ ReturnBuffer = Buffer;
+
+ while (Length-- > 0) {
+ *(Buffer++) = MmioRead8 (StartAddress++);
+ }
+
+ return ReturnBuffer;
+}
+
+/**
+ Copy data from MMIO region to system memory by using 16-bit access.
+
+ Copy data from MMIO region specified by starting address StartAddress
+ to system memory specified by Buffer by using 16-bit access. The total
+ number of byte to be copied is specified by Length. Buffer is returned.
+
+ If StartAddress is not aligned on a 16-bit boundary, then ASSERT().
+
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ If Length is not aligned on a 16-bit boundary, then ASSERT().
+
+ If Buffer is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param StartAddress Starting address for the MMIO region to be copied from.
+ @param Length Size in bytes of the copy.
+ @param Buffer Pointer to a system memory buffer receiving the data read.
+
+ @return Buffer
+
+**/
+UINT16 *
+EFIAPI
+MmioReadBuffer16 (
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ OUT UINT16 *Buffer
+ )
+{
+ UINT16 *ReturnBuffer;
+
+ ASSERT ((StartAddress & (sizeof (UINT16) - 1)) == 0);
+
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
+
+ ASSERT ((Length & (sizeof (UINT16) - 1)) == 0);
+ ASSERT (((UINTN) Buffer & (sizeof (UINT16) - 1)) == 0);
+
+ ReturnBuffer = Buffer;
+
+ while (Length > 0) {
+ *(Buffer++) = MmioRead16 (StartAddress);
+ StartAddress += sizeof (UINT16);
+ Length -= sizeof (UINT16);
+ }
+
+ return ReturnBuffer;
+}
+
+/**
+ Copy data from MMIO region to system memory by using 32-bit access.
+
+ Copy data from MMIO region specified by starting address StartAddress
+ to system memory specified by Buffer by using 32-bit access. The total
+ number of byte to be copied is specified by Length. Buffer is returned.
+
+ If StartAddress is not aligned on a 32-bit boundary, then ASSERT().
+
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ If Length is not aligned on a 32-bit boundary, then ASSERT().
+ If Buffer is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param StartAddress Starting address for the MMIO region to be copied from.
+ @param Length Size in bytes of the copy.
+ @param Buffer Pointer to a system memory buffer receiving the data read.
+
+ @return Buffer
+
+**/
+UINT32 *
+EFIAPI
+MmioReadBuffer32 (
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ OUT UINT32 *Buffer
+ )
+{
+ UINT32 *ReturnBuffer;
+
+ ASSERT ((StartAddress & (sizeof (UINT32) - 1)) == 0);
+
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
+
+ ASSERT ((Length & (sizeof (UINT32) - 1)) == 0);
+ ASSERT (((UINTN) Buffer & (sizeof (UINT32) - 1)) == 0);
+
+ ReturnBuffer = Buffer;
+
+ while (Length > 0) {
+ *(Buffer++) = MmioRead32 (StartAddress);
+ StartAddress += sizeof (UINT32);
+ Length -= sizeof (UINT32);
+ }
+
+ return ReturnBuffer;
+}
+
+/**
+ Copy data from MMIO region to system memory by using 64-bit access.
+
+ Copy data from MMIO region specified by starting address StartAddress
+ to system memory specified by Buffer by using 64-bit access. The total
+ number of byte to be copied is specified by Length. Buffer is returned.
+
+ If StartAddress is not aligned on a 64-bit boundary, then ASSERT().
+
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ If Length is not aligned on a 64-bit boundary, then ASSERT().
+
+ If Buffer is not aligned on a 64-bit boundary, then ASSERT().
+
+ @param StartAddress Starting address for the MMIO region to be copied from.
+ @param Length Size in bytes of the copy.
+ @param Buffer Pointer to a system memory buffer receiving the data read.
+
+ @return Buffer
+
+**/
+UINT64 *
+EFIAPI
+MmioReadBuffer64 (
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ OUT UINT64 *Buffer
+ )
+{
+ UINT64 *ReturnBuffer;
+
+ ASSERT ((StartAddress & (sizeof (UINT64) - 1)) == 0);
+
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
+
+ ASSERT ((Length & (sizeof (UINT64) - 1)) == 0);
+ ASSERT (((UINTN) Buffer & (sizeof (UINT64) - 1)) == 0);
+
+ ReturnBuffer = Buffer;
+
+ while (Length > 0) {
+ *(Buffer++) = MmioRead64 (StartAddress);
+ StartAddress += sizeof (UINT64);
+ Length -= sizeof (UINT64);
+ }
+
+ return ReturnBuffer;
+}
+
+
+/**
+ Copy data from system memory to MMIO region by using 8-bit access.
+
+ Copy data from system memory specified by Buffer to MMIO region specified
+ by starting address StartAddress by using 8-bit access. The total number
+ of byte to be copied is specified by Length. Buffer is returned.
+
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
+ If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
+
+
+ @param StartAddress Starting address for the MMIO region to be copied to.
+ @param Length Size in bytes of the copy.
+ @param Buffer Pointer to a system memory buffer containing the data to write.
+
+ @return Buffer
+
+**/
+UINT8 *
+EFIAPI
+MmioWriteBuffer8 (
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ IN CONST UINT8 *Buffer
+ )
+{
+ VOID* ReturnBuffer;
+
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
+
+ ReturnBuffer = (UINT8 *) Buffer;
+
+ while (Length-- > 0) {
+ MmioWrite8 (StartAddress++, *(Buffer++));
+ }
+
+ return ReturnBuffer;
+
+}
+
+/**
+ Copy data from system memory to MMIO region by using 16-bit access.
+
+ Copy data from system memory specified by Buffer to MMIO region specified
+ by starting address StartAddress by using 16-bit access. The total number
+ of byte to be copied is specified by Length. Buffer is returned.
+
+ If StartAddress is not aligned on a 16-bit boundary, then ASSERT().
+
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
+ If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
+
+ If Length is not aligned on a 16-bit boundary, then ASSERT().
+
+ If Buffer is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param StartAddress Starting address for the MMIO region to be copied to.
+ @param Length Size in bytes of the copy.
+ @param Buffer Pointer to a system memory buffer containing the data to write.
+
+ @return Buffer
+
+**/
+UINT16 *
+EFIAPI
+MmioWriteBuffer16 (
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ IN CONST UINT16 *Buffer
+ )
+{
+ UINT16 *ReturnBuffer;
+
+ ASSERT ((StartAddress & (sizeof (UINT16) - 1)) == 0);
+
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
+
+ ASSERT ((Length & (sizeof (UINT16) - 1)) == 0);
+ ASSERT (((UINTN) Buffer & (sizeof (UINT16) - 1)) == 0);
+
+ ReturnBuffer = (UINT16 *) Buffer;
+
+ while (Length > 0) {
+ MmioWrite16 (StartAddress, *(Buffer++));
+
+ StartAddress += sizeof (UINT16);
+ Length -= sizeof (UINT16);
+ }
+
+ return ReturnBuffer;
+}
+
+
+/**
+ Copy data from system memory to MMIO region by using 32-bit access.
+
+ Copy data from system memory specified by Buffer to MMIO region specified
+ by starting address StartAddress by using 32-bit access. The total number
+ of byte to be copied is specified by Length. Buffer is returned.
+
+ If StartAddress is not aligned on a 32-bit boundary, then ASSERT().
+
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
+ If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
+
+ If Length is not aligned on a 32-bit boundary, then ASSERT().
+
+ If Buffer is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param StartAddress Starting address for the MMIO region to be copied to.
+ @param Length Size in bytes of the copy.
+ @param Buffer Pointer to a system memory buffer containing the data to write.
+
+ @return Buffer
+
+**/
+UINT32 *
+EFIAPI
+MmioWriteBuffer32 (
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ IN CONST UINT32 *Buffer
+ )
+{
+ UINT32 *ReturnBuffer;
+
+ ASSERT ((StartAddress & (sizeof (UINT32) - 1)) == 0);
+
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
+
+ ASSERT ((Length & (sizeof (UINT32) - 1)) == 0);
+ ASSERT (((UINTN) Buffer & (sizeof (UINT32) - 1)) == 0);
+
+ ReturnBuffer = (UINT32 *) Buffer;
+
+ while (Length > 0) {
+ MmioWrite32 (StartAddress, *(Buffer++));
+
+ StartAddress += sizeof (UINT32);
+ Length -= sizeof (UINT32);
+ }
+
+ return ReturnBuffer;
+}
+
+/**
+ Copy data from system memory to MMIO region by using 64-bit access.
+
+ Copy data from system memory specified by Buffer to MMIO region specified
+ by starting address StartAddress by using 64-bit access. The total number
+ of byte to be copied is specified by Length. Buffer is returned.
+
+ If StartAddress is not aligned on a 64-bit boundary, then ASSERT().
+
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
+ If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
+
+ If Length is not aligned on a 64-bit boundary, then ASSERT().
+
+ If Buffer is not aligned on a 64-bit boundary, then ASSERT().
+
+ @param StartAddress Starting address for the MMIO region to be copied to.
+ @param Length Size in bytes of the copy.
+ @param Buffer Pointer to a system memory buffer containing the data to write.
+
+ @return Buffer
+
+**/
+UINT64 *
+EFIAPI
+MmioWriteBuffer64 (
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ IN CONST UINT64 *Buffer
+ )
+{
+ UINT64 *ReturnBuffer;
+
+ ASSERT ((StartAddress & (sizeof (UINT64) - 1)) == 0);
+
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
+
+ ASSERT ((Length & (sizeof (UINT64) - 1)) == 0);
+ ASSERT (((UINTN) Buffer & (sizeof (UINT64) - 1)) == 0);
+
+ ReturnBuffer = (UINT64 *) Buffer;
+
+ while (Length > 0) {
+ MmioWrite64 (StartAddress, *(Buffer++));
+
+ StartAddress += sizeof (UINT64);
+ Length -= sizeof (UINT64);
+ }
+
+ return ReturnBuffer;
+}
+
diff --git a/MdePkg/Library/SmmIoLibCpuIo/SmmCpuIoLibInternal.h b/MdePkg/Library/SmmIoLibCpuIo/SmmCpuIoLibInternal.h new file mode 100644 index 0000000000..e221bc8d9e --- /dev/null +++ b/MdePkg/Library/SmmIoLibCpuIo/SmmCpuIoLibInternal.h @@ -0,0 +1,121 @@ +/** @file
+ Internal include file of SMM CPU IO Library.
+ It includes all necessary protocol/library class's header file
+ for implementation of IoLib library instance. It is included
+ all source code of this library instance.
+
+ Copyright (c) 2009, Intel Corporation
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Module Name: DxeCpuIoLibInternal.h
+
+**/
+
+#ifndef _SMM_CPUIO_LIB_INTERNAL_H_
+#define _SMM_CPUIO_LIB_INTERNAL_H_
+
+
+#include <PiSmm.h>
+#include <Protocol/SmmCpuIo.h>
+#include <Protocol/SmmPciRootBridgeIo.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/SmmServicesTableLib.h>
+
+
+/**
+ Reads registers in the EFI CPU I/O space.
+
+ Reads the I/O port specified by Port with registers width specified by Width.
+ The read value is returned. If such operations are not supported, then ASSERT().
+ This function must guarantee that all I/O read and write operations are serialized.
+
+ @param Port The base address of the I/O operation.
+ The caller is responsible for aligning the Address if required.
+ @param Width The width of the I/O operation.
+
+ @return Data read from registers in the EFI CPU I/O space.
+
+**/
+UINT64
+EFIAPI
+IoReadWorker (
+ IN UINTN Port,
+ IN EFI_SMM_IO_WIDTH Width
+ );
+
+/**
+ Writes registers in the EFI CPU I/O space.
+
+ Writes the I/O port specified by Port with registers width and value specified by Width
+ and Data respectively. Data is returned. If such operations are not supported, then ASSERT().
+ This function must guarantee that all I/O read and write operations are serialized.
+
+ @param Port The base address of the I/O operation.
+ The caller is responsible for aligning the Address if required.
+ @param Width The width of the I/O operation.
+ @param Data The value to write to the I/O port.
+
+ @return The paramter of Data.
+
+**/
+UINT64
+EFIAPI
+IoWriteWorker (
+ IN UINTN Port,
+ IN EFI_SMM_IO_WIDTH Width,
+ IN UINT64 Data
+ );
+
+/**
+ Reads memory-mapped registers in the EFI system memory space.
+
+ Reads the MMIO registers specified by Address with registers width specified by Width.
+ The read value is returned. If such operations are not supported, then ASSERT().
+ This function must guarantee that all MMIO read and write operations are serialized.
+
+ @param Address The MMIO register to read.
+ The caller is responsible for aligning the Address if required.
+ @param Width The width of the I/O operation.
+
+ @return Data read from registers in the EFI system memory space.
+
+**/
+UINT64
+EFIAPI
+MmioReadWorker (
+ IN UINTN Address,
+ IN EFI_SMM_IO_WIDTH Width
+ );
+
+/**
+ Writes memory-mapped registers in the EFI system memory space.
+
+ Writes the MMIO registers specified by Address with registers width and value specified by Width
+ and Data respectively. Data is returned. If such operations are not supported, then ASSERT().
+ This function must guarantee that all MMIO read and write operations are serialized.
+
+ @param Address The MMIO register to read.
+ The caller is responsible for aligning the Address if required.
+ @param Width The width of the I/O operation.
+ @param Data The value to write to the I/O port.
+
+ @return Data read from registers in the EFI system memory space.
+
+**/
+UINT64
+EFIAPI
+MmioWriteWorker (
+ IN UINTN Address,
+ IN EFI_SMM_IO_WIDTH Width,
+ IN UINT64 Data
+ );
+
+#endif
diff --git a/MdePkg/Library/SmmIoLibCpuIo/SmmIoLibCpuIo.inf b/MdePkg/Library/SmmIoLibCpuIo/SmmIoLibCpuIo.inf new file mode 100644 index 0000000000..7be09dc878 --- /dev/null +++ b/MdePkg/Library/SmmIoLibCpuIo/SmmIoLibCpuIo.inf @@ -0,0 +1,56 @@ +#/** @file
+# Component description file for Cpu Io SMM Io Library.
+#
+# I/O Library implementation that uses the CPU I/O Protocol for I/O
+# and MMIO operations.
+# Copyright (c) 2009, Intel Corporation.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SmmIoLibCpuIo
+ FILE_GUID = DEEEA15E-4A77-4513-BA75-71D26FEF78A1
+ MODULE_TYPE = DXE_SMM_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = IoLib|DXE_SMM_DRIVER SMM_CORE
+ EFI_SPECIFICATION_VERSION = 0x00020000
+ PI_SPECIFICATION_VERSION = 0x0001000A
+
+ CONSTRUCTOR = IoLibConstructor
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[Sources.common]
+ IoLibMmioBuffer.c
+ SmmCpuIoLibInternal.h
+ IoHighLevel.c
+ IoLib.c
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ SmmServicesTableLib
+
+[Protocols]
+ gEfiSmmCpuIoProtocolGuid ## CONSUMES
+ gEfiSmmPciRootBridgeIoProtocolGuid ## CONSUMES
+
+[Depex]
+ gEfiSmmCpuIoProtocolGuid OR gEfiSmmPciRootBridgeIoProtocolGuid
\ No newline at end of file diff --git a/MdePkg/Library/SmmPciLibPciRootBridgeIo/PciLib.c b/MdePkg/Library/SmmPciLibPciRootBridgeIo/PciLib.c new file mode 100644 index 0000000000..5e16327667 --- /dev/null +++ b/MdePkg/Library/SmmPciLibPciRootBridgeIo/PciLib.c @@ -0,0 +1,1420 @@ +/** @file
+ PCI Library using SMM PCI Root Bridge I/O Protocol.
+
+ Copyright (c) 2009, Intel Corporation All rights
+ reserved. This program and the accompanying materials are
+ licensed and made available under the terms and conditions of
+ the BSD License which accompanies this distribution. The full
+ text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include <PiSmm.h>
+#include <Protocol/SmmCpuIo.h>
+#include <Protocol/SmmPciRootBridgeIo.h>
+#include <Library/PciLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/SmmServicesTableLib.h>
+
+
+/**
+ Assert the validity of a PCI address. A valid PCI address should contain 1's
+ only in the low 28 bits.
+
+ @param A The address to validate.
+ @param M Additional bits to assert to be zero.
+
+**/
+#define ASSERT_INVALID_PCI_ADDRESS(A,M) \
+ ASSERT (((A) & (~0xfffffff | (M))) == 0)
+
+/**
+ Translate PCI Lib address into format of PCI Root Bridge I/O Protocol.
+
+ @param A Address that encodes the PCI Bus, Device, Function and
+ Register.
+
+**/
+#define PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS(A) \
+ ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))
+
+//
+// Global varible to cache pointer to PCI Root Bridge I/O protocol.
+//
+EFI_SMM_PCI_ROOT_BRIDGE_IO_PROTOCOL *mSmmPciRootBridgeIo = NULL;
+
+/**
+ The constructor function caches the pointer to PCI Root Bridge I/O protocol.
+
+ The constructor function locates PCI Root Bridge I/O protocol from protocol database.
+ It will ASSERT() if that operation fails and it will always return EFI_SUCCESS.
+
+ @param ImageHandle The firmware allocated handle for the EFI image.
+ @param SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
+
+**/
+EFI_STATUS
+EFIAPI
+PciLibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ Status = gSmst->SmmLocateProtocol (&gEfiSmmPciRootBridgeIoProtocolGuid, NULL, (VOID**) &mSmmPciRootBridgeIo);
+ ASSERT_EFI_ERROR (Status);
+ ASSERT (mSmmPciRootBridgeIo != NULL);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Internal worker function to read a PCI configuration register.
+
+ This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Read() service.
+ It reads and returns the PCI configuration register specified by Address,
+ the width of data is specified by Width.
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param Width Width of data to read
+
+ @return The value read from the PCI configuration register.
+
+**/
+UINT32
+SmmPciLibPciRootBridgeIoReadWorker (
+ IN UINTN Address,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
+ )
+{
+ UINT32 Data;
+
+ mSmmPciRootBridgeIo->Pci.Read (
+ mSmmPciRootBridgeIo,
+ Width,
+ PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address),
+ 1,
+ &Data
+ );
+
+ return Data;
+}
+
+/**
+ Internal worker function to writes a PCI configuration register.
+
+ This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Write() service.
+ It writes the PCI configuration register specified by Address with the
+ value specified by Data. The width of data is specifed by Width.
+ Data is returned.
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param Width Width of data to write
+ @param Data The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+SmmPciLibPciRootBridgeIoWriteWorker (
+ IN UINTN Address,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT32 Data
+ )
+{
+ mSmmPciRootBridgeIo->Pci.Write (
+ mSmmPciRootBridgeIo,
+ Width,
+ PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address),
+ 1,
+ &Data
+ );
+ return Data;
+}
+
+/**
+ Registers a PCI device so PCI configuration registers may be accessed after
+ SetVirtualAddressMap().
+
+ Registers the PCI device specified by Address so all the PCI configuration registers
+ associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @retval RETURN_SUCCESS The PCI device was registered for runtime access.
+ @retval RETURN_UNSUPPORTED An attempt was made to call this function
+ after ExitBootServices().
+ @retval RETURN_UNSUPPORTED The resources required to access the PCI device
+ at runtime could not be mapped.
+ @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
+ complete the registration.
+
+**/
+RETURN_STATUS
+EFIAPI
+PciRegisterForRuntimeAccess (
+ IN UINTN Address
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address, 0);
+ return RETURN_UNSUPPORTED;
+}
+
+/**
+ Reads an 8-bit PCI configuration register.
+
+ Reads and returns the 8-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @return The read value from the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciRead8 (
+ IN UINTN Address
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address, 0);
+
+ return (UINT8) SmmPciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint8);
+}
+
+/**
+ Writes an 8-bit PCI configuration register.
+
+ Writes the 8-bit PCI configuration register specified by Address with the
+ value specified by Value. Value is returned. This function must guarantee
+ that all PCI read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciWrite8 (
+ IN UINTN Address,
+ IN UINT8 Value
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address, 0);
+
+ return (UINT8) SmmPciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Value);
+}
+
+/**
+ Performs a bitwise OR of an 8-bit PCI configuration register with
+ an 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 8-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciOr8 (
+ IN UINTN Address,
+ IN UINT8 OrData
+ )
+{
+ return PciWrite8 (Address, (UINT8) (PciRead8 (Address) | OrData));
+}
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
+ value.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 8-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciAnd8 (
+ IN UINTN Address,
+ IN UINT8 AndData
+ )
+{
+ return PciWrite8 (Address, (UINT8) (PciRead8 (Address) & AndData));
+}
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
+ value, followed a bitwise OR with another 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and
+ the value specified by OrData, and writes the result to the 8-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciAndThenOr8 (
+ IN UINTN Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return PciWrite8 (Address, (UINT8) ((PciRead8 (Address) & AndData) | OrData));
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in an 8-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciBitFieldRead8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead8 (PciRead8 (Address), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 8-bit register is returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciBitFieldWrite8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
+ )
+{
+ return PciWrite8 (
+ Address,
+ BitFieldWrite8 (PciRead8 (Address), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 8-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciBitFieldOr8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
+ )
+{
+ return PciWrite8 (
+ Address,
+ BitFieldOr8 (PciRead8 (Address), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 8-bit register.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 8-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciBitFieldAnd8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
+ )
+{
+ return PciWrite8 (
+ Address,
+ BitFieldAnd8 (PciRead8 (Address), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 8-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciBitFieldAndThenOr8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return PciWrite8 (
+ Address,
+ BitFieldAndThenOr8 (PciRead8 (Address), StartBit, EndBit, AndData, OrData)
+ );
+}
+
+/**
+ Reads a 16-bit PCI configuration register.
+
+ Reads and returns the 16-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @return The read value from the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciRead16 (
+ IN UINTN Address
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address, 1);
+
+ return (UINT16) SmmPciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint16);
+}
+
+/**
+ Writes a 16-bit PCI configuration register.
+
+ Writes the 16-bit PCI configuration register specified by Address with the
+ value specified by Value. Value is returned. This function must guarantee
+ that all PCI read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciWrite16 (
+ IN UINTN Address,
+ IN UINT16 Value
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address, 1);
+
+ return (UINT16) SmmPciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Value);
+}
+
+/**
+ Performs a bitwise OR of a 16-bit PCI configuration register with
+ a 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciOr16 (
+ IN UINTN Address,
+ IN UINT16 OrData
+ )
+{
+ return PciWrite16 (Address, (UINT16) (PciRead16 (Address) | OrData));
+}
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
+ value.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 16-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciAnd16 (
+ IN UINTN Address,
+ IN UINT16 AndData
+ )
+{
+ return PciWrite16 (Address, (UINT16) (PciRead16 (Address) & AndData));
+}
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
+ value, followed a bitwise OR with another 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and
+ the value specified by OrData, and writes the result to the 16-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciAndThenOr16 (
+ IN UINTN Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ return PciWrite16 (Address, (UINT16) ((PciRead16 (Address) & AndData) | OrData));
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 16-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciBitFieldRead16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead16 (PciRead16 (Address), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 16-bit register is returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciBitFieldWrite16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
+ )
+{
+ return PciWrite16 (
+ Address,
+ BitFieldWrite16 (PciRead16 (Address), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciBitFieldOr16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
+ )
+{
+ return PciWrite16 (
+ Address,
+ BitFieldOr16 (PciRead16 (Address), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 16-bit register.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 16-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciBitFieldAnd16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
+ )
+{
+ return PciWrite16 (
+ Address,
+ BitFieldAnd16 (PciRead16 (Address), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 16-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciBitFieldAndThenOr16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ return PciWrite16 (
+ Address,
+ BitFieldAndThenOr16 (PciRead16 (Address), StartBit, EndBit, AndData, OrData)
+ );
+}
+
+/**
+ Reads a 32-bit PCI configuration register.
+
+ Reads and returns the 32-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @return The read value from the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciRead32 (
+ IN UINTN Address
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address, 3);
+
+ return SmmPciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint32);
+}
+
+/**
+ Writes a 32-bit PCI configuration register.
+
+ Writes the 32-bit PCI configuration register specified by Address with the
+ value specified by Value. Value is returned. This function must guarantee
+ that all PCI read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address, 3);
+
+ return SmmPciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint32, Value);
+}
+
+/**
+ Performs a bitwise OR of a 32-bit PCI configuration register with
+ a 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 32-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciOr32 (
+ IN UINTN Address,
+ IN UINT32 OrData
+ )
+{
+ return PciWrite32 (Address, PciRead32 (Address) | OrData);
+}
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
+ value.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 32-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciAnd32 (
+ IN UINTN Address,
+ IN UINT32 AndData
+ )
+{
+ return PciWrite32 (Address, PciRead32 (Address) & AndData);
+}
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
+ value, followed a bitwise OR with another 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and
+ the value specified by OrData, and writes the result to the 32-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciAndThenOr32 (
+ IN UINTN Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return PciWrite32 (Address, (PciRead32 (Address) & AndData) | OrData);
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 32-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciBitFieldRead32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead32 (PciRead32 (Address), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 32-bit register is returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciBitFieldWrite32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ )
+{
+ return PciWrite32 (
+ Address,
+ BitFieldWrite32 (PciRead32 (Address), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 32-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciBitFieldOr32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ )
+{
+ return PciWrite32 (
+ Address,
+ BitFieldOr32 (PciRead32 (Address), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 32-bit register.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 32-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciBitFieldAnd32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ )
+{
+ return PciWrite32 (
+ Address,
+ BitFieldAnd32 (PciRead32 (Address), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 32-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciBitFieldAndThenOr32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return PciWrite32 (
+ Address,
+ BitFieldAndThenOr32 (PciRead32 (Address), StartBit, EndBit, AndData, OrData)
+ );
+}
+
+/**
+ Reads a range of PCI configuration registers into a caller supplied buffer.
+
+ Reads the range of PCI configuration registers specified by StartAddress and
+ Size into the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be read. Size is
+ returned. When possible 32-bit PCI configuration read cycles are used to read
+ from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
+ and 16-bit PCI configuration read cycles may be used at the beginning and the
+ end of the range.
+
+ If StartAddress > 0x0FFFFFFF, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress Starting address that encodes the PCI Bus, Device,
+ Function and Register.
+ @param Size Size in bytes of the transfer.
+ @param Buffer Pointer to a buffer receiving the data read.
+
+ @return Size
+
+**/
+UINTN
+EFIAPI
+PciReadBuffer (
+ IN UINTN StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
+ )
+{
+ UINTN ReturnValue;
+
+ ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
+
+ if (Size == 0) {
+ return Size;
+ }
+
+ ASSERT (Buffer != NULL);
+
+ //
+ // Save Size for return
+ //
+ ReturnValue = Size;
+
+ if ((StartAddress & BIT0) != 0) {
+ //
+ // Read a byte if StartAddress is byte aligned
+ //
+ *(volatile UINT8 *)Buffer = PciRead8 (StartAddress);
+ StartAddress += sizeof (UINT8);
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
+ //
+ // Read a word if StartAddress is word aligned
+ //
+ WriteUnaligned16 (Buffer, PciRead16 (StartAddress));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16*)Buffer + 1;
+ }
+
+ while (Size >= sizeof (UINT32)) {
+ //
+ // Read as many double words as possible
+ //
+ WriteUnaligned32 (Buffer, PciRead32 (StartAddress));
+ StartAddress += sizeof (UINT32);
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16)) {
+ //
+ // Read the last remaining word if exist
+ //
+ WriteUnaligned16 (Buffer, PciRead16 (StartAddress));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT8)) {
+ //
+ // Read the last remaining byte if exist
+ //
+ *(volatile UINT8 *)Buffer = PciRead8 (StartAddress);
+ }
+
+ return ReturnValue;
+}
+
+/**
+ Copies the data in a caller supplied buffer to a specified range of PCI
+ configuration space.
+
+ Writes the range of PCI configuration registers specified by StartAddress and
+ Size from the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be written. Size is
+ returned. When possible 32-bit PCI configuration write cycles are used to
+ write from StartAdress to StartAddress + Size. Due to alignment restrictions,
+ 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
+ and the end of the range.
+
+ If StartAddress > 0x0FFFFFFF, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress Starting address that encodes the PCI Bus, Device,
+ Function and Register.
+ @param Size Size in bytes of the transfer.
+ @param Buffer Pointer to a buffer containing the data to write.
+
+ @return Size written to StartAddress.
+
+**/
+UINTN
+EFIAPI
+PciWriteBuffer (
+ IN UINTN StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
+ )
+{
+ UINTN ReturnValue;
+
+ ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
+
+ if (Size == 0) {
+ return 0;
+ }
+
+ ASSERT (Buffer != NULL);
+
+ //
+ // Save Size for return
+ //
+ ReturnValue = Size;
+
+ if ((StartAddress & BIT0) != 0) {
+ //
+ // Write a byte if StartAddress is byte aligned
+ //
+ PciWrite8 (StartAddress, *(UINT8*)Buffer);
+ StartAddress += sizeof (UINT8);
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
+ //
+ // Write a word if StartAddress is word aligned
+ //
+ PciWrite16 (StartAddress, ReadUnaligned16 (Buffer));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16*)Buffer + 1;
+ }
+
+ while (Size >= sizeof (UINT32)) {
+ //
+ // Write as many double words as possible
+ //
+ PciWrite32 (StartAddress, ReadUnaligned32 (Buffer));
+ StartAddress += sizeof (UINT32);
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16)) {
+ //
+ // Write the last remaining word if exist
+ //
+ PciWrite16 (StartAddress, ReadUnaligned16 (Buffer));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT8)) {
+ //
+ // Write the last remaining byte if exist
+ //
+ PciWrite8 (StartAddress, *(UINT8*)Buffer);
+ }
+
+ return ReturnValue;
+}
diff --git a/MdePkg/Library/SmmPciLibPciRootBridgeIo/SmmPciLibPciRootBridgeIo.inf b/MdePkg/Library/SmmPciLibPciRootBridgeIo/SmmPciLibPciRootBridgeIo.inf new file mode 100644 index 0000000000..97f9a20faf --- /dev/null +++ b/MdePkg/Library/SmmPciLibPciRootBridgeIo/SmmPciLibPciRootBridgeIo.inf @@ -0,0 +1,54 @@ +# @file
+# PCI Library that layers on top of the SMM PCI Root Bridge I/O Protocol.
+#
+# This library produces the APIs from the PCI Library and implements these APIs
+# by calling into the PCI Root Bridge I/O Protocol. The PCI Root Bridge I/O Protocol is
+# typically produced by a chipset specific DXE driver.
+# This library binds to the first PCI Root Bridge I/O Protocol in the platform. As a result,
+# it should only be used on platforms that contain a single PCI root bridge.
+#
+# Copyright (c) 2009, Intel Corporation.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SmmPciLibPciRootBridgeIo
+ FILE_GUID = F6994CBA-2351-4ebc-A2DA-20BAC2FE2CF3
+ MODULE_TYPE = DXE_SMM_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciLib|DXE_SMM_DRIVER SMM_CORE
+ PI_SPECIFICATION_VERSION = 0x0001000A
+
+ CONSTRUCTOR = PciLibConstructor
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[Sources.common]
+ PciLib.c
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+
+[LibraryClasses]
+ BaseLib
+ SmmServicesTableLib
+ DebugLib
+
+[Protocols]
+ gEfiSmmPciRootBridgeIoProtocolGuid ## CONSUMES
+
diff --git a/MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.c b/MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.c new file mode 100644 index 0000000000..f44dd6ef70 --- /dev/null +++ b/MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.c @@ -0,0 +1,104 @@ +/** @file
+ SMM Services Table Library.
+
+ Copyright (c) 2009, Intel Corporation<BR>
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+#include <PiSmm.h>
+#include <Protocol/SmmBase2.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/SmmServicesTableLib.h>
+#include <Library/DebugLib.h>
+
+EFI_SMM_SYSTEM_TABLE2 *gSmst = NULL;
+EFI_SMM_BASE2_PROTOCOL *mInternalSmmBase2 = NULL;
+
+
+/**
+ The constructor function caches the pointer of Smm Services Table.
+
+ @param ImageHandle The firmware allocated handle for the EFI image.
+ @param SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
+
+**/
+EFI_STATUS
+EFIAPI
+SmmServicesTableLibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ BOOLEAN InSmm;
+
+ //
+ // Retrieve SMM Base2 Protocol
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiSmmBase2ProtocolGuid,
+ NULL,
+ (VOID **) &mInternalSmmBase2
+ );
+ ASSERT_EFI_ERROR (Status);
+ ASSERT (mInternalSmmBase2 != NULL);
+
+ //
+ // Check to see if we are already in SMM
+ //
+ mInternalSmmBase2->InSmm (mInternalSmmBase2, &InSmm);
+
+ if (!InSmm) {
+ //
+ // We are not in SMM, so SMST is not needed
+ //
+ return EFI_SUCCESS;
+ }
+
+ //
+ // We are in SMM, retrieve the pointer to SMM System Table
+ //
+ mInternalSmmBase2->GetSmstLocation (mInternalSmmBase2, &gSmst);
+
+ ASSERT (gSmst != NULL);
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function allows the caller to determine if the driver is executing in
+ System Management Mode(SMM).
+
+ This function returns TRUE if the driver is executing in SMM and FALSE if the
+ driver is not executing in SMM.
+
+ @retval TRUE The driver is executing in System Management Mode (SMM).
+ @retval FALSE The driver is not executing in System Management Mode (SMM).
+
+**/
+BOOLEAN
+EFIAPI
+InSmm (
+ VOID
+ )
+{
+ BOOLEAN InSmm;
+
+ //
+ // Check to see if we are already in SMM
+ //
+ mInternalSmmBase2->InSmm (mInternalSmmBase2, &InSmm);
+
+ return InSmm;
+}
diff --git a/MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf b/MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf new file mode 100644 index 0000000000..e0e699b001 --- /dev/null +++ b/MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf @@ -0,0 +1,47 @@ +#/** @file
+# SMM Services Table Library.
+#
+# Copyright (c) 2009, Intel Corporation.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SmmServicesTableLib
+ FILE_GUID = 064B4C5B-C5EF-4eff-85DF-65518EF1314D
+ MODULE_TYPE = DXE_SMM_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SmmServicesTableLib|SMM_CORE DXE_SMM_DRIVER
+ EDK_RELEASE_VERSION = 0x00020000
+ EFI_SPECIFICATION_VERSION = 0x00020000
+ PI_SPECIFICATION_VERSION = 0x0001000A
+
+ CONSTRUCTOR = SmmServicesTableLibConstructor
+
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[Sources.common]
+ SmmServicesTableLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ UefiBootServicesTableLib
+ DebugLib
+
+[Protocols]
+ gEfiSmmBase2ProtocolGuid # PROTOCOL ALWAYS_CONSUMED
+
+[Depex.common.DXE_DRIVER]
+ gEfiSmmBase2ProtocolGuid
diff --git a/MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf b/MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf index 297739c177..74e80b7e39 100644 --- a/MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +++ b/MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf @@ -1,7 +1,7 @@ #/** @file
# UEFI Boot Services Table Library implementation.
#
-# Copyright (c) 2007 - 2008, Intel Corporation.
+# Copyright (c) 2007 - 2009, Intel Corporation.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -19,7 +19,7 @@ FILE_GUID = ff5c7a2c-ab7a-4366-8616-11c6e53247b6
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = UefiBootServicesTableLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
+ LIBRARY_CLASS = UefiBootServicesTableLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE
CONSTRUCTOR = UefiBootServicesTableLibConstructor
diff --git a/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf b/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf index 1ca67c6814..7ba1a9e751 100644 --- a/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +++ b/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf @@ -3,7 +3,7 @@ #
# Device Path Library that layers on top of the Memory Allocation Library.
#
-# Copyright (c) 2007 - 2008, Intel Corporation
+# Copyright (c) 2007 - 2009, Intel Corporation
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -21,7 +21,7 @@ FILE_GUID = 91c1677a-e57f-4191-8b8e-eb7711a716e0
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = DevicePathLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
+ LIBRARY_CLASS = DevicePathLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE
#
diff --git a/MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf b/MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf index 72ff4e1188..8e55bf6b5f 100644 --- a/MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +++ b/MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf @@ -1,7 +1,7 @@ #/** @file
# Module entry point library for UEFI driver.
#
-# Copyright (c) 2007 - 2008, Intel Corporation.
+# Copyright (c) 2007 - 2009, Intel Corporation.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -19,7 +19,7 @@ FILE_GUID = 331deb15-454b-48d8-9b74-70d01f3f3556
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = UefiDriverEntryPoint|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER UEFI_DRIVER
+ LIBRARY_CLASS = UefiDriverEntryPoint|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER UEFI_DRIVER SMM_CORE DXE_SMM_DRIVER
EFI_SPECIFICATION_VERSION = 0x00020000
diff --git a/MdePkg/Library/UefiLib/UefiLib.inf b/MdePkg/Library/UefiLib/UefiLib.inf index 11a2a63f34..15b56d68cd 100644 --- a/MdePkg/Library/UefiLib/UefiLib.inf +++ b/MdePkg/Library/UefiLib/UefiLib.inf @@ -7,7 +7,7 @@ # EFI Driver Model related protocols, manage Unicode string tables for UEFI Drivers,
# and print messages on the console output and standard error devices.
#
-# Copyright (c) 2007 - 2008, Intel Corporation
+# Copyright (c) 2007 - 2009, Intel Corporation
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -25,7 +25,7 @@ FILE_GUID = 3a004ba5-efe0-4a61-9f1a-267a46ae5ba9
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = UefiLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
+ LIBRARY_CLASS = UefiLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE
#
diff --git a/MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf b/MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf index 8a0e0744c9..f28819d8b7 100644 --- a/MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +++ b/MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf @@ -4,7 +4,7 @@ # Memory Allocation Library that uses EFI Boot Services to allocate
# and free memory.
#
-# Copyright (c) 2007 - 2008, Intel Corporation
+# Copyright (c) 2007 - 2009, Intel Corporation
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -22,7 +22,7 @@ FILE_GUID = 4674739d-3195-4fb2-8094-ac1d22d00194
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = MemoryAllocationLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
+ LIBRARY_CLASS = MemoryAllocationLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE
#
diff --git a/MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf b/MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf index 82126db448..212ae63875 100644 --- a/MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf +++ b/MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf @@ -1,7 +1,7 @@ #/** @file
# UEFI Runtime Services Table Library implementation.
#
-# Copyright (c) 2007 - 2008, Intel Corporation.
+# Copyright (c) 2007 - 2009, Intel Corporation.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -19,7 +19,7 @@ FILE_GUID = 19cbbb97-ff61-45ff-8c3f-dfa66dd118c8
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = UefiRuntimeServicesTableLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
+ LIBRARY_CLASS = UefiRuntimeServicesTableLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE
CONSTRUCTOR = UefiRuntimeServicesTableLibConstructor
|