diff options
Diffstat (limited to 'Omap35xxPkg/Include/Omap3530/Omap3530Prcm.h')
-rw-r--r-- | Omap35xxPkg/Include/Omap3530/Omap3530Prcm.h | 86 |
1 files changed, 43 insertions, 43 deletions
diff --git a/Omap35xxPkg/Include/Omap3530/Omap3530Prcm.h b/Omap35xxPkg/Include/Omap3530/Omap3530Prcm.h index e85bb9317b..5d842639f0 100644 --- a/Omap35xxPkg/Include/Omap3530/Omap3530Prcm.h +++ b/Omap35xxPkg/Include/Omap3530/Omap3530Prcm.h @@ -40,29 +40,29 @@ #define PRM_RSTST (0x48307258) //CORE clock -#define CM_FCLKEN1_CORE_EN_I2C1_MASK (1UL << 15) +#define CM_FCLKEN1_CORE_EN_I2C1_MASK BIT15 #define CM_FCLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15) -#define CM_FCLKEN1_CORE_EN_I2C1_ENABLE (1UL << 15) +#define CM_FCLKEN1_CORE_EN_I2C1_ENABLE BIT15 -#define CM_ICLKEN1_CORE_EN_I2C1_MASK (1UL << 15) +#define CM_ICLKEN1_CORE_EN_I2C1_MASK BIT15 #define CM_ICLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15) -#define CM_ICLKEN1_CORE_EN_I2C1_ENABLE (1UL << 15) +#define CM_ICLKEN1_CORE_EN_I2C1_ENABLE BIT15 -#define CM_FCLKEN1_CORE_EN_MMC1_MASK (1UL << 24) +#define CM_FCLKEN1_CORE_EN_MMC1_MASK BIT24 #define CM_FCLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24) -#define CM_FCLKEN1_CORE_EN_MMC1_ENABLE (1UL << 24) +#define CM_FCLKEN1_CORE_EN_MMC1_ENABLE BIT24 -#define CM_FCLKEN3_CORE_EN_USBTLL_MASK (1UL << 2) +#define CM_FCLKEN3_CORE_EN_USBTLL_MASK BIT2 #define CM_FCLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2) -#define CM_FCLKEN3_CORE_EN_USBTLL_ENABLE (1UL << 2) +#define CM_FCLKEN3_CORE_EN_USBTLL_ENABLE BIT2 -#define CM_ICLKEN1_CORE_EN_MMC1_MASK (1UL << 24) +#define CM_ICLKEN1_CORE_EN_MMC1_MASK BIT24 #define CM_ICLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24) -#define CM_ICLKEN1_CORE_EN_MMC1_ENABLE (1UL << 24) +#define CM_ICLKEN1_CORE_EN_MMC1_ENABLE BIT24 -#define CM_ICLKEN3_CORE_EN_USBTLL_MASK (1UL << 2) +#define CM_ICLKEN3_CORE_EN_USBTLL_MASK BIT2 #define CM_ICLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2) -#define CM_ICLKEN3_CORE_EN_USBTLL_ENABLE (1UL << 2) +#define CM_ICLKEN3_CORE_EN_USBTLL_ENABLE BIT2 #define CM_CLKEN_FREQSEL_075_100 (0x03UL << 4) #define CM_CLKEN_ENABLE (7UL << 0) @@ -72,93 +72,93 @@ #define CM_CLKSEL_DIV_120M(x) (((x) & 0x1F) << 0) -#define CM_FCLKEN_USBHOST_EN_USBHOST2_MASK (1UL << 1) +#define CM_FCLKEN_USBHOST_EN_USBHOST2_MASK BIT1 #define CM_FCLKEN_USBHOST_EN_USBHOST2_DISABLE (0UL << 1) -#define CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE (1UL << 1) +#define CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE BIT1 -#define CM_FCLKEN_USBHOST_EN_USBHOST1_MASK (1UL << 0) +#define CM_FCLKEN_USBHOST_EN_USBHOST1_MASK BIT0 #define CM_FCLKEN_USBHOST_EN_USBHOST1_DISABLE (0UL << 0) -#define CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE (1UL << 0) +#define CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE BIT0 -#define CM_ICLKEN_USBHOST_EN_USBHOST_MASK (1UL << 0) +#define CM_ICLKEN_USBHOST_EN_USBHOST_MASK BIT0 #define CM_ICLKEN_USBHOST_EN_USBHOST_DISABLE (0UL << 0) -#define CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE (1UL << 0) +#define CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE BIT0 //Wakeup functional clock #define CM_FCLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3) -#define CM_FCLKEN_WKUP_EN_GPIO1_ENABLE (1UL << 3) +#define CM_FCLKEN_WKUP_EN_GPIO1_ENABLE BIT3 #define CM_FCLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5) -#define CM_FCLKEN_WKUP_EN_WDT2_ENABLE (1UL << 5) +#define CM_FCLKEN_WKUP_EN_WDT2_ENABLE BIT5 //Wakeup interface clock #define CM_ICLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3) -#define CM_ICLKEN_WKUP_EN_GPIO1_ENABLE (1UL << 3) +#define CM_ICLKEN_WKUP_EN_GPIO1_ENABLE BIT3 #define CM_ICLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5) -#define CM_ICLKEN_WKUP_EN_WDT2_ENABLE (1UL << 5) +#define CM_ICLKEN_WKUP_EN_WDT2_ENABLE BIT5 //Peripheral functional clock #define CM_FCLKEN_PER_EN_GPT3_DISABLE (0UL << 4) -#define CM_FCLKEN_PER_EN_GPT3_ENABLE (1UL << 4) +#define CM_FCLKEN_PER_EN_GPT3_ENABLE BIT4 #define CM_FCLKEN_PER_EN_GPT4_DISABLE (0UL << 5) -#define CM_FCLKEN_PER_EN_GPT4_ENABLE (1UL << 5) +#define CM_FCLKEN_PER_EN_GPT4_ENABLE BIT5 #define CM_FCLKEN_PER_EN_UART3_DISABLE (0UL << 11) -#define CM_FCLKEN_PER_EN_UART3_ENABLE (1UL << 11) +#define CM_FCLKEN_PER_EN_UART3_ENABLE BIT11 #define CM_FCLKEN_PER_EN_GPIO2_DISABLE (0UL << 13) -#define CM_FCLKEN_PER_EN_GPIO2_ENABLE (1UL << 13) +#define CM_FCLKEN_PER_EN_GPIO2_ENABLE BIT13 #define CM_FCLKEN_PER_EN_GPIO3_DISABLE (0UL << 14) -#define CM_FCLKEN_PER_EN_GPIO3_ENABLE (1UL << 14) +#define CM_FCLKEN_PER_EN_GPIO3_ENABLE BIT14 #define CM_FCLKEN_PER_EN_GPIO4_DISABLE (0UL << 15) -#define CM_FCLKEN_PER_EN_GPIO4_ENABLE (1UL << 15) +#define CM_FCLKEN_PER_EN_GPIO4_ENABLE BIT15 #define CM_FCLKEN_PER_EN_GPIO5_DISABLE (0UL << 16) -#define CM_FCLKEN_PER_EN_GPIO5_ENABLE (1UL << 16) +#define CM_FCLKEN_PER_EN_GPIO5_ENABLE BIT16 #define CM_FCLKEN_PER_EN_GPIO6_DISABLE (0UL << 17) -#define CM_FCLKEN_PER_EN_GPIO6_ENABLE (1UL << 17) +#define CM_FCLKEN_PER_EN_GPIO6_ENABLE BIT17 //Peripheral interface clock #define CM_ICLKEN_PER_EN_GPT3_DISABLE (0UL << 4) -#define CM_ICLKEN_PER_EN_GPT3_ENABLE (1UL << 4) +#define CM_ICLKEN_PER_EN_GPT3_ENABLE BIT4 #define CM_ICLKEN_PER_EN_GPT4_DISABLE (0UL << 5) -#define CM_ICLKEN_PER_EN_GPT4_ENABLE (1UL << 5) +#define CM_ICLKEN_PER_EN_GPT4_ENABLE BIT5 #define CM_ICLKEN_PER_EN_UART3_DISABLE (0UL << 11) -#define CM_ICLKEN_PER_EN_UART3_ENABLE (1UL << 11) +#define CM_ICLKEN_PER_EN_UART3_ENABLE BIT11 #define CM_ICLKEN_PER_EN_GPIO2_DISABLE (0UL << 13) -#define CM_ICLKEN_PER_EN_GPIO2_ENABLE (1UL << 13) +#define CM_ICLKEN_PER_EN_GPIO2_ENABLE BIT13 #define CM_ICLKEN_PER_EN_GPIO3_DISABLE (0UL << 14) -#define CM_ICLKEN_PER_EN_GPIO3_ENABLE (1UL << 14) +#define CM_ICLKEN_PER_EN_GPIO3_ENABLE BIT14 #define CM_ICLKEN_PER_EN_GPIO4_DISABLE (0UL << 15) -#define CM_ICLKEN_PER_EN_GPIO4_ENABLE (1UL << 15) +#define CM_ICLKEN_PER_EN_GPIO4_ENABLE BIT15 #define CM_ICLKEN_PER_EN_GPIO5_DISABLE (0UL << 16) -#define CM_ICLKEN_PER_EN_GPIO5_ENABLE (1UL << 16) +#define CM_ICLKEN_PER_EN_GPIO5_ENABLE BIT16 #define CM_ICLKEN_PER_EN_GPIO6_DISABLE (0UL << 17) -#define CM_ICLKEN_PER_EN_GPIO6_ENABLE (1UL << 17) +#define CM_ICLKEN_PER_EN_GPIO6_ENABLE BIT17 //Timer source clock selection #define CM_CLKSEL_PER_CLKSEL_GPT3_32K (0UL << 1) -#define CM_CLKSEL_PER_CLKSEL_GPT3_SYS (1UL << 1) +#define CM_CLKSEL_PER_CLKSEL_GPT3_SYS BIT1 #define CM_CLKSEL_PER_CLKSEL_GPT4_32K (0UL << 2) -#define CM_CLKSEL_PER_CLKSEL_GPT4_SYS (1UL << 2) +#define CM_CLKSEL_PER_CLKSEL_GPT4_SYS BIT2 //Reset management (Global and Cold reset) -#define RST_GS (0x1UL << 1) -#define RST_DPLL3 (0x1UL << 2) -#define GLOBAL_SW_RST (0x1UL << 1) +#define RST_GS BIT1 +#define RST_DPLL3 BIT2 +#define GLOBAL_SW_RST BIT1 #define GLOBAL_COLD_RST (0x0UL << 0) #endif // __OMAP3530PRCM_H__ |