diff options
Diffstat (limited to 'Omap35xxPkg/Library/Omap35xxTimerLib/TimerLib.c')
| -rw-r--r-- | Omap35xxPkg/Library/Omap35xxTimerLib/TimerLib.c | 33 |
1 files changed, 32 insertions, 1 deletions
diff --git a/Omap35xxPkg/Library/Omap35xxTimerLib/TimerLib.c b/Omap35xxPkg/Library/Omap35xxTimerLib/TimerLib.c index efd3d1a223..0b61020805 100644 --- a/Omap35xxPkg/Library/Omap35xxTimerLib/TimerLib.c +++ b/Omap35xxPkg/Library/Omap35xxTimerLib/TimerLib.c @@ -12,7 +12,7 @@ **/
-#include <Base.h>
+#include <Uefi.h>
#include <Library/BaseLib.h>
#include <Library/TimerLib.h>
@@ -23,6 +23,37 @@ #include <Omap3530/Omap3530.h>
+RETURN_STATUS
+EFIAPI
+TimerConstructor (
+ VOID
+ )
+{
+ UINTN Timer = PcdGet32(PcdOmap35xxFreeTimer);
+ UINT32 TimerBaseAddress = TimerBase(Timer);
+
+ if ((MmioRead32 (TimerBaseAddress + GPTIMER_TCLR) & TCLR_ST_ON) == 0) {
+ // Set source clock for GPT3 & GPT4 to SYS_CLK
+ MmioOr32 (CM_CLKSEL_PER, CM_CLKSEL_PER_CLKSEL_GPT3_SYS | CM_CLKSEL_PER_CLKSEL_GPT4_SYS);
+
+ // Set count & reload registers
+ MmioWrite32 (TimerBaseAddress + GPTIMER_TCRR, 0x00000000);
+ MmioWrite32 (TimerBaseAddress + GPTIMER_TLDR, 0x00000000);
+
+ // Disable interrupts
+ MmioWrite32 (TimerBaseAddress + GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE);
+
+ // Start Timer
+ MmioWrite32 (TimerBaseAddress + GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
+
+ // Disable OMAP Watchdog timer (WDT2)
+ MmioWrite32 (WDTIMER2_BASE + WSPR, 0xAAAA);
+ DEBUG ((EFI_D_ERROR, "Magic delay to disable watchdog timers properly.\n"));
+ MmioWrite32 (WDTIMER2_BASE + WSPR, 0x5555);
+ }
+ return EFI_SUCCESS;
+}
+
UINTN
EFIAPI
MicroSecondDelay (
|