diff options
Diffstat (limited to 'OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c')
-rw-r--r-- | OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c | 24 |
1 files changed, 14 insertions, 10 deletions
diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c index 28280539b6..58938b5d8b 100644 --- a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c +++ b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c @@ -21,8 +21,9 @@ //
// Power Management PCI Configuration Register fields
//
-#define PMBA_RTE BIT0
-#define PMIOSE BIT0
+#define PMBA_RTE BIT0
+#define PIIX4_PMIOSE BIT0
+#define Q35_ACPI_EN BIT7
//
// Offset in the Power Management Base Address to the ACPI Timer
@@ -49,7 +50,8 @@ AcpiTimerLibConstructor ( {
UINT16 HostBridgeDevId;
UINTN Pmba;
- UINTN PmRegMisc;
+ UINTN AcpiCtlReg;
+ UINT8 AcpiEnBit;
//
// Query Host Bridge DID to determine platform type
@@ -57,12 +59,14 @@ AcpiTimerLibConstructor ( HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
switch (HostBridgeDevId) {
case INTEL_82441_DEVICE_ID:
- Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);
- PmRegMisc = POWER_MGMT_REGISTER_PIIX4 (0x80);
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);
+ AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (0x80); // PMREGMISC
+ AcpiEnBit = PIIX4_PMIOSE;
break;
case INTEL_Q35_MCH_DEVICE_ID:
- Pmba = POWER_MGMT_REGISTER_Q35 (0x40);
- PmRegMisc = POWER_MGMT_REGISTER_Q35 (0x80);
+ Pmba = POWER_MGMT_REGISTER_Q35 (0x40);
+ AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (0x44); // ACPI_CNTL
+ AcpiEnBit = Q35_ACPI_EN;
break;
default:
DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
@@ -76,7 +80,7 @@ AcpiTimerLibConstructor ( //
// Check to see if the Power Management Base Address is already enabled
//
- if ((PciRead8 (PmRegMisc) & PMIOSE) == 0) {
+ if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
//
// If the Power Management Base Address is not programmed,
// then program the Power Management Base Address from a PCD.
@@ -84,9 +88,9 @@ AcpiTimerLibConstructor ( PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));
//
- // Enable PMBA I/O port decodes in PMREGMISC
+ // Enable PMBA I/O port decodes
//
- PciOr8 (PmRegMisc, PMIOSE);
+ PciOr8 (AcpiCtlReg, AcpiEnBit);
}
return RETURN_SUCCESS;
|