diff options
Diffstat (limited to 'PcAtChipsetPkg/PciHostBridgeDxe')
| -rw-r--r-- | PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c | 142 | ||||
| -rw-r--r-- | PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.h | 257 | ||||
| -rw-r--r-- | PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c | 74 |
3 files changed, 355 insertions, 118 deletions
diff --git a/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c b/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c index b05b415349..27a54461cd 100644 --- a/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c +++ b/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c @@ -67,6 +67,7 @@ PCI_HOST_BRIDGE_INSTANCE mPciHostBridgeInstanceTemplate = { //
// Implementation
//
+
/**
Entry point of this driver
@@ -200,7 +201,7 @@ InitializePciHostBridge ( required here. This notification can be used to perform any chipsetspecific
programming.
- @param[in] PciResAlloc The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+ @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
@param[in] Phase The phase during enumeration
@retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error
@@ -309,7 +310,7 @@ NotifyPhase( //
// Get the number of '1' in Alignment.
//
- BitsOfAlignment = HighBitSet64 (RootBridgeInstance->ResAllocNode[Index].Alignment) + 1;
+ BitsOfAlignment = (UINTN) (HighBitSet64 (RootBridgeInstance->ResAllocNode[Index].Alignment) + 1);
switch (Index) {
@@ -485,7 +486,7 @@ NotifyPhase( For D945 implementation, there is only one root bridge in PCI host bridge.
@param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
- @param[in][out] RootBridgeHandle Returns the device handle of the next PCI root bridge.
+ @param[in, out] RootBridgeHandle Returns the device handle of the next PCI root bridge.
@retval EFI_SUCCESS If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the
specific Host bridge and return EFI_SUCCESS.
@@ -835,7 +836,7 @@ SubmitResources( PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
UINT8 *Temp;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ptr;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
UINT64 AddrLen;
UINT64 Alignment;
@@ -862,30 +863,30 @@ SubmitResources( RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
if (RootBridgeHandle == RootBridgeInstance->Handle) {
while ( *Temp == 0x8A) {
- ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;
+ Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;
//
// Check Address Length
//
- if (ptr->AddrLen > 0xffffffff) {
+ if (Ptr->AddrLen > 0xffffffff) {
return EFI_INVALID_PARAMETER;
}
//
// Check address range alignment
//
- if (ptr->AddrRangeMax >= 0xffffffff || ptr->AddrRangeMax != (GetPowerOfTwo64 (ptr->AddrRangeMax + 1) - 1)) {
+ if (Ptr->AddrRangeMax >= 0xffffffff || Ptr->AddrRangeMax != (GetPowerOfTwo64 (Ptr->AddrRangeMax + 1) - 1)) {
return EFI_INVALID_PARAMETER;
}
- switch (ptr->ResType) {
+ switch (Ptr->ResType) {
case 0:
//
// Check invalid Address Sapce Granularity
//
- if (ptr->AddrSpaceGranularity != 32) {
+ if (Ptr->AddrSpaceGranularity != 32) {
return EFI_INVALID_PARAMETER;
}
@@ -893,14 +894,14 @@ SubmitResources( // check the memory resource request is supported by PCI root bridge
//
if (RootBridgeInstance->RootBridgeAttrib == EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM &&
- ptr->SpecificFlag == 0x06) {
+ Ptr->SpecificFlag == 0x06) {
return EFI_INVALID_PARAMETER;
}
- AddrLen = ptr->AddrLen;
- Alignment = ptr->AddrRangeMax;
- if (ptr->AddrSpaceGranularity == 32) {
- if (ptr->SpecificFlag == 0x06) {
+ AddrLen = Ptr->AddrLen;
+ Alignment = Ptr->AddrRangeMax;
+ if (Ptr->AddrSpaceGranularity == 32) {
+ if (Ptr->SpecificFlag == 0x06) {
//
// Apply from GCD
//
@@ -913,8 +914,8 @@ SubmitResources( }
}
- if (ptr->AddrSpaceGranularity == 64) {
- if (ptr->SpecificFlag == 0x06) {
+ if (Ptr->AddrSpaceGranularity == 64) {
+ if (Ptr->SpecificFlag == 0x06) {
RootBridgeInstance->ResAllocNode[TypePMem64].Status = ResSubmitted;
} else {
RootBridgeInstance->ResAllocNode[TypeMem64].Status = ResSubmitted;
@@ -923,8 +924,8 @@ SubmitResources( break;
case 1:
- AddrLen = (UINTN)ptr->AddrLen;
- Alignment = (UINTN)ptr->AddrRangeMax;
+ AddrLen = (UINTN) Ptr->AddrLen;
+ Alignment = (UINTN) Ptr->AddrRangeMax;
RootBridgeInstance->ResAllocNode[TypeIo].Length = AddrLen;
RootBridgeInstance->ResAllocNode[TypeIo].Alignment = Alignment;
RootBridgeInstance->ResAllocNode[TypeIo].Status = ResRequested;
@@ -982,7 +983,7 @@ GetProposedResources( UINTN Number;
VOID *Buffer;
UINT8 *Temp;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ptr;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
UINT64 ResStatus;
Buffer = NULL;
@@ -1017,7 +1018,7 @@ GetProposedResources( Temp = Buffer;
for (Index = 0; Index < TypeBus; Index ++) {
if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
- ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;
+ Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;
ResStatus = RootBridgeInstance->ResAllocNode[Index].Status;
switch (Index) {
@@ -1026,81 +1027,81 @@ GetProposedResources( //
// Io
//
- ptr->Desc = 0x8A;
- ptr->Len = 0x2B;
- ptr->ResType = 1;
- ptr->GenFlag = 0;
- ptr->SpecificFlag = 0;
- ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;
- ptr->AddrRangeMax = 0;
- ptr->AddrTranslationOffset = \
+ Ptr->Desc = 0x8A;
+ Ptr->Len = 0x2B;
+ Ptr->ResType = 1;
+ Ptr->GenFlag = 0;
+ Ptr->SpecificFlag = 0;
+ Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;
+ Ptr->AddrRangeMax = 0;
+ Ptr->AddrTranslationOffset = \
(ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
- ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
+ Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
break;
case TypeMem32:
//
// Memory 32
//
- ptr->Desc = 0x8A;
- ptr->Len = 0x2B;
- ptr->ResType = 0;
- ptr->GenFlag = 0;
- ptr->SpecificFlag = 0;
- ptr->AddrSpaceGranularity = 32;
- ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;
- ptr->AddrRangeMax = 0;
- ptr->AddrTranslationOffset = \
+ Ptr->Desc = 0x8A;
+ Ptr->Len = 0x2B;
+ Ptr->ResType = 0;
+ Ptr->GenFlag = 0;
+ Ptr->SpecificFlag = 0;
+ Ptr->AddrSpaceGranularity = 32;
+ Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;
+ Ptr->AddrRangeMax = 0;
+ Ptr->AddrTranslationOffset = \
(ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
- ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
+ Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
break;
case TypePMem32:
//
// Prefetch memory 32
//
- ptr->Desc = 0x8A;
- ptr->Len = 0x2B;
- ptr->ResType = 0;
- ptr->GenFlag = 0;
- ptr->SpecificFlag = 6;
- ptr->AddrSpaceGranularity = 32;
- ptr->AddrRangeMin = 0;
- ptr->AddrRangeMax = 0;
- ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;
- ptr->AddrLen = 0;
+ Ptr->Desc = 0x8A;
+ Ptr->Len = 0x2B;
+ Ptr->ResType = 0;
+ Ptr->GenFlag = 0;
+ Ptr->SpecificFlag = 6;
+ Ptr->AddrSpaceGranularity = 32;
+ Ptr->AddrRangeMin = 0;
+ Ptr->AddrRangeMax = 0;
+ Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;
+ Ptr->AddrLen = 0;
break;
case TypeMem64:
//
// Memory 64
//
- ptr->Desc = 0x8A;
- ptr->Len = 0x2B;
- ptr->ResType = 0;
- ptr->GenFlag = 0;
- ptr->SpecificFlag = 0;
- ptr->AddrSpaceGranularity = 64;
- ptr->AddrRangeMin = 0;
- ptr->AddrRangeMax = 0;
- ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;
- ptr->AddrLen = 0;
+ Ptr->Desc = 0x8A;
+ Ptr->Len = 0x2B;
+ Ptr->ResType = 0;
+ Ptr->GenFlag = 0;
+ Ptr->SpecificFlag = 0;
+ Ptr->AddrSpaceGranularity = 64;
+ Ptr->AddrRangeMin = 0;
+ Ptr->AddrRangeMax = 0;
+ Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;
+ Ptr->AddrLen = 0;
break;
case TypePMem64:
//
// Prefetch memory 64
//
- ptr->Desc = 0x8A;
- ptr->Len = 0x2B;
- ptr->ResType = 0;
- ptr->GenFlag = 0;
- ptr->SpecificFlag = 6;
- ptr->AddrSpaceGranularity = 64;
- ptr->AddrRangeMin = 0;
- ptr->AddrRangeMax = 0;
- ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;
- ptr->AddrLen = 0;
+ Ptr->Desc = 0x8A;
+ Ptr->Len = 0x2B;
+ Ptr->ResType = 0;
+ Ptr->GenFlag = 0;
+ Ptr->SpecificFlag = 6;
+ Ptr->AddrSpaceGranularity = 64;
+ Ptr->AddrRangeMin = 0;
+ Ptr->AddrRangeMax = 0;
+ Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;
+ Ptr->AddrLen = 0;
break;
};
@@ -1128,7 +1129,6 @@ GetProposedResources( @param RootBridge Point to PCI root bridge.
@param PciAddress The specific device PCI address
**/
-STATIC
VOID
UpdateRootBridgeAttributes (
IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge,
@@ -1256,7 +1256,7 @@ UpdateRootBridgeAttributes ( EFI_STATUS
EFIAPI
PreprocessController (
- IN struct _EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
IN EFI_HANDLE RootBridgeHandle,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
diff --git a/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.h b/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.h index 42a3d591c0..f81982985a 100644 --- a/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.h +++ b/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.h @@ -66,20 +66,75 @@ typedef struct { #define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) \
CR(a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE)
-
-//
-// Driver Entry Point
-//
-EFI_STATUS
-EFIAPI
-EfiMain (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- );
//
// HostBridge Resource Allocation interface
//
+
+/**
+ These are the notifications from the PCI bus driver that it is about to enter a certain
+ phase of the PCI enumeration process.
+
+ This member function can be used to notify the host bridge driver to perform specific actions,
+ including any chipset-specific initialization, so that the chipset is ready to enter the next phase.
+ Eight notification points are defined at this time. See belows:
+ EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data
+ structures. The PCI enumerator should issue this notification
+ before starting a fresh enumeration process. Enumeration cannot
+ be restarted after sending any other notification such as
+ EfiPciHostBridgeBeginBusAllocation.
+ EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is
+ required here. This notification can be used to perform any
+ chipset-specific programming.
+ EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No
+ specific action is required here. This notification can be used to
+ perform any chipset-specific programming.
+ EfiPciHostBridgeBeginResourceAllocation
+ The resource allocation phase is about to begin. No specific
+ action is required here. This notification can be used to perform
+ any chipset-specific programming.
+ EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI
+ root bridges. These resource settings are returned on the next call to
+ GetProposedResources(). Before calling NotifyPhase() with a Phase of
+ EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible
+ for gathering I/O and memory requests for
+ all the PCI root bridges and submitting these requests using
+ SubmitResources(). This function pads the resource amount
+ to suit the root bridge hardware, takes care of dependencies between
+ the PCI root bridges, and calls the Global Coherency Domain (GCD)
+ with the allocation request. In the case of padding, the allocated range
+ could be bigger than what was requested.
+ EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated
+ resources (proposed resources) for all the PCI root bridges. After the
+ hardware is programmed, reassigning resources will not be supported.
+ The bus settings are not affected.
+ EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI
+ root bridges and resets the I/O and memory apertures to their initial
+ state. The bus settings are not affected. If the request to allocate
+ resources fails, the PCI enumerator can use this notification to
+ deallocate previous resources, adjust the requests, and retry
+ allocation.
+ EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is
+ required here. This notification can be used to perform any chipsetspecific
+ programming.
+
+ @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+ @param[in] Phase The phase during enumeration
+
+ @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error
+ is valid for a Phase of EfiPciHostBridgeAllocateResources if
+ SubmitResources() has not been called for one or more
+ PCI root bridges before this call
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid
+ for a Phase of EfiPciHostBridgeSetResources.
+ @retval EFI_INVALID_PARAMETER Invalid phase parameter
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+ This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the
+ previously submitted resource requests cannot be fulfilled or
+ were only partially fulfilled.
+ @retval EFI_SUCCESS The notification was accepted without any errors.
+
+**/
EFI_STATUS
EFIAPI
NotifyPhase(
@@ -87,6 +142,28 @@ NotifyPhase( IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
);
+/**
+ Return the device handle of the next PCI root bridge that is associated with this Host Bridge.
+
+ This function is called multiple times to retrieve the device handles of all the PCI root bridges that
+ are associated with this PCI host bridge. Each PCI host bridge is associated with one or more PCI
+ root bridges. On each call, the handle that was returned by the previous call is passed into the
+ interface, and on output the interface returns the device handle of the next PCI root bridge. The
+ caller can use the handle to obtain the instance of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
+ for that root bridge. When there are no more PCI root bridges to report, the interface returns
+ EFI_NOT_FOUND. A PCI enumerator must enumerate the PCI root bridges in the order that they
+ are returned by this function.
+ For D945 implementation, there is only one root bridge in PCI host bridge.
+
+ @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+ @param[in, out] RootBridgeHandle Returns the device handle of the next PCI root bridge.
+
+ @retval EFI_SUCCESS If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the
+ specific Host bridge and return EFI_SUCCESS.
+ @retval EFI_NOT_FOUND Can not find the any more root bridge in specific host bridge.
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was
+ returned on a previous call to GetNextRootBridge().
+**/
EFI_STATUS
EFIAPI
GetNextRootBridge(
@@ -94,6 +171,44 @@ GetNextRootBridge( IN OUT EFI_HANDLE *RootBridgeHandle
);
+/**
+ Returns the allocation attributes of a PCI root bridge.
+
+ The function returns the allocation attributes of a specific PCI root bridge. The attributes can vary
+ from one PCI root bridge to another. These attributes are different from the decode-related
+ attributes that are returned by the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The
+ RootBridgeHandle parameter is used to specify the instance of the PCI root bridge. The device
+ handles of all the root bridges that are associated with this host bridge must be obtained by calling
+ GetNextRootBridge(). The attributes are static in the sense that they do not change during or
+ after the enumeration process. The hardware may provide mechanisms to change the attributes on
+ the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is
+ installed. The permitted values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in
+ "Related Definitions" below. The caller uses these attributes to combine multiple resource requests.
+ For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI bus enumerator needs to
+ include requests for the prefetchable memory in the nonprefetchable memory pool and not request any
+ prefetchable memory.
+ Attribute Description
+ ------------------------------------ ----------------------------------------------------------------------
+ EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set, then the PCI root bridge does not support separate
+ windows for nonprefetchable and prefetchable memory. A PCI bus
+ driver needs to include requests for prefetchable memory in the
+ nonprefetchable memory pool.
+
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set, then the PCI root bridge supports 64-bit memory
+ windows. If this bit is not set, the PCI bus driver needs to include
+ requests for a 64-bit memory address in the corresponding 32-bit
+ memory pool.
+
+ @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+ @param[in] RootBridgeHandle The device handle of the PCI root bridge in which the caller is interested. Type
+ EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
+ @param[out] Attributes The pointer to attribte of root bridge, it is output parameter
+
+ @retval EFI_INVALID_PARAMETER Attribute pointer is NULL
+ @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid.
+ @retval EFI_SUCCESS Success to get attribute of interested root bridge.
+
+**/
EFI_STATUS
EFIAPI
GetAttributes(
@@ -102,6 +217,21 @@ GetAttributes( OUT UINT64 *Attributes
);
+/**
+ Sets up the specified PCI root bridge for the bus enumeration process.
+
+ This member function sets up the root bridge for bus enumeration and returns the PCI bus range
+ over which the search should be performed in ACPI 2.0 resource descriptor format.
+
+ @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.
+ @param[in] RootBridgeHandle The PCI Root Bridge to be set up.
+ @param[out] Configuration Pointer to the pointer to the PCI bus resource descriptor.
+
+ @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle
+ @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor tag.
+ @retval EFI_SUCCESS Sucess to allocate ACPI resource descriptor.
+
+**/
EFI_STATUS
EFIAPI
StartBusEnumeration(
@@ -110,6 +240,30 @@ StartBusEnumeration( OUT VOID **Configuration
);
+/**
+ Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.
+
+ This member function programs the specified PCI root bridge to decode the bus range that is
+ specified by the input parameter Configuration.
+ The bus range information is specified in terms of the ACPI 2.0 resource descriptor format.
+
+ @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance
+ @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to be programmed
+ @param[in] Configuration The pointer to the PCI bus resource descriptor
+
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
+ @retval EFI_INVALID_PARAMETER Configuration is NULL.
+ @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.
+ @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI 2.0 bus resource descriptor.
+ @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 resource descriptors other than
+ bus descriptors.
+ @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid ACPI resource descriptors.
+ @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this root bridge.
+ @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this root bridge.
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
+ @retval EFI_SUCCESS The bus range for the PCI root bridge was programmed.
+
+**/
EFI_STATUS
EFIAPI
SetBusNumbers(
@@ -118,6 +272,31 @@ SetBusNumbers( IN VOID *Configuration
);
+/**
+ Submits the I/O and memory resource requirements for the specified PCI root bridge.
+
+ This function is used to submit all the I/O and memory resources that are required by the specified
+ PCI root bridge. The input parameter Configuration is used to specify the following:
+ - The various types of resources that are required
+ - The associated lengths in terms of ACPI 2.0 resource descriptor format
+
+ @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
+ @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory resource requirements are being submitted.
+ @param[in] Configuration The pointer to the PCI I/O and PCI memory resource descriptor.
+
+ @retval EFI_SUCCESS The I/O and memory resource requests for a PCI root bridge were accepted.
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
+ @retval EFI_INVALID_PARAMETER Configuration is NULL.
+ @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.
+ @retval EFI_INVALID_PARAMETER Configuration includes requests for one or more resource types that are
+ not supported by this PCI root bridge. This error will happen if the caller
+ did not combine resources according to Attributes that were returned by
+ GetAllocAttributes().
+ @retval EFI_INVALID_PARAMETER Address Range Maximum" is invalid.
+ @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI root bridge.
+ @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for this PCI root bridge.
+
+**/
EFI_STATUS
EFIAPI
SubmitResources(
@@ -126,6 +305,26 @@ SubmitResources( IN VOID *Configuration
);
+/**
+ Returns the proposed resource settings for the specified PCI root bridge.
+
+ This member function returns the proposed resource settings for the specified PCI root bridge. The
+ proposed resource settings are prepared when NotifyPhase() is called with a Phase of
+ EfiPciHostBridgeAllocateResources. The output parameter Configuration
+ specifies the following:
+ - The various types of resources, excluding bus resources, that are allocated
+ - The associated lengths in terms of ACPI 2.0 resource descriptor format
+
+ @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
+ @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
+ @param[out] Configuration The pointer to the pointer to the PCI I/O and memory resource descriptor.
+
+ @retval EFI_SUCCESS The requested parameters were returned.
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
EFI_STATUS
EFIAPI
GetProposedResources(
@@ -134,6 +333,33 @@ GetProposedResources( OUT VOID **Configuration
);
+/**
+ Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various
+ stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual
+ PCI controllers before enumeration.
+
+ This function is called during the PCI enumeration process. No specific action is expected from this
+ member function. It allows the host bridge driver to preinitialize individual PCI controllers before
+ enumeration.
+
+ @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
+ @param RootBridgeHandle The associated PCI root bridge handle. Type EFI_HANDLE is defined in
+ InstallProtocolInterface() in the UEFI 2.0 Specification.
+ @param PciAddress The address of the PCI device on the PCI bus. This address can be passed to the
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to access the PCI
+ configuration space of the device. See Table 12-1 in the UEFI 2.0 Specification for
+ the definition of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.
+ @param Phase The phase of the PCI device enumeration.
+
+ @retval EFI_SUCCESS The requested parameters were returned.
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
+ @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in
+ EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should
+ not enumerate this device, including its child devices if it is a PCI-to-PCI
+ bridge.
+
+**/
EFI_STATUS
EFIAPI
PreprocessController (
@@ -249,7 +475,18 @@ typedef struct { #define DRIVER_INSTANCE_FROM_LIST_ENTRY(a) \
CR(a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE)
+/**
+
+ Construct the Pci Root Bridge Io protocol
+
+ @param Protocol Point to protocol instance
+ @param HostBridgeHandle Handle of host bridge
+ @param Attri Attribute of host bridge
+ @param ResAppeture ResourceAppeture for host bridge
+
+ @retval EFI_SUCCESS Success to initialize the Pci Root Bridge.
+**/
EFI_STATUS
RootBridgeConstructor (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol,
diff --git a/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c b/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c index a33836569b..cd39f2bbf7 100644 --- a/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c @@ -145,7 +145,7 @@ RootBridgeIoMemRead ( IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
- IN OUT VOID *Buffer
+ OUT VOID *Buffer
);
/**
@@ -162,7 +162,7 @@ RootBridgeIoMemRead ( responsible for aligning the Address if required.
@param[in] Count The number of memory operations to perform. Bytes moved is
Width size * Count, starting at Address.
- @param[out] Buffer For read operations, the destination buffer to store the results. For
+ @param[in] Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@@ -177,7 +177,7 @@ RootBridgeIoMemWrite ( IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
- IN OUT VOID *Buffer
+ IN VOID *Buffer
);
/**
@@ -185,11 +185,11 @@ RootBridgeIoMemWrite ( @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param[in] Width Signifies the width of the memory operations.
- @param[in] Address The base address of the I/O operation. The caller is responsible for
+ @param[in] UserAddress The base address of the I/O operation. The caller is responsible for
aligning the Address if required.
@param[in] Count The number of I/O operations to perform. Bytes moved is Width
size * Count, starting at Address.
- @param[out] Buffer For read operations, the destination buffer to store the results. For
+ @param[out] UserBuffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@@ -205,7 +205,7 @@ RootBridgeIoIoRead ( IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 UserAddress,
IN UINTN Count,
- IN OUT VOID *UserBuffer
+ OUT VOID *UserBuffer
);
/**
@@ -213,11 +213,11 @@ RootBridgeIoIoRead ( @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param[in] Width Signifies the width of the memory operations.
- @param[in] Address The base address of the I/O operation. The caller is responsible for
+ @param[in] UserAddress The base address of the I/O operation. The caller is responsible for
aligning the Address if required.
@param[in] Count The number of I/O operations to perform. Bytes moved is Width
size * Count, starting at Address.
- @param[out] Buffer For read operations, the destination buffer to store the results. For
+ @param[in] UserBuffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@@ -233,7 +233,7 @@ RootBridgeIoIoWrite ( IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 UserAddress,
IN UINTN Count,
- IN OUT VOID *UserBuffer
+ IN VOID *UserBuffer
);
/**
@@ -300,7 +300,7 @@ RootBridgeIoPciRead ( IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
- IN OUT VOID *Buffer
+ OUT VOID *Buffer
);
/**
@@ -317,7 +317,7 @@ RootBridgeIoPciRead ( @param[in] Address The address within the PCI configuration space for the PCI controller.
@param[in] Count The number of PCI configuration operations to perform. Bytes
moved is Width size * Count, starting at Address.
- @param[out] Buffer For read operations, the destination buffer to store the results. For
+ @param[in] Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@@ -333,7 +333,7 @@ RootBridgeIoPciWrite ( IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
- IN OUT VOID *Buffer
+ IN VOID *Buffer
);
/**
@@ -346,7 +346,7 @@ RootBridgeIoPciWrite ( @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param[in] Operation Indicates if the bus master is going to read or write to system memory.
@param[in] HostAddress The system memory address to map to the PCI controller.
- @param[in][out] NumberOfBytes On input the number of bytes to map. On output the number of bytes that were mapped.
+ @param[in, out] NumberOfBytes On input the number of bytes to map. On output the number of bytes that were mapped.
@param[out] DeviceAddress The resulting map address for the bus master PCI controller to use
to access the system memory's HostAddress.
@param[out] Mapping The value to pass to Unmap() when the bus master DMA operation is complete.
@@ -523,9 +523,9 @@ RootBridgeIoGetAttributes ( MEMORY_WRITE_COMBINE, MEMORY_CACHED, and
MEMORY_DISABLE are not set, then ResourceBase and
ResourceLength are ignored, and may be NULL.
- @param[in][out] ResourceBase A pointer to the base address of the resource range to be modified
+ @param[in, out] ResourceBase A pointer to the base address of the resource range to be modified
by the attributes specified by Attributes.
- @param[in][out] ResourceLength A pointer to the length of the resource range to be modified by the
+ @param[in, out] ResourceLength A pointer to the length of the resource range to be modified by the
attributes specified by Attributes.
@retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.
@@ -866,7 +866,7 @@ RootBridgeIoCheckParameter ( @param[in] UserAddress The address within the PCI configuration space for the PCI controller.
@param[in] Count The number of PCI configuration operations to perform. Bytes
moved is Width size * Count, starting at Address.
- @param[out] UserBuffer For read operations, the destination buffer to store the results. For
+ @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@@ -958,7 +958,7 @@ RootBridgeIoMemRW ( @param[in] UserAddress The address within the PCI configuration space for the PCI controller.
@param[in] Count The number of PCI configuration operations to perform. Bytes
moved is Width size * Count, starting at Address.
- @param[out] UserBuffer For read operations, the destination buffer to store the results. For
+ @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@@ -1044,7 +1044,7 @@ RootBridgeIoIoRW ( @param[in] UserAddress The address within the PCI configuration space for the PCI controller.
@param[in] Count The number of PCI configuration operations to perform. Bytes
moved is Width size * Count, starting at Address.
- @param[out] UserBuffer For read operations, the destination buffer to store the results. For
+ @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@@ -1219,7 +1219,7 @@ RootBridgeIoPollMem ( }
NumberOfTicks += 1;
- while (NumberOfTicks) {
+ while (NumberOfTicks != 0) {
mMetronome->WaitForTick (mMetronome, 1);
@@ -1320,7 +1320,7 @@ RootBridgeIoPollIo ( }
NumberOfTicks += 1;
- while (NumberOfTicks) {
+ while (NumberOfTicks != 0) {
mMetronome->WaitForTick (mMetronome, 1);
@@ -1369,7 +1369,7 @@ RootBridgeIoMemRead ( IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
- IN OUT VOID *Buffer
+ OUT VOID *Buffer
)
{
return RootBridgeIoMemRW (This, FALSE, Width, Address, Count, Buffer);
@@ -1389,7 +1389,7 @@ RootBridgeIoMemRead ( responsible for aligning the Address if required.
@param[in] Count The number of memory operations to perform. Bytes moved is
Width size * Count, starting at Address.
- @param[out] Buffer For read operations, the destination buffer to store the results. For
+ @param[in] Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@@ -1404,7 +1404,7 @@ RootBridgeIoMemWrite ( IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
- IN OUT VOID *Buffer
+ IN VOID *Buffer
)
{
return RootBridgeIoMemRW (This, TRUE, Width, Address, Count, Buffer);
@@ -1435,7 +1435,7 @@ RootBridgeIoIoRead ( IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
- IN OUT VOID *Buffer
+ OUT VOID *Buffer
)
{
return RootBridgeIoIoRW (This, FALSE, Width, Address, Count, Buffer);
@@ -1450,7 +1450,7 @@ RootBridgeIoIoRead ( aligning the Address if required.
@param[in] Count The number of I/O operations to perform. Bytes moved is Width
size * Count, starting at Address.
- @param[out] Buffer For read operations, the destination buffer to store the results. For
+ @param[in] Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@@ -1466,7 +1466,7 @@ RootBridgeIoIoWrite ( IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
- IN OUT VOID *Buffer
+ IN VOID *Buffer
)
{
return RootBridgeIoIoRW (This, TRUE, Width, Address, Count, Buffer);
@@ -1499,7 +1499,7 @@ RootBridgeIoIoWrite ( EFI_STATUS
EFIAPI
RootBridgeIoCopyMem (
- IN struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 DestAddress,
IN UINT64 SrcAddress,
@@ -1591,7 +1591,7 @@ RootBridgeIoPciRead ( IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
- IN OUT VOID *Buffer
+ OUT VOID *Buffer
)
{
return RootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer);
@@ -1611,7 +1611,7 @@ RootBridgeIoPciRead ( @param[in] Address The address within the PCI configuration space for the PCI controller.
@param[in] Count The number of PCI configuration operations to perform. Bytes
moved is Width size * Count, starting at Address.
- @param[out] Buffer For read operations, the destination buffer to store the results. For
+ @param[in] Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@@ -1627,7 +1627,7 @@ RootBridgeIoPciWrite ( IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
- IN OUT VOID *Buffer
+ IN VOID *Buffer
)
{
return RootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer);
@@ -1643,7 +1643,7 @@ RootBridgeIoPciWrite ( @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param[in] Operation Indicates if the bus master is going to read or write to system memory.
@param[in] HostAddress The system memory address to map to the PCI controller.
- @param[in][out] NumberOfBytes On input the number of bytes to map. On output the number of bytes that were mapped.
+ @param[in, out] NumberOfBytes On input the number of bytes to map. On output the number of bytes that were mapped.
@param[out] DeviceAddress The resulting map address for the bus master PCI controller to use
to access the system memory's HostAddress.
@param[out] Mapping The value to pass to Unmap() when the bus master DMA operation is complete.
@@ -1872,7 +1872,7 @@ RootBridgeIoAllocateBuffer ( //
// Validate Attributes
//
- if (Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) {
+ if ((Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) != 0) {
return EFI_UNSUPPORTED;
}
@@ -2000,11 +2000,11 @@ RootBridgeIoGetAttributes ( //
// Set the return value for Supported and Attributes
//
- if (Supported) {
+ if (Supported != NULL) {
*Supported = PrivateData->Supports;
}
- if (Attributes) {
+ if (Attributes != NULL) {
*Attributes = PrivateData->Attributes;
}
@@ -2031,9 +2031,9 @@ RootBridgeIoGetAttributes ( MEMORY_WRITE_COMBINE, MEMORY_CACHED, and
MEMORY_DISABLE are not set, then ResourceBase and
ResourceLength are ignored, and may be NULL.
- @param[in][out] ResourceBase A pointer to the base address of the resource range to be modified
+ @param[in, out] ResourceBase A pointer to the base address of the resource range to be modified
by the attributes specified by Attributes.
- @param[in][out] ResourceLength A pointer to the length of the resource range to be modified by the
+ @param[in, out] ResourceLength A pointer to the length of the resource range to be modified by the
attributes specified by Attributes.
@retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.
@@ -2054,7 +2054,7 @@ RootBridgeIoSetAttributes ( PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);
- if (Attributes) {
+ if (Attributes != 0) {
if ((Attributes & (~(PrivateData->Supports))) != 0) {
return EFI_UNSUPPORTED;
}
|