summaryrefslogtreecommitdiff
path: root/Platform/96Boards/Secure96Dxe/Secure96.dts
diff options
context:
space:
mode:
Diffstat (limited to 'Platform/96Boards/Secure96Dxe/Secure96.dts')
-rw-r--r--Platform/96Boards/Secure96Dxe/Secure96.dts85
1 files changed, 85 insertions, 0 deletions
diff --git a/Platform/96Boards/Secure96Dxe/Secure96.dts b/Platform/96Boards/Secure96Dxe/Secure96.dts
new file mode 100644
index 0000000000..b56ce59985
--- /dev/null
+++ b/Platform/96Boards/Secure96Dxe/Secure96.dts
@@ -0,0 +1,85 @@
+/** @file
+ * Copyright (c) 2018, Linaro Limited. All rights reserved.
+ *
+ * This program and the accompanying materials are licensed and made
+ * available under the terms and conditions of the BSD License which
+ * accompanies this distribution. The full text of the license may be
+ * found at http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+ * IMPLIED.
+ */
+
+#include "Secure96.h"
+
+//
+// Define a placeholder value for the GPIO phandle property cells appearing
+// in this file. It is up to the driver code to discover the actual phandle
+// value from the platform device tree and patch the overlay DTB before it
+// can be applied.
+//
+#define GPIO_PARENT_PLACEHOLDER_PHANDLE 0x0
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ fragment@0 {
+ target-path = "I2C_PARENT_PLACEHOLDER_STRING";
+ __overlay__ {
+ clock-frequency = <100000>;
+
+ ATSHA204A_DT_NODENAME {
+ compatible = "atmel,atsha204a";
+ reg = <ATSHA204A_SLAVE_ADDRESS>;
+ };
+
+ ATECC508A_DT_NODENAME {
+ compatible = "atmel,atecc508a";
+ reg = <ATECC508A_SLAVE_ADDRESS>;
+ };
+ };
+ };
+
+ fragment@1 {
+ target-path = "SPI_PARENT_PLACEHOLDER_STRING";
+ __overlay__ {
+ INFINEON_SLB9670_DT_NODENAME {
+ compatible = "infineon,slb9670";
+ reg = <INFINEON_SLB9670_SPI_CS>;
+ spi-max-frequency = <22500000>;
+ };
+ };
+ };
+
+ fragment@2 {
+ target-path = "/";
+ __overlay__ {
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ secure96-u1 {
+ gpios = <GPIO_PARENT_PLACEHOLDER_PHANDLE
+ FixedPcdGet32 (PcdGpioPinG)
+ FixedPcdGet32 (PcdGpioPolarity)>;
+ };
+ secure96-u2 {
+ gpios = <GPIO_PARENT_PLACEHOLDER_PHANDLE
+ FixedPcdGet32 (PcdGpioPinF)
+ FixedPcdGet32 (PcdGpioPolarity)>;
+ };
+ secure96-u3 {
+ gpios = <GPIO_PARENT_PLACEHOLDER_PHANDLE
+ FixedPcdGet32 (PcdGpioPinI)
+ FixedPcdGet32 (PcdGpioPolarity)>;
+ };
+ secure96-u4 {
+ gpios = <GPIO_PARENT_PLACEHOLDER_PHANDLE
+ FixedPcdGet32 (PcdGpioPinH)
+ FixedPcdGet32 (PcdGpioPolarity)>;
+ };
+ };
+ };
+ };
+};