diff options
Diffstat (limited to 'Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem')
7 files changed, 875 insertions, 0 deletions
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInit.c b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInit.c new file mode 100644 index 0000000000..bda774cb2a --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInit.c @@ -0,0 +1,183 @@ +/** @file
+ Board Init driver.
+
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "BoardInit.h"
+
+EFI_STATUS
+EFIAPI
+AuroraGlacierPreMemInit (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN PEI_BOARD_PRE_MEM_INIT_PPI *This
+ );
+
+static PEI_BOARD_PRE_MEM_INIT_PPI mAuroraPreMemInitPpiInstance = {
+ AuroraGlacierPreMemInit
+};
+
+static EFI_PEI_PPI_DESCRIPTOR mAuroraGlacierPreMemInitPpi = {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gBoardPreMemInitPpiGuid,
+ &mAuroraPreMemInitPpiInstance
+};
+
+static EFI_PEI_PPI_DESCRIPTOR mAuroraGlacierPreMemInitDonePpi = {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gBoardPreMemInitDoneGuid,
+ NULL
+};
+
+EFI_STATUS
+EFIAPI
+AuroraGlacierPreMemInit (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN PEI_BOARD_PRE_MEM_INIT_PPI *This
+ )
+{
+ EFI_STATUS Status;
+ VOID *Instance;
+ UINT8 BoardId;
+ UINT8 FabId;
+
+ BoardId = 0;
+ FabId = 0;
+ Status = PeiServicesLocatePpi (
+ &gBoardPreMemInitDoneGuid,
+ 0,
+ NULL,
+ &Instance
+ );
+ if (!EFI_ERROR (Status)) {
+ return EFI_SUCCESS;
+ }
+
+ //
+ // Pre Mem Board Init
+ //
+ Status = AuroraGetBoardId (PeiServices, &BoardId);
+
+ if (BoardId != (UINT8) BOARD_ID_AURORA) {
+ return EFI_SUCCESS;
+ }
+
+ DEBUG ((EFI_D_INFO, "This is Aurora Glacier board.\n"));
+
+ //
+ //Status = AuroraGetFabId (PeiServices, &FabId);
+ //if (FabId == 1) {
+ // DEBUG ((EFI_D_INFO, "This is Aurora Glacier FAB B.\n"));
+ //} else if (FabId == 0) {
+ // DEBUG ((EFI_D_INFO, "This is Aurora Glacier FAB A.\n"));
+ //}
+ //
+ FabId = 0;
+
+ PcdSet8 (PcdBoardId, BoardId);
+ PcdSet8 (PcdFabId, FabId);
+
+ //
+ // Set board specific function as dynamic PCD to be called by common platform code
+ //
+ PcdSet64 (PcdUpdateFspmUpdFunc, (UINT64) (UINTN) mAuroraUpdateFspmUpdPtr);
+ PcdSet64 (PcdDramCreatePolicyDefaultsFunc, (UINT64) (UINTN) mAuroraDramCreatePolicyDefaultsPtr);
+
+ //
+ // Install a flag signalling a board is detected and pre-mem init is done
+ //
+ Status = PeiServicesInstallPpi (&mAuroraGlacierPreMemInitDonePpi);
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function performs Board initialization in Pre-Memory.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES No enough resoruces (such as out of memory).
+
+**/
+EFI_STATUS
+EFIAPI
+AuroraGlacierInitConstructor (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ VOID *Ppi;
+ EFI_PEI_PPI_DESCRIPTOR *PeiPpiDescriptor;
+ UINTN Instance;
+
+ DEBUG ((EFI_D_INFO, "AuroraGlacier Pre Mem Init Constructor \n"));
+
+ Status = PeiServicesLocatePpi (
+ &gBoardPreMemInitDoneGuid,
+ 0,
+ &PeiPpiDescriptor,
+ &Ppi
+ );
+ if (!EFI_ERROR (Status)) {
+ //
+ // Board detection previously done, so this is a re-invocation shadowed in memory.
+ // Reinstall PPIs to eliminate PPI descriptors in torn down temp RAM.
+ //
+ //
+ // Reinstall PreMemInit Done PPI
+ //
+ DEBUG ((EFI_D_INFO, "Reinstall Pre Mem Init Done PPI\n"));
+ Status = PeiServicesReInstallPpi (
+ PeiPpiDescriptor,
+ &mAuroraGlacierPreMemInitDonePpi
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Reinstall all instances of Pre Mem Init PPIs.
+ // These PPIs are no longer used so it doesn't matter which board's instance is finally installed.
+ // According to PeiServicesReInstallPpi behavior:
+ // The first run of this loop would replace all descrioptors with a singe in-RAM descriptor;
+ // Subsequent runs of this loop will only replace the first (already in-RAM) descriptor.
+ // As long as all descriptors are in ram, we are fine.
+ //
+ Instance = 0;
+ do {
+ Status = PeiServicesLocatePpi (
+ &gBoardPreMemInitPpiGuid,
+ Instance,
+ &PeiPpiDescriptor,
+ &Ppi
+ );
+ if (Status == EFI_NOT_FOUND) {
+ break;
+ }
+ ASSERT_EFI_ERROR (Status);
+ DEBUG ((EFI_D_INFO, "Reinstall Pre Mem Init PPI\n"));
+ Status = PeiServicesReInstallPpi (
+ PeiPpiDescriptor,
+ &mAuroraGlacierPreMemInitPpi
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Instance++;
+ } while (TRUE);
+ return Status;
+ }
+
+ DEBUG ((EFI_D_INFO, "Install Pre Mem Init PPI \n"));
+ Status = PeiServicesInstallPpi (&mAuroraGlacierPreMemInitPpi);
+ return Status;
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInit.h b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInit.h new file mode 100644 index 0000000000..1cec6b18ac --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInit.h @@ -0,0 +1,41 @@ +/** @file
+ GPIO setting for CherryView.
+ This file includes package header files, library classes.
+
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _AURORA_BOARDINIT_H_
+#define _AURORA_BOARDINIT_H_
+
+#include <PiPei.h>
+
+#include <Guid/PlatformInfo_Aplk.h>
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/GpioLib.h>
+#include <Library/HobLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/TimerLib.h>
+
+#include <Ppi/BoardInitSignalling.h>
+
+#include "BoardInitMiscs.h"
+#include "PlatformId.h"
+
+VOID AuroraGpioTest (VOID);
+
+#endif
+
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInitMiscs.c b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInitMiscs.c new file mode 100644 index 0000000000..64f1bdef59 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInitMiscs.c @@ -0,0 +1,332 @@ +/** @file
+ This file does Multiplatform initialization.
+
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "BoardInitMiscs.h"
+#include "MmrcData.h"
+
+UPDATE_FSPM_UPD_FUNC mAuroraUpdateFspmUpdPtr = AuroraUpdateFspmUpd;
+DRAM_CREATE_POLICY_DEFAULTS_FUNC mAuroraDramCreatePolicyDefaultsPtr = AuroraDramCreatePolicyDefaults;
+
+//
+// Aurora Glacier swizzling
+//
+UINT8 ChSwizzleAurora[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS] = {
+ {9,11,10,12,14,15,8,13,0,3,5,1,2,6,7,4,28,25,27,26,29,30,31,24,17,22,23,18,19,20,21,16}, // Channel 0
+ {0,1,5,4,3,6,7,2,12,13,10,14,15,8,9,11,20,23,22,17,21,19,18,16,26,28,29,24,31,25,30,27}, // Channel 1
+ {13,9,15,8,11,10,12,14,2,3,7,4,1,6,0,5,31,29,26,28,25,24,30,27,21,23,16,18,20,19,17,22}, // Channel 2
+ {3,1,6,7,2,5,4,0,8,9,11,10,12,14,13,15,21,17,18,19,23,22,16,20,29,27,25,30,28,24,31,26} // Channel 3
+};
+
+EFI_STATUS
+EFIAPI
+AuroraUpdateFspmUpd (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN FSPM_UPD *FspUpdRgn
+ )
+{
+ EFI_PEI_HOB_POINTERS Hob;
+ EFI_PLATFORM_INFO_HOB *PlatformInfo = NULL;
+ DRAM_POLICY_PPI *DramPolicy;
+ EFI_STATUS Status;
+ MRC_NV_DATA_FRAME *MrcNvData;
+ MRC_PARAMS_SAVE_RESTORE *MrcParamsHob;
+ BOOT_VARIABLE_NV_DATA *BootVariableNvDataHob;
+ SYSTEM_CONFIGURATION SystemConfiguration;
+ UINTN VariableSize;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi;
+
+ Status = (*PeiServices)->LocatePpi (
+ PeiServices,
+ &gDramPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &DramPolicy
+ );
+
+ if (!EFI_ERROR (Status)) {
+ FspUpdRgn->FspmConfig.Package = DramPolicy->Package;
+ FspUpdRgn->FspmConfig.Profile = DramPolicy->Profile;
+ FspUpdRgn->FspmConfig.MemoryDown = DramPolicy->MemoryDown;
+ FspUpdRgn->FspmConfig.DDR3LPageSize = DramPolicy->DDR3LPageSize;
+ FspUpdRgn->FspmConfig.DDR3LASR = DramPolicy->DDR3LASR;
+ FspUpdRgn->FspmConfig.MemorySizeLimit = DramPolicy->SystemMemorySizeLimit;
+ FspUpdRgn->FspmConfig.DIMM0SPDAddress = DramPolicy->SpdAddress[0];
+ FspUpdRgn->FspmConfig.DIMM1SPDAddress = DramPolicy->SpdAddress[1];
+ FspUpdRgn->FspmConfig.DDR3LPageSize = DramPolicy->DDR3LPageSize;
+ FspUpdRgn->FspmConfig.DDR3LASR = DramPolicy->DDR3LASR;
+ FspUpdRgn->FspmConfig.HighMemoryMaxValue = DramPolicy->HighMemMaxVal;
+ FspUpdRgn->FspmConfig.LowMemoryMaxValue = DramPolicy->LowMemMaxVal;
+ FspUpdRgn->FspmConfig.DisableFastBoot = DramPolicy->DisableFastBoot;
+ FspUpdRgn->FspmConfig.RmtMode = DramPolicy->RmtMode;
+ FspUpdRgn->FspmConfig.RmtCheckRun = DramPolicy->RmtCheckRun;
+ FspUpdRgn->FspmConfig.RmtMarginCheckScaleHighThreshold = DramPolicy->RmtMarginCheckScaleHighThreshold;
+ FspUpdRgn->FspmConfig.MsgLevelMask = DramPolicy->MsgLevelMask;
+
+ FspUpdRgn->FspmConfig.ChannelHashMask = DramPolicy->ChannelHashMask;
+ FspUpdRgn->FspmConfig.SliceHashMask = DramPolicy->SliceHashMask;
+ FspUpdRgn->FspmConfig.ChannelsSlicesEnable = DramPolicy->ChannelsSlicesEnabled;
+ FspUpdRgn->FspmConfig.ScramblerSupport = DramPolicy->ScramblerSupport;
+ FspUpdRgn->FspmConfig.InterleavedMode = DramPolicy->InterleavedMode;
+ FspUpdRgn->FspmConfig.MinRefRate2xEnable = DramPolicy->MinRefRate2xEnabled;
+ FspUpdRgn->FspmConfig.DualRankSupportEnable = DramPolicy->DualRankSupportEnabled;
+
+ CopyMem (&(FspUpdRgn->FspmConfig.Ch0_RankEnable), &DramPolicy->ChDrp, sizeof(DramPolicy->ChDrp));
+ CopyMem (&(FspUpdRgn->FspmConfig.Ch0_Bit_swizzling), &DramPolicy->ChSwizzle, sizeof (DramPolicy->ChSwizzle));
+
+ if (((VOID *)(UINT32)DramPolicy->MrcTrainingDataPtr != 0) &&
+ ((VOID *)(UINT32)DramPolicy->MrcBootDataPtr != 0)) {
+ MrcNvData = (MRC_NV_DATA_FRAME *) AllocateZeroPool (sizeof (MRC_NV_DATA_FRAME));
+ MrcParamsHob = (MRC_PARAMS_SAVE_RESTORE*)((UINT32)DramPolicy->MrcTrainingDataPtr);
+ BootVariableNvDataHob = (BOOT_VARIABLE_NV_DATA*)((UINT32)DramPolicy->MrcBootDataPtr);
+ CopyMem(&(MrcNvData->MrcParamsSaveRestore), MrcParamsHob, sizeof (MRC_PARAMS_SAVE_RESTORE));
+ CopyMem(&(MrcNvData->BootVariableNvData), BootVariableNvDataHob, sizeof (BOOT_VARIABLE_NV_DATA));
+ FspUpdRgn->FspmArchUpd.NvsBufferPtr = (VOID *)(UINT32)MrcNvData;
+ }
+
+ }
+
+ DEBUG ((DEBUG_INFO, "UpdateFspmUpd - gEfiPlatformInfoGuid\n"));
+ Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+ ASSERT (Hob.Raw != NULL);
+ PlatformInfo = GET_GUID_HOB_DATA (Hob.Raw);
+
+ DEBUG ((DEBUG_INFO, "**** Aurora - UpdateFspmUpd,BoardId = 0x%02x\n", PlatformInfo->BoardId));
+ if (PlatformInfo->BoardId != BOARD_ID_AURORA) {
+ //
+ // ASSERT false if BoardId isn't Aurora
+ //
+ ASSERT (FALSE);
+ }
+
+ //
+ // Overrides for Aurora Glacier (Micron #MT53B512M32D2NP-062 AIT:C) from Platfrom4 profile
+ //
+ FspUpdRgn->FspmConfig.Package = 0x01;
+ FspUpdRgn->FspmConfig.Profile = 0x0B; // LPDDR4_2400_24_22_22
+ FspUpdRgn->FspmConfig.MemoryDown = 0x01;
+ FspUpdRgn->FspmConfig.DualRankSupportEnable = 0x01;
+
+ FspUpdRgn->FspmConfig.Ch0_RankEnable = 0x03; // [0]: Rank 0 [1]: Rank 1
+ FspUpdRgn->FspmConfig.Ch0_DeviceWidth = 0x01; // x16
+ FspUpdRgn->FspmConfig.Ch0_DramDensity = 0x02; // 8Gb
+ FspUpdRgn->FspmConfig.Ch0_Option = 0x03;
+
+ FspUpdRgn->FspmConfig.Ch1_RankEnable = 0x03; // [0]: Rank 0 [1]: Rank 1
+ FspUpdRgn->FspmConfig.Ch1_DeviceWidth = 0x01; // x16
+ FspUpdRgn->FspmConfig.Ch1_DramDensity = 0x02; // 8Gb
+ FspUpdRgn->FspmConfig.Ch1_Option = 0x03;
+
+ FspUpdRgn->FspmConfig.Ch2_RankEnable = 0x03; // [0]: Rank 0 [1]: Rank 1
+ FspUpdRgn->FspmConfig.Ch2_DeviceWidth = 0x01; // x16
+ FspUpdRgn->FspmConfig.Ch2_DramDensity = 0x02; // 8Gb
+ FspUpdRgn->FspmConfig.Ch2_Option = 0x03;
+
+ FspUpdRgn->FspmConfig.Ch3_RankEnable = 0x03; // [0]: Rank 0 [1]: Rank 1
+ FspUpdRgn->FspmConfig.Ch3_DeviceWidth = 0x01; // x16
+ FspUpdRgn->FspmConfig.Ch3_DramDensity = 0x02; // 8Gb
+ FspUpdRgn->FspmConfig.Ch3_Option = 0x03;
+
+ //
+ // Swizzling
+ //
+ if (ChSwizzleAurora != NULL) {
+ CopyMem (&(FspUpdRgn->FspmConfig.Ch0_Bit_swizzling), ChSwizzleAurora[0], DRAM_POLICY_NUMBER_BITS * sizeof(UINT8));
+ CopyMem (&(FspUpdRgn->FspmConfig.Ch1_Bit_swizzling), ChSwizzleAurora[1], DRAM_POLICY_NUMBER_BITS * sizeof(UINT8));
+ CopyMem (&(FspUpdRgn->FspmConfig.Ch2_Bit_swizzling), ChSwizzleAurora[2], DRAM_POLICY_NUMBER_BITS * sizeof(UINT8));
+ CopyMem (&(FspUpdRgn->FspmConfig.Ch3_Bit_swizzling), ChSwizzleAurora[3], DRAM_POLICY_NUMBER_BITS * sizeof(UINT8));
+ }
+
+ //
+ // Disable NPK based on DciEn
+ //
+ Status = PeiServicesLocatePpi (&gEfiPeiReadOnlyVariable2PpiGuid, 0, NULL, (VOID **) &VariablePpi);
+ if (!EFI_ERROR (Status)) {
+ VariableSize = sizeof (SYSTEM_CONFIGURATION);
+ Status = VariablePpi->GetVariable (
+ VariablePpi,
+ PLATFORM_SETUP_VARIABLE_NAME,
+ &gEfiSetupVariableGuid,
+ NULL,
+ &VariableSize,
+ &SystemConfiguration
+ );
+ if (!EFI_ERROR (Status)) {
+ if (SystemConfiguration.DciEn == 0) {
+ FspUpdRgn->FspmConfig.NpkEn = 0;
+ } else if (SystemConfiguration.DciAutoDetect == 1) {
+ FspUpdRgn->FspmConfig.NpkEn = 3;
+ } else {
+ FspUpdRgn->FspmConfig.NpkEn = 1;
+ }
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ DramCreatePolicyDefaults creates the default setting of Dram Policy.
+
+ @param[out] DramPolicyPpi The pointer to get Dram Policy PPI instance
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+AuroraDramCreatePolicyDefaults (
+ IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi,
+ OUT DRAM_POLICY_PPI **DramPolicyPpi,
+ IN IAFWDramConfig *DramConfigData,
+ IN UINTN *MrcTrainingDataAddr,
+ IN UINTN *MrcBootDataAddr,
+ IN UINT8 BoardId
+ )
+{
+ DRAM_POLICY_PPI *DramPolicy;
+ SYSTEM_CONFIGURATION SystemConfiguration;
+ UINTN VariableSize;
+ EFI_STATUS Status;
+ DRP_DRAM_POLICY *DrpPtr;
+ UINT8 (*ChSwizlePtr)[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS];
+ PlatfromDramConf *DramConfig;
+ BOOLEAN ReadSetupVars;
+
+ DEBUG ((EFI_D_INFO, "*** Aurora Glacier DramCreatePolicyDefaults\n"));
+ DramPolicy = (DRAM_POLICY_PPI *) AllocateZeroPool (sizeof (DRAM_POLICY_PPI));
+ if (DramPolicy == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ ReadSetupVars = FALSE;
+ DrpPtr = NULL;
+ ChSwizlePtr = NULL;
+ DramConfig = NULL;
+
+ VariableSize = sizeof (SYSTEM_CONFIGURATION);
+ Status = VariablePpi->GetVariable (
+ VariablePpi,
+ PLATFORM_SETUP_VARIABLE_NAME,
+ &gEfiSetupVariableGuid,
+ NULL,
+ &VariableSize,
+ &SystemConfiguration
+ );
+
+#if !(ONLY_USE_SMIP_DRAM_POLICY == 1)
+ Status = EFI_UNSUPPORTED;
+#endif
+
+ if (!EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_INFO, "Using setup options data for DRAM policy\n"));
+ ReadSetupVars = TRUE;
+ DramPolicy->ChannelHashMask = SystemConfiguration.ChannelHashMask;
+ DramPolicy->SliceHashMask = SystemConfiguration.SliceHashMask;
+ DramPolicy->ChannelsSlicesEnabled = SystemConfiguration.ChannelsSlicesEnabled;
+ DramPolicy->ScramblerSupport = SystemConfiguration.ScramblerSupport;
+ DramPolicy->InterleavedMode = SystemConfiguration.InterleavedMode;
+ DramPolicy->MinRefRate2xEnabled = SystemConfiguration.MinRefRate2xEnabled;
+ DramPolicy->DualRankSupportEnabled = SystemConfiguration.DualRankSupportEnabled;
+ }
+
+ DramConfig = &(DramConfigData->PlatformDram4);
+
+ DEBUG ((EFI_D_INFO, "Using smip platform override: %d\n", DramConfigData->Platform_override));
+ switch (DramConfigData->Platform_override) {
+ case 0:
+ DramConfig = &(DramConfigData->PlatformDram0);
+ break;
+ case 1:
+ DramConfig = &(DramConfigData->PlatformDram1);
+ break;
+ case 2:
+ DramConfig = &(DramConfigData->PlatformDram2);
+ break;
+ case 3:
+ DramConfig = &(DramConfigData->PlatformDram3);
+ break;
+ case 4:
+ DramConfig = &(DramConfigData->PlatformDram4);
+ break;
+ default:
+ //
+ // Do nothing if the override value does not exist. 0xFF is the
+ // default Platform_override value when no override is selected
+ //
+ break;
+ }
+
+ DramPolicy->Package = DramConfig->Package;
+ DramPolicy->Profile = DramConfig->Profile;
+ DramPolicy->MemoryDown = DramConfig->MemoryDown;
+ DramPolicy->DDR3LPageSize = DramConfig->DDR3LPageSize;
+ DramPolicy->DDR3LASR = DramConfig->DDR3LASR;
+ DramPolicy->SystemMemorySizeLimit = DramConfig->MemorySizeLimit;
+ DramPolicy->SpdAddress[0] = DramConfig->SpdAddress0;
+ DramPolicy->SpdAddress[1] = DramConfig->SpdAddress1;
+ DramPolicy->DDR3LPageSize = DramConfig->DDR3LPageSize;
+ DramPolicy->DDR3LASR = DramConfig->DDR3LASR;
+ DramPolicy->HighMemMaxVal = DramConfig->HighMemMaxVal;
+ DramPolicy->LowMemMaxVal = DramConfig->LowMemMaxVal;
+ DramPolicy->DisableFastBoot = DramConfig->DisableFastBoot;
+ DramPolicy->RmtMode = DramConfig->RmtMode;
+ DramPolicy->RmtCheckRun = DramConfig->RmtCheckRun;
+ DramPolicy->RmtMarginCheckScaleHighThreshold = DramConfig->RmtMarginCheckScaleHighThreshold;
+
+ DramPolicy->MsgLevelMask = DramConfigData->Message_level_mask;
+ DrpPtr = (DRP_DRAM_POLICY *) (&(DramConfig->Ch0RankEnabled));
+ ChSwizlePtr = (UINT8(*)[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS]) (&(DramConfig->Ch0_Bit00_swizzling));
+
+ if (!ReadSetupVars) {
+ DEBUG ((EFI_D_INFO, "Using smip data for DRAM policy\n"));
+ DramPolicy->ChannelHashMask = DramConfig->ChannelHashMask;
+ DramPolicy->SliceHashMask = DramConfig->SliceHashMask;
+ DramPolicy->ChannelsSlicesEnabled = DramConfig->ChannelsSlicesEnabled;
+ DramPolicy->ScramblerSupport = DramConfig->ScramblerSupport;
+ DramPolicy->InterleavedMode = DramConfig->InterleavedMode;
+ DramPolicy->MinRefRate2xEnabled = DramConfig->MinRefRate2xEnabled;
+ DramPolicy->DualRankSupportEnabled = DramConfig->DualRankSupportEnabled;
+ }
+
+ //
+ // DRP
+ //
+ if (DrpPtr != NULL) {
+ CopyMem (DramPolicy->ChDrp, DrpPtr, sizeof (DramPolicy->ChDrp));
+ }
+
+ //
+ // Swizzling
+ //
+ if (ChSwizlePtr != NULL) {
+ CopyMem (DramPolicy->ChSwizzle, ChSwizlePtr, sizeof (DramPolicy->ChSwizzle));
+ }
+
+ if (ReadSetupVars) {
+ if (SystemConfiguration.Max2G == 0) {
+ DramPolicy->SystemMemorySizeLimit = 0x800;
+ }
+ }
+
+ DramPolicy->MrcTrainingDataPtr = (EFI_PHYSICAL_ADDRESS) *MrcTrainingDataAddr;
+ DramPolicy->MrcBootDataPtr = (EFI_PHYSICAL_ADDRESS) *MrcBootDataAddr;
+
+ *DramPolicyPpi = DramPolicy;
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInitMiscs.h b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInitMiscs.h new file mode 100644 index 0000000000..9c498bfaa2 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInitMiscs.h @@ -0,0 +1,46 @@ +/** @file
+ Multiplatform initialization header file.
+ This file includes package header files, library classes.
+
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _AURORA_MULTIPLATFORM_LIB_H_
+#define _AURORA_MULTIPLATFORM_LIB_H_
+
+#include <BoardFunctionsPei.h>
+#include <Guid/SetupVariable.h>
+#include <Library/MemoryAllocationLib.h>
+
+extern UPDATE_FSPM_UPD_FUNC mAuroraUpdateFspmUpdPtr;
+extern DRAM_CREATE_POLICY_DEFAULTS_FUNC mAuroraDramCreatePolicyDefaultsPtr;
+
+EFI_STATUS
+EFIAPI
+AuroraUpdateFspmUpd (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN FSPM_UPD *FspUpdRgn
+ );
+
+EFI_STATUS
+EFIAPI
+AuroraDramCreatePolicyDefaults (
+ IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi,
+ OUT DRAM_POLICY_PPI **DramPolicyPpi,
+ IN IAFWDramConfig *DramConfigData,
+ IN UINTN *MrcTrainingDataAddr,
+ IN UINTN *MrcBootDataAddr,
+ IN UINT8 BoardId
+ );
+
+#endif
+
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInitPreMem.inf b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInitPreMem.inf new file mode 100644 index 0000000000..53312b7f01 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/BoardInitPreMem.inf @@ -0,0 +1,58 @@ +## @file
+# Board detected module for Intel(R) Atom(TM) E3900 Processor Series.
+# It will detect the board ID.
+#
+# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = AuroraGlacierInitPreMem
+ FILE_GUID = 6D2C88A1-78D0-428B-BB8E-47CCA5A3AEEF
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ CONSTRUCTOR = AuroraGlacierInitConstructor
+
+[Sources]
+ BoardInit.c
+ PlatformId.c
+ BoardInitMiscs.c
+
+[LibraryClasses]
+ PeiServicesLib
+ PcdLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ BroxtonPlatformPkg/PlatformPkg.dec
+ BroxtonSiPkg/BroxtonSiPkg.dec
+ BroxtonFspPkg/BroxtonFspPkg.dec
+ IntelFsp2Pkg/IntelFsp2Pkg.dec
+ BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/MemoryInit.dec
+
+[Pcd]
+ gPlatformModuleTokenSpaceGuid.PcdBoardId
+ gPlatformModuleTokenSpaceGuid.PcdFabId
+ gPlatformModuleTokenSpaceGuid.PcdUpdateFspmUpdFunc
+ gPlatformModuleTokenSpaceGuid.PcdDramCreatePolicyDefaultsFunc
+ gMinnowModuleTokenSpaceGuid.PcdDefaultFabId ## CONSUMES
+ gMinnowModuleTokenSpaceGuid.PcdMinnowBoardDetectionRun ## CONSUMES
+ gMinnowModuleTokenSpaceGuid.PcdMinnowBoardDetected ## CONSUMES
+
+[Guids]
+
+[Ppis]
+ gBoardPreMemInitPpiGuid
+ gBoardPreMemInitDoneGuid
+
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/PlatformId.c b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/PlatformId.c new file mode 100644 index 0000000000..af1a0da609 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/PlatformId.c @@ -0,0 +1,144 @@ +/** @file
+ Implement Platform ID code.
+
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Uefi.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/I2CLib.h>
+#include <Library/GpioLib.h>
+#include <Guid/PlatformInfo.h>
+#include "PlatformId.h"
+
+//
+// Board ID pin definiton
+//
+// Bit SoC Pin Value (Leaf Hill) Value (Minnow Board 3) Value (Benson Glacier) Value (Aurora Glacier)
+// 0 GPIO_224 (J45) PU (1) PU (1) PD (0) PD (0)
+// 1 GPIO_213 (M47) PU (1) PU (1) PD (0) PU (1)
+// 2 GPIO_223 (H48) PU (1) PU (1) PU (1) PU (1)
+// 3 GP_CAMERASB10 (R34) PD (0) PU (1) PU (1) PU (1)
+//
+
+
+EFI_STATUS
+EFIAPI
+AuroraGetBoardId(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT UINT8 *BoardId
+ )
+{
+ BXT_CONF_PAD0 padConfg0;
+ BXT_CONF_PAD1 padConfg1;
+ UINT32 CommAndOffset;
+
+ DEBUG ((DEBUG_INFO, "GetBoardId.\n"));
+
+ //
+ // Board_ID0: PMIC_STDBY
+ //
+ CommAndOffset = GetCommOffset (NORTHWEST, 0x00F0);
+ padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);
+ padConfg0.r.PMode = 0; // Set to GPIO mode
+ padConfg0.r.GPIORxTxDis = 0x1; // Set to GPI
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);
+ padConfg1.padCnf1 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET);
+ //
+ // Set to Pull Up 20K
+ //
+ padConfg1.r.Term = 0xC;
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCnf1);
+ //
+ // Board_ID1: PMIC_SDWN_B
+ //
+ CommAndOffset = GetCommOffset (NORTHWEST, 0x00D0);
+ padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);
+ padConfg0.r.PMode = 0;
+ padConfg0.r.GPIORxTxDis = 0x1;
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);
+ //
+ // Board_ID2: PMIC_RESET_B
+ //
+ CommAndOffset = GetCommOffset (NORTHWEST, 0x00C8);
+ padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);
+ padConfg0.r.PMode = 0;
+ padConfg0.r.GPIORxTxDis = 0x1;
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);
+
+ //
+ // Board_ID3: GP_CAMERASB10
+ //
+
+ CommAndOffset = GetCommOffset (NORTH, 0x01E0);
+ padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);
+ padConfg1.padCnf1 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET);
+
+ padConfg0.r.PMode = M0; // Set to GPIO mode
+ padConfg0.r.GPIORxTxDis = GPI; // Set to GPI
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);
+
+ padConfg1.r.IOSTerm = EnPu; // Enable pull-up
+ padConfg1.r.Term = P_20K_H; // Set to 20K pull-up
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCnf1);
+
+ //
+ // Read out Board_ID
+ //
+ *BoardId = (UINT8) (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00F0) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) | \
+ (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00D0) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 1) | \
+ (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00C8) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 2) | \
+ (((GpioPadRead (GetCommOffset (NORTH, 0x01E0) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 3));
+
+ DEBUG ((DEBUG_INFO, "BoardId: %02X\n", *BoardId));
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+AuroraGetFabId(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT UINT8 *FabId
+ )
+{
+ BXT_CONF_PAD0 padConfg0;
+ BXT_CONF_PAD1 padConfg1;
+ UINT32 CommAndOffset;
+
+ DEBUG ((DEBUG_INFO, "Aurora GetFabId++\n"));
+
+
+ //
+ // FAB_ID: GPIO_30
+ //
+
+ CommAndOffset = GetCommOffset (NORTH, 0x0F0);
+ padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);
+ padConfg1.padCnf1 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET);
+
+ padConfg0.r.PMode = M0; // Set to GPIO mode
+ padConfg0.r.GPIORxTxDis = GPI; // Set to GPI
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);
+
+ padConfg1.r.IOSTerm = EnPd; // Enable pull-down
+ padConfg1.r.Term = P_20K_L; // Set to 20K pull-down
+ GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCnf1);
+
+
+ *FabId = (UINT8) (((GpioPadRead (GetCommOffset (NORTH, 0x0F0) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1));
+
+ DEBUG ((EFI_D_INFO, "FabId: %02X\n", *FabId));
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/PlatformId.h b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/PlatformId.h new file mode 100644 index 0000000000..f92d5162b0 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/PlatformId.h @@ -0,0 +1,71 @@ +/** @file
+ Header file for the Platform ID code.
+
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __AURORA_PLATFORM_ID_H__
+#define __AURORAPLATFORM_ID_H__
+
+//
+// Strap Fw Cfg ID define
+//
+#define IO_EXPANDER_I2C_BUS_NO 0x06
+#define IO_EXPANDER_SLAVE_ADDR 0x22
+#define IO_EXPANDER_INPUT_REG_0 0x00
+#define IO_EXPANDER_INPUT_REG_1 0x01
+#define IO_EXPANDER_INPUT_REG_2 0x02
+
+EFI_STATUS
+EFIAPI
+AuroraGetFwCfgId (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT UINT8 *FwCfgId
+ );
+
+EFI_STATUS
+EFIAPI
+AuroraGetBoardId (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT UINT8 *BoardId
+ );
+
+EFI_STATUS
+EFIAPI
+AuroraGetFabId (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT UINT8 *FabId
+ );
+
+EFI_STATUS
+EFIAPI
+AuroraGetDockId (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT UINT8 *DockId
+ );
+
+EFI_STATUS
+EFIAPI
+AuroraGetOsSelPss (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT UINT8 *OsSelPss
+ );
+
+EFI_STATUS
+EFIAPI
+AuroraGetBomIdPss (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT UINT8 *BomIdPss
+ );
+
+#endif
+
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