diff options
Diffstat (limited to 'Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitDxe/BoardInitDxe.c')
| -rw-r--r-- | Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitDxe/BoardInitDxe.c | 115 |
1 files changed, 114 insertions, 1 deletions
diff --git a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitDxe/BoardInitDxe.c b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitDxe/BoardInitDxe.c index d49d2594e7..702c53c49c 100644 --- a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitDxe/BoardInitDxe.c +++ b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitDxe/BoardInitDxe.c @@ -2,7 +2,7 @@ Board specific functions in DXE phase to be set as dynamic PCD and consumed by
commmon platform code.
- Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -15,6 +15,7 @@ **/
#include "BoardInitDxe.h"
+#include <Protocol/SmbusHc.h>
GET_BOARD_NAME mBgGetBoardNamePtr = BgGetBoardName;
@@ -38,6 +39,110 @@ BgGetBoardName ( }
+VOID
+EFIAPI
+BensonProgramPmicPowerSequence (
+ EFI_EVENT Event,
+ VOID *Context
+ )
+{
+ EFI_STATUS Status;
+ EFI_SMBUS_DEVICE_ADDRESS SlaveAddress;
+ EFI_SMBUS_DEVICE_COMMAND Command;
+ UINTN Length;
+ UINT8 BufferData[1];
+ EFI_SMBUS_HC_PROTOCOL *SmbusControllerProtocol;
+
+ //
+ // Programe PMIC.
+ //
+
+ DEBUG ((EFI_D_INFO, "Programe IDTP9810 PMIC. \n"));
+
+ //
+ // Locate SMBus protocol
+ //
+ Status = gBS->LocateProtocol (&gEfiSmbusHcProtocolGuid, NULL, (VOID **)&SmbusControllerProtocol);
+ ASSERT_EFI_ERROR(Status);
+
+ SlaveAddress.SmbusDeviceAddress = (0xBC >> 1); // 0x5E
+ Command = 0x00; // Offset
+ Length = 1;
+
+ //
+ // Read one byte
+ //
+ Status = SmbusControllerProtocol->Execute (
+ SmbusControllerProtocol,
+ SlaveAddress,
+ Command,
+ EfiSmbusReadByte,
+ FALSE,
+ &Length,
+ BufferData
+ );
+
+
+ DEBUG ((EFI_D_INFO, "PMIC Vendor ID = %0x. \n", (UINT32) BufferData[0]));
+
+
+ SlaveAddress.SmbusDeviceAddress = (0xBC >> 1); // 0x5E
+ Command = 0x2A; // Offset
+ Length = 1;
+
+ //
+ // Read one byte
+ //
+ Status = SmbusControllerProtocol->Execute (
+ SmbusControllerProtocol,
+ SlaveAddress,
+ Command,
+ EfiSmbusReadByte,
+ FALSE,
+ &Length,
+ BufferData
+ );
+
+
+ DEBUG ((EFI_D_INFO, "PMIC Power Sequence Configuration Offset 0x2A PWRSEQCFG = %0x. \n", (UINT32) BufferData[0]));
+
+ //
+ // Set Bit 2 (SUSPWRDNACKCFG) of PWRSEQCFG.
+ // 0 = SUSPWRDNACK signal is ignored. PMIC will not go to G3 when SUSPWRDNACK goes high in S4 state.
+ // 1 = PMIC responses to SUSPWRDNACK signal.
+ //
+ BufferData[0] = BufferData[0] | 0x04;
+ Status = SmbusControllerProtocol->Execute (
+ SmbusControllerProtocol,
+ SlaveAddress,
+ Command,
+ EfiSmbusWriteByte,
+ FALSE,
+ &Length,
+ BufferData
+ );
+ DEBUG ((EFI_D_INFO, "PMIC Power Sequence Configuration Set Bit 2 (SUSPWRDNACKCFG) of PWRSEQCFG. \n"));
+
+
+ //
+ // Read one byte
+ //
+ Status = SmbusControllerProtocol->Execute (
+ SmbusControllerProtocol,
+ SlaveAddress,
+ Command,
+ EfiSmbusReadByte,
+ FALSE,
+ &Length,
+ BufferData
+ );
+
+
+ DEBUG ((EFI_D_INFO, "PMIC Power Sequence Configuration Offset 0x2A PWRSEQCFG = %0x. \n", (UINT32) BufferData[0]));
+}
+
+
+
/**
Set PCDs for board specific functions.
@@ -55,6 +160,7 @@ BgBoardInitDxeConstructor ( )
{
UINT8 BoardId;
+ EFI_EVENT ReadyToBootEvent;
BoardId = PcdGet8 (PcdBoardId);
if (BoardId != (UINT8) BOARD_ID_BENSON) {
@@ -63,6 +169,13 @@ BgBoardInitDxeConstructor ( PcdSet64 (PcdGetBoardNameFunc, (UINT64) mBgGetBoardNamePtr);
+ EfiCreateEventReadyToBootEx (
+ TPL_CALLBACK,
+ BensonProgramPmicPowerSequence,
+ NULL,
+ &ReadyToBootEvent
+ );
+
return EFI_SUCCESS;
}
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