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-rw-r--r--Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/SueCreek/SueCreek.asl42
1 files changed, 42 insertions, 0 deletions
diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/SueCreek/SueCreek.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/SueCreek/SueCreek.asl
new file mode 100644
index 0000000000..d67b3c4c39
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/SueCreek/SueCreek.asl
@@ -0,0 +1,42 @@
+/** @file
+
+Copyright (c) 2017 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope (\_SB.PCI0.SPI1) {
+ Device (TP0) {
+ Name (_HID, "SPT0001")
+ Name (_DDN, "SueCreek - SPI0, CS0")
+ Name (_CRS, ResourceTemplate () {
+ SpiSerialBus (
+ 0, // Chip select (0, 1, 2)
+ PolarityLow, // Chip select is active low
+ FourWireMode, // Full duplex
+ 8, // Bits per word is 8 (byte)
+ ControllerInitiated, // Don't care
+ 1000000, // 1 MHz
+ ClockPolarityLow, // SPI mode 0
+ ClockPhaseFirst, // SPI mode 0
+ "\\_SB.PCI0.SPI1", // SPI host controller
+ 0 // Must be 0
+ )
+ })
+ Method (_STA, 0x0, NotSerialized) {
+ If (LEqual (OSYS, 2015)) {
+ Return (0x0)
+ } else {
+ Return (0xF)
+ }
+ }
+ }
+}
+