diff options
Diffstat (limited to 'Platform/BroxtonPlatformPkg/Common/Acpi')
4 files changed, 17 insertions, 6 deletions
diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatform.c b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatform.c index d3c10b1e5a..f0a77d15bd 100644 --- a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatform.c +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatform.c @@ -1439,6 +1439,8 @@ AcpiPlatformEntryPoint ( mGlobalNvsArea.Area->BatteryCapacity0 = 100;
mGlobalNvsArea.Area->Mmio32Base = (MmioRead32 ((UINTN) PcdGet64 (PcdPciExpressBaseAddress) + 0xBC) & 0xFFF00000);;
mGlobalNvsArea.Area->Mmio32Length = ACPI_MMIO_BASE_ADDRESS - mGlobalNvsArea.Area->Mmio32Base;
+ mGlobalNvsArea.Area->SueCreekEnable = PcdGetBool(PcdSueCreek);
+
//
// Initialize IGD state by checking if IGD Device 2 Function 0 is enabled in the chipset
//
diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf index 5e876dcbe0..be047c13fc 100644 --- a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf @@ -86,6 +86,7 @@ gEfiBxtTokenSpaceGuid.PcdPmcGcrBaseAddress
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
gPlatformModuleTokenSpaceGuid.PcdResetType
+ gPlatformModuleTokenSpaceGuid.PcdSueCreek
[Depex]
gEfiAcpiSupportProtocolGuid AND
diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/GloblNvs.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/GloblNvs.asl index b2f6f56093..78416f67ab 100644 --- a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/GloblNvs.asl +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/GloblNvs.asl @@ -1,7 +1,7 @@ /** @file
ACPI GNVS
- Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -474,5 +474,11 @@ IC5S, 32, // (906) I2C5 Speed - Standard mode/Fast mode/FastPlus mode/HighSpeed mode
IC6S, 32, // (910) I2C6 Speed - Standard mode/Fast mode/FastPlus mode/HighSpeed mode
IC7S, 32, // (914) I2C7 Speed - Standard mode/Fast mode/FastPlus mode/HighSpeed mode
+ SEN2, 8, // (918) EnableSen2Participant
+ PTTP, 8, // (919) PassiveThermalTripPointSen2
+ CTTP, 8, // (920) CriticalThermalTripPointSen2S3
+ HTTP, 8, // (921) HotThermalTripPointSen2
+ CRTP, 8, // (922) CriticalThermalTripPointSen2
+ SUCE, 8, // (923) SueCreekEnable: 0: disabled; 1: enabled
}
diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/SueCreek/SueCreek.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/SueCreek/SueCreek.asl index d67b3c4c39..3baa88cc41 100644 --- a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/SueCreek/SueCreek.asl +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/SueCreek/SueCreek.asl @@ -14,7 +14,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. Scope (\_SB.PCI0.SPI1) {
Device (TP0) {
- Name (_HID, "SPT0001")
+ Name (_HID, "SUE1000") Name (_DDN, "SueCreek - SPI0, CS0")
Name (_CRS, ResourceTemplate () {
SpiSerialBus (
@@ -23,15 +23,17 @@ Scope (\_SB.PCI0.SPI1) { FourWireMode, // Full duplex
8, // Bits per word is 8 (byte)
ControllerInitiated, // Don't care
- 1000000, // 1 MHz
- ClockPolarityLow, // SPI mode 0
- ClockPhaseFirst, // SPI mode 0
+ 9600000, // 9.6 MHz + ClockPolarityHigh, // SPI mode 3 + ClockPhaseSecond, // SPI mode 3 "\\_SB.PCI0.SPI1", // SPI host controller
0 // Must be 0
)
})
+
+ External(\SUCE, IntObj)
Method (_STA, 0x0, NotSerialized) {
- If (LEqual (OSYS, 2015)) {
+ If (LEqual (SUCE, 0)) {
Return (0x0)
} else {
Return (0xF)
|