1 files changed, 34 insertions, 0 deletions
diff --git a/Platform/Hisilicon/D02/Include/Library/CpldD02.h b/Platform/Hisilicon/D02/Include/Library/CpldD02.h
new file mode 100644
index 0000000000..b899dbb377
--- /dev/null
+++ b/Platform/Hisilicon/D02/Include/Library/CpldD02.h
@@ -0,0 +1,34 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __CPLDD02_H__
+#define __CPLDD02_H__
+#define CPLD_LOGIC_VERSION                (0x52)
+#define PRODUCT_VERSION                   (0x53)
+#define CPLD_LOGIC_COMPLIER_YEAR          (0x54)
+#define CPLD_LOGIC_COMPLIER_MONTH         (0x55)
+#define CPLD_LOGIC_COMPLIER_DAY           (0x56)
+#define CPLD_LOGIC_COMPLIER_HOUR          (0x57)
+#define CPLD_LOGIC_COMPLIER_MINUTE        (0x58)
+#define BOARD_ID                          (0x59)
+#define BOM_VERSION                       (0x5A)
+#define CPLD_BIOS_CURRENT_CHANNEL_REG_D02 (0x5B)
+
+#define CPU0_PCIE1_RESET_REG                (0x12)
+#define CPU0_PCIE2_RESET_REG                (0x13)
+#define CPU1_PCIE1_RESET_REG                (0x14)
+#define CPU1_PCIE2_RESET_REG                (0x15)
+
+#endif /* __CPLDD02_H__ */