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-rw-r--r--Platform/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c105
-rw-r--r--Platform/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02Strings.unibin0 -> 1796 bytes
-rw-r--r--Platform/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.c77
-rw-r--r--Platform/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.inf45
-rw-r--r--Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c147
-rw-r--r--Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf182
6 files changed, 556 insertions, 0 deletions
diff --git a/Platform/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c b/Platform/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c
new file mode 100644
index 0000000000..49942e5151
--- /dev/null
+++ b/Platform/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c
@@ -0,0 +1,105 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <PlatformArch.h>
+#include <Library/OemMiscLib.h>
+#include <Library/SerdesLib.h>
+#include <Library/CpldIoLib.h>
+#include <Library/CpldD02.h>
+#include <Library/TimerLib.h>
+#include <Library/I2CLib.h>
+#include <Library/HiiLib.h>
+
+I2C_DEVICE gDS3231RtcDevice = {
+ .Socket = 0,
+ .Port = 7,
+ .DeviceType = DEVICE_TYPE_SPD,
+ .SlaveDeviceAddress = 0x68
+};
+
+// Set Tx output polarity. Not inverting data is default. For Phosphor660 D02 Board
+//if((1 == ulMacroId) && ((7 == ulDsNum)||(0 == ulDsNum)))
+SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[] =
+{
+ {1, 7},
+ {1, 0},
+ {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+
+// Set Rx data polarity. Not inverting data is default. For Phosphor660 D02 Board
+//if((1 == ulMacroId) && ((0 == ulDsNum) || (1 == ulDsNum)))
+SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[] =
+{
+ {1, 0},
+ {1, 1},
+ {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+
+SERDES_PARAM gSerdesParam = {
+ .Hilink0Mode = EmHilink0Pcie1X8,
+ .Hilink1Mode = EmHilink1Pcie0X8,
+ .Hilink2Mode = EmHilink2Pcie2X8,
+ .Hilink3Mode = EmHilink3GeX4,
+ .Hilink4Mode = EmHilink4XgeX4,
+ .Hilink5Mode = EmHilink5Sas1X4,
+};
+
+EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId)
+{
+ if (ParamA == NULL) {
+ DEBUG((DEBUG_ERROR, "[%a]:[%dL] ParamA == NULL!\n", __FUNCTION__, __LINE__));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ (VOID) CopyMem(ParamA, &gSerdesParam, sizeof(*ParamA));
+ return EFI_SUCCESS;
+}
+
+
+VOID OemPcieResetAndOffReset(void)
+ {
+ WriteCpldReg(CPU0_PCIE1_RESET_REG,0x0);
+ WriteCpldReg(CPU0_PCIE2_RESET_REG,0x0);
+ WriteCpldReg(CPU1_PCIE1_RESET_REG,0x0);
+ WriteCpldReg(CPU1_PCIE2_RESET_REG,0x0);
+ MicroSecondDelay(100000);
+ WriteCpldReg(CPU0_PCIE1_RESET_REG,0x55);
+ WriteCpldReg(CPU0_PCIE2_RESET_REG,0x55);
+ WriteCpldReg(CPU1_PCIE1_RESET_REG,0x55);
+ WriteCpldReg(CPU1_PCIE2_RESET_REG,0x55);
+ return;
+ }
+
+EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] = {
+ {{STRING_TOKEN(STR_D02_DIMM_000), STRING_TOKEN(STR_D02_DIMM_001), 0xFFFF},
+ {STRING_TOKEN(STR_D02_DIMM_010), STRING_TOKEN(STR_D02_DIMM_011), 0xFFFF}}
+};
+
+EFI_HII_HANDLE
+EFIAPI
+OemGetPackages (
+ )
+{
+ return HiiAddPackages (
+ &gEfiCallerIdGuid,
+ NULL,
+ OemMiscLibD02Strings,
+ NULL,
+ NULL
+ );
+}
diff --git a/Platform/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02Strings.uni b/Platform/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02Strings.uni
new file mode 100644
index 0000000000..dcd79eb3d5
--- /dev/null
+++ b/Platform/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02Strings.uni
Binary files differ
diff --git a/Platform/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.c b/Platform/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.c
new file mode 100644
index 0000000000..df7d158c2d
--- /dev/null
+++ b/Platform/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.c
@@ -0,0 +1,77 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/TimerLib.h>
+#include <Library/CpldIoLib.h>
+#include <Library/OemMiscLib.h>
+#include <PlatformArch.h>
+#include <Library/PlatformSysCtrlLib.h>
+#include <Library/OemAddressMapLib.h>
+#include <Library/SerialPortLib.h>
+
+// Right now we only support 1P
+BOOLEAN OemIsSocketPresent (UINTN Socket)
+{
+ if (0 == Socket)
+ {
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+UINTN OemGetSocketNumber (VOID)
+{
+ return 1;
+}
+
+UINTN OemGetDimmSlot(UINTN Socket, UINTN Channel)
+{
+ return 2;
+}
+
+UINTN OemGetDdrChannel (VOID)
+{
+ return 2;
+}
+
+VOID CoreSelectBoot(VOID)
+{
+ if (!PcdGet64 (PcdTrustedFirmwareEnable))
+ {
+ StartupAp ();
+ }
+
+ return;
+}
+
+BOOLEAN OemIsMpBoot()
+{
+ return FALSE;
+}
+
+VOID OemBiosSwitch(UINT32 Master)
+{
+ return;
+}
+
+UINT32 OemIsWarmBoot(VOID)
+{
+ return 0;
+}
diff --git a/Platform/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.inf b/Platform/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.inf
new file mode 100644
index 0000000000..3b50ddf9bc
--- /dev/null
+++ b/Platform/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.inf
@@ -0,0 +1,45 @@
+#/** @file
+#
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = OemMiscLibD02
+ FILE_GUID = 1DCE7EC8-3DB6-47cf-A2B5-717FD9AB2570
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = OemMiscLib
+
+[Sources.common]
+ BoardFeatureD02.c
+ OemMiscLibD02.c
+ BoardFeatureD02Strings.uni
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+
+ Platform/Hisilicon/D02/Pv660D02.dec
+ Silicon/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ SerialPortLib
+ CpldIoLib
+
+[BuildOptions]
+
+[Pcd]
+ gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+
diff --git a/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c b/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c
new file mode 100644
index 0000000000..797163a5fc
--- /dev/null
+++ b/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c
@@ -0,0 +1,147 @@
+/** @file
+
+ Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/PcdLib.h>
+#include <Library/PlatformPciLib.h>
+
+PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {
+ {// HostBridge 0
+ /* Port 0 */
+ {
+ PCI_HB0RB0_ECAM_BASE,
+ 0, //BusBase
+ 63, //BusLimit
+ (PCI_HB0RB0_ECAM_BASE + SIZE_64MB), //MemBase
+ (PCI_HB0RB0_ECAM_BASE + PCI_HB0RB0_ECAM_SIZE - 1), //MemLimit
+ (0), //IoBase
+ (0), //IoLimit
+ 0,
+ 0,
+ (PCI_HB0RB0_PCI_BASE), //RbPciBar
+ 0,
+ 0
+ },
+ /* Port 1 */
+ {
+ PCI_HB0RB1_ECAM_BASE,
+ 64, //BusBase
+ 127, //BusLimit
+ PCI_HB0RB1_PCIREGION_BASE,
+ PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1,
+ PCI_HB0RB1_IO_BASE, //IoBase
+ PCI_HB0RB1_IO_BASE + PCI_HB0RB1_IO_SIZE - 1, //IoLimit
+ PCI_HB0RB1_CPUMEMREGIONBASE,
+ PCI_HB0RB2_CPUIOREGIONBASE,
+ (PCI_HB0RB1_PCI_BASE), //RbPciBar
+ PCI_HB0RB1_PCIREGION_BASE,
+ PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1
+ },
+ /* Port 2 */
+ {
+ PCI_HB0RB2_ECAM_BASE,
+ 128, //BusBase
+ 191, //BusLimit
+ PCI_HB0RB2_PCIREGION_BASE ,
+ PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1,
+ PCI_HB0RB2_IO_BASE, //IoBase
+ PCI_HB0RB2_IO_BASE + PCI_HB0RB2_IO_SIZE - 1, //IoLimit
+ PCI_HB0RB2_CPUMEMREGIONBASE,
+ PCI_HB0RB2_CPUIOREGIONBASE,
+ (PCI_HB0RB2_PCI_BASE), //RbPciBar
+ PCI_HB0RB2_PCIREGION_BASE ,
+ PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1
+ },
+
+ /* Port 3 */
+ {
+ PCI_HB0RB3_ECAM_BASE,
+ 192, //BusBase
+ 255, //BusLimit
+ (PCI_HB0RB3_ECAM_BASE), //MemBase
+ (PCI_HB0RB3_ECAM_BASE + PCI_HB0RB3_ECAM_SIZE - 1), //MemLimit
+ (0), //IoBase
+ (0), //IoLimit
+ 0,
+ 0,
+ (PCI_HB0RB3_PCI_BASE), //RbPciBar
+ 0,
+ 0
+ }
+ },
+{// HostBridge 1
+ /* Port 0 */
+ {
+ PCI_HB1RB0_ECAM_BASE,
+ 0, //BusBase
+ 0x1, //BusLimit
+ (PCI_HB1RB0_ECAM_BASE), //MemBase
+ (PCI_HB1RB0_ECAM_BASE + PCI_HB1RB0_ECAM_SIZE - 1), //MemLimit
+ (0), //IoBase
+ (0), //IoLimit
+ 0,
+ 0,
+ (PCI_HB1RB0_PCI_BASE), //RbPciBar
+ 0,
+ 0
+ },
+ /* Port 1 */
+ {
+ PCI_HB1RB1_ECAM_BASE,
+ 0x2, //BusBase
+ 0x3, //BusLimit
+ (PCI_HB1RB1_ECAM_BASE), //MemBase
+ (PCI_HB1RB1_ECAM_BASE + PCI_HB1RB1_ECAM_SIZE - 1), //MemLimit
+ (0), //IoBase
+ (0), //IoLimit
+ 0,
+ 0,
+ (PCI_HB1RB1_PCI_BASE), //RbPciBar
+ 0,
+ 0
+ },
+ /* Port 2 */
+ {
+ PCI_HB1RB2_ECAM_BASE,
+ 0x4, //BusBase
+ 0x5, //BusLimit
+ (PCI_HB1RB2_ECAM_BASE), //MemBase
+ (PCI_HB1RB2_ECAM_BASE + PCI_HB1RB2_ECAM_SIZE - 1), //MemLimit
+ (0), //IoBase
+ (0), //IoLimit
+ 0,
+ 0,
+ (PCI_HB1RB2_PCI_BASE), //RbPciBar
+ 0,
+ 0
+ },
+
+ /* Port 3 */
+ {
+ PCI_HB1RB3_ECAM_BASE,
+ 0x6, //BusBase
+ 0x7, //BusLimit
+ (PCI_HB1RB3_ECAM_BASE), //MemBase
+ (PCI_HB1RB3_ECAM_BASE + PCI_HB1RB3_ECAM_SIZE - 1), //MemLimit
+ (0), //IoBase
+ (0), //IoLimit
+ 0,
+ 0,
+ (PCI_HB1RB3_PCI_BASE), //RbPciBar
+ 0,
+ 0
+ }
+ }
+};
+
diff --git a/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf b/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf
new file mode 100644
index 0000000000..4d2dbbaf0d
--- /dev/null
+++ b/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf
@@ -0,0 +1,182 @@
+## @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
+# Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PlatformPciLib
+ FILE_GUID = 61b7276a-fc67-11e5-82fd-47ea9896dd5d
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+
+[Sources]
+ PlatformPciLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ PcdLib
+
+[FixedPcd]
+ gHisiTokenSpaceGuid.PcdHb1BaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PciHb0Rb0Base
+ gHisiTokenSpaceGuid.PciHb0Rb1Base
+ gHisiTokenSpaceGuid.PciHb0Rb2Base
+ gHisiTokenSpaceGuid.PciHb0Rb3Base
+ gHisiTokenSpaceGuid.PciHb0Rb4Base
+ gHisiTokenSpaceGuid.PciHb0Rb5Base
+ gHisiTokenSpaceGuid.PciHb0Rb6Base
+ gHisiTokenSpaceGuid.PciHb0Rb7Base
+ gHisiTokenSpaceGuid.PciHb1Rb0Base
+ gHisiTokenSpaceGuid.PciHb1Rb1Base
+ gHisiTokenSpaceGuid.PciHb1Rb2Base
+ gHisiTokenSpaceGuid.PciHb1Rb3Base
+ gHisiTokenSpaceGuid.PciHb1Rb4Base
+ gHisiTokenSpaceGuid.PciHb1Rb5Base
+ gHisiTokenSpaceGuid.PciHb1Rb6Base
+ gHisiTokenSpaceGuid.PciHb1Rb7Base
+ gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress
+
+ gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize
+
+ gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase
+
+ gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase
+
+ gHisiTokenSpaceGuid.PcdHb0Rb0IoBase
+ gHisiTokenSpaceGuid.PcdHb0Rb0IoSize
+ gHisiTokenSpaceGuid.PcdHb0Rb1IoBase
+ gHisiTokenSpaceGuid.PcdHb0Rb1IoSize
+ gHisiTokenSpaceGuid.PcdHb0Rb2IoBase
+ gHisiTokenSpaceGuid.PcdHb0Rb2IoSize
+ gHisiTokenSpaceGuid.PcdHb0Rb3IoBase
+ gHisiTokenSpaceGuid.PcdHb0Rb3IoSize
+ gHisiTokenSpaceGuid.PcdHb0Rb4IoBase
+ gHisiTokenSpaceGuid.PcdHb0Rb4IoSize
+ gHisiTokenSpaceGuid.PcdHb0Rb5IoBase
+ gHisiTokenSpaceGuid.PcdHb0Rb5IoSize
+ gHisiTokenSpaceGuid.PcdHb0Rb6IoBase
+ gHisiTokenSpaceGuid.PcdHb0Rb6IoSize
+ gHisiTokenSpaceGuid.PcdHb0Rb7IoBase
+ gHisiTokenSpaceGuid.PcdHb0Rb7IoSize
+ gHisiTokenSpaceGuid.PcdHb1Rb0IoBase
+ gHisiTokenSpaceGuid.PcdHb1Rb0IoSize
+ gHisiTokenSpaceGuid.PcdHb1Rb1IoBase
+ gHisiTokenSpaceGuid.PcdHb1Rb1IoSize
+ gHisiTokenSpaceGuid.PcdHb1Rb2IoBase
+ gHisiTokenSpaceGuid.PcdHb1Rb2IoSize
+ gHisiTokenSpaceGuid.PcdHb1Rb3IoBase
+ gHisiTokenSpaceGuid.PcdHb1Rb3IoSize
+ gHisiTokenSpaceGuid.PcdHb1Rb4IoBase
+ gHisiTokenSpaceGuid.PcdHb1Rb4IoSize
+ gHisiTokenSpaceGuid.PcdHb1Rb5IoBase
+ gHisiTokenSpaceGuid.PcdHb1Rb5IoSize
+ gHisiTokenSpaceGuid.PcdHb1Rb6IoBase
+ gHisiTokenSpaceGuid.PcdHb1Rb6IoSize
+ gHisiTokenSpaceGuid.PcdHb1Rb7IoBase
+ gHisiTokenSpaceGuid.PcdHb1Rb7IoSize
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-03 09:58:01 +0000