diff options
Diffstat (limited to 'Platform/Hisilicon/D03/Drivers')
6 files changed, 1124 insertions, 0 deletions
diff --git a/Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig.h b/Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig.h new file mode 100644 index 0000000000..46c77d3061 --- /dev/null +++ b/Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig.h @@ -0,0 +1,40 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __OEM_NIC_CONFIG_H__
+#define __OEM_NIC_CONFIG_H__
+
+#define I2C_SLAVEADDR_EEPROM (0x52)
+
+#define I2C_OFFSET_EEPROM_ETH0 (0xc00)
+#define I2C_OFFSET_EEPROM_ETH1 (I2C_OFFSET_EEPROM_ETH0 + 6)
+#define I2C_OFFSET_EEPROM_ETH2 (I2C_OFFSET_EEPROM_ETH1 + 6)
+#define I2C_OFFSET_EEPROM_ETH3 (I2C_OFFSET_EEPROM_ETH2 + 6)
+#define I2C_OFFSET_EEPROM_ETH4 (I2C_OFFSET_EEPROM_ETH3 + 6)
+#define I2C_OFFSET_EEPROM_ETH5 (I2C_OFFSET_EEPROM_ETH4 + 6)
+#define I2C_OFFSET_EEPROM_ETH6 (I2C_OFFSET_EEPROM_ETH5 + 6)
+#define I2C_OFFSET_EEPROM_ETH7 (I2C_OFFSET_EEPROM_ETH6 + 6)
+
+#define MAC_ADDR_LEN 6
+
+#pragma pack(1)
+typedef struct {
+ UINT16 Crc16;
+ UINT16 MacLen;
+ UINT8 Mac[MAC_ADDR_LEN];
+} NIC_MAC_ADDRESS;
+#pragma pack()
+
+#endif
diff --git a/Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c b/Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c new file mode 100644 index 0000000000..dcaf3aa827 --- /dev/null +++ b/Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c @@ -0,0 +1,362 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/TimerLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/HisiBoardNicProtocol.h>
+#include <OemNicConfig.h>
+#include <Library/CpldIoLib.h>
+
+#include <Library/I2CLib.h>
+
+#define EEPROM_I2C_PORT 6
+#define EEPROM_PAGE_SIZE 0x40
+
+EFI_STATUS
+EFIAPI OemGetMac2P (IN OUT EFI_MAC_ADDRESS *Mac, IN UINTN Port);
+
+EFI_STATUS
+EFIAPI OemSetMac2P (IN EFI_MAC_ADDRESS *Mac, IN UINTN Port);
+
+EFI_STATUS OemGetMacE2prom(IN UINT32 Port, OUT UINT8 *pucAddr);
+EFI_STATUS OemSetMacE2prom(IN UINT32 Port, IN UINT8 *pucAddr);
+
+volatile unsigned char g_2pserveraddr[4][6] =
+{
+ {0x00, 0x18, 0x16, 0x29, 0x11, 0x00},
+ {0x00, 0x18, 0x16, 0x29, 0x11, 0x01},
+ {0x00, 0x18, 0x16, 0x29, 0x11, 0x02},
+ {0x00, 0x18, 0x16, 0x29, 0x11, 0x03}
+};
+
+UINT16 crc_tab[256] = {
+ 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50A5, 0x60C6, 0x70E7,
+ 0x8108, 0x9129, 0xA14A, 0xB16B, 0xC18C, 0xD1AD, 0xE1CE, 0xF1EF,
+ 0x1231, 0x0210, 0x3273, 0x2252, 0x52B5, 0x4294, 0x72F7, 0x62D6,
+ 0x9339, 0x8318, 0xB37B, 0xA35A, 0xD3BD, 0xC39C, 0xF3FF, 0xE3DE,
+ 0x2462, 0x3443, 0x0420, 0x1401, 0x64E6, 0x74C7, 0x44A4, 0x5485,
+ 0xA56A, 0xB54B, 0x8528, 0x9509, 0xE5EE, 0xF5CF, 0xC5AC, 0xD58D,
+ 0x3653, 0x2672, 0x1611, 0x0630, 0x76D7, 0x66F6, 0x5695, 0x46B4,
+ 0xB75B, 0xA77A, 0x9719, 0x8738, 0xF7DF, 0xE7FE, 0xD79D, 0xC7BC,
+ 0x48C4, 0x58E5, 0x6886, 0x78A7, 0x0840, 0x1861, 0x2802, 0x3823,
+ 0xC9CC, 0xD9ED, 0xE98E, 0xF9AF, 0x8948, 0x9969, 0xA90A, 0xB92B,
+ 0x5AF5, 0x4AD4, 0x7AB7, 0x6A96, 0x1A71, 0x0A50, 0x3A33, 0x2A12,
+ 0xDBFD, 0xCBDC, 0xFBBF, 0xEB9E, 0x9B79, 0x8B58, 0xBB3B, 0xAB1A,
+ 0x6CA6, 0x7C87, 0x4CE4, 0x5CC5, 0x2C22, 0x3C03, 0x0C60, 0x1C41,
+ 0xEDAE, 0xFD8F, 0xCDEC, 0xDDCD, 0xAD2A, 0xBD0B, 0x8D68, 0x9D49,
+ 0x7E97, 0x6EB6, 0x5ED5, 0x4EF4, 0x3E13, 0x2E32, 0x1E51, 0x0E70,
+ 0xFF9F, 0xEFBE, 0xDFDD, 0xCFFC, 0xBF1B, 0xAF3A, 0x9F59, 0x8F78,
+ 0x9188, 0x81A9, 0xB1CA, 0xA1EB, 0xD10C, 0xC12D, 0xF14E, 0xE16F,
+ 0x1080, 0x00A1, 0x30C2, 0x20E3, 0x5004, 0x4025, 0x7046, 0x6067,
+ 0x83B9, 0x9398, 0xA3FB, 0xB3DA, 0xC33D, 0xD31C, 0xE37F, 0xF35E,
+ 0x02B1, 0x1290, 0x22F3, 0x32D2, 0x4235, 0x5214, 0x6277, 0x7256,
+ 0xB5EA, 0xA5CB, 0x95A8, 0x8589, 0xF56E, 0xE54F, 0xD52C, 0xC50D,
+ 0x34E2, 0x24C3, 0x14A0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
+ 0xA7DB, 0xB7FA, 0x8799, 0x97B8, 0xE75F, 0xF77E, 0xC71D, 0xD73C,
+ 0x26D3, 0x36F2, 0x0691, 0x16B0, 0x6657, 0x7676, 0x4615, 0x5634,
+ 0xD94C, 0xC96D, 0xF90E, 0xE92F, 0x99C8, 0x89E9, 0xB98A, 0xA9AB,
+ 0x5844, 0x4865, 0x7806, 0x6827, 0x18C0, 0x08E1, 0x3882, 0x28A3,
+ 0xCB7D, 0xDB5C, 0xEB3F, 0xFB1E, 0x8BF9, 0x9BD8, 0xABBB, 0xBB9A,
+ 0x4A75, 0x5A54, 0x6A37, 0x7A16, 0x0AF1, 0x1AD0, 0x2AB3, 0x3A92,
+ 0xFD2E, 0xED0F, 0xDD6C, 0xCD4D, 0xBDAA, 0xAD8B, 0x9DE8, 0x8DC9,
+ 0x7C26, 0x6C07, 0x5C64, 0x4C45, 0x3CA2, 0x2C83, 0x1CE0, 0x0CC1,
+ 0xEF1F, 0xFF3E, 0xCF5D, 0xDF7C, 0xAF9B, 0xBFBA, 0x8FD9, 0x9FF8,
+ 0x6E17, 0x7E36, 0x4E55, 0x5E74, 0x2E93, 0x3EB2, 0x0ED1, 0x1EF0,
+};
+
+UINT16 make_crc_checksum(UINT8 *buf, UINT32 len)
+{
+ UINT16 StartCRC = 0;
+
+ if (len > (512 * 1024))
+ {
+ return 0;
+ }
+
+ if (NULL == buf)
+ {
+ return 0;
+ }
+
+ while (len)
+ {
+ StartCRC = crc_tab[((UINT8)((StartCRC >> 8) & 0xff)) ^ *(buf++)] ^ ((UINT16)(StartCRC << 8));
+ len--;
+ }
+
+ return StartCRC;
+}
+
+
+EFI_STATUS OemGetMacE2prom(IN UINT32 Port, OUT UINT8 *pucAddr)
+{
+ I2C_DEVICE stI2cDev = {0};
+ EFI_STATUS Status;
+ UINT16 I2cOffset;
+ UINT16 crc16;
+ NIC_MAC_ADDRESS stMacDesc = {0};
+ UINT16 RemainderMacOffset;
+ UINT16 LessSizeOfPage;
+
+ Status = I2CInit(0, EEPROM_I2C_PORT, Normal);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2CInit failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status));
+ return Status;
+ }
+
+ I2cOffset = I2C_OFFSET_EEPROM_ETH0 + (Port * sizeof(NIC_MAC_ADDRESS));
+
+ stI2cDev.DeviceType = DEVICE_TYPE_E2PROM;
+ stI2cDev.Port = EEPROM_I2C_PORT;
+ stI2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM;
+ stI2cDev.Socket = 0;
+ RemainderMacOffset = I2cOffset % EEPROM_PAGE_SIZE;
+ LessSizeOfPage = EEPROM_PAGE_SIZE - RemainderMacOffset;
+ //The length of NIC_MAC_ADDRESS is 10 bytes long,
+ //It surly less than EEPROM page size, so we could
+ //code as bellow, check the address whether across the page boundary,
+ //and split the data when across page boundary.
+ if (sizeof(NIC_MAC_ADDRESS) <= LessSizeOfPage) {
+ Status = I2CRead(&stI2cDev, I2cOffset, sizeof(NIC_MAC_ADDRESS), (UINT8 *)&stMacDesc);
+ } else {
+ Status = I2CRead(&stI2cDev, I2cOffset, LessSizeOfPage, (UINT8 *)&stMacDesc);
+ if (!(EFI_ERROR(Status))) {
+ Status |= I2CRead(
+ &stI2cDev,
+ I2cOffset + LessSizeOfPage,
+ sizeof(NIC_MAC_ADDRESS) - LessSizeOfPage,
+ (UINT8 *)&stMacDesc + LessSizeOfPage
+ );
+ }
+ }
+ if (EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2cRead failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status));
+ return Status;
+ }
+
+ crc16 = make_crc_checksum((UINT8 *)&(stMacDesc.MacLen), sizeof(stMacDesc.MacLen) + sizeof(stMacDesc.Mac));
+ if ((crc16 != stMacDesc.Crc16) || (0 == crc16))
+ {
+ return EFI_NOT_FOUND;
+ }
+
+ gBS->CopyMem((VOID *)(pucAddr), (VOID *)(stMacDesc.Mac), MAC_ADDR_LEN);
+
+
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS OemSetMacE2prom(IN UINT32 Port, IN UINT8 *pucAddr)
+{
+ I2C_DEVICE stI2cDev = {0};
+ EFI_STATUS Status;
+ UINT16 I2cOffset;
+ NIC_MAC_ADDRESS stMacDesc = {0};
+
+
+ stMacDesc.MacLen = MAC_ADDR_LEN;
+ UINT16 RemainderMacOffset;
+ UINT16 LessSizeOfPage;
+ gBS->CopyMem((VOID *)(stMacDesc.Mac), (VOID *)pucAddr, MAC_ADDR_LEN);
+
+ stMacDesc.Crc16 = make_crc_checksum((UINT8 *)&(stMacDesc.MacLen), sizeof(stMacDesc.MacLen) + MAC_ADDR_LEN);
+
+ Status = I2CInit(0, EEPROM_I2C_PORT, Normal);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2CInit failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status));
+ return Status;
+ }
+
+ I2cOffset = I2C_OFFSET_EEPROM_ETH0 + (Port * sizeof(NIC_MAC_ADDRESS));
+
+ stI2cDev.DeviceType = DEVICE_TYPE_E2PROM;
+ stI2cDev.Port = EEPROM_I2C_PORT;
+ stI2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM;
+ stI2cDev.Socket = 0;
+ RemainderMacOffset = I2cOffset % EEPROM_PAGE_SIZE;
+ LessSizeOfPage = EEPROM_PAGE_SIZE - RemainderMacOffset;
+ //The length of NIC_MAC_ADDRESS is 10 bytes long,
+ //It surly less than EEPROM page size, so we could
+ //code as bellow, check the address whether across the page boundary,
+ //and split the data when across page boundary.
+ if (sizeof(NIC_MAC_ADDRESS) <= LessSizeOfPage) {
+ Status = I2CWrite(&stI2cDev, I2cOffset, sizeof(NIC_MAC_ADDRESS), (UINT8 *)&stMacDesc);
+ } else {
+ Status = I2CWrite(&stI2cDev, I2cOffset, LessSizeOfPage, (UINT8 *)&stMacDesc);
+ if (!(EFI_ERROR(Status))) {
+ Status |= I2CWrite(
+ &stI2cDev,
+ I2cOffset + LessSizeOfPage,
+ sizeof(NIC_MAC_ADDRESS) - LessSizeOfPage,
+ (UINT8 *)&stMacDesc + LessSizeOfPage
+ );
+ }
+ }
+ if (EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2cWrite failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status));
+ return Status;
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI OemGetMac2P (
+ IN OUT EFI_MAC_ADDRESS *Mac,
+ IN UINTN Port
+ )
+{
+ EFI_STATUS Status;
+
+ if (NULL == Mac)
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Mac buffer is null!\n", __FUNCTION__, __LINE__));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = OemGetMacE2prom(Port, Mac->Addr);
+ if ((EFI_ERROR(Status)))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Get mac failed!\n", __FUNCTION__, __LINE__));
+
+ Mac->Addr[0] = 0x00;
+ Mac->Addr[1] = 0x18;
+ Mac->Addr[2] = 0x82;
+ Mac->Addr[3] = 0x2F;
+ Mac->Addr[4] = 0x02;
+ Mac->Addr[5] = Port;
+ return Status;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI OemSetMac2P (
+ IN EFI_MAC_ADDRESS *Mac,
+ IN UINTN Port
+ )
+{
+ EFI_STATUS Status;
+
+ if (NULL == Mac)
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Mac buffer is null!\n", __FUNCTION__, __LINE__));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = OemSetMacE2prom(Port, Mac->Addr);
+ if ((EFI_ERROR(Status)))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Set mac failed!\n", __FUNCTION__, __LINE__));
+ return Status;
+ }
+
+ return EFI_SUCCESS;
+}
+
+HISI_BOARD_NIC_PROTOCOL mHisiBoardNicProtocol2P = {
+ .GetMac = OemGetMac2P,
+ .SetMac = OemSetMac2P,
+};
+
+VOID OemFeedbackXGeStatus(BOOLEAN IsLinkup, BOOLEAN IsActOK, UINT32 port)
+{
+ UINT8 CpldValue = 0;
+ UINTN RegOffset = 0x10 + (UINTN)port * 4;
+
+ if (port > 2)
+ {
+ return;
+ }
+
+ if (IsLinkup)
+ {
+ CpldValue = ReadCpldReg(RegOffset);
+ CpldValue |= BIT2;
+ WriteCpldReg(RegOffset, CpldValue);
+ }
+ else
+ {
+ CpldValue = ReadCpldReg(RegOffset);
+ CpldValue &= ~((UINT8)BIT2);
+ WriteCpldReg(RegOffset, CpldValue);
+ }
+
+ if (IsActOK)
+ {
+ CpldValue = ReadCpldReg(RegOffset);
+ CpldValue |= BIT4;
+ WriteCpldReg(RegOffset, CpldValue);
+ }
+ else
+ {
+ CpldValue = ReadCpldReg(RegOffset);
+ CpldValue &= ~((UINT8)BIT4);
+ WriteCpldReg(RegOffset, CpldValue);
+ }
+}
+
+HISI_BOARD_XGE_STATUS_PROTOCOL mHisiBoardXgeStatusProtocol2p = {
+ .FeedbackXgeStatus = OemFeedbackXGeStatus,
+};
+
+
+EFI_STATUS
+EFIAPI
+OemNicConfigEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ Status = gBS->InstallProtocolInterface(
+ &ImageHandle,
+ &gHisiBoardNicProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &mHisiBoardNicProtocol2P
+ );
+
+ if(EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Install Protocol failed %r\n", __FUNCTION__, __LINE__, Status));
+ return Status;
+ }
+
+ Status = gBS->InstallProtocolInterface(
+ &ImageHandle,
+ &gHisiBoardXgeStatusProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &mHisiBoardXgeStatusProtocol2p
+ );
+
+ if(EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Install Protocol failed %r\n", __FUNCTION__, __LINE__, Status));
+ return Status;
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf b/Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf new file mode 100644 index 0000000000..ee5596a4ce --- /dev/null +++ b/Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf @@ -0,0 +1,52 @@ +#/** @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = OemNicConfigPangea
+ FILE_GUID = 3A23A929-1F38-4d04-8A01-38AD993EB2CE
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = OemNicConfigEntry
+
+[Sources.common]
+ OemNicConfig2P.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/Hisilicon/HisiPkg.dec
+
+[Protocols]
+ gHisiBoardNicProtocolGuid ##Produce
+ gHisiBoardXgeStatusProtocolGuid
+
+[LibraryClasses]
+ CpldIoLib
+ UefiDriverEntryPoint
+ UefiBootServicesTableLib
+ DebugLib
+ IoLib
+ TimerLib
+ I2CLib
+ PcdLib
+
+[FixedPcd]
+
+[Depex]
+ TRUE
+
+[BuildOptions]
+
diff --git a/Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.c b/Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.c new file mode 100644 index 0000000000..8bfac2d99f --- /dev/null +++ b/Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.c @@ -0,0 +1,437 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiLib.h>
+#include <Protocol/PciPlatform.h>
+#include <Protocol/PciIo.h>
+#include <Protocol/FirmwareVolume2.h>
+#include <IndustryStandard/Pci22.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/MemoryAllocationLib.h>
+
+//
+// Global variables for Option ROMs
+//
+#define NULL_ROM_FILE_GUID \
+ { \
+ 0x00000000, 0x0000, 0x0000, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} \
+ }
+
+#define SAS_OPTION_ROM_FILE_GUID \
+{ 0xb47533c7, 0xcc78, 0x4e5e, {0x94, 0x33, 0xf2, 0x8b, 0x16, 0xcd, 0x66, 0xdb}}
+
+#define SAS3108_OPTION_ROM_FILE_GUID \
+{ 0xb47533c8, 0xcc78, 0x4e5e, {0x94, 0x33, 0xf2, 0x8b, 0x16, 0xcd, 0x66, 0xd8}}
+
+#define INVALID 0xBD
+
+
+typedef struct {
+ EFI_HANDLE PciPlatformHandle;
+ EFI_PCI_PLATFORM_PROTOCOL PciPlatform;
+} PCI_PLATFORM_PRIVATE_DATA;
+
+
+#define MAX_ROM_NUMBER 2
+
+
+typedef struct {
+ EFI_GUID FileName;
+ UINTN Segment;
+ UINTN Bus;
+ UINTN Device;
+ UINTN Function;
+ UINT16 VendorId;
+ UINT16 DeviceId;
+} PCI_OPTION_ROM_TABLE;
+
+typedef struct {
+ UINTN RomSize;
+ VOID *RomBase;
+} OPTION_ROM_INFO;
+
+PCI_PLATFORM_PRIVATE_DATA *mPciPrivateData = NULL;
+
+PCI_OPTION_ROM_TABLE mPciOptionRomTable[] = {
+ {
+ SAS_OPTION_ROM_FILE_GUID,
+ 0,
+ 2,
+ 0,
+ 0,
+ 0x1000,
+ 0x0097
+ },
+ {
+ SAS3108_OPTION_ROM_FILE_GUID,
+ 0,
+ 1,
+ 0,
+ 0,
+ 0x1000,
+ 0x005D
+ },
+
+ //
+ // End of OptionROM Entries
+ //
+ {
+ NULL_ROM_FILE_GUID, // Guid
+ 0, // Segment
+ 0, // Bus Number
+ 0, // Device Number
+ 0, // Function Number
+ 0xffff, // Vendor ID
+ 0xffff // Device ID
+ }
+};
+
+EFI_STATUS
+EFIAPI
+GetPlatformPolicy (
+ IN CONST EFI_PCI_PLATFORM_PROTOCOL *This,
+ OUT EFI_PCI_PLATFORM_POLICY *PciPolicy
+ )
+/*++
+
+Routine Description:
+
+ Set the PciPolicy as EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_NO_ALIAS.
+
+Arguments:
+
+ This - The pointer to the Protocol itself.
+ PciPolicy - the returned Policy.
+
+Returns:
+
+ EFI_UNSUPPORTED - Function not supported.
+ EFI_INVALID_PARAMETER - Invalid PciPolicy value.
+
+--*/
+{
+ if (PciPolicy == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+GetRawImage (
+ IN EFI_GUID *NameGuid,
+ IN OUT VOID **Buffer,
+ IN OUT UINTN *Size
+ )
+/*++
+
+Routine Description:
+
+ Get an indicated image in raw sections.
+
+Arguments:
+
+ NameGuid - NameGuid of the image to get.
+ Buffer - Buffer to store the image get.
+ Size - size of the image get.
+
+Returns:
+
+ EFI_NOT_FOUND - Could not find the image.
+ EFI_LOAD_ERROR - Error occurred during image loading.
+ EFI_SUCCESS - Image has been successfully loaded.
+
+--*/
+{
+ EFI_STATUS Status;
+ EFI_HANDLE *HandleBuffer;
+ UINTN HandleCount;
+ UINTN Index;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;
+ UINT32 AuthenticationStatus;
+
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiFirmwareVolume2ProtocolGuid,
+ NULL,
+ &HandleCount,
+ &HandleBuffer
+ );
+ if (EFI_ERROR (Status) || HandleCount == 0) {
+ return EFI_NOT_FOUND;
+ }
+ //
+ // Find desired image in all Fvs
+ //
+ for (Index = 0; Index < HandleCount; Index++) {
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ &gEfiFirmwareVolume2ProtocolGuid,
+ (VOID **)&Fv
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_LOAD_ERROR;
+ }
+ //
+ // Try a raw file
+ //
+ *Buffer = NULL;
+ *Size = 0;
+ Status = Fv->ReadSection (
+ Fv,
+ NameGuid,
+ EFI_SECTION_RAW,
+ 0,
+ Buffer,
+ Size,
+ &AuthenticationStatus
+ );
+
+ if (!EFI_ERROR (Status)) {
+ break;
+ }
+ }
+
+ if (Index >= HandleCount) {
+ return EFI_NOT_FOUND;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+GetPciRom (
+ IN CONST EFI_PCI_PLATFORM_PROTOCOL *This,
+ IN EFI_HANDLE PciHandle,
+ OUT VOID **RomImage,
+ OUT UINTN *RomSize
+ )
+/*++
+
+Routine Description:
+
+ Return a PCI ROM image for the onboard device represented by PciHandle.
+
+Arguments:
+
+ This - Protocol instance pointer.
+ PciHandle - PCI device to return the ROM image for.
+ RomImage - PCI Rom Image for onboard device.
+ RomSize - Size of RomImage in bytes.
+
+Returns:
+
+ EFI_SUCCESS - RomImage is valid.
+ EFI_NOT_FOUND - No RomImage.
+
+--*/
+{
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT16 VendorId;
+ UINT16 DeviceId;
+ UINTN TableIndex;
+ UINTN RomImageNumber;
+ OPTION_ROM_INFO OptionRominfo[MAX_ROM_NUMBER];
+
+ Status = gBS->HandleProtocol (
+ PciHandle,
+ &gEfiPciIoProtocolGuid,
+ (VOID **) &PciIo
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_FOUND;
+ }
+
+ (VOID)PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_VENDOR_ID_OFFSET, 1, &VendorId);
+ (VOID)PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_DEVICE_ID_OFFSET, 1, &DeviceId);
+
+ //
+ // Loop through table of video option rom descriptions
+ //
+ RomImageNumber = 0;
+ for (TableIndex = 0; mPciOptionRomTable[TableIndex].VendorId != 0xffff; TableIndex++) {
+ //
+ // See if the PCI device specified by PciHandle matches at device in mPciOptionRomTable
+ //
+ if ((VendorId != mPciOptionRomTable[TableIndex].VendorId)
+ || (DeviceId != mPciOptionRomTable[TableIndex].DeviceId)
+ )
+ {
+ continue;
+ }
+
+ Status = GetRawImage (
+ &mPciOptionRomTable[TableIndex].FileName,
+ &(OptionRominfo[RomImageNumber].RomBase),
+ &(OptionRominfo[RomImageNumber].RomSize)
+ );
+
+ if (EFI_ERROR (Status)) {
+ continue;
+ } else {
+ RomImageNumber++;
+ if (RomImageNumber == MAX_ROM_NUMBER) {
+ break;
+ }
+ }
+ }
+
+ if (RomImageNumber == 0) {
+
+ return EFI_NOT_FOUND;
+
+ } else {
+ *RomImage = OptionRominfo[RomImageNumber - 1].RomBase;
+ *RomSize = OptionRominfo[RomImageNumber - 1].RomSize;
+
+ if (RomImageNumber > 1) {
+ //
+ // More than one OPROM have been found!
+ //
+
+ }
+
+ return EFI_SUCCESS;
+ }
+}
+
+EFI_STATUS
+EFIAPI
+PlatformPrepController (
+ IN EFI_PCI_PLATFORM_PROTOCOL *This,
+ IN EFI_HANDLE HostBridge,
+ IN EFI_HANDLE RootBridge,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
+ IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase,
+ IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase
+ )
+/*++
+
+Routine Description:
+
+ The PlatformPrepController() function can be used to notify the platform driver so that
+ it can perform platform-specific actions. No specific actions are required.
+ Several notification points are defined at this time. More synchronization points may be
+ added as required in the future. The PCI bus driver calls the platform driver twice for
+ every PCI controller-once before the PCI Host Bridge Resource Allocation Protocol driver
+ is notified, and once after the PCI Host Bridge Resource Allocation Protocol driver has
+ been notified.
+ This member function may not perform any error checking on the input parameters. It also
+ does not return any error codes. If this member function detects any error condition, it
+ needs to handle those errors on its own because there is no way to surface any errors to
+ the caller.
+
+Arguments:
+
+ This - Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.
+ HostBridge - The associated PCI host bridge handle.
+ RootBridge - The associated PCI root bridge handle.
+ PciAddress - The address of the PCI device on the PCI bus.
+ Phase - The phase of the PCI controller enumeration.
+ ChipsetPhase - Defines the execution phase of the PCI chipset driver.
+
+Returns:
+
+ EFI_SUCCESS - The function completed successfully.
+ EFI_UNSUPPORTED - Not supported.
+
+--*/
+{
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+PhaseNotify (
+ IN EFI_PCI_PLATFORM_PROTOCOL *This,
+ IN EFI_HANDLE HostBridge,
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase,
+ IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase
+ )
+/*++
+
+Routine Description:
+
+ Perform initialization by the phase indicated.
+
+Arguments:
+
+ This - Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.
+ HostBridge - The associated PCI host bridge handle.
+ Phase - The phase of the PCI controller enumeration.
+ ChipsetPhase - Defines the execution phase of the PCI chipset driver.
+
+Returns:
+
+ EFI_SUCCESS - Must return with success.
+
+--*/
+{
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PciPlatformDriverEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+/*++
+
+Routine Description:
+ Main Entry point of the Pci Platform Driver.
+
+Arguments:
+
+ ImageHandle - Handle to the image.
+ SystemTable - Handle to System Table.
+
+Returns:
+
+ EFI_STATUS - Status of the function calling.
+
+--*/
+{
+ EFI_STATUS Status;
+ PCI_PLATFORM_PRIVATE_DATA *PciPrivateData;
+
+ PciPrivateData = AllocateZeroPool (sizeof (PCI_PLATFORM_PRIVATE_DATA));
+ mPciPrivateData = PciPrivateData;
+
+ mPciPrivateData->PciPlatform.PlatformNotify = PhaseNotify;
+ mPciPrivateData->PciPlatform.PlatformPrepController = PlatformPrepController;
+ mPciPrivateData->PciPlatform.GetPlatformPolicy = GetPlatformPolicy;
+ mPciPrivateData->PciPlatform.GetPciRom = GetPciRom;
+
+ //
+ // Install on a new handle
+ //
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &mPciPrivateData->PciPlatformHandle,
+ &gEfiPciPlatformProtocolGuid,
+ &mPciPrivateData->PciPlatform,
+ NULL
+ );
+
+ return Status;
+}
diff --git a/Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.h b/Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.h new file mode 100644 index 0000000000..a89f7c61b6 --- /dev/null +++ b/Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.h @@ -0,0 +1,180 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef PCI_PLATFORM_H_
+#define PCI_PLATFORM_H_
+
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiLib.h>
+#include <Protocol/PciPlatform.h>
+
+
+//
+// Global variables for Option ROMs
+//
+#define NULL_ROM_FILE_GUID \
+ { \
+ 0x00000000, 0x0000, 0x0000, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 \
+ }
+
+
+typedef struct {
+ EFI_GUID FileName;
+ UINTN Segment;
+ UINTN Bus;
+ UINTN Device;
+ UINTN Function;
+ UINT16 VendorId;
+ UINT16 DeviceId;
+} PCI_OPTION_ROM_TABLE;
+
+#define INVALID 0xBD
+
+
+typedef struct {
+ EFI_HANDLE PciPlatformHandle;
+ EFI_PCI_PLATFORM_PROTOCOL PciPlatform;
+} PCI_PLATFORM_PRIVATE_DATA;
+
+
+
+extern PCI_PLATFORM_PRIVATE_DATA mPciPrivateData;
+
+EFI_STATUS
+EFIAPI
+PhaseNotify (
+ IN EFI_PCI_PLATFORM_PROTOCOL *This,
+ IN EFI_HANDLE HostBridge,
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase,
+ IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase
+ )
+/*++
+
+Routine Description:
+
+ Perform initialization by the phase indicated.
+
+Arguments:
+
+ This - Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.
+ HostBridge - The associated PCI host bridge handle.
+ Phase - The phase of the PCI controller enumeration.
+ ChipsetPhase - Defines the execution phase of the PCI chipset driver.
+
+Returns:
+
+ EFI_SUCCESS - Must return with success.
+
+--*/
+;
+
+EFI_STATUS
+EFIAPI
+PlatformPrepController (
+ IN EFI_PCI_PLATFORM_PROTOCOL *This,
+ IN EFI_HANDLE HostBridge,
+ IN EFI_HANDLE RootBridge,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
+ IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase,
+ IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase
+ )
+/*++
+
+Routine Description:
+
+ The PlatformPrepController() function can be used to notify the platform driver so that
+ it can perform platform-specific actions. No specific actions are required.
+ Several notification points are defined at this time. More synchronization points may be
+ added as required in the future. The PCI bus driver calls the platform driver twice for
+ every PCI controller-once before the PCI Host Bridge Resource Allocation Protocol driver
+ is notified, and once after the PCI Host Bridge Resource Allocation Protocol driver has
+ been notified.
+ This member function may not perform any error checking on the input parameters. It also
+ does not return any error codes. If this member function detects any error condition, it
+ needs to handle those errors on its own because there is no way to surface any errors to
+ the caller.
+
+Arguments:
+
+ This - Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.
+ HostBridge - The associated PCI host bridge handle.
+ RootBridge - The associated PCI root bridge handle.
+ PciAddress - The address of the PCI device on the PCI bus.
+ Phase - The phase of the PCI controller enumeration.
+ ChipsetPhase - Defines the execution phase of the PCI chipset driver.
+
+Returns:
+
+ EFI_SUCCESS - The function completed successfully.
+
+--*/
+;
+
+EFI_STATUS
+EFIAPI
+GetPlatformPolicy (
+ IN EFI_PCI_PLATFORM_PROTOCOL *This,
+ OUT EFI_PCI_PLATFORM_POLICY *PciPolicy
+ )
+/*++
+
+Routine Description:
+
+ Set the PciPolicy as EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_NO_ALIAS.
+
+Arguments:
+
+ This - The pointer to the Protocol itself.
+ PciPolicy - the returned Policy.
+
+Returns:
+
+ EFI_UNSUPPORTED - Function not supported.
+ EFI_INVALID_PARAMETER - Invalid PciPolicy value.
+
+--*/
+;
+
+EFI_STATUS
+EFIAPI
+GetPciRom (
+ IN EFI_PCI_PLATFORM_PROTOCOL *This,
+ IN EFI_HANDLE PciHandle,
+ OUT VOID **RomImage,
+ OUT UINTN *RomSize
+ )
+/*++
+
+Routine Description:
+
+ Return a PCI ROM image for the onboard device represented by PciHandle.
+
+Arguments:
+
+ This - Protocol instance pointer.
+ PciHandle - PCI device to return the ROM image for.
+ RomImage - PCI Rom Image for onboard device.
+ RomSize - Size of RomImage in bytes.
+
+Returns:
+
+ EFI_SUCCESS - RomImage is valid.
+ EFI_NOT_FOUND - No RomImage.
+
+--*/
+;
+
+#endif
diff --git a/Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf b/Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf new file mode 100644 index 0000000000..8b170d2654 --- /dev/null +++ b/Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf @@ -0,0 +1,53 @@ +#/** @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PciPlatform
+ FILE_GUID = E2441B64-7EF4-41fe-B3A3-8CAA7F8D3017
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PciPlatformDriverEntry
+
+[sources.common]
+ PciPlatform.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+ Silicon/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ UefiLib
+ BaseLib
+ DebugLib
+ ArmLib
+ IoLib
+ MemoryAllocationLib
+
+[Protocols]
+ gEfiPciPlatformProtocolGuid
+ gEfiFirmwareVolume2ProtocolGuid
+ gEfiPciIoProtocolGuid
+
+[Pcd]
+
+[FixedPcd]
+
+[Depex]
+ TRUE
+
|