diff options
Diffstat (limited to 'Platform/Hisilicon/D03/Library')
11 files changed, 1997 insertions, 0 deletions
diff --git a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClock.h b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClock.h new file mode 100644 index 0000000000..d1e6c41dd7 --- /dev/null +++ b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClock.h @@ -0,0 +1,178 @@ +/** @file
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+**/
+
+
+#ifndef __DS3231_REAL_TIME_CLOCK_H__
+#define __DS3231_REAL_TIME_CLOCK_H__
+
+#define DS3231_REGADDR_SECONDS 0x00
+#define DS3231_REGADDR_MIUTES 0x01
+#define DS3231_REGADDR_HOURS 0x02
+#define DS3231_REGADDR_DAY 0x03
+#define DS3231_REGADDR_DATE 0x04
+#define DS3231_REGADDR_MONTH 0x05
+#define DS3231_REGADDR_YEAR 0x06
+#define DS3231_REGADDR_ALARM1SEC 0x07
+#define DS3231_REGADDR_ALARM1MIN 0x08
+#define DS3231_REGADDR_ALARM1HOUR 0x09
+#define DS3231_REGADDR_ALARM1DAY 0x0A
+#define DS3231_REGADDR_ALARM2MIN 0x0B
+#define DS3231_REGADDR_ALARM2HOUR 0x0C
+#define DS3231_REGADDR_ALARM2DAY 0x0D
+#define DS3231_REGADDR_CONTROL 0x0E
+#define DS3231_REGADDR_STATUS 0x0F
+#define DS3231_REGADDR_AGOFFSET 0x10
+#define DS3231_REGADDR_TEMPMSB 0x11
+#define DS3231_REGADDR_TEMPLSB 0x12
+
+
+typedef union {
+ struct{
+ UINT8 A1IE:1;
+ UINT8 A2IE:1;
+ UINT8 INTCN:1;
+ UINT8 RSV:2;
+ UINT8 CONV:1;
+ UINT8 BBSQW:1;
+ UINT8 EOSC_N:1;
+ }bits;
+ UINT8 u8;
+}RTC_DS3231_CONTROL;
+
+typedef union {
+ struct{
+ UINT8 A1F:1;
+ UINT8 A2F:1;
+ UINT8 BSY:1;
+ UINT8 EN32KHZ:2;
+ UINT8 Rsv:3;
+ UINT8 OSF:1;
+ }bits;
+ UINT8 u8;
+}RTC_DS3231_STATUS;
+
+
+typedef union {
+ struct{
+ UINT8 Data:7;
+ UINT8 Sign:1;
+ }bits;
+ UINT8 u8;
+}RTC_DS3231_AGOFFSET;
+
+typedef union {
+ struct{
+ UINT8 Data:7;
+ UINT8 Sign:1;
+ }bits;
+ UINT8 u8;
+}RTC_DS3231_TEMPMSB;
+
+
+typedef union {
+ struct{
+ UINT8 Rsv:6;
+ UINT8 Data:2;
+ }bits;
+ UINT8 u8;
+}RTC_DS3231_TEMPLSB;
+
+typedef union {
+ struct{
+ UINT8 Seconds:4;
+ UINT8 Seconds10:3;
+ UINT8 Rsv:1;
+ }bits;
+ UINT8 u8;
+}RTC_DS3231_SECONDS;
+
+typedef union {
+ struct{
+ UINT8 Minutes:4;
+ UINT8 Minutes10:3;
+ UINT8 Rsv:1;
+ }bits;
+ UINT8 u8;
+}RTC_DS3231_MINUTES;
+
+typedef union {
+ struct{
+ UINT8 Hour:4;
+ UINT8 Hours10:1;
+ UINT8 PM_20Hours:1;
+ UINT8 Hour24_n:1;
+ UINT8 Rsv:1;
+ }bits;
+ UINT8 u8;
+}RTC_DS3231_HOURS;
+
+typedef union {
+ struct{
+ UINT8 Day:3;
+ UINT8 Rsv:5;
+ }bits;
+ UINT8 u8;
+}RTC_DS3231_DAY;
+
+typedef union {
+ struct{
+ UINT8 Month:4;
+ UINT8 Month10:1;
+ UINT8 Rsv:2;
+ UINT8 Century:1;
+ }bits;
+ UINT8 u8;
+}RTC_DS3231_MONTH;
+
+typedef union {
+ struct{
+ UINT8 Year:4;
+ UINT8 Year10:4;
+ }bits;
+ UINT8 u8;
+}RTC_DS3231_YEAR;
+
+typedef union {
+ struct{
+ UINT8 Seconds:4;
+ UINT8 Seconds10:3;
+ UINT8 A1M1:1;
+ }bits;
+ UINT8 u8;
+}RTC_DS3231_ALARM1SEC;
+
+typedef union {
+ struct{
+ UINT8 Minutes:4;
+ UINT8 Minutes10:3;
+ UINT8 A1M2:1;
+ }bits;
+ UINT8 u8;
+}RTC_DS3231_ALARM1MIN;
+
+typedef union {
+ struct{
+ UINT8 Hour:4;
+ UINT8 Hours10:1;
+ UINT8 PM_20Hours:1;
+ UINT8 Hours24:1;
+ UINT8 A1M3:1;
+ }bits;
+ UINT8 u8;
+}RTC_DS3231_ALARM1HOUR;
+
+#endif
diff --git a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c new file mode 100644 index 0000000000..07fa52aa78 --- /dev/null +++ b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c @@ -0,0 +1,504 @@ +/** @file
+ Implement EFI RealTimeClock runtime services via RTC Lib.
+
+ Currently this driver does not support runtime virtual calling.
+
+ Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+
+**/
+
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+// Use EfiAtRuntime to check stage
+#include <Library/UefiRuntimeLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/TimerLib.h>
+#include <Library/TimeBaseLib.h>
+#include <Protocol/RealTimeClock.h>
+#include <Library/I2CLib.h>
+#include "DS3231RealTimeClock.h"
+#include <Library/CpldD03.h>
+#include <Library/CpldIoLib.h>
+
+extern I2C_DEVICE gDS3231RtcDevice;
+
+STATIC BOOLEAN mDS3231Initialized = FALSE;
+
+EFI_STATUS
+IdentifyDS3231 (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ Status = EFI_SUCCESS;
+ return Status;
+}
+
+EFI_STATUS
+SwitchRtcI2cChannelAndLock (
+ VOID
+ )
+{
+ UINT8 Temp;
+ UINT8 Count;
+
+ for (Count = 0; Count < 20; Count++) {
+ Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG);
+
+ if ((Temp & BMC_I2C_STATUS) != 0) {
+ //The I2C channel is shared with BMC,
+ //Check if BMC has taken ownership of I2C.
+ //If so, wait 30ms, then try again.
+ //If not, start using I2C.
+ //And the CPLD_I2C_SWITCH_FLAG will be set to CPU_GET_I2C_CONTROL
+ //BMC will check this flag to decide to use I2C or not.
+ MicroSecondDelay (30000);
+ continue;
+ }
+
+ Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG);
+ Temp = Temp | CPU_GET_I2C_CONTROL;
+ WriteCpldReg (CPLD_I2C_SWITCH_FLAG, Temp);
+
+ //This is empirical value,give cpld some time to make sure the
+ //value is wrote in
+ MicroSecondDelay (2);
+ Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG);
+
+ if ((Temp & CPU_GET_I2C_CONTROL) == CPU_GET_I2C_CONTROL) {
+ return EFI_SUCCESS;
+ }
+
+ //There need 30ms to keep consistent with the previous loops if the CPU failed
+ //to get control of I2C
+ MicroSecondDelay (30000);
+ }
+
+ Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG);
+ Temp = Temp & ~CPU_GET_I2C_CONTROL;
+ WriteCpldReg (CPLD_I2C_SWITCH_FLAG, Temp);
+
+ return EFI_NOT_READY;
+}
+
+
+EFI_STATUS
+InitializeDS3231 (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ I2C_DEVICE Dev;
+ RTC_DS3231_CONTROL Temp;
+ RTC_DS3231_HOURS Hours;
+
+ // Prepare the hardware
+ (VOID)IdentifyDS3231();
+
+ (VOID) CopyMem(&Dev, &gDS3231RtcDevice, sizeof(Dev));
+
+ Status = I2CInit(Dev.Socket,Dev.Port,Normal);
+ if (EFI_ERROR (Status)) {
+ goto EXIT;
+ }
+ // Ensure interrupts are masked. We do not want RTC interrupts in UEFI
+ Status = I2CRead(&Dev,DS3231_REGADDR_CONTROL,1,&Temp.u8);
+ if (EFI_ERROR (Status)) {
+ goto EXIT;
+ }
+ Temp.bits.INTCN = 0;
+ Status = I2CWrite(&Dev,DS3231_REGADDR_CONTROL,1,&Temp.u8);
+ if (EFI_ERROR (Status)) {
+ goto EXIT;
+ }
+
+ MicroSecondDelay(2000);
+ Status = I2CRead(&Dev,DS3231_REGADDR_HOURS,1,&Hours.u8);
+ if (EFI_ERROR (Status)) {
+ goto EXIT;
+ }
+ Hours.bits.Hour24_n = 0;
+ Status = I2CWrite(&Dev,DS3231_REGADDR_HOURS,1,&Hours.u8);
+ if (EFI_ERROR (Status)) {
+ goto EXIT;
+ }
+
+
+ mDS3231Initialized = TRUE;
+
+ EXIT:
+ return Status;
+}
+
+/**
+ Returns the current time and date information, and the time-keeping capabilities
+ of the hardware platform.
+
+ @param Time A pointer to storage to receive a snapshot of the current time.
+ @param Capabilities An optional pointer to a buffer to receive the real time clock
+ device's capabilities.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER Time is NULL.
+ @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.
+ @retval EFI_SECURITY_VIOLATION The time could not be retrieved due to an authentication failure.
+**/
+EFI_STATUS
+EFIAPI
+LibGetTime (
+ OUT EFI_TIME *Time,
+ OUT EFI_TIME_CAPABILITIES *Capabilities
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ UINT8 Temp;
+ UINT8 BaseHour = 0;
+
+ UINT16 BaseYear = 1900;
+
+ I2C_DEVICE Dev;
+
+ // Ensure Time is a valid pointer
+ if (NULL == Time) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = SwitchRtcI2cChannelAndLock();
+ if(EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // Initialize the hardware if not already done
+ if (!mDS3231Initialized) {
+ Status = InitializeDS3231 ();
+ if (EFI_ERROR (Status)) {
+ Status = EFI_NOT_READY;
+ goto GExit;
+ }
+ }
+
+ (VOID) CopyMem(&Dev, &gDS3231RtcDevice, sizeof(Dev));
+
+ Status |= I2CRead(&Dev,DS3231_REGADDR_MONTH,1,&Temp);
+
+ Time->Month = ((Temp>>4)&1)*10+(Temp&0x0F);
+
+
+ if(Temp&0x80){
+ BaseYear = 2000;
+ }
+
+ Status |= I2CRead(&Dev,DS3231_REGADDR_YEAR,1,&Temp);
+
+ Time->Year = BaseYear+(Temp>>4) *10 + (Temp&0x0F);
+
+ Status |= I2CRead(&Dev,DS3231_REGADDR_DATE,1,&Temp);
+
+ Time->Day = ((Temp>>4)&3) *10 + (Temp&0x0F);
+
+ Status |= I2CRead(&Dev,DS3231_REGADDR_HOURS,1,&Temp);
+
+ BaseHour = 0;
+ if((Temp&0x30) == 0x30){
+ Status = EFI_DEVICE_ERROR;
+ goto GExit;
+ }else if(Temp&0x20){
+ BaseHour = 20;
+ }else if(Temp&0x10){
+ BaseHour = 10;
+ }
+ Time->Hour = BaseHour + (Temp&0x0F);
+
+ Status |= I2CRead(&Dev,DS3231_REGADDR_MIUTES,1,&Temp);
+
+ Time->Minute = ((Temp>>4)&7) * 10 + (Temp&0x0F);
+
+ Status |= I2CRead(&Dev,DS3231_REGADDR_SECONDS,1,&Temp);
+
+ Time->Second = (Temp>>4) * 10 + (Temp&0x0F);
+
+ Time->Nanosecond = 0;
+ Time->Daylight = 0;
+ Time->TimeZone = EFI_UNSPECIFIED_TIMEZONE;
+
+ if((EFI_ERROR(Status)) || (!IsTimeValid(Time)) || ((Time->Year - BaseYear) > 99)) {
+ Status = EFI_UNSUPPORTED;
+ }
+
+GExit:
+ Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG);
+ Temp = Temp & ~CPU_GET_I2C_CONTROL;
+ WriteCpldReg (CPLD_I2C_SWITCH_FLAG, Temp);
+
+ return Status;
+
+}
+
+
+/**
+ Sets the current local time and date information.
+
+ @param Time A pointer to the current time.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The time could not be set due due to hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetTime (
+ IN EFI_TIME *Time
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ I2C_DEVICE Dev;
+ UINT8 Temp;
+
+ UINT16 BaseYear = 1900;
+
+
+
+ // Check the input parameters are within the range specified by UEFI
+ if(!IsTimeValid(Time)){
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = SwitchRtcI2cChannelAndLock();
+ if(EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // Initialize the hardware if not already done
+ if (!mDS3231Initialized) {
+ Status = InitializeDS3231 ();
+ if (EFI_ERROR (Status)) {
+ goto EXIT;
+ }
+ }
+
+ (VOID) CopyMem(&Dev, &gDS3231RtcDevice, sizeof(Dev));
+
+ Temp = ((Time->Second/10)<<4) | (Time->Second%10);
+ MicroSecondDelay(1000);
+ Status = I2CWrite(&Dev,DS3231_REGADDR_SECONDS,1,&Temp);
+ if(EFI_ERROR (Status)){
+ goto EXIT;
+ }
+
+ Temp = ((Time->Minute/10)<<4) | (Time->Minute%10);
+ MicroSecondDelay(1000);
+ Status = I2CWrite(&Dev,DS3231_REGADDR_MIUTES,1,&Temp);
+ if(EFI_ERROR (Status)){
+ goto EXIT;
+ }
+
+ Temp = 0;
+ if(Time->Hour > 19){
+ Temp = 2;
+ } else if(Time->Hour > 9){
+ Temp = 1;
+ }
+
+ Temp = (Temp << 4) | (Time->Hour%10);
+ MicroSecondDelay(1000);
+ Status = I2CWrite(&Dev,DS3231_REGADDR_HOURS,1,&Temp);
+ if(EFI_ERROR (Status)){
+ goto EXIT;
+ }
+
+ Temp = ((Time->Day/10)<<4) | (Time->Day%10);
+ MicroSecondDelay(1000);
+ Status = I2CWrite(&Dev,DS3231_REGADDR_DATE,1,&Temp);
+ if(EFI_ERROR (Status)){
+ goto EXIT;
+ }
+
+
+ Temp = 0;
+ if(Time->Year >= 2000){
+ Temp = 0x8;
+ BaseYear = 2000;
+ }
+
+ if(Time->Month > 9){
+ Temp |= 0x1;
+ }
+ Temp = (Temp<<4) | (Time->Month%10);
+ MicroSecondDelay(1000);
+ Status = I2CWrite(&Dev,DS3231_REGADDR_MONTH,1,&Temp);
+ if(EFI_ERROR (Status)){
+ goto EXIT;
+ }
+
+ Temp = (((Time->Year-BaseYear)/10)<<4) | (Time->Year%10);
+ MicroSecondDelay(1000);
+ Status = I2CWrite(&Dev,DS3231_REGADDR_YEAR,1,&Temp);
+ if(EFI_ERROR (Status)){
+ goto EXIT;
+ }
+
+ EXIT:
+
+ Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG);
+ Temp = Temp & ~CPU_GET_I2C_CONTROL;
+ WriteCpldReg (CPLD_I2C_SWITCH_FLAG, Temp);
+
+ return Status;
+}
+
+
+/**
+ Returns the current wakeup alarm clock setting.
+
+ @param Enabled Indicates if the alarm is currently enabled or disabled.
+ @param Pending Indicates if the alarm signal is pending and requires acknowledgement.
+ @param Time The current alarm setting.
+
+ @retval EFI_SUCCESS The alarm settings were returned.
+ @retval EFI_INVALID_PARAMETER Any parameter is NULL.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetWakeupTime (
+ OUT BOOLEAN *Enabled,
+ OUT BOOLEAN *Pending,
+ OUT EFI_TIME *Time
+ )
+{
+ // Not a required feature
+ return EFI_UNSUPPORTED;
+}
+
+
+/**
+ Sets the system wakeup alarm clock time.
+
+ @param Enabled Enable or disable the wakeup alarm.
+ @param Time If Enable is TRUE, the time to set the wakeup alarm for.
+
+ @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If
+ Enable is FALSE, then the wakeup alarm was disabled.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetWakeupTime (
+ IN BOOLEAN Enabled,
+ OUT EFI_TIME *Time
+ )
+{
+ // Not a required feature
+ return EFI_UNSUPPORTED;
+}
+
+
+
+/**
+ This is the declaration of an EFI image entry point. This can be the entry point to an application
+ written to this specification, an EFI boot service driver, or an EFI runtime driver.
+
+ @param ImageHandle Handle that identifies the loaded image.
+ @param SystemTable System Table for this image.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+LibRtcInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+
+
+ EFI_TIME EfiTime;
+
+ // Setup the setters and getters
+ gRT->GetTime = LibGetTime;
+ gRT->SetTime = LibSetTime;
+ gRT->GetWakeupTime = LibGetWakeupTime;
+ gRT->SetWakeupTime = LibSetWakeupTime;
+
+
+ (VOID)gRT->GetTime (&EfiTime, NULL);
+ if((EfiTime.Year < 2015) || (EfiTime.Year > 2099)){
+ EfiTime.Year = 2015;
+ EfiTime.Month = 1;
+ EfiTime.Day = 1;
+ EfiTime.Hour = 0;
+ EfiTime.Minute = 0;
+ EfiTime.Second = 0;
+ EfiTime.Nanosecond = 0;
+ Status = gRT->SetTime(&EfiTime);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Status : %r\n", __FUNCTION__, __LINE__, Status));
+ }
+ }
+
+ // Install the protocol
+ Handle = NULL;
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Handle,
+ &gEfiRealTimeClockArchProtocolGuid, NULL,
+ NULL
+ );
+
+ return Status;
+}
+
+
+/**
+ Fixup internal data so that EFI can be call in virtual mode.
+ Call the passed in Child Notify event and convert any pointers in
+ lib to virtual mode.
+
+ @param[in] Event The Event that is being processed
+ @param[in] Context Event Context
+**/
+VOID
+EFIAPI
+LibRtcVirtualNotifyEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ //
+ // Only needed if you are going to support the OS calling RTC functions in virtual mode.
+ // You will need to call EfiConvertPointer (). To convert any stored physical addresses
+ // to virtual address. After the OS transitions to calling in virtual mode, all future
+ // runtime calls will be made in virtual mode.
+ //
+ return;
+}
diff --git a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf new file mode 100644 index 0000000000..319c35c724 --- /dev/null +++ b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf @@ -0,0 +1,48 @@ +#/** @file
+#
+# Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
+# Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = DS3231RealTimeClockLib
+ FILE_GUID = 470DFB96-E205-4515-A75E-2E60F853E79D
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RealTimeClockLib
+
+[Sources.common]
+ DS3231RealTimeClockLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ Platform/Hisilicon/D03/D03.dec
+ Silicon/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ IoLib
+ UefiLib
+ DebugLib
+ PcdLib
+ I2CLib
+ TimeBaseLib
+ TimerLib
+# Use EFiAtRuntime to check stage
+ UefiRuntimeLib
+ CpldIoLib
+
+[Pcd]
+
diff --git a/Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.c b/Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.c new file mode 100755 index 0000000000..d00cb9b2ab --- /dev/null +++ b/Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.c @@ -0,0 +1,487 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/ArmArchTimer.h>
+#include <Library/BaseLib.h>
+#include <libfdt.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/FdtUpdateLib.h>
+#include <PlatformArch.h>
+#include <Library/PcdLib.h>
+#include <Library/PlatformSysCtrlLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Protocol/HisiBoardNicProtocol.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/OemMiscLib.h>
+
+typedef union AA_DAW
+{
+ /* Define the struct bits */
+ struct
+ {
+ unsigned int sysdaw_id : 7 ; /* [6:0] */
+ unsigned int interleave_en : 1 ; /* [7] */
+ unsigned int sysdaw_size : 4 ; /* [11:8] */
+ unsigned int reserved : 4 ; /* [15:12] */
+ unsigned int sysdaw_addr : 16 ; /* [31:16] */
+ } bits;
+
+ /* Define an unsigned member */
+ unsigned int u32;
+
+} AA_DAW_U;
+
+
+
+MAC_ADDRESS gMacAddress[1];
+
+
+CHAR8 *EthName[8]=
+{
+ "ethernet@0","ethernet@1",
+ "ethernet@2","ethernet@3",
+ "ethernet@4","ethernet@5",
+ "ethernet@6","ethernet@7"
+};
+
+UINT8 DawNum[4] = {0, 0, 0, 0};
+PHY_MEM_REGION *NodemRegion[4] = {NULL, NULL, NULL, NULL};
+UINTN NumaPages[4] = {0, 0, 0, 0};
+
+CHAR8 *NumaNodeName[4]=
+{
+ "p0-ta","p0-tc",
+ "p1-ta","p1-tc",
+};
+
+STATIC
+BOOLEAN
+IsMemMapRegion (
+ IN EFI_MEMORY_TYPE MemoryType
+ )
+{
+ switch(MemoryType)
+ {
+ case EfiRuntimeServicesCode:
+ case EfiRuntimeServicesData:
+ case EfiConventionalMemory:
+ case EfiACPIReclaimMemory:
+ case EfiACPIMemoryNVS:
+ case EfiLoaderCode:
+ case EfiLoaderData:
+ case EfiBootServicesCode:
+ case EfiBootServicesData:
+ case EfiPalCode:
+ return TRUE;
+ default:
+ return FALSE;
+ }
+}
+
+
+EFI_STATUS
+GetMacAddress (UINT32 Port)
+{
+ EFI_MAC_ADDRESS Mac;
+ EFI_STATUS Status;
+ HISI_BOARD_NIC_PROTOCOL *OemNic = NULL;
+
+ Status = gBS->LocateProtocol(&gHisiBoardNicProtocolGuid, NULL, (VOID **)&OemNic);
+ if(EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] LocateProtocol failed %r\n", __FUNCTION__, __LINE__, Status));
+ return Status;
+ }
+
+ Status = OemNic->GetMac(&Mac, Port);
+ if(EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] GetMac failed %r\n", __FUNCTION__, __LINE__, Status));
+ return Status;
+ }
+
+ gMacAddress[0].data0=Mac.Addr[0];
+ gMacAddress[0].data1=Mac.Addr[1];
+ gMacAddress[0].data2=Mac.Addr[2];
+ gMacAddress[0].data3=Mac.Addr[3];
+ gMacAddress[0].data4=Mac.Addr[4];
+ gMacAddress[0].data5=Mac.Addr[5];
+ DEBUG((EFI_D_INFO, "Port%d:0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
+ Port,gMacAddress[0].data0,gMacAddress[0].data1,gMacAddress[0].data2,
+ gMacAddress[0].data3,gMacAddress[0].data4,gMacAddress[0].data5));
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+DelPhyhandleUpdateMacAddress(IN VOID* Fdt)
+{
+ UINT8 port;
+ INTN ethernetnode;
+ INTN node;
+ INTN Error;
+ struct fdt_property *m_prop;
+ int m_oldlen;
+ EFI_STATUS Status = EFI_SUCCESS;
+ EFI_STATUS GetMacStatus = EFI_SUCCESS;
+
+ node = fdt_subnode_offset(Fdt, 0, "soc");
+ if (node < 0)
+ {
+ DEBUG ((EFI_D_ERROR, "can not find soc root node\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+ else
+ {
+ for( port=0; port<8; port++ )
+ {
+ GetMacStatus= GetMacAddress(port);
+ ethernetnode = fdt_subnode_offset(Fdt, node,EthName[port]);
+ if(!EFI_ERROR(GetMacStatus))
+ {
+
+ if (ethernetnode < 0)
+ {
+ DEBUG ((EFI_D_WARN, "Can not find ethernet@%d node\n",port));
+ DEBUG ((EFI_D_WARN, "Suppose port %d is not enabled.\n", port));
+ continue;
+ }
+ m_prop = fdt_get_property_w(Fdt, ethernetnode, "local-mac-address", &m_oldlen);
+ if(m_prop)
+ {
+ Error = fdt_delprop(Fdt, ethernetnode, "local-mac-address");
+ if (Error)
+ {
+ DEBUG ((EFI_D_ERROR, "ERROR:fdt_delprop() Local-mac-address: %a\n", fdt_strerror (Error)));
+ Status = EFI_INVALID_PARAMETER;
+ }
+ Error = fdt_setprop(Fdt, ethernetnode, "local-mac-address",gMacAddress,sizeof(MAC_ADDRESS));
+ if (Error)
+ {
+ DEBUG ((EFI_D_ERROR, "ERROR:fdt_setprop():local-mac-address %a\n", fdt_strerror (Error)));
+ Status = EFI_INVALID_PARAMETER;
+ }
+ }
+ }
+ }
+ }
+ return Status;
+}
+
+STATIC
+EFI_STATUS
+UpdateRefClk (IN VOID* Fdt)
+{
+ INTN node;
+ INTN Error;
+ struct fdt_property *m_prop;
+ int m_oldlen;
+ UINTN ArchTimerFreq = 0;
+ UINT32 Data;
+ CONST CHAR8 *Property = "clock-frequency";
+
+ ArmArchTimerReadReg (CntFrq, &ArchTimerFreq);
+ if (!ArchTimerFreq) {
+ DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Get timer frequency failed!\n", __FUNCTION__, __LINE__));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ node = fdt_subnode_offset(Fdt, 0, "soc");
+ if (node < 0) {
+ DEBUG ((DEBUG_ERROR, "can not find soc node\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ node = fdt_subnode_offset(Fdt, node, "refclk");
+ if (node < 0) {
+ DEBUG ((DEBUG_ERROR, "can not find refclk node\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ m_prop = fdt_get_property_w(Fdt, node, Property, &m_oldlen);
+ if(!m_prop) {
+ DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Can't find property %a\n", __FUNCTION__, __LINE__, Property));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Error = fdt_delprop(Fdt, node, Property);
+ if (Error) {
+ DEBUG ((DEBUG_ERROR, "ERROR: fdt_delprop() %a: %a\n", Property, fdt_strerror (Error)));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // UINT32 is enough for refclk data length
+ Data = (UINT32) ArchTimerFreq;
+ Data = cpu_to_fdt32 (Data);
+ Error = fdt_setprop(Fdt, node, Property, &Data, sizeof(Data));
+ if (Error) {
+ DEBUG ((DEBUG_ERROR, "ERROR:fdt_setprop() %a: %a\n", Property, fdt_strerror (Error)));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ DEBUG ((DEBUG_INFO, "Update refclk successfully.\n"));
+ return EFI_SUCCESS;
+}
+
+INTN
+GetMemoryNode(VOID* Fdt)
+{
+ INTN node;
+ int m_oldlen;
+ struct fdt_property *m_prop;
+ INTN Error = 0;
+
+
+ node = fdt_subnode_offset(Fdt, 0, "memory");
+ if (node < 0)
+ {
+ // Create the memory node
+ node = fdt_add_subnode(Fdt, 0, "memory");
+
+ if(node < 0)
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] fdt add subnode error\n", __FUNCTION__, __LINE__));
+
+ return node;
+ }
+
+ }
+ //find the memory node property
+ m_prop = fdt_get_property_w(Fdt, node, "memory", &m_oldlen);
+ if(m_prop)
+ {
+ Error = fdt_delprop(Fdt, node, "reg");
+
+ if (Error)
+ {
+ DEBUG ((EFI_D_ERROR, "ERROR:fdt_delprop(): %a\n", fdt_strerror (Error)));
+ node = -1;
+ return node;
+ }
+ }
+
+ return node;
+}
+
+
+EFI_STATUS UpdateMemoryNode(VOID* Fdt)
+{
+ INTN Error = 0;
+ EFI_STATUS Status = EFI_SUCCESS;
+ UINT32 Index = 0;
+ UINT32 MemIndex;
+ INTN node;
+ EFI_MEMORY_DESCRIPTOR *MemoryMap;
+ EFI_MEMORY_DESCRIPTOR *MemoryMapPtr;
+ EFI_MEMORY_DESCRIPTOR *MemoryMapPtrCurrent;
+ UINTN MemoryMapSize;
+ UINTN Pages0 = 0;
+ UINTN Pages1 = 0;
+ UINTN MapKey;
+ UINTN DescriptorSize;
+ UINT32 DescriptorVersion;
+ PHY_MEM_REGION *mRegion;
+ UINTN MemoryMapLastEndAddress ;
+ UINTN MemoryMapcontinuousStartAddress ;
+ UINTN MemoryMapCurrentStartAddress;
+ BOOLEAN FindMemoryRegionFlag = FALSE;
+
+ node = GetMemoryNode(Fdt);
+ if (node < 0)
+ {
+ DEBUG((EFI_D_ERROR, "Can not find memory node\n"));
+ return EFI_NOT_FOUND;
+ }
+ MemoryMap = NULL;
+ MemoryMapSize = 0;
+ MemIndex = 0;
+
+ Status = gBS->GetMemoryMap (&MemoryMapSize, MemoryMap, &MapKey, &DescriptorSize, &DescriptorVersion);
+ if (Status == EFI_BUFFER_TOO_SMALL)
+ {
+ // The UEFI specification advises to allocate more memory for the MemoryMap buffer between successive
+ // calls to GetMemoryMap(), since allocation of the new buffer may potentially increase memory map size.
+ Pages0 = EFI_SIZE_TO_PAGES (MemoryMapSize) + 1;
+ MemoryMap = AllocatePages (Pages0);
+ if (MemoryMap == NULL)
+ {
+ Status = EFI_OUT_OF_RESOURCES;
+ return Status;
+ }
+ Status = gBS->GetMemoryMap (&MemoryMapSize, MemoryMap, &MapKey, &DescriptorSize, &DescriptorVersion);
+
+ if (EFI_ERROR(Status))
+ {
+ DEBUG ((EFI_D_ERROR, "FdtUpdateLib GetMemoryMap Error\n"));
+ FreePages (MemoryMap, Pages0);
+ return Status;
+ }
+ }
+ else
+ {
+ DEBUG ((EFI_D_ERROR, "FdtUpdateLib GetmemoryMap Status: %r\n",Status));
+ return EFI_ABORTED;
+ }
+
+ mRegion = NULL;
+ Pages1 = EFI_SIZE_TO_PAGES (sizeof(PHY_MEM_REGION) *( MemoryMapSize / DescriptorSize));
+
+ mRegion = (PHY_MEM_REGION*)AllocatePool(Pages1);
+ if (mRegion == NULL)
+ {
+ Status = EFI_OUT_OF_RESOURCES;
+ FreePages (MemoryMap, Pages0);
+ return Status;
+ }
+
+
+ MemoryMapPtr = MemoryMap;
+ MemoryMapPtrCurrent = MemoryMapPtr;
+ MemoryMapLastEndAddress = 0;
+ MemoryMapcontinuousStartAddress = 0;
+ MemoryMapCurrentStartAddress = 0;
+ for (Index = 0; Index < (MemoryMapSize / DescriptorSize); Index++)
+ {
+ MemoryMapPtrCurrent = (EFI_MEMORY_DESCRIPTOR*)((UINTN)MemoryMapPtr + Index*DescriptorSize);
+ MemoryMapCurrentStartAddress = (UINTN)MemoryMapPtrCurrent->PhysicalStart;
+
+ if (!IsMemMapRegion ((EFI_MEMORY_TYPE)MemoryMapPtrCurrent->Type))
+ {
+ continue;
+ }
+ else
+ {
+ FindMemoryRegionFlag = TRUE;
+ if(MemoryMapCurrentStartAddress != MemoryMapLastEndAddress)
+ {
+ mRegion[MemIndex].BaseHigh= cpu_to_fdt32(MemoryMapcontinuousStartAddress>>32);
+ mRegion[MemIndex].BaseLow=cpu_to_fdt32(MemoryMapcontinuousStartAddress);
+ mRegion[MemIndex].LengthHigh= cpu_to_fdt32((MemoryMapLastEndAddress-MemoryMapcontinuousStartAddress)>>32);
+ mRegion[MemIndex].LengthLow=cpu_to_fdt32(MemoryMapLastEndAddress-MemoryMapcontinuousStartAddress);
+ MemIndex+=1;
+ MemoryMapcontinuousStartAddress=MemoryMapCurrentStartAddress;
+ }
+ }
+ MemoryMapLastEndAddress = (UINTN)(MemoryMapPtrCurrent->PhysicalStart + MemoryMapPtrCurrent->NumberOfPages * EFI_PAGE_SIZE);
+ }
+ if (FindMemoryRegionFlag)
+ {
+ mRegion[MemIndex].BaseHigh = cpu_to_fdt32(MemoryMapcontinuousStartAddress>>32);
+ mRegion[MemIndex].BaseLow = cpu_to_fdt32(MemoryMapcontinuousStartAddress);
+ mRegion[MemIndex].LengthHigh = cpu_to_fdt32((MemoryMapLastEndAddress-MemoryMapcontinuousStartAddress)>>32);
+ mRegion[MemIndex].LengthLow = cpu_to_fdt32(MemoryMapLastEndAddress-MemoryMapcontinuousStartAddress);
+ }
+
+ Error = fdt_setprop(Fdt, node, "reg",mRegion,sizeof(PHY_MEM_REGION) *(MemIndex+1));
+
+ FreePool (mRegion);
+ FreePages (MemoryMap, Pages0);
+ if (Error)
+ {
+ DEBUG ((EFI_D_ERROR, "ERROR:fdt_setprop(): %a\n", fdt_strerror (Error)));
+ Status = EFI_INVALID_PARAMETER;
+ return Status;
+ }
+
+ return Status;
+}
+
+
+EFI_STATUS
+UpdateNumaNode(VOID* Fdt)
+{
+ //TODO: Need to update numa node
+ return EFI_SUCCESS;
+}
+/*
+ * Entry point for fdtupdate lib.
+ */
+
+EFI_STATUS EFIFdtUpdate(UINTN FdtFileAddr)
+{
+ INTN Error;
+ VOID* Fdt;
+ UINT32 Size;
+ UINTN NewFdtBlobSize;
+ UINTN NewFdtBlobBase;
+ EFI_STATUS Status = EFI_SUCCESS;
+ EFI_STATUS UpdateNumaStatus = EFI_SUCCESS;
+
+
+ Error = fdt_check_header ((VOID*)(FdtFileAddr));
+ if (0 != Error)
+ {
+ DEBUG ((EFI_D_ERROR,"ERROR: Device Tree header not valid (%a)\n", fdt_strerror(Error)));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Size = (UINTN)fdt_totalsize ((VOID*)(UINTN)(FdtFileAddr));
+ NewFdtBlobSize = Size + ADD_FILE_LENGTH;
+ Fdt = (VOID*)(UINTN)FdtFileAddr;
+
+ Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, EFI_SIZE_TO_PAGES(NewFdtBlobSize), &NewFdtBlobBase);
+ if (EFI_ERROR (Status))
+ {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+
+ Error = fdt_open_into(Fdt,(VOID*)(UINTN)(NewFdtBlobBase), (NewFdtBlobSize));
+ if (Error) {
+ DEBUG ((EFI_D_ERROR, "ERROR:fdt_open_into(): %a\n", fdt_strerror (Error)));
+ Status = EFI_INVALID_PARAMETER;
+ goto EXIT;
+ }
+
+ Fdt = (VOID*)(UINTN)NewFdtBlobBase;
+ Status = DelPhyhandleUpdateMacAddress(Fdt);
+ if (EFI_ERROR (Status))
+ {
+ DEBUG ((EFI_D_ERROR, "DelPhyhandleUpdateMacAddress fail:\n"));
+ Status = EFI_SUCCESS;
+ }
+
+ Status = UpdateRefClk (Fdt);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "UpdateiRefClk fail.\n"));
+ }
+
+ Status = UpdateMemoryNode(Fdt);
+ if (EFI_ERROR (Status))
+ {
+ DEBUG ((EFI_D_ERROR, "UpdateMemoryNode Error\n"));
+ goto EXIT;
+ }
+
+ UpdateNumaStatus = UpdateNumaNode(Fdt);
+ if (EFI_ERROR (UpdateNumaStatus))
+ {
+ DEBUG ((EFI_D_ERROR, "Update NumaNode fail\n"));
+ }
+
+ gBS->CopyMem(((VOID*)(UINTN)(FdtFileAddr)),((VOID*)(UINTN)(NewFdtBlobBase)),NewFdtBlobSize);
+
+EXIT:
+ gBS->FreePages(NewFdtBlobBase,EFI_SIZE_TO_PAGES(NewFdtBlobSize));
+
+ return Status;
+
+
+
+}
diff --git a/Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf b/Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf new file mode 100755 index 0000000000..9569b918b2 --- /dev/null +++ b/Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf @@ -0,0 +1,50 @@ +#/** @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = FdtUpdateLib
+ FILE_GUID = 02CF1727-E697-47fc-8CC2-5DCB81B26DD9
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = FdtUpdateLib
+
+
+[Sources.common]
+ FdtUpdateLib.c
+
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ ArmLib
+ FdtLib
+ PlatformSysCtrlLib
+ OemMiscLib
+
+[Protocols]
+ gHisiBoardNicProtocolGuid
+
+[Guids]
+
+[Pcd]
+ gHisiTokenSpaceGuid.PcdNumaEnable
+
+
diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c b/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c new file mode 100644 index 0000000000..66d62895a6 --- /dev/null +++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c @@ -0,0 +1,197 @@ +/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Protocol/Smbios.h>
+#include <IndustryStandard/SmBios.h>
+
+#include <PlatformArch.h>
+#include <Library/OemMiscLib.h>
+#include <Library/SerdesLib.h>
+#include <Library/I2CLib.h>
+#include <Library/HiiLib.h>
+
+I2C_DEVICE gDS3231RtcDevice = {
+ .Socket = 0,
+ .Port = 6,
+ .DeviceType = DEVICE_TYPE_SPD,
+ .SlaveDeviceAddress = 0x68
+};
+
+SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[] =
+{
+ {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+
+SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[] =
+{
+ {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+
+SERDES_PARAM gSerdesParam = {
+ .Hilink0Mode = EmHilink0Pcie1X8,
+ .Hilink1Mode = EmHilink1Pcie0X8,
+ .Hilink2Mode = EmHilink2Pcie2X8,
+ .Hilink3Mode = 0x0,
+ .Hilink4Mode = 0xF,
+ .Hilink5Mode = EmHilink5Sas1X4,
+ .Hilink6Mode = 0x0,
+ .UseSsc = 0,
+};
+
+SERDES_PARAM gSerdesParam0 = {
+ .Hilink0Mode = EmHilink0Hccs1X8Width16,
+ .Hilink1Mode = EmHilink1Hccs0X8Width16,
+ .Hilink2Mode = EmHilink2Pcie2X8,
+ .Hilink3Mode = 0x0,
+ .Hilink4Mode = 0xF,
+ .Hilink5Mode = EmHilink5Sas1X4,
+ .Hilink6Mode = 0x0,
+ .UseSsc = 0,
+};
+
+SERDES_PARAM gSerdesParam1 = {
+ .Hilink0Mode = EmHilink0Hccs1X8Width16,
+ .Hilink1Mode = EmHilink1Hccs0X8Width16,
+ .Hilink2Mode = EmHilink2Pcie2X8,
+ .Hilink3Mode = 0x0,
+ .Hilink4Mode = 0xF,
+ .Hilink5Mode = EmHilink5Pcie3X4,
+ .Hilink6Mode = 0xF,
+ .UseSsc = 0,
+};
+
+EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId)
+{
+ if (ParamA == NULL) {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ (VOID) CopyMem(ParamA, &gSerdesParam, sizeof(*ParamA));
+ return EFI_SUCCESS;
+}
+
+
+VOID OemPcieResetAndOffReset(void)
+ {
+ return;
+ }
+
+SMBIOS_TABLE_TYPE9 gPcieSlotInfo[] = {
+ // PCIe0 Slot 1
+ {
+ { // Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type,
+ 0, // Length,
+ 0 // Handle
+ },
+ 1, // SlotDesignation
+ SlotTypePciExpressX8, // SlotType
+ SlotDataBusWidth8X, // SlotDataBusWidth
+ SlotUsageAvailable, // SlotUsage
+ SlotLengthOther, // SlotLength
+ 0x0001, // SlotId
+ { // SlotCharacteristics1
+ 0, // CharacteristicsUnknown :1;
+ 0, // Provides50Volts :1;
+ 0, // Provides33Volts :1;
+ 0, // SharedSlot :1;
+ 0, // PcCard16Supported :1;
+ 0, // CardBusSupported :1;
+ 0, // ZoomVideoSupported :1;
+ 0 // ModemRingResumeSupported:1;
+ },
+ { // SlotCharacteristics2
+ 0, // PmeSignalSupported :1;
+ 0, // HotPlugDevicesSupported :1;
+ 0, // SmbusSignalSupported :1;
+ 0 // Reserved :5;
+ },
+ 0x00, // SegmentGroupNum
+ 0x00, // BusNum
+ 0 // DevFuncNum
+ },
+
+ // PCIe0 Slot 4
+ {
+ { // Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type,
+ 0, // Length,
+ 0 // Handle
+ },
+ 1, // SlotDesignation
+ SlotTypePciExpressX8, // SlotType
+ SlotDataBusWidth8X, // SlotDataBusWidth
+ SlotUsageAvailable, // SlotUsage
+ SlotLengthOther, // SlotLength
+ 0x0004, // SlotId
+ { // SlotCharacteristics1
+ 0, // CharacteristicsUnknown :1;
+ 0, // Provides50Volts :1;
+ 0, // Provides33Volts :1;
+ 0, // SharedSlot :1;
+ 0, // PcCard16Supported :1;
+ 0, // CardBusSupported :1;
+ 0, // ZoomVideoSupported :1;
+ 0 // ModemRingResumeSupported:1;
+ },
+ { // SlotCharacteristics2
+ 0, // PmeSignalSupported :1;
+ 0, // HotPlugDevicesSupported :1;
+ 0, // SmbusSignalSupported :1;
+ 0 // Reserved :5;
+ },
+ 0x00, // SegmentGroupNum
+ 0x00, // BusNum
+ 0 // DevFuncNum
+ }
+};
+
+
+UINT8 OemGetPcieSlotNumber ()
+{
+ return sizeof (gPcieSlotInfo) / sizeof (SMBIOS_TABLE_TYPE9);
+}
+
+EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] = {
+ {{STRING_TOKEN(STR_LEMON_C10_DIMM_000), STRING_TOKEN(STR_LEMON_C10_DIMM_001), STRING_TOKEN(STR_LEMON_C10_DIMM_002)},
+ {STRING_TOKEN(STR_LEMON_C10_DIMM_010), STRING_TOKEN(STR_LEMON_C10_DIMM_011), STRING_TOKEN(STR_LEMON_C10_DIMM_012)},
+ {STRING_TOKEN(STR_LEMON_C10_DIMM_020), STRING_TOKEN(STR_LEMON_C10_DIMM_021), STRING_TOKEN(STR_LEMON_C10_DIMM_022)},
+ {STRING_TOKEN(STR_LEMON_C10_DIMM_030), STRING_TOKEN(STR_LEMON_C10_DIMM_031), STRING_TOKEN(STR_LEMON_C10_DIMM_032)}},
+
+ {{STRING_TOKEN(STR_LEMON_C10_DIMM_100), STRING_TOKEN(STR_LEMON_C10_DIMM_101), STRING_TOKEN(STR_LEMON_C10_DIMM_102)},
+ {STRING_TOKEN(STR_LEMON_C10_DIMM_110), STRING_TOKEN(STR_LEMON_C10_DIMM_111), STRING_TOKEN(STR_LEMON_C10_DIMM_112)},
+ {STRING_TOKEN(STR_LEMON_C10_DIMM_120), STRING_TOKEN(STR_LEMON_C10_DIMM_121), STRING_TOKEN(STR_LEMON_C10_DIMM_122)},
+ {STRING_TOKEN(STR_LEMON_C10_DIMM_130), STRING_TOKEN(STR_LEMON_C10_DIMM_131), STRING_TOKEN(STR_LEMON_C10_DIMM_132)}}
+};
+
+EFI_HII_HANDLE
+EFIAPI
+OemGetPackages (
+ )
+{
+ return HiiAddPackages (
+ &gEfiCallerIdGuid,
+ NULL,
+ OemMiscLib2PStrings,
+ NULL,
+ NULL
+ );
+}
+
+
diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610Strings.uni b/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610Strings.uni Binary files differnew file mode 100644 index 0000000000..38def406b9 --- /dev/null +++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610Strings.uni diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c new file mode 100644 index 0000000000..fa1039bda1 --- /dev/null +++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c @@ -0,0 +1,141 @@ +/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/TimerLib.h>
+#include <Library/SerialPortLib.h>
+#include <Library/OemMiscLib.h>
+#include <PlatformArch.h>
+#include <Library/PlatformSysCtrlLib.h>
+#include <Library/OemAddressMapLib.h>
+#include <Library/LpcLib.h>
+REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = {
+ {67,0,0,0},
+ {225,0,0,3},
+ {0xFFFF,0xFFFF,0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF,0xFFFF,0xFFFF}
+};
+
+// Right now we only support 1P
+BOOLEAN OemIsSocketPresent (UINTN Socket)
+{
+ if (0 == Socket)
+ {
+ return TRUE;
+ }
+
+ if(1 == Socket)
+ {
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+
+UINTN OemGetSocketNumber (VOID)
+{
+
+ if(!OemIsMpBoot())
+ {
+ return 1;
+ }
+
+ return 2;
+
+}
+
+
+UINTN OemGetDdrChannel (VOID)
+{
+ return 4;
+}
+
+
+UINTN OemGetDimmSlot(UINTN Socket, UINTN Channel)
+{
+ return 2;
+}
+
+
+// Nothing to do for EVB
+VOID OemPostEndIndicator (VOID)
+{
+
+ DEBUG((EFI_D_ERROR,"M3 release reset CONFIG........."));
+
+ MmioWrite32(0xd0002180, 0x3);
+ MmioWrite32(0xd0002194, 0xa4);
+ MmioWrite32(0xd0000a54, 0x1);
+
+ MicroSecondDelay(10000);
+
+ MmioWrite32(0xd0002108, 0x1);
+ MmioWrite32(0xd0002114, 0x1);
+ MmioWrite32(0xd0002120, 0x1);
+ MmioWrite32(0xd0003108, 0x1);
+
+ MicroSecondDelay(500000);
+ DEBUG((EFI_D_ERROR,"Done\n"));
+
+}
+
+
+
+VOID CoreSelectBoot(VOID)
+{
+ if (!PcdGet64 (PcdTrustedFirmwareEnable))
+ {
+ StartupAp ();
+ }
+
+ return;
+}
+
+BOOLEAN OemIsMpBoot()
+{
+ UINT32 Tmp;
+
+ Tmp = MmioRead32(0x602E0050);
+ if ( ((Tmp >> 10) & 0xF) == 0x3)
+ return TRUE;
+ else
+ return FALSE;
+}
+
+VOID OemLpcInit(VOID)
+{
+ LpcInit();
+ return;
+}
+
+UINT32 OemIsWarmBoot(VOID)
+{
+ return 0;
+}
+
+VOID OemBiosSwitch(UINT32 Master)
+{
+ (VOID)Master;
+ return;
+}
+
+BOOLEAN OemIsNeedDisableExpanderBuffer(VOID)
+{
+ return TRUE;
+}
diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf new file mode 100644 index 0000000000..310bbaea84 --- /dev/null +++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf @@ -0,0 +1,54 @@ +#/** @file
+#
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = OemMiscLib2P
+ FILE_GUID = B9CE7465-21A2-4ecd-B347-BBDDBD098CEE
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = OemMiscLib
+
+[Sources.common]
+ BoardFeature2PHi1610.c
+ OemMiscLib2PHi1610.c
+ BoardFeature2PHi1610Strings.uni
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+
+ Silicon/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ PcdLib
+ TimerLib
+
+[BuildOptions]
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid ## SOMETIMES_CONSUMES
+
+[Pcd]
+ gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
+
+[FixedPcd.common]
+
+[Guids]
+
+[Protocols]
+
diff --git a/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c b/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c new file mode 100644 index 0000000000..c58118fe5e --- /dev/null +++ b/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c @@ -0,0 +1,156 @@ +/** @file
+
+ Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/PcdLib.h>
+#include <Library/PlatformPciLib.h>
+UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0000000, 0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000},
+ {0xb0000000,0xb0000000,0xb0000000,0xb0000000, 0xb0000000,0xb0000000,0xb0000000,0xb0000000}};
+UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000},
+ {0xb0090000, 0xb0200000, 0xb00a0000, 0xb00b0000}};
+UINT64 PCIE_PHY_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000},
+ {0xb00c0000,0xb00d0000, 0xb00e0000, 0xb00f0000}};
+UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040},
+ {0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040}};
+
+PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {
+ {// HostBridge 0
+ /* Port 0 */
+ {
+ PCI_HB0RB0_ECAM_BASE, //ecam
+ 0, //BusBase
+ 31, //BusLimit
+ PCI_HB0RB0_PCIREGION_BASE, //Membase
+ PCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //Memlimit
+ PCI_HB0RB0_IO_BASE, //IoBase
+ (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
+ PCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBase
+ PCI_HB0RB0_CPUIOREGIONBASE, //CpuIoRegionBase
+ (PCI_HB0RB0_PCI_BASE), //RbPciBar
+ PCI_HB0RB0_PCIREGION_BASE, //PciRegionBase
+ PCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //PciRegionLimit
+
+ },
+ /* Port 1 */
+ {
+ PCI_HB0RB1_ECAM_BASE,//ecam
+ 224, //BusBase
+ 254, //BusLimit
+ PCI_HB0RB1_PCIREGION_BASE, //Membase
+ PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //MemLimit
+ (PCI_HB0RB1_IO_BASE), //IoBase
+ (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimit
+ PCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBase
+ PCI_HB0RB1_CPUIOREGIONBASE, //CpuIoRegionBase
+ (PCI_HB0RB1_PCI_BASE), //RbPciBar
+ PCI_HB0RB1_PCIREGION_BASE, //PciRegionBase
+ PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //PciRegionLimit
+ },
+ /* Port 2 */
+ {
+ PCI_HB0RB2_ECAM_BASE,
+ 128, //BusBase
+ 159, //BusLimit
+ PCI_HB0RB2_PCIREGION_BASE ,//MemBase
+ PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit
+ (PCI_HB0RB2_IO_BASE), //IOBase
+ (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimit
+ PCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBase
+ PCI_HB0RB2_CPUIOREGIONBASE, //CpuIoRegionBase
+ (PCI_HB0RB2_PCI_BASE), //RbPciBar
+ PCI_HB0RB2_PCIREGION_BASE, //PciRegionBase
+ PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //PciRegionLimit
+ },
+
+ /* Port 3 */
+ {
+ PCI_HB0RB3_ECAM_BASE,
+ 96, //BusBase
+ 127, //BusLimit
+ (PCI_HB0RB3_ECAM_BASE), //MemBase
+ (PCI_HB0RB3_ECAM_BASE + PCI_HB0RB3_ECAM_SIZE - 1), //MemLimit
+ (0), //IoBase
+ (0), //IoLimit
+ 0,
+ 0,
+ (PCI_HB0RB3_PCI_BASE), //RbPciBar
+ 0,
+ 0
+ }
+ },
+{// HostBridge 1
+ /* Port 0 */
+ {
+ PCI_HB1RB0_ECAM_BASE,
+ 128, //BusBase
+ 159, //BusLimit
+ (PCI_HB1RB0_ECAM_BASE), //MemBase
+ (PCI_HB1RB0_ECAM_BASE + PCI_HB1RB0_ECAM_SIZE - 1), //MemLimit
+ (0), //IoBase
+ (0), //IoLimit
+ 0,
+ 0,
+ (PCI_HB1RB0_PCI_BASE), //RbPciBar
+ 0,
+ 0
+ },
+ /* Port 1 */
+ {
+ PCI_HB1RB1_ECAM_BASE,
+ 160, //BusBase
+ 191, //BusLimit
+ (PCI_HB1RB1_ECAM_BASE), //MemBase
+ (PCI_HB1RB1_ECAM_BASE + PCI_HB1RB1_ECAM_SIZE - 1), //MemLimit
+ (0), //IoBase
+ (0), //IoLimit
+ 0,
+ 0,
+ (PCI_HB1RB1_PCI_BASE), //RbPciBar
+ 0,
+ 0
+ },
+ /* Port 2 */
+ {
+ PCI_HB1RB2_ECAM_BASE,
+ 192, //BusBase
+ 223, //BusLimit
+ (PCI_HB1RB2_ECAM_BASE), //MemBase
+ (PCI_HB1RB2_ECAM_BASE + PCI_HB1RB2_ECAM_SIZE - 1), //MemLimit
+ (0), //IoBase
+ (0), //IoLimit
+ 0,
+ 0,
+ (PCI_HB1RB2_PCI_BASE), //RbPciBar
+ 0,
+ 0
+ },
+
+ /* Port 3 */
+ {
+ PCI_HB1RB3_ECAM_BASE,
+ 224, //BusBase
+ 255, //BusLimit
+ (PCI_HB1RB3_ECAM_BASE), //MemBase
+ (PCI_HB1RB3_ECAM_BASE + PCI_HB1RB3_ECAM_SIZE - 1), //MemLimit
+ (0), //IoBase
+ (0), //IoLimit
+ 0,
+ 0,
+ (PCI_HB1RB3_PCI_BASE), //RbPciBar
+ 0,
+ 0
+ }
+ }
+};
+
diff --git a/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf b/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf new file mode 100644 index 0000000000..4d2dbbaf0d --- /dev/null +++ b/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf @@ -0,0 +1,182 @@ +## @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
+# Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PlatformPciLib
+ FILE_GUID = 61b7276a-fc67-11e5-82fd-47ea9896dd5d
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+
+[Sources]
+ PlatformPciLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ PcdLib
+
+[FixedPcd]
+ gHisiTokenSpaceGuid.PcdHb1BaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PciHb0Rb0Base
+ gHisiTokenSpaceGuid.PciHb0Rb1Base
+ gHisiTokenSpaceGuid.PciHb0Rb2Base
+ gHisiTokenSpaceGuid.PciHb0Rb3Base
+ gHisiTokenSpaceGuid.PciHb0Rb4Base
+ gHisiTokenSpaceGuid.PciHb0Rb5Base
+ gHisiTokenSpaceGuid.PciHb0Rb6Base
+ gHisiTokenSpaceGuid.PciHb0Rb7Base
+ gHisiTokenSpaceGuid.PciHb1Rb0Base
+ gHisiTokenSpaceGuid.PciHb1Rb1Base
+ gHisiTokenSpaceGuid.PciHb1Rb2Base
+ gHisiTokenSpaceGuid.PciHb1Rb3Base
+ gHisiTokenSpaceGuid.PciHb1Rb4Base
+ gHisiTokenSpaceGuid.PciHb1Rb5Base
+ gHisiTokenSpaceGuid.PciHb1Rb6Base
+ gHisiTokenSpaceGuid.PciHb1Rb7Base
+ gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress
+
+ gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize
+
+ gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase
+
+ gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase
+
+ gHisiTokenSpaceGuid.PcdHb0Rb0IoBase
+ gHisiTokenSpaceGuid.PcdHb0Rb0IoSize
+ gHisiTokenSpaceGuid.PcdHb0Rb1IoBase
+ gHisiTokenSpaceGuid.PcdHb0Rb1IoSize
+ gHisiTokenSpaceGuid.PcdHb0Rb2IoBase
+ gHisiTokenSpaceGuid.PcdHb0Rb2IoSize
+ gHisiTokenSpaceGuid.PcdHb0Rb3IoBase
+ gHisiTokenSpaceGuid.PcdHb0Rb3IoSize
+ gHisiTokenSpaceGuid.PcdHb0Rb4IoBase
+ gHisiTokenSpaceGuid.PcdHb0Rb4IoSize
+ gHisiTokenSpaceGuid.PcdHb0Rb5IoBase
+ gHisiTokenSpaceGuid.PcdHb0Rb5IoSize
+ gHisiTokenSpaceGuid.PcdHb0Rb6IoBase
+ gHisiTokenSpaceGuid.PcdHb0Rb6IoSize
+ gHisiTokenSpaceGuid.PcdHb0Rb7IoBase
+ gHisiTokenSpaceGuid.PcdHb0Rb7IoSize
+ gHisiTokenSpaceGuid.PcdHb1Rb0IoBase
+ gHisiTokenSpaceGuid.PcdHb1Rb0IoSize
+ gHisiTokenSpaceGuid.PcdHb1Rb1IoBase
+ gHisiTokenSpaceGuid.PcdHb1Rb1IoSize
+ gHisiTokenSpaceGuid.PcdHb1Rb2IoBase
+ gHisiTokenSpaceGuid.PcdHb1Rb2IoSize
+ gHisiTokenSpaceGuid.PcdHb1Rb3IoBase
+ gHisiTokenSpaceGuid.PcdHb1Rb3IoSize
+ gHisiTokenSpaceGuid.PcdHb1Rb4IoBase
+ gHisiTokenSpaceGuid.PcdHb1Rb4IoSize
+ gHisiTokenSpaceGuid.PcdHb1Rb5IoBase
+ gHisiTokenSpaceGuid.PcdHb1Rb5IoSize
+ gHisiTokenSpaceGuid.PcdHb1Rb6IoBase
+ gHisiTokenSpaceGuid.PcdHb1Rb6IoSize
+ gHisiTokenSpaceGuid.PcdHb1Rb7IoBase
+ gHisiTokenSpaceGuid.PcdHb1Rb7IoSize
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