4 files changed, 136 insertions, 1 deletions
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
index 139ce8c057..6dd6234a63 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
@@ -107,6 +107,11 @@
   BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull/BoardInitLibNull.inf
   TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf
 
+# Tbt
+!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
+  TbtCommonLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.inf
+  DxeTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLib.inf
+!endif
 #
 # Silicon Init Package
 #
@@ -124,6 +129,11 @@
   MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/PeiMultiBoardInitSupportLib.inf
   BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/PeiMultiBoardInitSupportLib.inf
 
+# Tbt
+!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
+  PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.inf
+  PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Private/PeiDTbtInitLib/PeiDTbtInitLib.inf
+!endif
 #
 # Silicon Init Package
 #
@@ -232,6 +242,11 @@
   IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
   IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
 
+# Tbt
+!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
+  $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
+!endif
+
 [Components.X64]
 
 #
@@ -254,6 +269,13 @@
 #
 !include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc
 
+# Tbt
+!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
+  $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf
+  $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
+  $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf
+!endif
+
 #
 # Platform
 #
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
index 3d2ef2b4aa..574d2b7878 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
@@ -600,7 +600,74 @@ FILE FV_IMAGE = C83522D9-80A1-4D95-8C25-3F1370497406 {
          SECTION FV_IMAGE = FvSecurityLate
        }
      }
-     
+
+[FV.FvAdvancedPreMem]
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+FvNameGuid         = 6053D78A-457E-4490-A237-31D0FBE2F305
+
+!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
+INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
+!endif
+
+[FV.FvAdvancedPostMem]
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+FvNameGuid         = BE3DF86F-E464-44A3-83F7-0D27E6B88C27
+
+[FV.FvAdvancedLate]
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+FvNameGuid         = 11F6E304-43F9-4B2F-90AB-B8FFEAD6205D
+
+!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
+INF  $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
+INF  $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf
+INF  $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf
+!endif
+
 [FV.FvAdvanced]
 BlockSize          = $(FLASH_BLOCK_SIZE)
 FvAlignment        = 16
@@ -621,6 +688,20 @@ READ_LOCK_CAP      = TRUE
 READ_LOCK_STATUS   = TRUE
 FvNameGuid         = B23E7388-9953-45C7-9201-0473DDE5487A
 
+FILE FV_IMAGE = 35E7406A-5842-4F2B-BC62-19022C12AF74 {
+       SECTION FV_IMAGE = FvAdvancedPreMem
+     }
+
+FILE FV_IMAGE = F5DCB34F-27EA-48AC-9406-C894F6D587CA {
+       SECTION FV_IMAGE = FvAdvancedPostMem
+     }
+
+FILE FV_IMAGE = 5248467B-B87B-4E74-AC02-398AF4BCB712 {
+       SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+         SECTION FV_IMAGE = FvAdvancedLate
+       }
+     }
+
 ################################################################################
 #
 # Rules are use with the [FV] section's module INF type to define
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgConfig.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgConfig.dsc
index d566967b86..600a3288ae 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgConfig.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgConfig.dsc
@@ -52,6 +52,7 @@
   gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE
 !endif
   
+  gBoardModuleTokenSpaceGuid.PcdTbtEnable|TRUE
   #
   # More fine granularity control below:
   #
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
index 36274af337..92b9ad8bcf 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
@@ -249,4 +249,35 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000
   gEfiSecurityPkgTokenSpaceGuid.PcdTcg2HashAlgorithmBitmap|0
   gEfiSecurityPkgTokenSpaceGuid.PcdTpm2HashMask|0x0000001F
   gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|1
+  
+# Tbt
+gBoardModuleTokenSpaceGuid.PcdDTbtControllerEn | 0x1
+gBoardModuleTokenSpaceGuid.PcdDTbtControllerType | 0x1
+gBoardModuleTokenSpaceGuid.PcdDTbtPcieRpNumber | 0x1
+gBoardModuleTokenSpaceGuid.PcdDTbtGpioAccessType | 0x2
+gBoardModuleTokenSpaceGuid.PcdExpander | 0x0
+gBoardModuleTokenSpaceGuid.PcdDTbtGpioLevel | 0x1
+gBoardModuleTokenSpaceGuid.PcdDTbtForcepowerGpioPad | 13
+gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad | 0x02010011
+gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignature | 0
+gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignaturePorting | 0
+gBoardModuleTokenSpaceGuid.PcdDTbtSecurityMode | 0x1
+#gBoardModuleTokenSpaceGuid.PcdDTbtGpio5Filter | 0x0
+gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport | 0x0
+gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI | 0x1
+gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify | 0x1
+gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq| 0x1
+gBoardModuleTokenSpaceGuid.PcdDTbtAspm | 0x0
+gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch | 0x0
+gBoardModuleTokenSpaceGuid.PcdRtd3Tbt | 0x1
+gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq | 0x1
+gBoardModuleTokenSpaceGuid.PcdDTbtWin10Support | 0x0
+gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReqDelay | 0x0
+gBoardModuleTokenSpaceGuid.PcdRtd3TbtOffDelay | 5000
+gBoardModuleTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd | 56
+gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemRsvd | 100
+gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax | 26
+gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd | 100
+gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax | 28
+gBoardModuleTokenSpaceGuid.PcdPchPcieRootPortHpe| 0x00000001