diff options
Diffstat (limited to 'Platform/Intel/MinPlatformPkg/Include/Library/TestPointCheckLib.h')
| -rw-r--r-- | Platform/Intel/MinPlatformPkg/Include/Library/TestPointCheckLib.h | 306 |
1 files changed, 226 insertions, 80 deletions
diff --git a/Platform/Intel/MinPlatformPkg/Include/Library/TestPointCheckLib.h b/Platform/Intel/MinPlatformPkg/Include/Library/TestPointCheckLib.h index 7caea0a53e..c551650824 100644 --- a/Platform/Intel/MinPlatformPkg/Include/Library/TestPointCheckLib.h +++ b/Platform/Intel/MinPlatformPkg/Include/Library/TestPointCheckLib.h @@ -20,10 +20,16 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. //
// Below is Test Point Hook Point.
//
+// Naming: TestPoint<Phase/Event><Function>
+//
+// Phase/Event(PEI) = MemoryDiscovered|EndOfPei
+// Phase/Event(DXE) = PciEnumerationDone|EndOfDxe|DxeSmmReadyToLock|ReadyToBoot
+// Phase/Event(SMM) = SmmEndOfDxe|SmmReadyToLock|SmmReadyToBoot
+//
EFI_STATUS
EFIAPI
-TestPointTempMemoryInitDone (
+TestPointTempMemoryFunction (
IN VOID *TempRamStart,
IN VOID *TempRamEnd
);
@@ -34,39 +40,148 @@ TestPointDebugInitDone ( VOID
);
+
+EFI_STATUS
+EFIAPI
+TestPointMemoryDiscoveredMtrrFunctional (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+TestPointMemoryDiscoveredMemoryResourceFunctional (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+TestPointMemoryDiscoveredFvInfoFunctional (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+TestPointEndOfPeiSystemResourceFunctional (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+TestPointEndOfPeiMtrrFunctional (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+TestPointEndOfPeiPciBusMasterDisabled (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+TestPointPciEnumerationDonePciBusMasterDisabled (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+TestPointPciEnumerationDonePciResourceAllocated (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+TestPointEndOfDxeDmarTableFuntional (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+TestPointEndOfDxeNoThirdPartyPciOptionRom (
+ VOID
+ );
+
EFI_STATUS
EFIAPI
-TestPointMemoryDiscovered (
+TestPointDxeSmmReadyToLockSmramAligned (
VOID
);
EFI_STATUS
EFIAPI
-TestPointEndOfPei (
+TestPointDxeSmmReadyToLockWsmtTableFuntional (
VOID
);
EFI_STATUS
EFIAPI
-TestPointPciEnumerationDone (
+TestPointReadyToBootAcpiTableFuntional (
VOID
);
EFI_STATUS
EFIAPI
-TestPointEndOfDxe (
+TestPointReadyToBootMemoryTypeInformationFunctional (
VOID
);
EFI_STATUS
EFIAPI
-TestPointDxeSmmReadyToLock (
+TestPointReadyToBootUefiMemoryAttributeTableFunctional (
VOID
);
EFI_STATUS
EFIAPI
-TestPointReadyToBoot (
+TestPointReadyToBootUefiBootVariableFunctional (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+TestPointReadyToBootUefiConsoleVariableFunctional (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+TestPointReadyToBootHstiTableFunctional (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+TestPointReadyToBootEsrtTableFunctional (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+TestPointReadyToBootUefiSecureBootEnabled (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+TestPointReadyToBootPiSignedFvBootEnabled (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+TestPointReadyToBootTcgTrustedBootEnabled (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+TestPointReadyToBootTcgMorEnabled (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+TestPointReadyToBootSmiHandlerInstrument (
VOID
);
@@ -78,19 +193,25 @@ TestPointExitBootServices ( EFI_STATUS
EFIAPI
-TestPointSmmEndOfDxe (
+TestPointSmmEndOfDxeSmrrFunctional (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+TestPointSmmReadyToLockSmmMemoryAttributeTableFunctional (
VOID
);
EFI_STATUS
EFIAPI
-TestPointSmmReadyToLock (
+TestPointSmmReadyToLockSecureSmmCommunicationBuffer (
VOID
);
EFI_STATUS
EFIAPI
-TestPointSmmReadyToBoot (
+TestPointSmmReadyToBootSmmPageProtection (
VOID
);
@@ -104,9 +225,12 @@ TestPointSmmExitBootServices ( // Below is detail definition for MinPlatform implementation
//
-#define TEST_POINT_IMPLEMENTATION_ID_PLATFORM L"Intel MinPlatform TestPoint"
+#define TEST_POINT_IMPLEMENTATION_ID_PLATFORM L"Intel MinPlatform TestPoint"
+#define TEST_POINT_IMPLEMENTATION_ID_PLATFORM_PEI TEST_POINT_IMPLEMENTATION_ID_PLATFORM L" (PEI)"
+#define TEST_POINT_IMPLEMENTATION_ID_PLATFORM_DXE TEST_POINT_IMPLEMENTATION_ID_PLATFORM L" (DXE)"
+#define TEST_POINT_IMPLEMENTATION_ID_PLATFORM_SMM TEST_POINT_IMPLEMENTATION_ID_PLATFORM L" (SMM)"
-#define TEST_POINT_FEATURE_SIZE 4
+#define TEST_POINT_FEATURE_SIZE 0x10
#define TEST_POINT_ERROR L"Error "
#define TEST_POINT_PLATFORM_TEST_POINT L" Platform TestPoint"
@@ -115,8 +239,6 @@ TestPointSmmExitBootServices ( #define TEST_POINT_TEMP_MEMORY_INIT_DONE L" - Temp Memory Init Done - "
#define TEST_POINT_BYTE0_TEMP_INIT_DONE BIT0
-#define TEST_POINT_BYTE0_TEMP_MEMORY_INIT_DONE_ERROR_CODE_1 L"0x00000001"
-#define TEST_POINT_BYTE0_TEMP_MEMORY_INIT_DONE_ERROR_STRING_1 L"Invalid Temp Ram\r\n"
// Byte 1 - PEI
#define TEST_POINT_DEBUG_INIT_DONE L" - Debug Init Done - "
@@ -124,82 +246,107 @@ TestPointSmmExitBootServices ( #define TEST_POINT_END_OF_PEI L" - End Of PEI - "
#define TEST_POINT_BYTE1_DEBUG_INIT_DONE BIT0
-#define TEST_POINT_BYTE1_MEMORY_DISCOVERED BIT1
-#define TEST_POINT_BYTE1_MEMORY_DISCOVERED_ERROR_CODE_1 L"0x01010001"
-#define TEST_POINT_BYTE1_MEMORY_DISCOVERED_ERROR_STRING_1 L"Invalid Memory Resource\r\n"
-#define TEST_POINT_BYTE1_MEMORY_DISCOVERED_ERROR_CODE_2 L"0x01010002"
-#define TEST_POINT_BYTE1_MEMORY_DISCOVERED_ERROR_STRING_2 L"Invalid MTRR Setting\r\n"
-#define TEST_POINT_BYTE1_MEMORY_DISCOVERED_ERROR_CODE_3 L"0x01010002"
-#define TEST_POINT_BYTE1_MEMORY_DISCOVERED_ERROR_STRING_3 L"Invalid SMRAM Resource\r\n"
-#define TEST_POINT_BYTE1_END_OF_PEI BIT2
-#define TEST_POINT_BYTE1_END_OF_PEI_ERROR_CODE_1 L"0x01020001"
-#define TEST_POINT_BYTE1_END_OF_PEI_ERROR_STRING_1 L"Invalid System Resource\r\n"
-#define TEST_POINT_BYTE1_END_OF_PEI_ERROR_CODE_2 L"0x01020002"
-#define TEST_POINT_BYTE1_END_OF_PEI_ERROR_STRING_2 L"Invalid MTRR Setting\r\n"
-#define TEST_POINT_BYTE1_END_OF_PEI_ERROR_CODE_3 L"0x01010003"
-#define TEST_POINT_BYTE1_END_OF_PEI_ERROR_STRING_3 L"Invalid FV Information\r\n"
-
-// Byte 2 - DXE
+#define TEST_POINT_BYTE1_MEMORY_DISCOVERED_MTRR_FUNCTIONAL BIT1
+#define TEST_POINT_BYTE1_MEMORY_DISCOVERED_MEMORY_RESOURCE_FUNCTIONAL BIT2
+#define TEST_POINT_BYTE1_MEMORY_DISCOVERED_FV_INFO_FUNCTIONAL BIT3
+#define TEST_POINT_BYTE1_END_OF_PEI_SYSTEM_RESOURCE_FUNCTIONAL BIT4
+#define TEST_POINT_BYTE1_END_OF_PEI_MTRR_FUNCTIONAL BIT5
+#define TEST_POINT_BYTE1_END_OF_PEI_PCI_BUS_MASTER_DISABLED BIT6
+#define TEST_POINT_BYTE1_MEMORY_DISCOVERED_MTRR_FUNCTIONAL_ERROR_CODE L"0x01010000"
+#define TEST_POINT_BYTE1_MEMORY_DISCOVERED_MTRR_FUNCTIONAL_ERROR_STRING L"Invalid MTRR Setting\r\n"
+#define TEST_POINT_BYTE1_MEMORY_DISCOVERED_MEMORY_RESOURCE_FUNCTIONAL_ERROR_CODE L"0x01020000"
+#define TEST_POINT_BYTE1_MEMORY_DISCOVERED_MEMORY_RESOURCE_FUNCTIONAL_ERROR_STRING L"Invalid Memory Resource\r\n"
+#define TEST_POINT_BYTE1_MEMORY_DISCOVERED_FV_INFO_FUNCTIONAL_ERROR_CODE L"0x01030000"
+#define TEST_POINT_BYTE1_MEMORY_DISCOVERED_FV_INFO_FUNCTIONAL_ERROR_STRING L"Invalid FV Information\r\n"
+#define TEST_POINT_BYTE1_END_OF_PEI_SYSTEM_RESOURCE_FUNCTIONAL_ERROR_CODE L"0x01040000"
+#define TEST_POINT_BYTE1_END_OF_PEI_SYSTEM_RESOURCE_FUNCTIONAL_ERROR_STRING L"Invalid System Resource\r\n"
+#define TEST_POINT_BYTE1_END_OF_PEI_MTRR_FUNCTIONAL_ERROR_CODE L"0x01050000"
+#define TEST_POINT_BYTE1_END_OF_PEI_MTRR_FUNCTIONAL_ERROR_STRING L"Invalid MTRR Setting\r\n"
+#define TEST_POINT_BYTE1_END_OF_PEI_PCI_BUS_MASTER_DISABLED_ERROR_CODE L"0x01060000"
+#define TEST_POINT_BYTE1_END_OF_PEI_PCI_BUS_MASTER_DISABLED_ERROR_STRING L"PCI Bus Master Enabled\r\n"
+
+// Byte 2/3/4 - DXE
#define TEST_POINT_PCI_ENUMERATION_DONE L" - PCI Enumeration Done - "
#define TEST_POINT_END_OF_DXE L" - End Of DXE - "
#define TEST_POINT_DXE_SMM_READY_TO_LOCK L" - DXE SMM Ready To Lock - "
#define TEST_POINT_READY_TO_BOOT L" - Ready To Boot - "
#define TEST_POINT_EXIT_BOOT_SERVICES L" - Exit Boot Services - "
-#define TEST_POINT_BYTE2_PCI_ENUMERATION_DONE BIT0
-#define TEST_POINT_BYTE2_PCI_ENUMERATION_DONE_ERROR_CODE_1 L"0x02010001"
-#define TEST_POINT_BYTE2_PCI_ENUMERATION_DONE_ERROR_STRING_1 L"Invalid PCI Resource\r\n"
-#define TEST_POINT_BYTE2_END_OF_DXE BIT1
-#define TEST_POINT_BYTE2_END_OF_DXE_ERROR_CODE_1 L"0x02020001"
-#define TEST_POINT_BYTE2_END_OF_DXE_ERROR_STRING_1 L"Invalid PCI OROM\r\n"
-#define TEST_POINT_BYTE2_END_OF_DXE_ERROR_CODE_2 L"0x02020002"
-#define TEST_POINT_BYTE2_END_OF_DXE_ERROR_STRING_2 L"Invalid Memory Map\r\n"
-#define TEST_POINT_BYTE2_END_OF_DXE_ERROR_CODE_3 L"0x02020003"
-#define TEST_POINT_BYTE2_END_OF_DXE_ERROR_STRING_3 L"Invalid GCD Map\r\n"
-#define TEST_POINT_BYTE2_END_OF_DXE_ERROR_CODE_4 L"0x02020004"
-#define TEST_POINT_BYTE2_END_OF_DXE_ERROR_STRING_4 L"Invalid Console Variable\r\n"
-#define TEST_POINT_BYTE2_END_OF_DXE_ERROR_CODE_5 L"0x02020005"
-#define TEST_POINT_BYTE2_END_OF_DXE_ERROR_STRING_5 L"Invalid Boot Variable\r\n"
-#define TEST_POINT_BYTE2_DXE_SMM_READY_TO_LOCK BIT2
-#define TEST_POINT_BYTE2_DXE_SMM_READY_TO_LOCK_ERROR_CODE_1 L"0x02040001"
-#define TEST_POINT_BYTE2_DXE_SMM_READY_TO_LOCK_ERROR_STRING_1 L"Invalid SMRAM Information\r\n"
-#define TEST_POINT_BYTE2_READY_TO_BOOT BIT3
-#define TEST_POINT_BYTE2_READY_TO_BOOT_ERROR_CODE_1 L"0x02080001"
-#define TEST_POINT_BYTE2_READY_TO_BOOT_ERROR_STRING_1 L"Invalid Device\r\n"
-#define TEST_POINT_BYTE2_READY_TO_BOOT_ERROR_CODE_2 L"0x02080002"
-#define TEST_POINT_BYTE2_READY_TO_BOOT_ERROR_STRING_2 L"Invalid Memory Type Information\r\n"
-#define TEST_POINT_BYTE2_READY_TO_BOOT_ERROR_CODE_3 L"0x02080003"
-#define TEST_POINT_BYTE2_READY_TO_BOOT_ERROR_STRING_3 L"Invalid UEFI Variable\r\n"
-#define TEST_POINT_BYTE2_READY_TO_BOOT_ERROR_CODE_4 L"0x02080004"
-#define TEST_POINT_BYTE2_READY_TO_BOOT_ERROR_STRING_4 L"Invalid Memory Attribute Table\r\n"
-#define TEST_POINT_BYTE2_READY_TO_BOOT_ERROR_CODE_5 L"0x02080005"
-#define TEST_POINT_BYTE2_READY_TO_BOOT_ERROR_STRING_5 L"Invalid ACPI Table\r\n"
-#define TEST_POINT_BYTE2_READY_TO_BOOT_ERROR_CODE_6 L"0x02080006"
-#define TEST_POINT_BYTE2_READY_TO_BOOT_ERROR_STRING_6 L"Invalid WSMT Table\r\n"
-#define TEST_POINT_BYTE2_READY_TO_BOOT_ERROR_CODE_7 L"0x02080007"
-#define TEST_POINT_BYTE2_READY_TO_BOOT_ERROR_STRING_7 L"Invalid DMAR Table\r\n"
-#define TEST_POINT_BYTE2_READY_TO_BOOT_ERROR_CODE_8 L"0x02080008"
-#define TEST_POINT_BYTE2_READY_TO_BOOT_ERROR_STRING_8 L"Invalid HSTI\r\n"
-#define TEST_POINT_BYTE2_READY_TO_BOOT_ERROR_CODE_9 L"0x02080009"
-#define TEST_POINT_BYTE2_READY_TO_BOOT_ERROR_STRING_9 L"Invalid ESRT\r\n"
-#define TEST_POINT_BYTE2_EXIT_BOOT_SERVICES BIT4
-
-// Byte 3 - SMM
+#define TEST_POINT_BYTE2_PCI_ENUMERATION_DONE_PCI_BUS_MASTER_DISABLED BIT0
+#define TEST_POINT_BYTE2_PCI_ENUMERATION_DONE_RESOURCE_ALLOCATED BIT1
+#define TEST_POINT_BYTE2_END_OF_DXE_NO_THIRD_PARTY_PCI_OPTION_ROM BIT2
+#define TEST_POINT_BYTE2_END_OF_DXE_DMAT_TABLE_FUNCTIONAL BIT3
+#define TEST_POINT_BYTE2_DXE_SMM_READY_TO_LOCK_SMRAM_ALIGNED BIT4
+#define TEST_POINT_BYTE2_DXE_SMM_READY_TO_LOCK_WSMT_TABLE_FUNCTIONAL BIT5
+#define TEST_POINT_BYTE2_PCI_ENUMERATION_DONE_PCI_BUS_MASTER_DISABLED_ERROR_CODE L"0x02000000"
+#define TEST_POINT_BYTE2_PCI_ENUMERATION_DONE_PCI_BUS_MASTER_DISABLED_ERROR_STRING L"PCI Bus Master Enabled\r\n"
+#define TEST_POINT_BYTE2_PCI_ENUMERATION_DONE_PCI_RESOURCE_ALLOCATED_ERROR_CODE L"0x02010000"
+#define TEST_POINT_BYTE2_PCI_ENUMERATION_DONE_PCI_RESOURCE_ALLOCATED_ERROR_STRING L"Invalid PCI Resource\r\n"
+#define TEST_POINT_BYTE2_END_OF_DXE_NO_THIRD_PARTY_PCI_OPTION_ROM_ERROR_CODE L"0x02020000"
+#define TEST_POINT_BYTE2_END_OF_DXE_NO_THIRD_PARTY_PCI_OPTION_ROM_ERROR_STRING L"Third Party Option ROM dispatched\r\n"
+#define TEST_POINT_BYTE2_END_OF_DXE_DMAT_TABLE_FUNCTIONAL_ERROR_CODE L"0x02030000"
+#define TEST_POINT_BYTE2_END_OF_DXE_DMAT_TABLE_FUNCTIONAL_ERROR_STRING L"No DMAR table\r\n"
+#define TEST_POINT_BYTE2_DXE_SMM_READY_TO_LOCK_SMRAM_ALIGNED_ERROR_CODE L"0x02040000"
+#define TEST_POINT_BYTE2_DXE_SMM_READY_TO_LOCK_SMRAM_ALIGNED_ERROR_STRING L"Invalid SMRAM Information\r\n"
+#define TEST_POINT_BYTE2_DXE_SMM_READY_TO_LOCK_WSMT_TABLE_FUNCTIONAL_ERROR_CODE L"0x02050000"
+#define TEST_POINT_BYTE2_DXE_SMM_READY_TO_LOCK_WSMT_TABLE_FUNCTIONAL_ERROR_STRING L"No WSMT table\r\n"
+
+#define TEST_POINT_BYTE3_READY_TO_BOOT_ACPI_TABLE_FUNCTIONAL BIT0
+#define TEST_POINT_BYTE3_READY_TO_BOOT_MEMORY_TYPE_INFORMATION_FUNCTIONAL BIT1
+#define TEST_POINT_BYTE3_READY_TO_BOOT_UEFI_MEMORY_ATTRIBUTE_TABLE_FUNCTIONAL BIT2
+#define TEST_POINT_BYTE3_READY_TO_BOOT_UEFI_BOOT_VARIABLE_FUNCTIONAL BIT3
+#define TEST_POINT_BYTE3_READY_TO_BOOT_UEFI_CONSOLE_VARIABLE_FUNCTIONAL BIT4
+#define TEST_POINT_BYTE3_READY_TO_BOOT_HSTI_TABLE_FUNCTIONAL BIT5
+#define TEST_POINT_BYTE3_READY_TO_BOOT_SMI_HANDLER_INSTRUMENT BIT6
+#define TEST_POINT_BYTE3_READY_TO_BOOT_ACPI_TABLE_FUNCTIONAL_ERROR_CODE L"0x03000000"
+#define TEST_POINT_BYTE3_READY_TO_BOOT_ACPI_TABLE_FUNCTIONAL_ERROR_STRING L"Invalid ACPI Table\r\n"
+#define TEST_POINT_BYTE3_READY_TO_BOOT_MEMORY_TYPE_INFORMATION_FUNCTIONAL_ERROR_CODE L"0x03010000"
+#define TEST_POINT_BYTE3_READY_TO_BOOT_MEMORY_TYPE_INFORMATION_FUNCTIONAL_ERROR_STRING L"Invalid Memory Type Information\r\n"
+#define TEST_POINT_BYTE3_READY_TO_BOOT_UEFI_MEMORY_ATTRIBUTE_TABLE_FUNCTIONAL_ERROR_CODE L"0x03020000"
+#define TEST_POINT_BYTE3_READY_TO_BOOT_UEFI_MEMORY_ATTRIBUTE_TABLE_FUNCTIONAL_ERROR_STRING L"Invalid Memory Attribute Table\r\n"
+#define TEST_POINT_BYTE3_READY_TO_BOOT_UEFI_BOOT_VARIABLE_FUNCTIONAL_ERROR_CODE L"0x03030000"
+#define TEST_POINT_BYTE3_READY_TO_BOOT_UEFI_BOOT_VARIABLE_FUNCTIONAL_ERROR_STRING L"Invalid Boot Variable\r\n"
+#define TEST_POINT_BYTE3_READY_TO_BOOT_UEFI_CONSOLE_VARIABLE_FUNCTIONAL_ERROR_CODE L"0x03040000"
+#define TEST_POINT_BYTE3_READY_TO_BOOT_UEFI_CONSOLE_VARIABLE_FUNCTIONAL_ERROR_STRING L"Invalid Console Variable\r\n"
+#define TEST_POINT_BYTE3_READY_TO_BOOT_HSTI_TABLE_FUNCTIONAL_ERROR_CODE L"0x03050000"
+#define TEST_POINT_BYTE3_READY_TO_BOOT_HSTI_TABLE_FUNCTIONAL_ERROR_STRING L"No HSTI\r\n"
+#define TEST_POINT_BYTE3_READY_TO_BOOT_SMI_HANDLER_INSTRUMENT_ERROR_CODE L"0x03060000"
+#define TEST_POINT_BYTE3_READY_TO_BOOT_SMI_HANDLER_INSTRUMENT_ERROR_STRING L"No SMI Instrument\r\n"
+
+#define TEST_POINT_BYTE4_READY_TO_BOOT_UEFI_SECURE_BOOT_ENABLED BIT0
+#define TEST_POINT_BYTE4_READY_TO_BOOT_PI_SIGNED_FV_BOOT_ENABLED BIT1
+#define TEST_POINT_BYTE4_READY_TO_BOOT_TCG_TRUSTED_BOOT_ENABLED BIT2
+#define TEST_POINT_BYTE4_READY_TO_BOOT_TCG_MOR_ENABLED BIT3
+#define TEST_POINT_BYTE4_READY_TO_BOOT_ESRT_TABLE_FUNCTIONAL BIT4
+#define TEST_POINT_BYTE4_READY_TO_BOOT_UEFI_SECURE_BOOT_ENABLED_ERROR_CODE L"0x04000000"
+#define TEST_POINT_BYTE4_READY_TO_BOOT_UEFI_SECURE_BOOT_ENABLED_ERROR_STRING L"UEFI Secure Boot Disable\r\n"
+#define TEST_POINT_BYTE4_READY_TO_BOOT_PI_SIGNED_FV_BOOT_ENABLED_ERROR_CODE L"0x04010000"
+#define TEST_POINT_BYTE4_READY_TO_BOOT_PI_SIGNED_FV_BOOT_ENABLED_ERROR_STRING L"PI Signed FV Boot Disable\r\n"
+#define TEST_POINT_BYTE4_READY_TO_BOOT_TCG_TRUSTED_BOOT_ENABLED_ERROR_CODE L"0x04020000"
+#define TEST_POINT_BYTE4_READY_TO_BOOT_TCG_TRUSTED_BOOT_ENABLED_ERROR_STRING L"TCG Trusted Boot Disable\r\n"
+#define TEST_POINT_BYTE4_READY_TO_BOOT_TCG_MOR_ENABLED_ERROR_CODE L"0x04030000"
+#define TEST_POINT_BYTE4_READY_TO_BOOT_TCG_MOR_ENABLED_ERROR_STRING L"TCG MOR not enabled\r\n"
+#define TEST_POINT_BYTE4_READY_TO_BOOT_ESRT_TABLE_FUNCTIONAL_ERROR_CODE L"0x04040000"
+#define TEST_POINT_BYTE4_READY_TO_BOOT_ESRT_TABLE_FUNCTIONAL_ERROR_STRING L"No ESRT\r\n"
+
+// Byte 5 - SMM
#define TEST_POINT_SMM_END_OF_DXE L" - SMM End Of DXE - "
#define TEST_POINT_SMM_READY_TO_LOCK L" - SMM Ready To Lock - "
#define TEST_POINT_SMM_READY_TO_BOOT L" - SMM Ready To Boot - "
#define TEST_POINT_SMM_EXIT_BOOT_SERVICES L" - SMM Exit Boot Services - "
-#define TEST_POINT_BYTE3_SMM_END_OF_DXE BIT0
-#define TEST_POINT_BYTE3_SMM_END_OF_DXE_ERROR_CODE_1 L"0x03010001"
-#define TEST_POINT_BYTE3_SMM_END_OF_DXE_ERROR_STRING_1 L"Invalid SMM Image\r\n"
-#define TEST_POINT_BYTE3_SMM_READY_TO_LOCK BIT1
-#define TEST_POINT_BYTE2_SMM_READY_TO_LOCK_ERROR_CODE_1 L"0x03020001"
-#define TEST_POINT_BYTE2_SMM_READY_TO_LOCK_ERROR_STRING_1 L"Invalid SMM Memory Attribute Table\r\n"
-#define TEST_POINT_BYTE2_SMM_READY_TO_LOCK_ERROR_CODE_2 L"0x03020002"
-#define TEST_POINT_BYTE2_SMM_READY_TO_LOCK_ERROR_STRING_2 L"Invalid SMRR\r\n"
-#define TEST_POINT_BYTE3_SMM_READY_TO_BOOT BIT2
-#define TEST_POINT_BYTE3_SMM_EXIT_BOOT_SERVICES BIT3
+#define TEST_POINT_BYTE5_SMM_END_OF_DXE_SMRR_FUNCTIONAL BIT0
+#define TEST_POINT_BYTE5_SMM_READY_TO_LOCK_SMM_MEMORY_ATTRIBUTE_TABLE_FUNCTIONAL BIT1
+#define TEST_POINT_BYTE5_SMM_READY_TO_LOCK_SECURE_SMM_COMMUNICATION_BUFFER BIT2
+#define TEST_POINT_BYTE5_SMM_READY_TO_BOOT_SMM_PAGE_LEVEL_PROTECTION BIT3
+#define TEST_POINT_BYTE5_SMM_END_OF_DXE_SMRR_FUNCTIONAL_ERROR_CODE L"0x05000000"
+#define TEST_POINT_BYTE5_SMM_END_OF_DXE_SMRR_FUNCTIONAL_ERROR_STRING L"Invalid SMRR\r\n"
+#define TEST_POINT_BYTE5_SMM_READY_TO_LOCK_SMM_MEMORY_ATTRIBUTE_TABLE_FUNCTIONAL_ERROR_CODE L"0x05010000"
+#define TEST_POINT_BYTE5_SMM_READY_TO_LOCK_SMM_MEMORY_ATTRIBUTE_TABLE_FUNCTIONAL_ERROR_STRING L"Invalid SMM Memory Attribute Table\r\n"
+#define TEST_POINT_BYTE5_SMM_READY_TO_LOCK_SECURE_SMM_COMMUNICATION_BUFFER_ERROR_CODE L"0x05020000"
+#define TEST_POINT_BYTE5_SMM_READY_TO_LOCK_SECURE_SMM_COMMUNICATION_BUFFER_ERROR_STRING L"Unsecure SMM communication buffer\r\n"
+#define TEST_POINT_BYTE5_SMM_READY_TO_BOOT_SMM_PAGE_LEVEL_PROTECTION_ERROR_CODE L"0x05030000"
+#define TEST_POINT_BYTE5_SMM_READY_TO_BOOT_SMM_PAGE_LEVEL_PROTECTION_ERROR_STRING L"SMM page level protection disabled\r\n"
#pragma pack (1)
@@ -208,7 +355,6 @@ typedef struct { UINT32 Role;
CHAR16 ImplementationID[256];
UINT32 FeaturesSize;
- UINT8 FeaturesRequired[TEST_POINT_FEATURE_SIZE];
UINT8 FeaturesImplemented[TEST_POINT_FEATURE_SIZE];
UINT8 FeaturesVerified[TEST_POINT_FEATURE_SIZE];
CHAR16 End;
|