diff options
Diffstat (limited to 'Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe')
92 files changed, 29065 insertions, 0 deletions
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/AmlOffsetTable.c b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/AmlOffsetTable.c new file mode 100644 index 0000000000..5d8714f589 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/AmlOffsetTable.c @@ -0,0 +1,284 @@ +/*
+ *
+ * Intel ACPI Component Architecture
+ *
+ *
+ */
+#ifndef __AML_OFFSET_TABLE_H
+#define __AML_OFFSET_TABLE_H
+
+typedef struct {
+ char *Pathname; /* Full pathname (from root) to the object */
+ unsigned short ParentOpcode; /* AML opcode for the parent object */
+ unsigned long NamesegOffset; /* Offset of last nameseg in the parent namepath */
+ unsigned char Opcode; /* AML opcode for the data */
+ unsigned long Offset; /* Offset for the data */
+ unsigned long long Value; /* Original value of the data (as applicable) */
+} AML_OFFSET_TABLE_ENTRY;
+
+#endif /* __AML_OFFSET_TABLE_H */
+
+/*
+ * Information specific to the supported object types:
+ *
+ * Integers:
+ * Opcode is the integer prefix, indicates length of the data
+ * (One of: BYTE, WORD, DWORD, QWORD, ZERO, ONE, ONES)
+ * Offset points to the actual integer data
+ * Value is the existing value in the AML
+ *
+ * Packages:
+ * Opcode is the package or var_package opcode
+ * Offset points to the package opcode
+ * Value is the package element count
+ *
+ * Operation Regions:
+ * Opcode is the address integer prefix, indicates length of the data
+ * Offset points to the region address
+ * Value is the existing address value in the AML
+ *
+ * Control Methods:
+ * Offset points to the method flags byte
+ * Value is the existing flags value in the AML
+ *
+ * Processors:
+ * Offset points to the first byte of the PBlock Address
+ *
+ * Resource Descriptors:
+ * Opcode is the descriptor type
+ * Offset points to the start of the descriptor
+ *
+ * Scopes/Devices/ThermalZones:
+ * Nameseg offset only
+ */
+AML_OFFSET_TABLE_ENTRY DSDT_PLATWFP__OffsetTable[] =
+{
+ {"PSYS", 0x5B80, 0x0000038B, 0x0C, 0x00000391, 0x0000000030584946}, /* OPERATIONREGION */
+ {"_SB_.PC00.FIX1", 0x0011, 0x00000000, 0x88, 0x0000D187, 0x0000000000000000}, /* WORDBUSNUMBER */
+ {"_SB_.PC00.FIX2", 0x0011, 0x00000000, 0x88, 0x0000D1AF, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC00.FIX5", 0x0011, 0x00000000, 0x87, 0x0000D1BF, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC00.FIX3", 0x0011, 0x00000000, 0x87, 0x0000D20D, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC00.FIX4", 0x0011, 0x00000000, 0x8A, 0x0000D227, 0x0000000000000000}, /* QWORDMEMORY */
+ {"_SB_.PC01.FIX1", 0x0011, 0x00000000, 0x88, 0x0000EA9B, 0x0000000000000000}, /* WORDBUSNUMBER */
+ {"_SB_.PC01.FIX5", 0x0011, 0x00000000, 0x87, 0x0000EAAB, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC01.FIX2", 0x0011, 0x00000000, 0x88, 0x0000EAC5, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC01.FIX6", 0x0011, 0x00000000, 0x88, 0x0000EAD5, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC01.FIX7", 0x0011, 0x00000000, 0x88, 0x0000EAE5, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC01.FIX3", 0x0011, 0x00000000, 0x87, 0x0000EAF5, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC01.FIX4", 0x0011, 0x00000000, 0x8A, 0x0000EB0F, 0x0000000000000000}, /* QWORDMEMORY */
+ {"_SB_.PC01.BR1A.MCTL", 0x5B80, 0x0000EB91, 0x0C, 0x0000EB97, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC01.BR1B.MCTL", 0x5B80, 0x0000F3B2, 0x0C, 0x0000F3B8, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC01.BR1C.MCTL", 0x5B80, 0x0000FBD3, 0x0C, 0x0000FBD9, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC01.BR1D.MCTL", 0x5B80, 0x000103F4, 0x0C, 0x000103FA, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC02.FIX1", 0x0011, 0x00000000, 0x88, 0x00010E93, 0x0000000000000000}, /* WORDBUSNUMBER */
+ {"_SB_.PC02.FIX5", 0x0011, 0x00000000, 0x87, 0x00010EA3, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC02.FIX2", 0x0011, 0x00000000, 0x88, 0x00010EBD, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC02.FIX6", 0x0011, 0x00000000, 0x88, 0x00010ECD, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC02.FIX7", 0x0011, 0x00000000, 0x88, 0x00010EDD, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC02.FIX3", 0x0011, 0x00000000, 0x87, 0x00010EED, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC02.FIX4", 0x0011, 0x00000000, 0x8A, 0x00010F07, 0x0000000000000000}, /* QWORDMEMORY */
+ {"_SB_.PC02.BR2A.MCTL", 0x5B80, 0x00010F89, 0x0C, 0x00010F8F, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC02.BR2B.MCTL", 0x5B80, 0x00011969, 0x0C, 0x0001196F, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC02.BR2C.MCTL", 0x5B80, 0x0001218A, 0x0C, 0x00012190, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC02.BR2D.MCTL", 0x5B80, 0x000129AB, 0x0C, 0x000129B1, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC03.FIX1", 0x0011, 0x00000000, 0x88, 0x000133E4, 0x0000000000000000}, /* WORDBUSNUMBER */
+ {"_SB_.PC03.FIX5", 0x0011, 0x00000000, 0x87, 0x000133F4, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC03.FIX2", 0x0011, 0x00000000, 0x88, 0x0001340E, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC03.FIX6", 0x0011, 0x00000000, 0x88, 0x0001341E, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC03.FIX7", 0x0011, 0x00000000, 0x88, 0x0001342E, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC03.FIX3", 0x0011, 0x00000000, 0x87, 0x0001343E, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC03.FIX4", 0x0011, 0x00000000, 0x8A, 0x00013458, 0x0000000000000000}, /* QWORDMEMORY */
+ {"_SB_.PC03.BR3A.MCTL", 0x5B80, 0x000134DA, 0x0C, 0x000134E0, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC03.BR3B.MCTL", 0x5B80, 0x00013CFB, 0x0C, 0x00013D01, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC03.BR3C.MCTL", 0x5B80, 0x0001451C, 0x0C, 0x00014522, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC03.BR3D.MCTL", 0x5B80, 0x00014D3D, 0x0C, 0x00014D43, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC04.FIX1", 0x0011, 0x00000000, 0x88, 0x000156F0, 0x0000000000000000}, /* WORDBUSNUMBER */
+ {"_SB_.PC04.FIX5", 0x0011, 0x00000000, 0x87, 0x00015700, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC04.FIX2", 0x0011, 0x00000000, 0x88, 0x0001571A, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC04.FIX6", 0x0011, 0x00000000, 0x88, 0x0001572A, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC04.FIX7", 0x0011, 0x00000000, 0x88, 0x0001573A, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC04.FIX3", 0x0011, 0x00000000, 0x87, 0x0001574A, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC04.FIX4", 0x0011, 0x00000000, 0x8A, 0x00015764, 0x0000000000000000}, /* QWORDMEMORY */
+ {"_SB_.PC04.MCP0.MCTL", 0x5B80, 0x000157E6, 0x0C, 0x000157EC, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC05.FIX1", 0x0011, 0x00000000, 0x88, 0x0001612D, 0x0000000000000000}, /* WORDBUSNUMBER */
+ {"_SB_.PC05.FIX5", 0x0011, 0x00000000, 0x87, 0x0001613D, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC05.FIX2", 0x0011, 0x00000000, 0x88, 0x00016157, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC05.FIX6", 0x0011, 0x00000000, 0x88, 0x00016167, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC05.FIX7", 0x0011, 0x00000000, 0x88, 0x00016177, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC05.FIX3", 0x0011, 0x00000000, 0x87, 0x00016187, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC05.FIX4", 0x0011, 0x00000000, 0x8A, 0x000161A1, 0x0000000000000000}, /* QWORDMEMORY */
+ {"_SB_.PC05.MCP1.MCTL", 0x5B80, 0x00016223, 0x0C, 0x00016229, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC06.FIX1", 0x0011, 0x00000000, 0x88, 0x00016FD9, 0x0000000000000000}, /* WORDBUSNUMBER */
+ {"_SB_.PC06.FIX5", 0x0011, 0x00000000, 0x87, 0x00016FE9, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC06.FIX2", 0x0011, 0x00000000, 0x88, 0x00017003, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC06.FIX6", 0x0011, 0x00000000, 0x88, 0x00017013, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC06.FIX7", 0x0011, 0x00000000, 0x88, 0x00017023, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC06.FIX3", 0x0011, 0x00000000, 0x87, 0x00017033, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC06.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001704D, 0x0000000000000000}, /* QWORDMEMORY */
+ {"_SB_.PC06.QRP0.MCTL", 0x5B80, 0x00017149, 0x0C, 0x0001714F, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC07.FIX1", 0x0011, 0x00000000, 0x88, 0x00017BC4, 0x0000000000000000}, /* WORDBUSNUMBER */
+ {"_SB_.PC07.FIX5", 0x0011, 0x00000000, 0x87, 0x00017BD4, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC07.FIX2", 0x0011, 0x00000000, 0x88, 0x00017BEE, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC07.FIX6", 0x0011, 0x00000000, 0x88, 0x00017BFE, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC07.FIX7", 0x0011, 0x00000000, 0x88, 0x00017C0E, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC07.FIX3", 0x0011, 0x00000000, 0x87, 0x00017C1E, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC07.FIX4", 0x0011, 0x00000000, 0x8A, 0x00017C38, 0x0000000000000000}, /* QWORDMEMORY */
+ {"_SB_.PC07.QR1A.MCTL", 0x5B80, 0x00017CCA, 0x0C, 0x00017CD0, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC07.QR1B.MCTL", 0x5B80, 0x00018506, 0x0C, 0x0001850C, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC07.QR1C.MCTL", 0x5B80, 0x00018D42, 0x0C, 0x00018D48, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC07.QR1D.MCTL", 0x5B80, 0x0001957E, 0x0C, 0x00019584, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC08.FIX1", 0x0011, 0x00000000, 0x88, 0x0001A04E, 0x0000000000000000}, /* WORDBUSNUMBER */
+ {"_SB_.PC08.FIX5", 0x0011, 0x00000000, 0x87, 0x0001A05E, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC08.FIX2", 0x0011, 0x00000000, 0x88, 0x0001A078, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC08.FIX6", 0x0011, 0x00000000, 0x88, 0x0001A088, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC08.FIX7", 0x0011, 0x00000000, 0x88, 0x0001A098, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC08.FIX3", 0x0011, 0x00000000, 0x87, 0x0001A0A8, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC08.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001A0C2, 0x0000000000000000}, /* QWORDMEMORY */
+ {"_SB_.PC08.QR2A.MCTL", 0x5B80, 0x0001A154, 0x0C, 0x0001A15A, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC08.QR2B.MCTL", 0x5B80, 0x0001A990, 0x0C, 0x0001A996, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC08.QR2C.MCTL", 0x5B80, 0x0001B1CC, 0x0C, 0x0001B1D2, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC08.QR2D.MCTL", 0x5B80, 0x0001BA08, 0x0C, 0x0001BA0E, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC09.FIX1", 0x0011, 0x00000000, 0x88, 0x0001C461, 0x0000000000000000}, /* WORDBUSNUMBER */
+ {"_SB_.PC09.FIX5", 0x0011, 0x00000000, 0x87, 0x0001C471, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC09.FIX2", 0x0011, 0x00000000, 0x88, 0x0001C48B, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC09.FIX6", 0x0011, 0x00000000, 0x88, 0x0001C49B, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC09.FIX7", 0x0011, 0x00000000, 0x88, 0x0001C4AB, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC09.FIX3", 0x0011, 0x00000000, 0x87, 0x0001C4BB, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC09.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001C4D5, 0x0000000000000000}, /* QWORDMEMORY */
+ {"_SB_.PC09.QR3A.MCTL", 0x5B80, 0x0001C567, 0x0C, 0x0001C56D, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC09.QR3B.MCTL", 0x5B80, 0x0001CDA3, 0x0C, 0x0001CDA9, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC09.QR3C.MCTL", 0x5B80, 0x0001D5DF, 0x0C, 0x0001D5E5, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC09.QR3D.MCTL", 0x5B80, 0x0001DE1B, 0x0C, 0x0001DE21, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC10.FIX1", 0x0011, 0x00000000, 0x88, 0x0001E7EE, 0x0000000000000000}, /* WORDBUSNUMBER */
+ {"_SB_.PC10.FIX5", 0x0011, 0x00000000, 0x87, 0x0001E7FE, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC10.FIX2", 0x0011, 0x00000000, 0x88, 0x0001E818, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC10.FIX6", 0x0011, 0x00000000, 0x88, 0x0001E828, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC10.FIX7", 0x0011, 0x00000000, 0x88, 0x0001E838, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC10.FIX3", 0x0011, 0x00000000, 0x87, 0x0001E848, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC10.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001E862, 0x0000000000000000}, /* QWORDMEMORY */
+ {"_SB_.PC10.MCP2.MCTL", 0x5B80, 0x0001E8F4, 0x0C, 0x0001E8FA, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC11.FIX1", 0x0011, 0x00000000, 0x88, 0x0001F250, 0x0000000000000000}, /* WORDBUSNUMBER */
+ {"_SB_.PC11.FIX5", 0x0011, 0x00000000, 0x87, 0x0001F260, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC11.FIX2", 0x0011, 0x00000000, 0x88, 0x0001F27A, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC11.FIX6", 0x0011, 0x00000000, 0x88, 0x0001F28A, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC11.FIX7", 0x0011, 0x00000000, 0x88, 0x0001F29A, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC11.FIX3", 0x0011, 0x00000000, 0x87, 0x0001F2AA, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC11.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001F2C4, 0x0000000000000000}, /* QWORDMEMORY */
+ {"_SB_.PC11.MCP3.MCTL", 0x5B80, 0x0001F356, 0x0C, 0x0001F35C, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC12.FIX1", 0x0011, 0x00000000, 0x88, 0x0002011C, 0x0000000000000000}, /* WORDBUSNUMBER */
+ {"_SB_.PC12.FIX5", 0x0011, 0x00000000, 0x87, 0x0002012C, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC12.FIX2", 0x0011, 0x00000000, 0x88, 0x00020146, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC12.FIX6", 0x0011, 0x00000000, 0x88, 0x00020156, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC12.FIX7", 0x0011, 0x00000000, 0x88, 0x00020166, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC12.FIX3", 0x0011, 0x00000000, 0x87, 0x00020176, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC12.FIX4", 0x0011, 0x00000000, 0x8A, 0x00020190, 0x0000000000000000}, /* QWORDMEMORY */
+ {"_SB_.PC12.RRP0.MCTL", 0x5B80, 0x0002028C, 0x0C, 0x00020292, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC13.FIX1", 0x0011, 0x00000000, 0x88, 0x00020D07, 0x0000000000000000}, /* WORDBUSNUMBER */
+ {"_SB_.PC13.FIX5", 0x0011, 0x00000000, 0x87, 0x00020D17, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC13.FIX2", 0x0011, 0x00000000, 0x88, 0x00020D31, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC13.FIX6", 0x0011, 0x00000000, 0x88, 0x00020D41, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC13.FIX7", 0x0011, 0x00000000, 0x88, 0x00020D51, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC13.FIX3", 0x0011, 0x00000000, 0x87, 0x00020D61, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC13.FIX4", 0x0011, 0x00000000, 0x8A, 0x00020D7B, 0x0000000000000000}, /* QWORDMEMORY */
+ {"_SB_.PC13.RR1A.MCTL", 0x5B80, 0x00020E0D, 0x0C, 0x00020E13, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC13.RR1B.MCTL", 0x5B80, 0x00021649, 0x0C, 0x0002164F, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC13.RR1C.MCTL", 0x5B80, 0x00021E85, 0x0C, 0x00021E8B, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC13.RR1D.MCTL", 0x5B80, 0x000226C1, 0x0C, 0x000226C7, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC14.FIX1", 0x0011, 0x00000000, 0x88, 0x0002316F, 0x0000000000000000}, /* WORDBUSNUMBER */
+ {"_SB_.PC14.FIX5", 0x0011, 0x00000000, 0x87, 0x0002317F, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC14.FIX2", 0x0011, 0x00000000, 0x88, 0x00023199, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC14.FIX6", 0x0011, 0x00000000, 0x88, 0x000231A9, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC14.FIX7", 0x0011, 0x00000000, 0x88, 0x000231B9, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC14.FIX3", 0x0011, 0x00000000, 0x87, 0x000231C9, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC14.FIX4", 0x0011, 0x00000000, 0x8A, 0x000231E3, 0x0000000000000000}, /* QWORDMEMORY */
+ {"_SB_.PC14.RR2A.MCTL", 0x5B80, 0x00023275, 0x0C, 0x0002327B, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC14.RR2B.MCTL", 0x5B80, 0x00023AB1, 0x0C, 0x00023AB7, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC14.RR2C.MCTL", 0x5B80, 0x000242ED, 0x0C, 0x000242F3, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC14.RR2D.MCTL", 0x5B80, 0x00024B29, 0x0C, 0x00024B2F, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC15.FIX1", 0x0011, 0x00000000, 0x88, 0x00025582, 0x0000000000000000}, /* WORDBUSNUMBER */
+ {"_SB_.PC15.FIX5", 0x0011, 0x00000000, 0x87, 0x00025592, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC15.FIX2", 0x0011, 0x00000000, 0x88, 0x000255AC, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC15.FIX6", 0x0011, 0x00000000, 0x88, 0x000255BC, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC15.FIX7", 0x0011, 0x00000000, 0x88, 0x000255CC, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC15.FIX3", 0x0011, 0x00000000, 0x87, 0x000255DC, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC15.FIX4", 0x0011, 0x00000000, 0x8A, 0x000255F6, 0x0000000000000000}, /* QWORDMEMORY */
+ {"_SB_.PC15.RR3A.MCTL", 0x5B80, 0x00025688, 0x0C, 0x0002568E, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC15.RR3B.MCTL", 0x5B80, 0x00025EC4, 0x0C, 0x00025ECA, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC15.RR3C.MCTL", 0x5B80, 0x00026700, 0x0C, 0x00026706, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC15.RR3D.MCTL", 0x5B80, 0x00026F3C, 0x0C, 0x00026F42, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC16.FIX1", 0x0011, 0x00000000, 0x88, 0x0002790F, 0x0000000000000000}, /* WORDBUSNUMBER */
+ {"_SB_.PC16.FIX5", 0x0011, 0x00000000, 0x87, 0x0002791F, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC16.FIX2", 0x0011, 0x00000000, 0x88, 0x00027939, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC16.FIX6", 0x0011, 0x00000000, 0x88, 0x00027949, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC16.FIX7", 0x0011, 0x00000000, 0x88, 0x00027959, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC16.FIX3", 0x0011, 0x00000000, 0x87, 0x00027969, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC16.FIX4", 0x0011, 0x00000000, 0x8A, 0x00027983, 0x0000000000000000}, /* QWORDMEMORY */
+ {"_SB_.PC16.MCP4.MCTL", 0x5B80, 0x00027A15, 0x0C, 0x00027A1B, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC17.FIX1", 0x0011, 0x00000000, 0x88, 0x00028371, 0x0000000000000000}, /* WORDBUSNUMBER */
+ {"_SB_.PC17.FIX5", 0x0011, 0x00000000, 0x87, 0x00028381, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC17.FIX2", 0x0011, 0x00000000, 0x88, 0x0002839B, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC17.FIX6", 0x0011, 0x00000000, 0x88, 0x000283AB, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC17.FIX7", 0x0011, 0x00000000, 0x88, 0x000283BB, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC17.FIX3", 0x0011, 0x00000000, 0x87, 0x000283CB, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC17.FIX4", 0x0011, 0x00000000, 0x8A, 0x000283E5, 0x0000000000000000}, /* QWORDMEMORY */
+ {"_SB_.PC17.MCP5.MCTL", 0x5B80, 0x00028477, 0x0C, 0x0002847D, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC18.FIX1", 0x0011, 0x00000000, 0x88, 0x0002923D, 0x0000000000000000}, /* WORDBUSNUMBER */
+ {"_SB_.PC18.FIX5", 0x0011, 0x00000000, 0x87, 0x0002924D, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC18.FIX2", 0x0011, 0x00000000, 0x88, 0x00029267, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC18.FIX6", 0x0011, 0x00000000, 0x88, 0x00029277, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC18.FIX7", 0x0011, 0x00000000, 0x88, 0x00029287, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC18.FIX3", 0x0011, 0x00000000, 0x87, 0x00029297, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC18.FIX4", 0x0011, 0x00000000, 0x8A, 0x000292B1, 0x0000000000000000}, /* QWORDMEMORY */
+ {"_SB_.PC18.SRP0.MCTL", 0x5B80, 0x000293AD, 0x0C, 0x000293B3, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC19.FIX1", 0x0011, 0x00000000, 0x88, 0x00029E28, 0x0000000000000000}, /* WORDBUSNUMBER */
+ {"_SB_.PC19.FIX5", 0x0011, 0x00000000, 0x87, 0x00029E38, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC19.FIX2", 0x0011, 0x00000000, 0x88, 0x00029E52, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC19.FIX6", 0x0011, 0x00000000, 0x88, 0x00029E62, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC19.FIX7", 0x0011, 0x00000000, 0x88, 0x00029E72, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC19.FIX3", 0x0011, 0x00000000, 0x87, 0x00029E82, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC19.FIX4", 0x0011, 0x00000000, 0x8A, 0x00029E9C, 0x0000000000000000}, /* QWORDMEMORY */
+ {"_SB_.PC19.SR1A.MCTL", 0x5B80, 0x00029F2E, 0x0C, 0x00029F34, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC19.SR1B.MCTL", 0x5B80, 0x0002A76A, 0x0C, 0x0002A770, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC19.SR1C.MCTL", 0x5B80, 0x0002AFA6, 0x0C, 0x0002AFAC, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC19.SR1D.MCTL", 0x5B80, 0x0002B7E2, 0x0C, 0x0002B7E8, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC20.FIX1", 0x0011, 0x00000000, 0x88, 0x0002C2B2, 0x0000000000000000}, /* WORDBUSNUMBER */
+ {"_SB_.PC20.FIX5", 0x0011, 0x00000000, 0x87, 0x0002C2C2, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC20.FIX2", 0x0011, 0x00000000, 0x88, 0x0002C2DC, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC20.FIX6", 0x0011, 0x00000000, 0x88, 0x0002C2EC, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC20.FIX7", 0x0011, 0x00000000, 0x88, 0x0002C2FC, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC20.FIX3", 0x0011, 0x00000000, 0x87, 0x0002C30C, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC20.FIX4", 0x0011, 0x00000000, 0x8A, 0x0002C326, 0x0000000000000000}, /* QWORDMEMORY */
+ {"_SB_.PC20.SR2A.MCTL", 0x5B80, 0x0002C3B8, 0x0C, 0x0002C3BE, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC20.SR2B.MCTL", 0x5B80, 0x0002CBF4, 0x0C, 0x0002CBFA, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC20.SR2C.MCTL", 0x5B80, 0x0002D430, 0x0C, 0x0002D436, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC20.SR2D.MCTL", 0x5B80, 0x0002DC6C, 0x0C, 0x0002DC72, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC21.FIX1", 0x0011, 0x00000000, 0x88, 0x0002E6C5, 0x0000000000000000}, /* WORDBUSNUMBER */
+ {"_SB_.PC21.FIX5", 0x0011, 0x00000000, 0x87, 0x0002E6D5, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC21.FIX2", 0x0011, 0x00000000, 0x88, 0x0002E6EF, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC21.FIX6", 0x0011, 0x00000000, 0x88, 0x0002E6FF, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC21.FIX7", 0x0011, 0x00000000, 0x88, 0x0002E70F, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC21.FIX3", 0x0011, 0x00000000, 0x87, 0x0002E71F, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC21.FIX4", 0x0011, 0x00000000, 0x8A, 0x0002E739, 0x0000000000000000}, /* QWORDMEMORY */
+ {"_SB_.PC21.SR3A.MCTL", 0x5B80, 0x0002E7CB, 0x0C, 0x0002E7D1, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC21.SR3B.MCTL", 0x5B80, 0x0002F007, 0x0C, 0x0002F00D, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC21.SR3C.MCTL", 0x5B80, 0x0002F843, 0x0C, 0x0002F849, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC21.SR3D.MCTL", 0x5B80, 0x0003007F, 0x0C, 0x00030085, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC22.FIX1", 0x0011, 0x00000000, 0x88, 0x00030A52, 0x0000000000000000}, /* WORDBUSNUMBER */
+ {"_SB_.PC22.FIX5", 0x0011, 0x00000000, 0x87, 0x00030A62, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC22.FIX2", 0x0011, 0x00000000, 0x88, 0x00030A7C, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC22.FIX6", 0x0011, 0x00000000, 0x88, 0x00030A8C, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC22.FIX7", 0x0011, 0x00000000, 0x88, 0x00030A9C, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC22.FIX3", 0x0011, 0x00000000, 0x87, 0x00030AAC, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC22.FIX4", 0x0011, 0x00000000, 0x8A, 0x00030AC6, 0x0000000000000000}, /* QWORDMEMORY */
+ {"_SB_.PC22.MCP6.MCTL", 0x5B80, 0x00030B58, 0x0C, 0x00030B5E, 0x0000000038584946}, /* OPERATIONREGION */
+ {"_SB_.PC23.FIX1", 0x0011, 0x00000000, 0x88, 0x000314B4, 0x0000000000000000}, /* WORDBUSNUMBER */
+ {"_SB_.PC23.FIX5", 0x0011, 0x00000000, 0x87, 0x000314C4, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC23.FIX2", 0x0011, 0x00000000, 0x88, 0x000314DE, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC23.FIX6", 0x0011, 0x00000000, 0x88, 0x000314EE, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC23.FIX7", 0x0011, 0x00000000, 0x88, 0x000314FE, 0x0000000000000000}, /* WORDIO */
+ {"_SB_.PC23.FIX3", 0x0011, 0x00000000, 0x87, 0x0003150E, 0x0000000000000000}, /* DWORDMEMORY */
+ {"_SB_.PC23.FIX4", 0x0011, 0x00000000, 0x8A, 0x00031528, 0x0000000000000000}, /* QWORDMEMORY */
+ {"_SB_.PC23.MCP7.MCTL", 0x5B80, 0x000315BA, 0x0C, 0x000315C0, 0x0000000038584946}, /* OPERATIONREGION */
+ {NULL,0,0,0,0,0} /* Table terminator */
+};
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c new file mode 100644 index 0000000000..b69bd8ace8 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c @@ -0,0 +1,552 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "BoardAcpiDxe.h"
+
+EFI_STATUS
+PatchDsdtTable (
+ IN OUT EFI_ACPI_COMMON_HEADER *Table
+ );
+
+#pragma optimize("",off)
+
+BIOS_ACPI_PARAM *mAcpiParameter;
+
+EFI_IIO_UDS_PROTOCOL *mIioUds;
+
+UINT32 mNumOfBitShift;
+BOOLEAN mForceX2ApicId;
+BOOLEAN mX2ApicEnabled;
+
+struct SystemMemoryMapHob *mSystemMemoryMap;
+
+SOCKET_MP_LINK_CONFIGURATION mSocketMpLinkConfiguration;
+SOCKET_IIO_CONFIGURATION mSocketIioConfiguration;
+SOCKET_POWERMANAGEMENT_CONFIGURATION mSocketPowermanagementConfiguration;
+
+BOOLEAN mFirstNotify;
+PCH_RC_CONFIGURATION mPchRcConfiguration;
+
+UINT8 mKBPresent = 0;
+UINT8 mMousePresent = 0;
+
+/**
+
+ Locate the first instance of a protocol. If the protocol requested is an
+ FV protocol, then it will return the first FV that contains the ACPI table
+ storage file.
+
+ @param Protocol - The protocol to find.
+ Instance - Return pointer to the first instance of the protocol.
+ Type - The type of protocol to locate.
+
+ @retval EFI_SUCCESS - The function completed successfully.
+ @retval EFI_NOT_FOUND - The protocol could not be located.
+ @retval EFI_OUT_OF_RESOURCES - There are not enough resources to find the protocol.
+
+**/
+EFI_STATUS
+LocateSupportProtocol (
+ IN EFI_GUID *Protocol,
+ IN EFI_GUID *gEfiAcpiMultiTableStorageGuid,
+ OUT VOID **Instance,
+ IN UINT32 Type
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE *HandleBuffer;
+ UINTN NumberOfHandles;
+ EFI_FV_FILETYPE FileType;
+ UINT32 FvStatus;
+ EFI_FV_FILE_ATTRIBUTES Attributes;
+ UINTN Size;
+ UINTN Index;
+
+ FvStatus = 0;
+ //
+ // Locate protocol.
+ //
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ Protocol,
+ NULL,
+ &NumberOfHandles,
+ &HandleBuffer
+ );
+ if (EFI_ERROR (Status)) {
+ //
+ // Defined errors at this time are not found and out of resources.
+ //
+ return Status;
+ }
+ //
+ // Looking for FV with ACPI storage file
+ //
+ for (Index = 0; Index < NumberOfHandles; Index++) {
+ //
+ // Get the protocol on this handle
+ // This should not fail because of LocateHandleBuffer
+ //
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ Protocol,
+ Instance
+ );
+ ASSERT (!EFI_ERROR (Status));
+
+ if (!Type) {
+ //
+ // Not looking for the FV protocol, so find the first instance of the
+ // protocol. There should not be any errors because our handle buffer
+ // should always contain at least one or LocateHandleBuffer would have
+ // returned not found.
+ //
+ break;
+ }
+ //
+ // See if it has the ACPI storage file
+ //
+ Status = ((EFI_FIRMWARE_VOLUME2_PROTOCOL *) (*Instance))->ReadFile (
+ *Instance,
+ gEfiAcpiMultiTableStorageGuid,
+ NULL,
+ &Size,
+ &FileType,
+ &Attributes,
+ &FvStatus
+ );
+
+ //
+ // If we found it, then we are done
+ //
+ if (!EFI_ERROR (Status)) {
+ break;
+ }
+ }
+ //
+ // Our exit status is determined by the success of the previous operations
+ // If the protocol was found, Instance already points to it.
+ //
+ //
+ // Free any allocated buffers
+ //
+ gBS->FreePool (HandleBuffer);
+
+ return Status;
+}
+
+/**
+
+ GC_TODO: add routine description
+
+ @param None
+
+ @retval EFI_SUCCESS - GC_TODO: add retval description
+
+**/
+EFI_STATUS
+PlatformHookInit (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS AcpiParameterAddr;
+ UINT32 RegEax;
+ UINT32 RegEbx;
+ UINT32 RegEcx;
+ UINT32 RegEdx;
+
+ CopyMem (&mSocketMpLinkConfiguration, PcdGetPtr(PcdSocketMpLinkConfigData), sizeof(SOCKET_MP_LINK_CONFIGURATION));
+ CopyMem (&mSocketPowermanagementConfiguration, PcdGetPtr(PcdSocketPowerManagementConfigData), sizeof(SOCKET_POWERMANAGEMENT_CONFIGURATION));
+ CopyMem (&mSocketIioConfiguration, PcdGetPtr(PcdSocketIioConfigData), sizeof(SOCKET_IIO_CONFIGURATION));
+ CopyMem (&mPchRcConfiguration, PcdGetPtr(PcdPchRcConfigurationData), sizeof(PCH_RC_CONFIGURATION));
+
+ DEBUG ((DEBUG_INFO, "mX2ApicEnabled - 0x%x\n", mX2ApicEnabled));
+ DEBUG ((DEBUG_INFO, "mForceX2ApicId - 0x%x\n", mForceX2ApicId));
+
+ {
+ UINT32 Index;
+
+ for (Index = 0; Index < 4; Index++) {
+ AsmCpuidEx(CPUID_EXTENDED_TOPOLOGY, Index, &RegEax, &RegEbx, &RegEcx, &RegEdx);
+ DEBUG ((DEBUG_INFO, "CPUID(0xB - %d) - 0x%08x.0x%08x.0x%08x.0x%08x\n", Index, RegEax, RegEbx, RegEcx, RegEdx));
+ }
+ }
+
+ //
+ // Allocate 256 runtime memory to pass ACPI parameter
+ // This Address must be < 4G because we only have 32bit in the dsdt
+ //
+ AcpiParameterAddr = 0xffffffff;
+ Status = gBS->AllocatePages (
+ AllocateMaxAddress,
+ EfiACPIMemoryNVS,
+ EFI_SIZE_TO_PAGES (sizeof(BIOS_ACPI_PARAM)),
+ &AcpiParameterAddr
+ );
+ ASSERT_EFI_ERROR (Status);
+ mAcpiParameter = (BIOS_ACPI_PARAM *)AcpiParameterAddr;
+
+ DEBUG ((EFI_D_ERROR, "ACPI Parameter Block Address: 0x%X\n", mAcpiParameter));
+ PcdSet64 (PcdAcpiGnvsAddress, (UINT64)(UINTN)mAcpiParameter);
+
+ ZeroMem (mAcpiParameter, sizeof (BIOS_ACPI_PARAM));
+ mAcpiParameter->PlatformId = 0;
+#if MAX_SOCKET > 4
+ mAcpiParameter->IoApicEnable = PcdGet32 (PcdPcIoApicEnable);
+#else
+ mAcpiParameter->IoApicEnable = (PcdGet32 (PcdPcIoApicEnable) << 1) | 1;
+#endif
+ DEBUG((EFI_D_ERROR, "io apic settings:%d\n", mAcpiParameter->IoApicEnable));
+
+ AsmCpuid (CPUID_VERSION_INFO, &RegEax, &RegEbx, &RegEcx, &RegEdx);
+ mAcpiParameter->ProcessorId = (RegEax & 0xFFFF0);
+
+ // support up to 64 threads/socket
+ AsmCpuidEx(CPUID_EXTENDED_TOPOLOGY, 1, &mNumOfBitShift, NULL, NULL, NULL);
+ mNumOfBitShift &= 0x1F;
+
+ // Set the bit shift value for CPU SKU
+ mAcpiParameter->CpuSkuNumOfBitShift = (UINT8) mNumOfBitShift;
+
+ mAcpiParameter->ProcessorApicIdBase[0] = (UINT32) (0 << mNumOfBitShift);
+ mAcpiParameter->ProcessorApicIdBase[1] = (UINT32) (1 << mNumOfBitShift);
+ mAcpiParameter->ProcessorApicIdBase[2] = (UINT32) (2 << mNumOfBitShift);
+ mAcpiParameter->ProcessorApicIdBase[3] = (UINT32) (3 << mNumOfBitShift);
+ mAcpiParameter->ProcessorApicIdBase[4] = (UINT32) (4 << mNumOfBitShift);
+ mAcpiParameter->ProcessorApicIdBase[5] = (UINT32) (5 << mNumOfBitShift);
+ mAcpiParameter->ProcessorApicIdBase[6] = (UINT32) (6 << mNumOfBitShift);
+ mAcpiParameter->ProcessorApicIdBase[7] = (UINT32) (7 << mNumOfBitShift);
+
+ if(mForceX2ApicId) {
+ mAcpiParameter->ProcessorApicIdBase[0] = 0x7F00;
+ mAcpiParameter->ProcessorApicIdBase[1] = 0x7F20;
+ mAcpiParameter->ProcessorApicIdBase[2] = 0x7F40;
+ mAcpiParameter->ProcessorApicIdBase[3] = 0x7F60;
+ mAcpiParameter->ProcessorApicIdBase[4] = 0x7F80;
+ mAcpiParameter->ProcessorApicIdBase[5] = 0x7Fa0;
+ mAcpiParameter->ProcessorApicIdBase[6] = 0x7Fc0;
+ mAcpiParameter->ProcessorApicIdBase[7] = 0x7Fe0;
+
+ if (mNumOfBitShift == 4) {
+ mAcpiParameter->ProcessorApicIdBase[0] = 0x7F00;
+ mAcpiParameter->ProcessorApicIdBase[1] = 0x7F10;
+ mAcpiParameter->ProcessorApicIdBase[2] = 0x7F20;
+ mAcpiParameter->ProcessorApicIdBase[3] = 0x7F30;
+ mAcpiParameter->ProcessorApicIdBase[4] = 0x7F40;
+ mAcpiParameter->ProcessorApicIdBase[5] = 0x7F50;
+ mAcpiParameter->ProcessorApicIdBase[6] = 0x7F60;
+ mAcpiParameter->ProcessorApicIdBase[7] = 0x7F70;
+ } else if(mNumOfBitShift == 6) {
+ mAcpiParameter->ProcessorApicIdBase[0] = 0x7E00;
+ mAcpiParameter->ProcessorApicIdBase[1] = 0x7E20;
+ mAcpiParameter->ProcessorApicIdBase[2] = 0x7E40;
+ mAcpiParameter->ProcessorApicIdBase[3] = 0x7E60;
+ mAcpiParameter->ProcessorApicIdBase[4] = 0x7E80;
+ mAcpiParameter->ProcessorApicIdBase[5] = 0x7Ea0;
+ mAcpiParameter->ProcessorApicIdBase[6] = 0x7Ec0;
+ mAcpiParameter->ProcessorApicIdBase[7] = 0x7Ee0;
+ }
+ }
+
+ //
+ // If SNC is enabled, and NumOfCluster is 2, set the ACPI variable for PXM value
+ //
+ if(mIioUds->IioUdsPtr->SystemStatus.OutSncEn && (mIioUds->IioUdsPtr->SystemStatus.OutNumOfCluster == 2)){
+ mAcpiParameter->SncAnd2Cluster = 1;
+ } else {
+ mAcpiParameter->SncAnd2Cluster = 0;
+ }
+
+ mAcpiParameter->MmCfg = (UINT32)mIioUds->IioUdsPtr->PlatformData.PciExpressBase;
+ mAcpiParameter->TsegSize = (UINT32)(mIioUds->IioUdsPtr->PlatformData.MemTsegSize >> 20);
+
+ return EFI_SUCCESS;
+}
+
+/**
+
+ This function will update any runtime platform specific information.
+ This currently includes:
+ Setting OEM table values, ID, table ID, creator ID and creator revision.
+ Enabling the proper processor entries in the APIC tables.
+
+ @param Table - The table to update
+
+ @retval EFI_SUCCESS - The function completed successfully.
+
+**/
+EFI_STATUS
+PlatformUpdateTables (
+ IN OUT EFI_ACPI_COMMON_HEADER *Table,
+ IN OUT EFI_ACPI_TABLE_VERSION *Version
+ )
+{
+ EFI_STATUS Status;
+
+ Status = EFI_SUCCESS;
+
+ //
+ // By default, a table belongs in all ACPI table versions published.
+ // Some tables will override this because they have different versions of the table.
+ //
+ *Version = EFI_ACPI_TABLE_VERSION_2_0;
+ //
+ // Update the processors in the APIC table
+ //
+ switch (Table->Signature) {
+
+ case EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:
+ //
+ // Patch the memory resource
+ //
+ Status = PatchDsdtTable(Table);
+ break;
+
+ default:
+ ASSERT(FALSE);
+ break;
+ }
+ //
+ //
+ // Update the hardware signature in the FACS structure
+ //
+ //
+ //
+ return Status;
+}
+
+
+
+/**
+
+ GC_TODO: Add function description
+
+ @param Event - GC_TODO: add argument description
+ @param Context - GC_TODO: add argument description
+
+ @retval GC_TODO: add return values
+
+**/
+STATIC
+VOID
+EFIAPI
+OnReadyToBoot (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ UINT32 RegEax;
+ UINT32 RegEbx;
+ UINT32 RegEcx;
+ UINT32 RegEdx;
+
+ if (mFirstNotify) {
+ return ;
+ }
+
+ mFirstNotify = TRUE;
+
+ CopyMem (&mSocketIioConfiguration, PcdGetPtr(PcdSocketIioConfigData), sizeof(SOCKET_IIO_CONFIGURATION));
+ CopyMem (&mSocketPowermanagementConfiguration,PcdGetPtr(PcdSocketPowerManagementConfigData), sizeof(SOCKET_POWERMANAGEMENT_CONFIGURATION));
+ CopyMem (&mPchRcConfiguration, PcdGetPtr(PcdPchRcConfigurationData), sizeof(PCH_RC_CONFIGURATION));
+
+ // CpuPm.Asl: External (CSEN, FieldUnitObj)
+ mAcpiParameter->CStateEnable = !mSocketPowermanagementConfiguration.ProcessorAutonomousCstateEnable;
+ // CpuPm.Asl: External (C3EN, FieldUnitObj)
+ mAcpiParameter->C3Enable = mSocketPowermanagementConfiguration.C3Enable;
+ // CpuPm.Asl: External (C6EN, FieldUnitObj)
+ if (mSocketPowermanagementConfiguration.C6Enable == PPM_AUTO) {
+ mAcpiParameter->C6Enable = 1; //POR Default = Enabled
+ } else {
+ mAcpiParameter->C6Enable = mSocketPowermanagementConfiguration.C6Enable;
+ }
+ if(mAcpiParameter->C6Enable && mAcpiParameter->C3Enable) { //C3 and C6 enable are exclusive
+ mAcpiParameter->C6Enable = 1;
+ mAcpiParameter->C3Enable = 0;
+ }
+ // CpuPm.Asl: External (C7EN, FieldUnitObj)
+ mAcpiParameter->C7Enable = 0;
+ // CpuPm.Asl: External (OSCX, FieldUnitObj)
+ mAcpiParameter->OSCX = mSocketPowermanagementConfiguration.OSCx;
+ // CpuPm.Asl: External (MWOS, FieldUnitObj)
+ mAcpiParameter->MonitorMwaitEnable = 1;
+ // CpuPm.Asl: External (PSEN, FieldUnitObj)
+ mAcpiParameter->PStateEnable = mSocketPowermanagementConfiguration.ProcessorEistEnable;
+ // CpuPm.Asl: External (HWAL, FieldUnitObj)
+ mAcpiParameter->HWAllEnable = 0; //Update in PatchGv3SsdtTable
+
+ mAcpiParameter->KBPresent = mKBPresent;
+ mAcpiParameter->MousePresent = mMousePresent;
+ mAcpiParameter->TStateEnable = mSocketPowermanagementConfiguration.TStateEnable;
+ //Fine grained T state
+ AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &RegEax, &RegEbx, &RegEcx, &RegEdx);
+ if ((RegEax & EFI_FINE_GRAINED_CLOCK_MODULATION) && (mSocketPowermanagementConfiguration.OnDieThermalThrottling > 0)){
+ mAcpiParameter->TStateFineGrained = 1;
+ }
+ if(RegEax & B_CPUID_POWER_MANAGEMENT_EAX_HWP_LVT_INTERRUPT_SUPPORT) {
+ mAcpiParameter->HwpInterrupt = 1;
+ }
+ // CpuPm.Asl: External (HWEN, FieldUnitObj)
+ mAcpiParameter->HWPMEnable = mSocketPowermanagementConfiguration.ProcessorHWPMEnable;
+ // CpuPm.Asl: External (ACEN, FieldUnitObj)
+ mAcpiParameter->AutoCstate = mSocketPowermanagementConfiguration.ProcessorAutonomousCstateEnable;
+
+ mAcpiParameter->EmcaEn = 0;
+
+ mAcpiParameter->PcieAcpiHotPlugEnable = (UINT8) (BOOLEAN) (mSocketIioConfiguration.PcieAcpiHotPlugEnable != 0);
+ //
+ // Initialize USB3 mode from setup data
+ //
+ // If mode != manual control
+ // just copy mode from setup
+ if (mPchRcConfiguration.PchUsbManualMode != 1) {
+ mAcpiParameter->XhciMode = mPchRcConfiguration.PchUsbManualMode;
+ }
+
+}
+
+/**
+
+ Entry point for Acpi platform driver.
+
+ @param ImageHandle - A handle for the image that is initializing this driver.
+ @param SystemTable - A pointer to the EFI system table.
+
+ @retval EFI_SUCCESS - Driver initialized successfully.
+ @retval EFI_LOAD_ERROR - Failed to Initialize or has been loaded.
+ @retval EFI_OUT_OF_RESOURCES - Could not allocate needed resources.
+
+**/
+EFI_STATUS
+EFIAPI
+InstallAcpiBoard (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_STATUS AcpiStatus;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
+ INTN Instance;
+ EFI_ACPI_COMMON_HEADER *CurrentTable;
+ UINTN TableHandle;
+ UINT32 FvStatus;
+ UINT32 Size;
+ EFI_EVENT Event;
+ EFI_ACPI_TABLE_VERSION TableVersion;
+ EFI_HOB_GUID_TYPE *GuidHob;
+
+ mFirstNotify = FALSE;
+
+ TableVersion = EFI_ACPI_TABLE_VERSION_NONE;
+ Instance = 0;
+ CurrentTable = NULL;
+ TableHandle = 0;
+
+ //
+ // Locate the IIO Protocol Interface
+ //
+ Status = gBS->LocateProtocol (&gEfiIioUdsProtocolGuid,NULL,&mIioUds);
+ ASSERT_EFI_ERROR (Status);
+
+ GuidHob = GetFirstGuidHob (&gEfiMemoryMapGuid);
+ ASSERT (GuidHob != NULL);
+ if (GuidHob == NULL) {
+ return EFI_NOT_FOUND;
+ }
+ mSystemMemoryMap = GET_GUID_HOB_DATA(GuidHob);
+
+ PlatformHookInit ();
+
+ //
+ // Find the AcpiTable protocol
+ //
+ Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, &AcpiTable);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Locate the firmware volume protocol
+ //
+ Status = LocateSupportProtocol (
+ &gEfiFirmwareVolume2ProtocolGuid,
+ &gEfiCallerIdGuid,
+ &FwVol,
+ TRUE
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = EFI_SUCCESS;
+ Instance = 0;
+
+ //
+ // Read tables from the storage file.
+ //
+ while (!EFI_ERROR (Status)) {
+ CurrentTable = NULL;
+
+ Status = FwVol->ReadSection (
+ FwVol,
+ &gEfiCallerIdGuid,
+ EFI_SECTION_RAW,
+ Instance,
+ &CurrentTable,
+ (UINTN *) &Size,
+ &FvStatus
+ );
+
+ if (!EFI_ERROR (Status)) {
+ //
+ // Allow platform specific code to reject the table or update it
+ //
+ {
+ //
+ // Perform any table specific updates.
+ //
+ AcpiStatus = PlatformUpdateTables (CurrentTable, &TableVersion);
+ if (!EFI_ERROR (AcpiStatus)) {
+ //
+ // Add the table
+ //
+ TableHandle = 0;
+ if (TableVersion != EFI_ACPI_TABLE_VERSION_NONE) {
+ AcpiStatus = AcpiTable->InstallAcpiTable (
+ AcpiTable,
+ CurrentTable,
+ CurrentTable->Length,
+ &TableHandle
+ );
+ }
+ ASSERT_EFI_ERROR (AcpiStatus);
+ }
+ }
+ //
+ // Increment the instance
+ //
+ Instance++;
+ }
+ }
+
+ Status = EfiCreateEventReadyToBootEx(
+ TPL_NOTIFY,
+ OnReadyToBoot,
+ NULL,
+ &Event
+ );
+
+ //
+ // Finished
+ //
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.h b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.h new file mode 100644 index 0000000000..5e4f293844 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.h @@ -0,0 +1,88 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _ACPI_PLATFORM_H_
+#define _ACPI_PLATFORM_H_
+
+//
+// Statements that include other header files
+//
+#include <PiDxe.h>
+#include <PchAccess.h>
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/Pci.h>
+#include <Protocol/AcpiSystemDescriptionTable.h>
+#include <Acpi/GlobalNvsAreaDef.h>
+#include <Protocol/IioUds.h>
+#include <Protocol/PciIo.h>
+#include <Protocol/FirmwareVolume2.h>
+#include <Protocol/SerialIo.h>
+#include <Protocol/MpService.h>
+#include <Protocol/AcpiTable.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/HobLib.h>
+#include <Library/UefiLib.h>
+#include <Library/PcdLib.h>
+#include <Guid/SetupVariable.h>
+#include <Guid/PchRcVariable.h>
+#include <Guid/SocketVariable.h>
+#include <Guid/HobList.h>
+#include <Guid/MemoryMapData.h>
+#include "Platform.h"
+#include "Register/PchRegsUsb.h"
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PchInfoLib.h>
+
+#include <Uefi/UefiBaseType.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+
+#include <IndustryStandard/Acpi.h>
+
+#include <Protocol/MpService.h>
+
+#include <Protocol/AcpiSystemDescriptionTable.h>
+
+#include <Guid/MemoryMapData.h>
+#include <Guid/GlobalVariable.h>
+
+#include <Platform.h>
+#include <Acpi/GlobalNvsAreaDef.h>
+#include <Protocol/IioUds.h>
+#include <Protocol/CpuIo2.h>
+#include <Protocol/SerialIo.h>
+#include <Protocol/DevicePath.h>
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/AcpiAml.h>
+
+#include <Guid/SocketMpLinkVariable.h>
+#include <Guid/SocketIioVariable.h>
+#include <Guid/SocketPowermanagementVariable.h>
+#include <Guid/SocketCommonRcVariable.h>
+
+#include "Register/PchRegsUsb.h"
+
+#include <Register/Cpuid.h>
+#define EFI_FINE_GRAINED_CLOCK_MODULATION BIT5
+#define B_CPUID_POWER_MANAGEMENT_EAX_HWP_LVT_INTERRUPT_SUPPORT BIT9
+
+#endif
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf new file mode 100644 index 0000000000..c4ec05b15d --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf @@ -0,0 +1,79 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BoardAcpiDxe
+ FILE_GUID = F3253A17-2AFE-419E-A5DA-B95A3F7DAB25
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = InstallAcpiBoard
+
+[Sources]
+ Dsdt/WFPPlatform.asl
+ AmlOffsetTable.c
+ BoardAcpiDxe.c
+ BoardAcpiDxeDsdt.c
+
+[Packages]
+ PurleyOpenBoardPkg/PlatPkg.dec
+ PurleySktPkg/SocketPkg.dec
+ PurleyRcPkg/RcPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ LewisburgPkg/PchRcPkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+
+[LibraryClasses]
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ BaseMemoryLib
+ DebugLib
+ UefiLib
+ UefiRuntimeServicesTableLib
+ HobLib
+ PcdLib
+ BoardAcpiTableLib
+
+[Protocols]
+ gEfiMpServiceProtocolGuid
+ gEfiIioUdsProtocolGuid
+ gEfiGlobalNvsAreaProtocolGuid
+ gEfiPciIoProtocolGuid
+ gEfiFirmwareVolume2ProtocolGuid
+ gEfiAcpiTableProtocolGuid
+ gEfiPciRootBridgeIoProtocolGuid
+
+[Guids]
+ gEfiMemoryMapGuid
+
+[Pcd]
+ gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData
+ gOemSkuTokenSpaceGuid.PcdSocketIioConfigData
+ gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData
+ gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData
+ gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData
+ gOemSkuTokenSpaceGuid.PcdAcpiGnvsAddress
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable
+
+[Depex]
+ gEfiAcpiTableProtocolGuid AND
+ gEfiMpServiceProtocolGuid
+
+[BuildOptions]
+ # add -vr and -so to generate offset.h
+ *_*_*_ASL_FLAGS = -oi -vr -so
+
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxeDsdt.c b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxeDsdt.c new file mode 100644 index 0000000000..df4c62403d --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxeDsdt.c @@ -0,0 +1,522 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+//
+// Statements that include other files
+//
+
+//
+// Statements that include other header files
+//
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/PcdLib.h>
+
+#include <Guid/MemoryMapData.h>
+#include <Guid/GlobalVariable.h>
+
+#include <IndustryStandard/HighPrecisionEventTimerTable.h>
+
+#include <Platform.h>
+#include <Acpi/GlobalNvsAreaDef.h>
+#include <Protocol/IioUds.h>
+#include <Protocol/CpuIo2.h>
+#include <Protocol/SerialIo.h>
+#include <Protocol/DevicePath.h>
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/HighPrecisionEventTimerTable.h>
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
+#include <IndustryStandard/AcpiAml.h>
+
+#include <Guid/SocketMpLinkVariable.h>
+#include <Guid/SocketIioVariable.h>
+#include <Guid/SocketPowermanagementVariable.h>
+#include <Guid/SocketCommonRcVariable.h>
+
+#include "Register/PchRegsUsb.h"
+
+#include <PiDxe.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+
+#include <IndustryStandard/Acpi.h>
+
+#include <Protocol/MpService.h>
+
+#include <Protocol/AcpiSystemDescriptionTable.h>
+
+extern BOOLEAN mCpuOrderSorted;
+
+typedef struct {
+ char *Pathname; /* Full pathname (from root) to the object */
+ unsigned short ParentOpcode; /* AML opcode for the parent object */
+ unsigned long NamesegOffset; /* Offset of last nameseg in the parent namepath */
+ unsigned char Opcode; /* AML opcode for the data */
+ unsigned long Offset; /* Offset for the data */
+ unsigned long long Value; /* Original value of the data (as applicable) */
+} AML_OFFSET_TABLE_ENTRY;
+
+extern AML_OFFSET_TABLE_ENTRY *mAmlOffsetTablePointer;
+extern AML_OFFSET_TABLE_ENTRY DSDT_PLATWFP__OffsetTable[];
+
+#define AML_NAME_OP 0x08
+#define AML_NAME_PREFIX_SIZE 0x06
+#define AML_NAME_DWORD_SIZE 0x0C
+
+#define MEM_ADDR_SHFT_VAL 26 // For 64 MB granularity
+
+#pragma pack(1)
+
+typedef struct {
+ UINT8 DescriptorType;
+ UINT16 ResourceLength;
+ UINT8 ResourceType;
+ UINT8 Flags;
+ UINT8 SpecificFlags;
+ UINT64 Granularity;
+ UINT64 Minimum;
+ UINT64 Maximum;
+ UINT64 TranslationOffset;
+ UINT64 AddressLength;
+} AML_RESOURCE_ADDRESS64;
+
+
+typedef struct {
+ UINT8 DescriptorType;
+ UINT16 ResourceLength;
+ UINT8 ResourceType;
+ UINT8 Flags;
+ UINT8 SpecificFlags;
+ UINT32 Granularity;
+ UINT32 Minimum;
+ UINT32 Maximum;
+ UINT32 TranslationOffset;
+ UINT32 AddressLength;
+} AML_RESOURCE_ADDRESS32;
+
+
+typedef struct {
+ UINT8 DescriptorType;
+ UINT16 ResourceLength;
+ UINT8 ResourceType;
+ UINT8 Flags;
+ UINT8 SpecificFlags;
+ UINT16 Granularity;
+ UINT16 Minimum;
+ UINT16 Maximum;
+ UINT16 TranslationOffset;
+ UINT16 AddressLength;
+} AML_RESOURCE_ADDRESS16;
+
+#pragma pack()
+
+#define PCIE_PORT_4_DEV 0x00
+#define PCIE_PORT_5_DEV 0x00
+
+#define PORTS_PER_SOCKET 0x0F
+#define PCIE_PORT_ALL_FUNC 0x00
+
+typedef struct _PCIE_PORT_INFO {
+ UINT8 Device;
+ UINT8 Stack;
+} PCIE_PORT_INFO;
+
+#pragma optimize("",off)
+
+extern BIOS_ACPI_PARAM *mAcpiParameter;
+
+extern struct SystemMemoryMapHob *mSystemMemoryMap;
+extern EFI_IIO_UDS_PROTOCOL *mIioUds;
+
+
+extern SOCKET_MP_LINK_CONFIGURATION mSocketMpLinkConfiguration;
+extern SOCKET_IIO_CONFIGURATION mSocketIioConfiguration;
+extern SOCKET_POWERMANAGEMENT_CONFIGURATION mSocketPowermanagementConfiguration;
+
+extern UINT32 mNumOfBitShift;
+
+AML_OFFSET_TABLE_ENTRY *mAmlOffsetTablePointer = DSDT_PLATWFP__OffsetTable;
+
+/**
+
+ Update the DSDT table
+
+ @param *TableHeader - The table to be set
+
+ @retval EFI_SUCCESS - DSDT updated
+ @retval EFI_INVALID_PARAMETER - DSDT not updated
+
+**/
+EFI_STATUS
+PatchDsdtTable (
+ IN OUT EFI_ACPI_COMMON_HEADER *Table
+ )
+{
+ PCIE_PORT_INFO PCIEPortDefaults[] = {
+ // DMI/PCIE 0
+ { PCIE_PORT_0_DEV, IIO_CSTACK },
+ //IOU0
+ { PCIE_PORT_1A_DEV, IIO_PSTACK0 },
+ { PCIE_PORT_1B_DEV, IIO_PSTACK0 },
+ { PCIE_PORT_1C_DEV, IIO_PSTACK0 },
+ { PCIE_PORT_1D_DEV, IIO_PSTACK0 },
+ //IOU1
+ { PCIE_PORT_2A_DEV, IIO_PSTACK1 },
+ { PCIE_PORT_2B_DEV, IIO_PSTACK1 },
+ { PCIE_PORT_2C_DEV, IIO_PSTACK1 },
+ { PCIE_PORT_2D_DEV, IIO_PSTACK1 },
+ //IOU2
+ { PCIE_PORT_3A_DEV, IIO_PSTACK2 },
+ { PCIE_PORT_3B_DEV, IIO_PSTACK2 },
+ { PCIE_PORT_3C_DEV, IIO_PSTACK2 },
+ { PCIE_PORT_3D_DEV, IIO_PSTACK2 },
+ //MCP0 and MCP1
+ { PCIE_PORT_4_DEV, IIO_PSTACK3 },
+ { PCIE_PORT_5_DEV, IIO_PSTACK4 }
+ };
+ EFI_STATUS Status;
+ UINT8 *DsdtPointer;
+ UINT32 *Signature;
+ UINT32 Fixes, NodeIndex;
+ UINT8 Counter;
+ UINT16 i; // DSDT_PLATEXRP_OffsetTable LUT entries extends beyond 256!
+ UINT64 MemoryBaseLimit = 0;
+ UINT64 PciHGPEAddr = 0;
+ UINT64 BusDevFunc = 0;
+ UINT64 PcieHpBus = 0;
+ UINT64 PcieHpDev = 0;
+ UINT64 PcieHpFunc= 0;
+ UINT8 PortCount = 0;
+ UINT8 StackNumBus = 0;
+ UINT8 StackNumIo = 0;
+ UINT8 StackNumMem32 = 0;
+ UINT8 StackNumMem64 = 0;
+ UINT8 StackNumVgaIo0 = 1; // Start looking for Stack 1
+ UINT8 StackNumVgaIo1 = 1; // Start looking for Stack 1
+ UINT8 StackNumVgaMmioL = 0;
+ UINT8 Stack = 0;
+ UINT8 CurrSkt = 0, CurrStack = 0;
+ UINT64 IioBusIndex = 0;
+ UINT8 BusBase = 0, BusLimit = 0;
+ UINT16 IoBase = 0, IoLimit = 0;
+ UINT32 MemBase32 = 0, MemLimit32 = 0;
+ UINT64 MemBase64 = 0, MemLimit64 = 0;
+ AML_RESOURCE_ADDRESS16 *AmlResourceAddress16Pointer;
+ AML_RESOURCE_ADDRESS32 *AmlResourceAddress32Pointer;
+ AML_RESOURCE_ADDRESS64 *AmlResourceAddress64Pointer;
+ EFI_ACPI_DESCRIPTION_HEADER *TableHeader;
+
+ Status = EFI_SUCCESS;
+ TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *)Table;
+
+ if (mAmlOffsetTablePointer == NULL) return EFI_INVALID_PARAMETER;
+
+ mAcpiParameter->MemoryBoardBitMask = 0;
+
+ for(Counter = 0; Counter < mSystemMemoryMap->numberEntries; Counter++) {
+ NodeIndex = mSystemMemoryMap->Element[Counter].NodeId;
+ if((mAcpiParameter->MemoryBoardBitMask) & (1 << NodeIndex)){
+ MemoryBaseLimit = mAcpiParameter->MemoryBoardRange[NodeIndex] + LShiftU64(mSystemMemoryMap->Element[Counter].ElementSize, MEM_ADDR_SHFT_VAL);
+ mAcpiParameter->MemoryBoardRange[NodeIndex] = MemoryBaseLimit;
+ } else {
+ mAcpiParameter->MemoryBoardBitMask |= 1 << NodeIndex;
+ MemoryBaseLimit = LShiftU64(mSystemMemoryMap->Element[Counter].BaseAddress, 30);
+ mAcpiParameter->MemoryBoardBase[NodeIndex] = MemoryBaseLimit;
+ MemoryBaseLimit = LShiftU64((mSystemMemoryMap->Element[Counter].BaseAddress + mSystemMemoryMap->Element[Counter].ElementSize), MEM_ADDR_SHFT_VAL);
+ mAcpiParameter->MemoryBoardRange[NodeIndex] = MemoryBaseLimit;
+ }
+ }
+
+ //
+ // Mark all spare memory controllers as 1 in MemSpareMask bitmap.
+ //
+ mAcpiParameter->MemSpareMask = ~mAcpiParameter->MemoryBoardBitMask;
+
+ mAcpiParameter->IioPresentBitMask = 0;
+ mAcpiParameter->SocketBitMask = 0;
+
+ for (Counter = 0; Counter < MAX_SOCKET; Counter++) {
+ if (!mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Counter].Valid) continue;
+ mAcpiParameter->SocketBitMask |= 1 << Counter;
+ mAcpiParameter->IioPresentBitMask |= LShiftU64(mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Counter].stackPresentBitmap, (Counter * 8));
+ for (Stack = 0; Stack < MAX_IIO_STACK; Stack++) {
+ mAcpiParameter->BusBase[Counter * MAX_IIO_STACK + Stack] = mIioUds->IioUdsPtr->PlatformData.IIO_resource[Counter].StackRes[Stack].BusBase;
+ }
+ }
+
+ PciHGPEAddr = mIioUds->IioUdsPtr->PlatformData.PciExpressBase + 0x188;
+ BusDevFunc = 0x00;
+ PcieHpBus = 0;
+ PcieHpDev = 0;
+ PcieHpFunc = 0;
+
+ Fixes = 0;
+ //
+ // Loop through the AML looking for values that we must fix up.
+ //
+ for (i = 0; mAmlOffsetTablePointer[i].Pathname != 0; i++) {
+ //
+ // Point to offset in DSDT for current item in AmlOffsetTable.
+ //
+ DsdtPointer = (UINT8 *) (TableHeader) + mAmlOffsetTablePointer[i].Offset;
+
+ if (mAmlOffsetTablePointer[i].Opcode == AML_DWORD_PREFIX) {
+ //
+ // If Opcode is 0x0C, then operator is Name() or OperationRegion().
+ // (TableHeader + AmlOffsetTable.Offset) is at offset for value to change.
+ //
+ // The assert below confirms that AML structure matches the offsets table.
+ // If not then patching the AML would just corrupt it and result in OS failure.
+ // If you encounter this assert something went wrong in *.offset.h files
+ // generation. Remove the files and rebuild.
+ //
+ ASSERT(DsdtPointer[-1] == mAmlOffsetTablePointer[i].Opcode);
+ //
+ // AmlOffsetTable.Value has FIX tag, so check that to decide what to modify.
+ //
+ Signature = (UINT32 *) (&mAmlOffsetTablePointer[i].Value);
+ switch (*Signature) {
+ //
+ // PSYS - "FIX0" OperationRegion() in Acpi\AcpiTables\Dsdt\CommonPlatform.asi
+ //
+ case (SIGNATURE_32 ('F', 'I', 'X', '0')):
+ DEBUG ((DEBUG_INFO, "FIX0 - 0x%x\n", mAcpiParameter));
+ * (UINT32 *) DsdtPointer = (UINT32) (UINTN) mAcpiParameter;
+ //
+ // "FIX8" OperationRegion() in Acpi\AcpiTables\Dsdt\PcieHp.asi
+ //
+ case (SIGNATURE_32 ('F', 'I', 'X', '8')):
+ Stack = PCIEPortDefaults[PortCount % PORTS_PER_SOCKET].Stack;
+ PcieHpBus = mIioUds->IioUdsPtr->PlatformData.IIO_resource[IioBusIndex].StackRes[Stack].BusBase;
+ PcieHpDev = PCIEPortDefaults[PortCount % PORTS_PER_SOCKET].Device;
+ PcieHpFunc = PCIE_PORT_ALL_FUNC;
+
+ //DEBUG((DEBUG_ERROR,"IioBus = %x, hpDev = %x, HpFunc= %x\n",IioBusIndex, PcieHpDev,PcieHpFunc));
+ PciHGPEAddr &= ~(0xFFFF000); // clear bus device func numbers
+ BusDevFunc = (PcieHpBus << 8) | (PcieHpDev << 3) | PcieHpFunc;
+ * (UINT32 *) DsdtPointer = (UINT32) (UINTN) (PciHGPEAddr + (BusDevFunc << 12));
+ //DEBUG((DEBUG_ERROR,", BusDevFunc= %x, PortCount = %x\n",BusDevFunc, PortCount));
+
+ PortCount++;
+ Fixes++;
+ break;
+
+ default:
+ break;
+ }
+ } else if (mAmlOffsetTablePointer[i].Opcode == AML_INDEX_OP) {
+ //
+ // If Opcode is 0x88, then operator is WORDBusNumber() or WORDIO().
+ // (TableHeader + AmlOffsetTable.Offset) must be cast to AML_RESOURCE_ADDRESS16 to change values.
+ //
+ AmlResourceAddress16Pointer = (AML_RESOURCE_ADDRESS16 *) (DsdtPointer);
+ //
+ // The assert below confirms that AML structure matches the offsets table.
+ // If not then patching the AML would just corrupt it and result in OS failure.
+ // If you encounter this assert something went wrong in *.offset.h files
+ // generation. Remove the files and rebuild.
+ //
+ ASSERT(AmlResourceAddress16Pointer->DescriptorType == mAmlOffsetTablePointer[i].Opcode);
+
+ //
+ // Last 4 chars of AmlOffsetTable.Pathname has FIX tag.
+ //
+ Signature = (UINT32 *) (mAmlOffsetTablePointer[i].Pathname + AsciiStrLen(mAmlOffsetTablePointer[i].Pathname) - 4);
+ switch (*Signature) {
+ //
+ // "FIX1" BUS resource for PCXX in Acpi\AcpiTables\Dsdt\SysBus.asi and PCXX.asi
+ //
+ case (SIGNATURE_32 ('F', 'I', 'X', '1')):
+ CurrSkt = StackNumBus / MAX_IIO_STACK;
+ CurrStack = StackNumBus % MAX_IIO_STACK;
+ BusBase = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].BusBase;
+ BusLimit = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].BusLimit;
+ AmlResourceAddress16Pointer->Granularity = 0;
+ if (BusLimit > BusBase) {
+ AmlResourceAddress16Pointer->Minimum = (UINT16) BusBase;
+ AmlResourceAddress16Pointer->Maximum = (UINT16) BusLimit;
+ AmlResourceAddress16Pointer->AddressLength = (UINT16) (BusLimit - BusBase + 1);
+ }
+ //DEBUG((DEBUG_ERROR,", FIX1 BusBase = 0x%x, BusLimit = 0x%x\n",BusBase, BusLimit));
+ StackNumBus++;
+ Fixes++;
+ break;
+
+ //
+ // "FIX2" IO resource for for PCXX in Acpi\AcpiTables\Dsdt\SysBus.asi and PCXX.asi
+ //
+ case (SIGNATURE_32 ('F', 'I', 'X', '2')):
+ AmlResourceAddress16Pointer->Granularity = 0;
+ CurrSkt = StackNumIo / MAX_IIO_STACK;
+ CurrStack = StackNumIo % MAX_IIO_STACK;
+ IoBase = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].PciResourceIoBase;
+ IoLimit = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].PciResourceIoLimit;
+ if (IoLimit > IoBase) {
+ AmlResourceAddress16Pointer->Minimum = (UINT16) IoBase;
+ AmlResourceAddress16Pointer->Maximum = (UINT16) IoLimit;
+ AmlResourceAddress16Pointer->AddressLength = (UINT16) (IoLimit - IoBase + 1);
+ }
+ //DEBUG((DEBUG_ERROR,", FIX2 IoBase = 0x%x, IoLimit = 0x%x\n",IoBase, IoLimit));
+ StackNumIo++;
+ Fixes++;
+ break;
+
+ //
+ // "FIX6" IO resource for PCXX in Acpi\AcpiTables\Dsdt\PCXX.asi
+ //
+ case (SIGNATURE_32 ('F', 'I', 'X', '6')):
+ AmlResourceAddress16Pointer->Granularity = 0;
+ CurrSkt = StackNumVgaIo0 / MAX_IIO_STACK;
+ CurrStack = StackNumVgaIo0 % MAX_IIO_STACK;
+ if ((mSocketMpLinkConfiguration.LegacyVgaSoc == CurrSkt) &&
+ (mSocketMpLinkConfiguration.LegacyVgaStack == CurrStack)){
+ AmlResourceAddress16Pointer->Minimum = (UINT16) 0x03b0;
+ AmlResourceAddress16Pointer->Maximum = (UINT16) 0x03bb;
+ AmlResourceAddress16Pointer->AddressLength = (UINT16) 0x000C;
+ }
+ StackNumVgaIo0++;
+ Fixes++;
+ break;
+
+ //
+ // "FIX7" IO resource for PCXX in Acpi\AcpiTables\Dsdt\PCXX.asi
+ //
+ case (SIGNATURE_32 ('F', 'I', 'X', '7')):
+ AmlResourceAddress16Pointer->Granularity = 0;
+ CurrSkt = StackNumVgaIo1 / MAX_IIO_STACK;
+ CurrStack = StackNumVgaIo1 % MAX_IIO_STACK;
+ if ((mSocketMpLinkConfiguration.LegacyVgaSoc == CurrSkt) &&
+ (mSocketMpLinkConfiguration.LegacyVgaStack == CurrStack)) {
+ AmlResourceAddress16Pointer->Minimum = (UINT16) 0x03c0;
+ AmlResourceAddress16Pointer->Maximum = (UINT16) 0x03df;
+ AmlResourceAddress16Pointer->AddressLength = (UINT16) 0x0020;
+ }
+ StackNumVgaIo1++;
+ Fixes++;
+ break;
+
+ default:
+ break;
+ }
+ } else if (mAmlOffsetTablePointer[i].Opcode == AML_SIZE_OF_OP) {
+ //
+ // If Opcode is 0x87, then operator is DWORDMemory().
+ // (TableHeader + AmlOffsetTable.Offset) must be cast to AML_RESOURCE_ADDRESS32 to change values.
+ //
+ AmlResourceAddress32Pointer = (AML_RESOURCE_ADDRESS32 *) (DsdtPointer);
+ //
+ // The assert below confirms that AML structure matches the offsets table.
+ // If not then patching the AML would just corrupt it and result in OS failure.
+ // If you encounter this assert something went wrong in *.offset.h files
+ // generation. Remove the files and rebuild.
+ //
+ ASSERT(AmlResourceAddress32Pointer->DescriptorType == mAmlOffsetTablePointer[i].Opcode);
+ //
+ // Last 4 chars of AmlOffsetTable.Pathname has FIX tag.
+ //
+ Signature = (UINT32 *) (mAmlOffsetTablePointer[i].Pathname + AsciiStrLen(mAmlOffsetTablePointer[i].Pathname) - 4);
+ switch (*Signature) {
+ //
+ // "FIX3" PCI32 resource for PCXX in Acpi\AcpiTables\Dsdt\SysBus.asi and PCXX.asi
+ //
+ case (SIGNATURE_32 ('F', 'I', 'X', '3')):
+ AmlResourceAddress32Pointer->Granularity = 0;
+ CurrSkt = StackNumMem32 / MAX_IIO_STACK;
+ CurrStack = StackNumMem32 % MAX_IIO_STACK;
+ MemBase32 = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].PciResourceMem32Base;
+ MemLimit32 = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].PciResourceMem32Limit;
+ if (MemLimit32 > MemBase32) {
+ AmlResourceAddress32Pointer->Minimum = (UINT32) MemBase32;
+ AmlResourceAddress32Pointer->Maximum = (UINT32) MemLimit32;
+ AmlResourceAddress32Pointer->AddressLength = (UINT32) (MemLimit32 - MemBase32 + 1);
+ }
+ //DEBUG((DEBUG_ERROR,", FIX3 MemBase32 = 0x%08x, MemLimit32 = 0x%08x\n",MemBase32, MemLimit32));
+ StackNumMem32++;
+ Fixes++;
+ break;
+
+ //
+ // "FIX5" IO resource for PCXX in Acpi\AcpiTables\Dsdt\PCXX.asi
+ //
+ case (SIGNATURE_32 ('F', 'I', 'X', '5')):
+ AmlResourceAddress32Pointer->Granularity = 0;
+ CurrSkt = StackNumVgaMmioL / MAX_IIO_STACK;
+ CurrStack = StackNumVgaMmioL % MAX_IIO_STACK;
+ if ((mSocketMpLinkConfiguration.LegacyVgaSoc == CurrSkt) &&
+ (mSocketMpLinkConfiguration.LegacyVgaStack == CurrStack)) {
+ AmlResourceAddress32Pointer->Minimum = 0x000a0000;
+ AmlResourceAddress32Pointer->Maximum = 0x000bffff;
+ AmlResourceAddress32Pointer->AddressLength = 0x00020000;
+ }
+ StackNumVgaMmioL++;
+ Fixes++;
+ break;
+
+ default:
+ break;
+ }
+ } else if (mAmlOffsetTablePointer[i].Opcode == AML_CREATE_DWORD_FIELD_OP) {
+ //
+ // If Opcode is 0x8A, then operator is QWORDMemory().
+ // (TableHeader + AmlOffsetTable.Offset) must be cast to AML_RESOURCE_ADDRESS64 to change values.
+ //
+ AmlResourceAddress64Pointer = (AML_RESOURCE_ADDRESS64 *) (DsdtPointer);
+ //
+ // The assert below confirms that AML structure matches the offsets table.
+ // If not then patching the AML would just corrupt it and result in OS failure.
+ // If you encounter this assert something went wrong in *.offset.h files
+ // generation. Remove the files and rebuild.
+ //
+ ASSERT(AmlResourceAddress64Pointer->DescriptorType == mAmlOffsetTablePointer[i].Opcode);
+ //
+ // Last 4 chars of AmlOffsetTable.Pathname has FIX tag.
+ //
+ Signature = (UINT32 *) (mAmlOffsetTablePointer[i].Pathname + AsciiStrLen(mAmlOffsetTablePointer[i].Pathname) - 4);
+ switch (*Signature) {
+ //
+ // "FIX4" PCI64 resource for PCXX in Acpi\AcpiTables\Dsdt\SysBus.asi and PCXX.asi
+ //
+ case (SIGNATURE_32 ('F', 'I', 'X', '4')):
+ DEBUG((DEBUG_ERROR,"Pci64BitResourceAllocation = 0x%x\n",mSocketIioConfiguration.Pci64BitResourceAllocation));
+ if (mSocketIioConfiguration.Pci64BitResourceAllocation) {
+ AmlResourceAddress64Pointer->Granularity = 0;
+ CurrSkt = StackNumMem64 / MAX_IIO_STACK;
+ CurrStack = StackNumMem64 % MAX_IIO_STACK;
+ MemBase64 = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].PciResourceMem64Base;
+ MemLimit64 = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].PciResourceMem64Limit;
+ if (MemLimit64 > MemBase64) {
+ AmlResourceAddress64Pointer->Minimum = (UINT64) MemBase64;
+ AmlResourceAddress64Pointer->Maximum = (UINT64) MemLimit64;
+ AmlResourceAddress64Pointer->AddressLength = (UINT64) (MemLimit64 - MemBase64 + 1);
+ }
+ DEBUG((DEBUG_ERROR,", FIX4 MemBase64 = 0x%x, MemLimit64 = 0x%x\n",MemBase64, MemLimit64));
+ StackNumMem64++;
+ Fixes++;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+ }
+
+ //return Status;
+ return EFI_SUCCESS;
+
+}
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt.inf b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt.inf new file mode 100644 index 0000000000..2c53d67d49 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt.inf @@ -0,0 +1,37 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = Dsdt
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Dsdt/WFPPlatform.asl
+
+[Packages]
+ MdePkg/MdePkg.dec
+ LewisburgPkg/PchRcPkg.dec
+ PurleyOpenBoardPkg/PlatPkg.dec
+ PurleySktPkg/SocketPkg.dec
+ PurleyRcPkg/RcPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+
+[BuildOptions]
+ # add -vr and -so to generate offset.h
+ *_*_*_ASL_FLAGS = -oi -vr -so
+
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl new file mode 100644 index 0000000000..e7986b8670 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl @@ -0,0 +1,25 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+///////////////////////////////////////////////////////////////////////////////////
+//Values are set like this to have ASL compiler reserve enough space for objects
+///////////////////////////////////////////////////////////////////////////////////
+//
+// Available Sleep states
+//
+Name(SS1,0)
+Name(SS2,0)
+Name(SS3,1)
+Name(SS4,1)
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CommonPlatform.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CommonPlatform.asi new file mode 100644 index 0000000000..8e9f2d5375 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CommonPlatform.asi @@ -0,0 +1,233 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "MaxSocket.h"
+
+ //
+ // External declarations
+ // HECI-1/HECI-2 are in PurleyPlatPkg\Me\Sps\Acpi\SpsNm.asl
+ //
+ External(\_SB.PC00.HEC2.HPTS, MethodObj)
+ External(\_SB.PC00.HEC2.HWAK, MethodObj)
+
+ //
+ // System Sleep States
+ //
+ Name (\_S0,Package (){0,0,0,0})
+ Name (\_S3,Package (){5,0,0,0}) // Name changed to \DS3 if disabled in Setup
+ Name (\_S4,Package (){6,0,0,0}) // Name changed to \DS4 if disabled in Setup
+ Name (\_S5,Package (){7,0,0,0})
+
+ //
+ // Native OS hot plug support, 0->ACPI, 1->OS
+ //
+ Name (\OSHF, 0)
+
+ //
+ // OS flag
+ //
+ #include "Os.asi"
+
+ //
+ // for determing PIC mode
+ //
+ Name (\PICM,Zero)
+ Method (\_PIC, 1, NotSerialized) {
+ Store(Arg0,\PICM)
+ }
+
+ OperationRegion (DBG0, SystemIO, 0x80, 2)
+ Field (DBG0, ByteAcc,NoLock,Preserve) {
+ IO80, 8,
+ IO81, 8
+ }
+
+ //
+ // Access CMOS range
+ //
+ OperationRegion (ACMS, SystemIO, 0x72, 2)
+ Field ( ACMS, ByteAcc, NoLock, Preserve) {
+ INDX, 8,
+ DATA, 8
+ }
+
+ //
+ // SWGPE_CTRL
+ //
+ OperationRegion (GPCT, SystemIO, 0x442, 1)
+ Field ( GPCT, ByteAcc, NoLock, Preserve) {
+ , 1,
+ SGPC , 1,
+ }
+
+ //
+ // GPI_INV
+ //
+ OperationRegion (GPIV, SystemIO, 0x52c, 2)
+ Field ( GPIV, ByteAcc, NoLock, Preserve) {
+ GP0I , 1,
+ }
+
+#include "Acpi/GlobalNvs.asi"
+
+ //
+ // Operation region for GPI status bits
+ //
+ OperationRegion (GSTS, SystemIO, 0x422, 2)
+ Field ( GSTS, ByteAcc, NoLock, Preserve) {
+ GP00 , 1,
+ , 12,
+ GP13 , 1,
+ }
+
+ //
+ // GPE0 HOT_PLUG_EN
+ //
+ OperationRegion (GPE0, SystemIO, 0x428, 8)
+ Field (GPE0, ByteAcc,NoLock,Preserve) {
+ ,1,
+ GPEH,1,
+ ,1,
+ USB1,1,
+ USB2,1,
+ USB5,1,
+ ,3,
+ PCIE,1,
+ ,1,
+ PMEE,1,
+ USB3,1,
+ PMB0,1,
+ USB4,1,
+ ,9,
+ ,1,
+ ,7,
+ USB6,1,
+ ,15,
+ }
+
+ //
+ // GPES Status
+ //
+ OperationRegion (GPES, SystemIO, 0x420, 8)
+ Field (GPES, ByteAcc,NoLock,Preserve) {
+ ,1,
+ GPSH,1,
+ SGPS,1,
+ US1S,1,
+ US2S,1,
+ US5S,1,
+ ,1,
+ SMWS,1,
+ ,1,
+ PEES,1,
+ ,1,
+ PMES,1,
+
+ US3S ,1,
+ PMBS,1,
+ US4S ,1,
+ ,9,
+ ,1,
+ ,7,
+ US6S,1,
+ ,15,
+ }
+
+ //
+ // System sleep down
+ //
+ Method (_PTS, 1, NotSerialized)
+ {
+ Store (0x72, IO80) // Sync with EfiPostCode.h
+
+ //
+ // Clear wake event status.
+ //
+ Store(1,US1S)
+ Store(1,US2S)
+ Store(1,US5S)
+ Store(1,SMWS)
+ Store(1,PMES)
+ Store(1,US3S)
+ Store(1,PMBS)
+ Store(1,US4S)
+ Store(1,US6S)
+
+ //
+ // Enable SCI and wake event sources.
+ //
+ Store(1,GPEH)
+ Store(1,USB1)
+ Store(1,USB2)
+ Store(1,USB5)
+ Store(1,PCIE)
+ Store(1,PMEE)
+ Store(1,USB3)
+ Store(1,PMB0)
+ Store(1,USB4)
+ Store(1,USB6)
+
+ //
+ // If HECI-2 exist call its prepare-to-sleep handler.
+ // The handler checks whether HECI-2 is enabled.
+ //
+ If (CondRefOf(\_SB.PC00.HEC2.HPTS))
+ {
+ \_SB.PC00.HEC2.HPTS()
+ }
+
+ /// WA for S3 on XHCI
+ \_SB.PC00.XHCI.XHCS()
+ }
+
+ //#include "Uncore.asi"
+
+ //
+ // System Wake up
+ //
+ Method (_WAK, 1, Serialized)
+ {
+ Store (0x73, IO80) // Sync with EfiPostCode.h
+
+ //
+ // If HECI-2 exist call its wake-up handler.
+ // The handler checks whether HECI-2 is enabled.
+ //
+ If (CondRefOf(\_SB.PC00.HEC2.HWAK))
+ {
+ \_SB.PC00.HEC2.HWAK()
+ }
+
+ //
+ // If waking from S3
+ //
+ If (LEqual(Arg0, 3)) {
+ }
+
+ Return(Package(){0, 0})
+ }
+
+ Scope(\_SB) {
+
+ // Information on CPU and Memory for hotplug SKUs
+ // #include "CpuMemHp.asi"
+
+ OperationRegion (IOB2, SystemIO, 0xB2, 2) //MKF_SMIPORT
+ Field (IOB2, ByteAcc, NoLock, Preserve) {
+ SMIC, 8, // SW-SMI ctrl port
+ SMIS, 8, // SW-SMI status port
+ }
+
+ } // end _SB scope
+
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.asl new file mode 100644 index 0000000000..427be161b5 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.asl @@ -0,0 +1,83 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+// Comment out includes as ifdefs don't work at trim stage
+
+//
+//
+
+Scope(\_SB) {
+ //
+ //---------------------------------------------------------------------------
+ // List of IRQ resource buffers compatible with _PRS return format.
+ //---------------------------------------------------------------------------
+ // Naming legend:
+ // RSxy, PRSy - name of the IRQ resource buffer to be returned by _PRS, "xy" - last two characters of IRQ Link name.
+ // Note. PRSy name is generated if IRQ Link name starts from "LNK".
+ // HLxy , LLxy - reference names, can be used to access bit mask of available IRQs. HL and LL stand for active High(Low) Level triggered Irq model.
+ //---------------------------------------------------------------------------
+ Name(PRSA, ResourceTemplate(){ // Link name: LNKA
+ IRQ(Level, ActiveLow, Shared, LLKA) {3,4,5,6,10,11,12,14,15}
+ })
+ Alias(PRSA,PRSB) // Link name: LNKB
+ Alias(PRSA,PRSC) // Link name: LNKC
+ Alias(PRSA,PRSD) // Link name: LNKD
+ Alias(PRSA,PRSE) // Link name: LNKE
+ Alias(PRSA,PRSF) // Link name: LNKF
+ Alias(PRSA,PRSG) // Link name: LNKG
+ Alias(PRSA,PRSH) // Link name: LNKH
+}
+
+//
+//
+
+ Scope(\_SB.PC00) {
+ //
+ // PCI-specific method's GUID
+ //
+ Name(PCIG, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))
+ //
+ // PCI's _DSM - an attempt at modular _DSM implementation
+ // When writing your own _DSM function that needs to include PCI-specific methods, do this:
+ //
+ // Method(_YOUR_DSM,4){
+ // if(Lequal(Arg0,PCIG)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }
+ // ...continue your _DSM by checking different GUIDs...
+ // else { return(0) }
+ // }
+ //
+ Method(PCID, 4, Serialized) {
+ If(LEqual(Arg0, PCIG)) { // PCIE capabilities UUID
+ If(LGreaterEqual(Arg1,3)) { // revision at least 3
+ If(LEqual(Arg2,0)) { Return (Buffer(2){0x01,0x03}) } // function 0: list of supported functions
+ If(LEqual(Arg2,8)) { Return (1) } // function 8: Avoiding Power-On Reset Delay Duplication on Sx Resume
+ If(LEqual(Arg2,9)) { Return (Package(5){50000,Ones,Ones,50000,Ones}) } // function 9: Specifying Device Readiness Durations
+ }
+ }
+ return (Buffer(1){0})
+ }
+ }//scope
+Scope(\_SB.PC00) {
+ //PciCheck, Arg0=UUID, returns true if support for 'PCI delays optimization ECR' is enabled and the UUID is correct
+ Method(PCIC,1,Serialized) {
+ If(LEqual(ECR1,1)) {
+ If(LEqual(Arg0, PCIG)) {
+ return (1)
+ }
+ }
+ return (0)
+ }
+}
+
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl new file mode 100644 index 0000000000..b2986a16a7 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl @@ -0,0 +1,140 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ // General Purpose Events. This Scope handles the Run-time and
+ // Wake-time SCIs. The specific method called will be determined by
+ // the _Lxx value, where xx equals the bit location in the General
+ // Purpose Event register(s).
+
+ //
+ // If the Root Port is enabled, run PCI_EXP_STS handler
+ //
+ If(LNotEqual(\_SB.PC00.RP01.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP01.HPME()
+ Notify(\_SB.PC00.RP01, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP02.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP02.HPME()
+ Notify(\_SB.PC00.RP02, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP03.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP03.HPME()
+ Notify(\_SB.PC00.RP03, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP04.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP04.HPME()
+ Notify(\_SB.PC00.RP04, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP05.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP05.HPME()
+ Notify(\_SB.PC00.RP05, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP06.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP06.HPME()
+ Notify(\_SB.PC00.RP06, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP07.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP07.HPME()
+ Notify(\_SB.PC00.RP07, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP08.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP08.HPME()
+ Notify(\_SB.PC00.RP08, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP09.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP09.HPME()
+ Notify(\_SB.PC00.RP09, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP10.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP10.HPME()
+ Notify(\_SB.PC00.RP10, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP11.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP11.HPME()
+ Notify(\_SB.PC00.RP11, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP12.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP12.HPME()
+ Notify(\_SB.PC00.RP12, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP13.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP13.HPME()
+ Notify(\_SB.PC00.RP13, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP14.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP14.HPME()
+ Notify(\_SB.PC00.RP14, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP15.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP15.HPME()
+ Notify(\_SB.PC00.RP15, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP16.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP16.HPME()
+ Notify(\_SB.PC00.RP16, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP17.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP17.HPME()
+ Notify(\_SB.PC00.RP17, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP18.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP18.HPME()
+ Notify(\_SB.PC00.RP18, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP19.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP19.HPME()
+ Notify(\_SB.PC00.RP19, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP20.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP20.HPME()
+ Notify(\_SB.PC00.RP20, 0x02)
+ }
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/HostBus.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/HostBus.asl new file mode 100644 index 0000000000..27a997cbfb --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/HostBus.asl @@ -0,0 +1,262 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+//
+// Define various System Agent (SA) PCI Configuration Space
+// registers which will be used to dynamically produce all
+// resources in the Host Bus _CRS.
+//
+OperationRegion (HBUS, PCI_Config, 0x00, 0x100)
+Field (HBUS, DWordAcc, NoLock, Preserve)
+{
+ Offset(0x40), // EPBAR (0:0:0:40)
+ EPEN, 1, // Enable
+ , 11,
+ EPBR, 20, // EPBAR [31:12]
+
+ Offset(0x48), // MCHBAR (0:0:0:48)
+ MHEN, 1, // Enable
+ , 14,
+ MHBR, 17, // MCHBAR [31:15]
+
+ Offset(0x50), // GGC (0:0:0:50)
+ GCLK, 1, // GGCLCK
+
+ Offset(0x54), // DEVEN (0:0:0:54)
+ D0EN, 1, // DEV0 Enable
+ D1F2, 1, // DEV1 FUN2 Enable
+ D1F1, 1, // DEV1 FUN1 Enable
+ D1F0, 1, // DEV1 FUN0 Enable
+
+ Offset(0x60), // PCIEXBAR (0:0:0:60)
+ PXEN, 1, // Enable
+ PXSZ, 2, // PCI Express Size
+ , 23,
+ PXBR, 6, // PCI Express BAR [31:26]
+
+ Offset(0x68), // DMIBAR (0:0:0:68)
+ DIEN, 1, // Enable
+ , 11,
+ DIBR, 20, // DMIBAR [31:12]
+
+ Offset(0x70), // MESEG_BASE (0:0:0:70)
+ , 20,
+ MEBR, 12, // MESEG_BASE [31:20]
+
+ Offset(0x80), // PAM0 Register (0:0:0:80)
+ , 4,
+ PM0H, 2, // PAM 0, High Nibble
+ , 2,
+
+ Offset(0x81), // PAM1 Register (0:0:0:81)
+ PM1L, 2, // PAM1, Low Nibble
+ , 2,
+ PM1H, 2, // PAM1, High Nibble
+ , 2,
+
+ Offset(0x82), // PAM2 Register (0:0:0:82)
+ PM2L, 2, // PAM2, Low Nibble
+ , 2,
+ PM2H, 2, // PAM2, High Nibble
+ , 2,
+
+ Offset(0x83), // PAM3 Register (0:0:0:83)
+ PM3L, 2, // PAM3, Low Nibble
+ , 2,
+ PM3H, 2, // PAM3, High Nibble
+ , 2,
+
+ Offset(0x84), // PAM4 Register (0:0:0:84)
+ PM4L, 2, // PAM4, Low Nibble
+ , 2,
+ PM4H, 2, // PAM4, High Nibble
+ , 2,
+
+ Offset(0x85), // PAM5 Register (0:0:0:85)
+ PM5L, 2, // PAM5, Low Nibble
+ , 2,
+ PM5H, 2, // PAM5, High Nibble
+ , 2,
+
+ Offset(0x86), // PAM6 Register (0:0:0:86)
+ PM6L, 2, // PAM6, Low Nibble
+ , 2,
+ PM6H, 2, // PAM6, High Nibble
+ , 2,
+
+ Offset(0xA8), // Top of Upper Usable DRAM Register (0:0:0:A8)
+ , 20,
+ TUUD, 19, // TOUUD [38:20]
+
+ Offset(0xBC), // Top of Lower Usable DRAM Register (0:0:0:BC)
+ , 20,
+ TLUD, 12, // TOLUD [31:20]
+
+ Offset(0xC8), // ERRSTS register (0:0:0:C8)
+ , 7,
+ HTSE, 1 // Host Thermal Sensor Event for SMI/SCI/SERR
+}
+//
+// Define a buffer that will store all the bus, memory, and IO information
+// relating to the Host Bus. This buffer will be dynamically altered in
+// the _CRS and passed back to the OS.
+//
+Name(BUF0,ResourceTemplate()
+{
+ //
+ // Bus Number Allocation: Bus 0 to 0xFF
+ //
+ WORDBusNumber(ResourceProducer,MinFixed,MaxFixed,PosDecode,0x00,
+ 0x0000,0x00FF,0x00,0x0100,,,PB00)
+
+ //
+ // I/O Region Allocation 0 ( 0x0000 - 0x0CF7 )
+ //
+ DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange,
+ 0x00,0x0000,0x0CF7,0x00,0x0CF8,,,PI00)
+
+ //
+ // PCI Configuration Registers ( 0x0CF8 - 0x0CFF )
+ //
+ Io(Decode16,0x0CF8,0x0CF8,1,0x08)
+
+ //
+ // I/O Region Allocation 1 ( 0x0D00 - 0xFFFF )
+ //
+ DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange,
+ 0x00,0x0D00,0xFFFF,0x00,0xF300,,,PI01)
+
+ //
+ // Video Buffer Area ( 0xA0000 - 0xBFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xA0000,0xBFFFF,0x00,0x20000,,,A000)
+
+ //
+ // ISA Add-on BIOS Area ( 0xC0000 - 0xC3FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xC0000,0xC3FFF,0x00,0x4000,,,C000)
+
+ //
+ // ISA Add-on BIOS Area ( 0xC4000 - 0xC7FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xC4000,0xC7FFF,0x00,0x4000,,,C400)
+
+ //
+ // ISA Add-on BIOS Area ( 0xC8000 - 0xCBFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xC8000,0xCBFFF,0x00,0x4000,,,C800)
+
+ //
+ // ISA Add-on BIOS Area ( 0xCC000 - 0xCFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xCC000,0xCFFFF,0x00,0x4000,,,CC00)
+
+ //
+ // ISA Add-on BIOS Area ( 0xD0000 - 0xD3FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xD0000,0xD3FFF,0x00,0x4000,,,D000)
+
+ //
+ // ISA Add-on BIOS Area ( 0xD4000 - 0xD7FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xD4000,0xD7FFF,0x00,0x4000,,,D400)
+
+ //
+ // ISA Add-on BIOS Area ( 0xD8000 - 0xDBFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xD8000,0xDBFFF,0x00,0x4000,,,D800)
+
+ //
+ // ISA Add-on BIOS Area ( 0xDC000 - 0xDFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xDC000,0xDFFFF,0x00,0x4000,,,DC00)
+
+ //
+ // BIOS Extension Area ( 0xE0000 - 0xE3FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xE0000,0xE3FFF,0x00,0x4000,,,E000)
+
+ //
+ // BIOS Extension Area ( 0xE4000 - 0xE7FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xE4000,0xE7FFF,0x00,0x4000,,,E400)
+
+ //
+ // BIOS Extension Area ( 0xE8000 - 0xEBFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xE8000,0xEBFFF,0x00,0x4000,,,E800)
+
+ //
+ // BIOS Extension Area ( 0xEC000 - 0xEFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xEC000,0xEFFFF,0x00,0x4000,,,EC00)
+
+ //
+ // BIOS Area ( 0xF0000 - 0xFFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xF0000,0xFFFFF,0x00,0x10000,,,F000)
+
+// //
+// // Memory Hole Region ( 0xF00000 - 0xFFFFFF )
+// //
+// DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+// ReadWrite,0x00,0xF00000,0xFFFFFF,0x00,0x100000,,,HOLE)
+
+ //
+ // PCI Memory Region ( TOLUD - 0xFEAFFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0x00000000,0xFEAFFFFF,0x00,0xFEB00000,,,PM01)
+
+ //
+ // PCI Memory Region ( TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE) )
+ // (This is dummy range for OS compatibility, will patch it in _CRS)
+ //
+ QWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0x10000,0x1FFFF,0x00,0x10000,,,PM02)
+})
+
+Name(EP_B, 0) // to store EP BAR
+Name(MH_B, 0) // to store MCH BAR
+Name(PC_B, 0) // to store PCIe BAR
+Name(PC_L, 0) // to store PCIe BAR Length
+Name(DM_B, 0) // to store DMI BAR
+
+
+//
+// Get PCIe BAR
+//
+Method(GPCB,0,Serialized)
+{
+ if(LEqual(PC_B,0))
+ {
+ //ShiftLeft(\_SB.PC00.PXBR,26,PC_B)
+ Store(MCFG,PC_B)
+ }
+ Return(PC_B)
+}
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieHotPlugGpeHandler.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieHotPlugGpeHandler.asl new file mode 100644 index 0000000000..03a7d13c2e --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieHotPlugGpeHandler.asl @@ -0,0 +1,848 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ //
+ // Delay introduced as initial delay after entering ACPI hotplug method
+ //
+ Sleep (200)
+ Store (0x01, IO80)
+ Sleep (10)
+ Store (0,Local1)
+
+ // PC01 Port 1A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC01.BR1A.PMEP,1) ) {
+ Store(\_SB.PC01.BR1A.PMEH(1), Local0)
+ } else {
+ Store (\_SB.PC01.BR1A.HPEH(1), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(1, Local1)
+ Notify(\_SB.PC01.BR1A, Local0)
+ }
+
+ // PC01 Port 1B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC01.BR1B.PMEP,1) ) {
+ Store(\_SB.PC01.BR1B.PMEH(2), Local0)
+ } else {
+ Store (\_SB.PC01.BR1B.HPEH(2), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(2, Local1)
+ Notify(\_SB.PC01.BR1B, Local0)
+ }
+
+ // PC01 Port 1C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC01.BR1C.PMEP,1) ) {
+ Store(\_SB.PC01.BR1C.PMEH(3), Local0)
+ } else {
+ Store (\_SB.PC01.BR1C.HPEH(3), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(3, Local1)
+ Notify(\_SB.PC01.BR1C, Local0)
+ }
+
+ // PC01 Port 1D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC01.BR1D.PMEP,1) ) {
+ Store(\_SB.PC01.BR1D.PMEH(4), Local0)
+ } else {
+ Store (\_SB.PC01.BR1D.HPEH(4), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(4, Local1)
+ Notify(\_SB.PC01.BR1D, Local0)
+ }
+
+ // PC02 Port 2A PCI-Ex Hot Plug
+ If( LEqual(\_SB.PC02.BR2A.PMEP,1) ) {
+ Store(\_SB.PC02.BR2A.PMEH(5), Local0)
+ } else {
+ Store (\_SB.PC02.BR2A.HPEH(5), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(5, Local1)
+ Notify(\_SB.PC02.BR2A, Local0)
+ }
+
+ // PC02 Port 2B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC02.BR2B.PMEP,1) ) {
+ Store(\_SB.PC02.BR2B.PMEH(6), Local0)
+ } else {
+ Store (\_SB.PC02.BR2B.HPEH(6), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(6, Local1)
+ Notify(\_SB.PC02.BR2B, Local0)
+ }
+
+ // PC02 Port 2C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC02.BR2C.PMEP,1) ) {
+ Store(\_SB.PC02.BR2C.PMEH(7), Local0)
+ } else {
+ Store (\_SB.PC02.BR2C.HPEH(7), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(7, Local1)
+ Notify(\_SB.PC02.BR2C, Local0)
+ }
+
+ // PC02 Port 2D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC02.BR2D.PMEP,1) ) {
+ Store(\_SB.PC02.BR2D.PMEH(8), Local0)
+ } else {
+ Store (\_SB.PC02.BR2D.HPEH(8), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(8, Local1)
+ Notify(\_SB.PC02.BR2D, Local0)
+ }
+
+ // PC03 Port 3A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC03.BR3A.PMEP,1) ) {
+ Store(\_SB.PC03.BR3A.PMEH(9), Local0)
+ } else {
+ Store (\_SB.PC03.BR3A.HPEH(9), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(9, Local1)
+ Notify(\_SB.PC03.BR3A, Local0)
+ }
+
+ // PC03 Port 3B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC03.BR3B.PMEP,10) ) {
+ Store(\_SB.PC03.BR3B.PMEH(10), Local0)
+ } else {
+ Store (\_SB.PC03.BR3B.HPEH(10), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(10, Local1)
+ Notify(\_SB.PC03.BR3B, Local0)
+ }
+
+ // PC03 Port 3C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC03.BR3C.PMEP,1) ) {
+ Store(\_SB.PC03.BR3C.PMEH(11), Local0)
+ } else {
+ Store (\_SB.PC03.BR3C.HPEH(11), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(11, Local1)
+ Notify(\_SB.PC03.BR3C, Local0)
+ }
+
+ // PC03 Port 3D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC03.BR3D.PMEP,1) ) {
+ Store(\_SB.PC03.BR3D.PMEH(12), Local0)
+ } else {
+ Store (\_SB.PC03.BR3D.HPEH(12), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(12, Local1)
+ Notify(\_SB.PC03.BR3D, Local0)
+ }
+
+ // PC06 Port 0 PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC06.QRP0.PMEP,1) ) {
+ Store(\_SB.PC06.QRP0.PMEH(1), Local0)
+ } else {
+ Store (\_SB.PC06.QRP0.HPEH(1), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(1, Local1)
+ Notify(\_SB.PC06.QRP0, Local0)
+ }
+
+ // PC07 Port 1A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC07.QR1A.PMEP,1) ) {
+ Store(\_SB.PC07.QR1A.PMEH(1), Local0)
+ } else {
+ Store (\_SB.PC07.QR1A.HPEH(1), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(1, Local1)
+ Notify(\_SB.PC07.QR1A, Local0)
+ }
+
+ // PC07 Port 1B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC07.QR1B.PMEP,1) ) {
+ Store(\_SB.PC07.QR1B.PMEH(2), Local0)
+ } else {
+ Store (\_SB.PC07.QR1B.HPEH(2), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(2, Local1)
+ Notify(\_SB.PC07.QR1B, Local0)
+ }
+
+ // PC07 Port 1C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC07.QR1C.PMEP,1) ) {
+ Store(\_SB.PC07.QR1C.PMEH(3), Local0)
+ } else {
+ Store (\_SB.PC07.QR1C.HPEH(3), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(3, Local1)
+ Notify(\_SB.PC07.QR1C, Local0)
+ }
+
+ // PC07 Port 1D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC07.QR1D.PMEP,1) ) {
+ Store(\_SB.PC07.QR1D.PMEH(4), Local0)
+ } else {
+ Store (\_SB.PC07.QR1D.HPEH(4), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(4, Local1)
+ Notify(\_SB.PC07.QR1D, Local0)
+ }
+
+ // PC08 Port 2A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC08.QR2A.PMEP,1) ) {
+ Store(\_SB.PC08.QR2A.PMEH(5), Local0)
+ } else {
+ Store (\_SB.PC08.QR2A.HPEH(5), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(5, Local1)
+ Notify(\_SB.PC08.QR2A, Local0)
+ }
+
+ // PC08 Port 2B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC08.QR2B.PMEP,1) ) {
+ Store(\_SB.PC08.QR2B.PMEH(6), Local0)
+ } else {
+ Store (\_SB.PC08.QR2B.HPEH(6), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(6, Local1)
+ Notify(\_SB.PC08.QR2B, Local0)
+ }
+
+ // PC08 Port 2C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC08.QR2C.PMEP,1) ) {
+ Store(\_SB.PC08.QR2C.PMEH(7), Local0)
+ } else {
+ Store (\_SB.PC08.QR2C.HPEH(7), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(7, Local1)
+ Notify(\_SB.PC08.QR2C, Local0)
+ }
+
+ // PC08 Port 2D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC08.QR2D.PMEP,1) ) {
+ Store(\_SB.PC08.QR2D.PMEH(8), Local0)
+ } else {
+ Store (\_SB.PC08.QR2D.HPEH(8), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(8, Local1)
+ Notify(\_SB.PC08.QR2D, Local0)
+ }
+
+ // PC09 Port 3A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC09.QR3A.PMEP,1) ) {
+ Store(\_SB.PC09.QR3A.PMEH(9), Local0)
+ } else {
+ Store (\_SB.PC09.QR3A.HPEH(9), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(9, Local1)
+ Notify(\_SB.PC09.QR3A, Local0)
+ }
+
+ // PC09 Port 3B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC09.QR3B.PMEP,1) ) {
+ Store(\_SB.PC09.QR3B.PMEH(10), Local0)
+ } else {
+ Store (\_SB.PC09.QR3B.HPEH(10), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(10, Local1)
+ Notify(\_SB.PC09.QR3B, Local0)
+ }
+
+ // PC09 Port 3C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC09.QR3C.PMEP,1) ) {
+ Store(\_SB.PC09.QR3C.PMEH(11), Local0)
+ } else {
+ Store (\_SB.PC09.QR3C.HPEH(11), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(11, Local1)
+ Notify(\_SB.PC09.QR3C, Local0)
+ }
+
+ // PC09 Port 3D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC09.QR3D.PMEP,1) ) {
+ Store(\_SB.PC09.QR3D.PMEH(12), Local0)
+ } else {
+ Store (\_SB.PC09.QR3D.HPEH(12), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(12, Local1)
+ Notify(\_SB.PC09.QR3D, Local0)
+ }
+
+ // PC12 Port 0 PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC12.RRP0.PMEP,1) ) {
+ Store(\_SB.PC12.RRP0.PMEH(1), Local0)
+ } else {
+ Store (\_SB.PC12.RRP0.HPEH(1), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(1, Local1)
+ Notify(\_SB.PC12.RRP0, Local0)
+ }
+
+ // PC13 Port 1A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC13.RR1A.PMEP,1) ) {
+ Store(\_SB.PC13.RR1A.PMEH(1), Local0)
+ } else {
+ Store (\_SB.PC13.RR1A.HPEH(1), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(1, Local1)
+ Notify(\_SB.PC13.RR1A, Local0)
+ }
+
+ // PC13 Port 1B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC13.RR1B.PMEP,1) ) {
+ Store(\_SB.PC13.RR1B.PMEH(2), Local0)
+ } else {
+ Store (\_SB.PC13.RR1B.HPEH(2), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(2, Local1)
+ Notify(\_SB.PC13.RR1B, Local0)
+ }
+
+ // PC13 Port 1C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC13.RR1C.PMEP,1) ) {
+ Store(\_SB.PC13.RR1C.PMEH(3), Local0)
+ } else {
+ Store (\_SB.PC13.RR1C.HPEH(3), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(3, Local1)
+ Notify(\_SB.PC13.RR1C, Local0)
+ }
+
+ // PC13 Port 1D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC13.RR1D.PMEP,1) ) {
+ Store(\_SB.PC13.RR1D.PMEH(4), Local0)
+ } else {
+ Store (\_SB.PC13.RR1D.HPEH(4), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(4, Local1)
+ Notify(\_SB.PC13.RR1D, Local0)
+ }
+
+ // PC14 Port 2A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC14.RR2A.PMEP,1) ) {
+ Store(\_SB.PC14.RR2A.PMEH(5), Local0)
+ } else {
+ Store (\_SB.PC14.RR2A.HPEH(5), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(5, Local1)
+ Notify(\_SB.PC14.RR2A, Local0)
+ }
+
+ // PC14 Port 2B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC14.RR2B.PMEP,1) ) {
+ Store(\_SB.PC14.RR2B.PMEH(6), Local0)
+ } else {
+ Store (\_SB.PC14.RR2B.HPEH(6), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(6, Local1)
+ Notify(\_SB.PC14.RR2B, Local0)
+ }
+
+ // PC14 Port 2C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC14.RR2C.PMEP,1) ) {
+ Store(\_SB.PC14.RR2C.PMEH(7), Local0)
+ } else {
+ Store (\_SB.PC14.RR2C.HPEH(7), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(7, Local1)
+ Notify(\_SB.PC14.RR2C, Local0)
+ }
+
+ // PC15 Port 2D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC14.RR2D.PMEP,1) ) {
+ Store(\_SB.PC14.RR2D.PMEH(8), Local0)
+ } else {
+ Store (\_SB.PC14.RR2D.HPEH(8), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(8, Local1)
+ Notify(\_SB.PC14.RR2D, Local0)
+ }
+
+ // PC15 Port 3A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC15.RR3A.PMEP,1) ) {
+ Store(\_SB.PC15.RR3A.PMEH(9), Local0)
+ } else {
+ Store (\_SB.PC15.RR3A.HPEH(9), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(9, Local1)
+ Notify(\_SB.PC15.RR3A, Local0)
+ }
+
+ // PC15 Port 3B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC15.RR3B.PMEP,1) ) {
+ Store(\_SB.PC15.RR3B.PMEH(10), Local0)
+ } else {
+ Store (\_SB.PC15.RR3B.HPEH(10), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(10, Local1)
+ Notify(\_SB.PC15.RR3B, Local0)
+ }
+
+ // PC15 Port 3C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC15.RR3C.PMEP,1) ) {
+ Store(\_SB.PC15.RR3C.PMEH(11), Local0)
+ } else {
+ Store (\_SB.PC15.RR3C.HPEH(11), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(11, Local1)
+ Notify(\_SB.PC15.RR3C, Local0)
+ }
+
+ // PC15 Port 3D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC15.RR3D.PMEP,1) ) {
+ Store(\_SB.PC15.RR3D.PMEH(12), Local0)
+ } else {
+ Store (\_SB.PC15.RR3D.HPEH(12), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(12, Local1)
+ Notify(\_SB.PC15.RR3D, Local0)
+ }
+
+ // PC18 Port 0 PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC18.SRP0.PMEP,1) ) {
+ Store(\_SB.PC18.SRP0.PMEH(1), Local0)
+ } else {
+ Store (\_SB.PC18.SRP0.HPEH(1), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(1, Local1)
+ Notify(\_SB.PC18.SRP0, Local0)
+ }
+
+ // PC19 Port 1A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC19.SR1A.PMEP,1) ) {
+ Store(\_SB.PC19.SR1A.PMEH(1), Local0)
+ } else {
+ Store (\_SB.PC19.SR1A.HPEH(1), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(1, Local1)
+ Notify(\_SB.PC19.SR1A, Local0)
+ }
+
+ // PC19 Port 1B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC19.SR1B.PMEP,1) ) {
+ Store(\_SB.PC19.SR1B.PMEH(2), Local0)
+ } else {
+ Store (\_SB.PC19.SR1B.HPEH(2), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(2, Local1)
+ Notify(\_SB.PC19.SR1B, Local0)
+ }
+
+ // PC19 Port 1C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC19.SR1C.PMEP,1) ) {
+ Store(\_SB.PC19.SR1C.PMEH(3), Local0)
+ } else {
+ Store (\_SB.PC19.SR1C.HPEH(3), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(3, Local1)
+ Notify(\_SB.PC19.SR1C, Local0)
+ }
+
+ // PC19 Port 1D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC19.SR1D.PMEP,1) ) {
+ Store(\_SB.PC19.SR1D.PMEH(4), Local0)
+ } else {
+ Store (\_SB.PC19.SR1D.HPEH(4), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(4, Local1)
+ Notify(\_SB.PC19.SR1D, Local0)
+ }
+
+ // PC20 Port 2A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC20.SR2A.PMEP,1) ) {
+ Store(\_SB.PC20.SR2A.PMEH(5), Local0)
+ } else {
+ Store (\_SB.PC20.SR2A.HPEH(5), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(5, Local1)
+ Notify(\_SB.PC20.SR2A, Local0)
+ }
+
+ // PC20 Port 2B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC20.SR2B.PMEP,1) ) {
+ Store(\_SB.PC20.SR2B.PMEH(6), Local0)
+ } else {
+ Store (\_SB.PC20.SR2B.HPEH(6), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(6, Local1)
+ Notify(\_SB.PC20.SR2B, Local0)
+ }
+
+ // PC20 Port 2C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC20.SR2C.PMEP,1) ) {
+ Store(\_SB.PC20.SR2C.PMEH(7), Local0)
+ } else {
+ Store (\_SB.PC20.SR2C.HPEH(7), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(7, Local1)
+ Notify(\_SB.PC20.SR2C, Local0)
+ }
+
+ // PC20 Port 2D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC20.SR2D.PMEP,1) ) {
+ Store(\_SB.PC20.SR2D.PMEH(8), Local0)
+ } else {
+ Store (\_SB.PC20.SR2D.HPEH(8), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(8, Local1)
+ Notify(\_SB.PC20.SR2D, Local0)
+ }
+
+ // PC21 Port 3A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC21.SR3A.PMEP,1) ) {
+ Store(\_SB.PC21.SR3A.PMEH(9), Local0)
+ } else {
+ Store (\_SB.PC21.SR3A.HPEH(9), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(9, Local1)
+ Notify(\_SB.PC21.SR3A, Local0)
+ }
+
+ // PC21 Port 3B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC21.SR3B.PMEP,1) ) {
+ Store(\_SB.PC21.SR3B.PMEH(10), Local0)
+ } else {
+ Store (\_SB.PC21.SR3B.HPEH(10), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(10, Local1)
+ Notify(\_SB.PC21.SR3B, Local0)
+ }
+
+ // PC21 Port 3C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC21.SR3C.PMEP,1) ) {
+ Store(\_SB.PC21.SR3C.PMEH(11), Local0)
+ } else {
+ Store (\_SB.PC21.SR3C.HPEH(11), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(11, Local1)
+ Notify(\_SB.PC21.SR3C, Local0)
+ }
+
+ // PC21 Port 3D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC21.SR3D.PMEP,1) ) {
+ Store(\_SB.PC21.SR3D.PMEH(12), Local0)
+ } else {
+ Store (\_SB.PC21.SR3D.HPEH(12), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(12, Local1)
+ Notify(\_SB.PC21.SR3D, Local0)
+ }
+
+ //If a hotplug event was serviced check if this was generated by PM_PME
+ If (Lnot (LEqual(Local0, 0))) {
+ //Clear the status bit 16 of PMEStatus
+ //Clear the PME Pending bit 17 of PMEStatus
+ If( LEqual(Local1, 1)) {
+ Store(1, \_SB.PC01.BR1A.PMES)
+ Store(1, \_SB.PC01.BR1A.PMEP)
+ }
+ If( LEqual(Local1, 2)) {
+ Store(1, \_SB.PC01.BR1B.PMES)
+ Store(1, \_SB.PC01.BR1B.PMEP)
+ }
+ If( LEqual(Local1, 3)) {
+ Store(1, \_SB.PC01.BR1C.PMES)
+ Store(1, \_SB.PC01.BR1C.PMEP)
+ }
+ If( LEqual(Local1, 4)) {
+ Store(1, \_SB.PC01.BR1D.PMES)
+ Store(1, \_SB.PC01.BR1D.PMEP)
+ }
+
+ If( LEqual(Local1, 5)) {
+ Store(1, \_SB.PC02.BR2A.PMES)
+ Store(1, \_SB.PC02.BR2A.PMEP)
+ }
+ If( LEqual(Local1, 6)) {
+ Store(1, \_SB.PC02.BR2B.PMES)
+ Store(1, \_SB.PC02.BR2B.PMEP)
+ }
+ If( LEqual(Local1, 7)) {
+ Store(1, \_SB.PC02.BR2C.PMES)
+ Store(1, \_SB.PC02.BR2C.PMEP)
+ }
+ If( LEqual(Local1, 8)) {
+ Store(1, \_SB.PC02.BR2D.PMES)
+ Store(1, \_SB.PC02.BR2D.PMEP)
+ }
+ If( LEqual(Local1, 9)) {
+ Store(1, \_SB.PC03.BR3A.PMES)
+ Store(1, \_SB.PC03.BR3A.PMEP)
+ }
+ If( LEqual(Local1, 10)) {
+ Store(1, \_SB.PC03.BR3B.PMES)
+ Store(1, \_SB.PC03.BR3B.PMEP)
+ }
+ If( LEqual(Local1, 11)) {
+ Store(1, \_SB.PC03.BR3C.PMES)
+ Store(1, \_SB.PC03.BR3C.PMEP)
+ }
+ If( LEqual(Local1, 12)) {
+ Store(1, \_SB.PC03.BR3D.PMES)
+ Store(1, \_SB.PC03.BR3D.PMEP)
+ }
+
+ If( LEqual(Local1, 1)) {
+ Store(1, \_SB.PC06.QRP0.PMES)
+ Store(1, \_SB.PC06.QRP0.PMEP)
+ }
+ If( LEqual(Local1, 1)) {
+ Store(1, \_SB.PC07.QR1A.PMES)
+ Store(1, \_SB.PC07.QR1A.PMEP)
+ }
+ If( LEqual(Local1, 2)) {
+ Store(1, \_SB.PC07.QR1B.PMES)
+ Store(1, \_SB.PC07.QR1B.PMEP)
+ }
+ If( LEqual(Local1, 3)) {
+ Store(1, \_SB.PC07.QR1C.PMES)
+ Store(1, \_SB.PC07.QR1C.PMEP)
+ }
+ If( LEqual(Local1, 4)) {
+ Store(1, \_SB.PC07.QR1D.PMES)
+ Store(1, \_SB.PC07.QR1D.PMEP)
+ }
+ If( LEqual(Local1, 5)) {
+ Store(1, \_SB.PC08.QR2A.PMES)
+ Store(1, \_SB.PC08.QR2A.PMEP)
+ }
+ If( LEqual(Local1, 6)) {
+ Store(1, \_SB.PC08.QR2B.PMES)
+ Store(1, \_SB.PC08.QR2B.PMEP)
+ }
+ If( LEqual(Local1, 7)) {
+ Store(1, \_SB.PC08.QR2C.PMES)
+ Store(1, \_SB.PC08.QR2C.PMEP)
+ }
+ If( LEqual(Local1, 8)) {
+ Store(1, \_SB.PC08.QR2D.PMES)
+ Store(1, \_SB.PC08.QR2D.PMEP)
+ }
+ If( LEqual(Local1, 9)) {
+ Store(1, \_SB.PC09.QR3A.PMES)
+ Store(1, \_SB.PC09.QR3A.PMEP)
+ }
+ If( LEqual(Local1, 10)) {
+ Store(1, \_SB.PC09.QR3B.PMES)
+ Store(1, \_SB.PC09.QR3B.PMEP)
+ }
+ If( LEqual(Local1, 11)) {
+ Store(1, \_SB.PC09.QR3C.PMES)
+ Store(1, \_SB.PC09.QR3C.PMEP)
+ }
+ If( LEqual(Local1, 12)) {
+ Store(1, \_SB.PC09.QR3D.PMES)
+ Store(1, \_SB.PC09.QR3D.PMEP)
+ }
+
+ If( LEqual(Local1, 1)) {
+ Store(1, \_SB.PC12.RRP0.PMES)
+ Store(1, \_SB.PC12.RRP0.PMEP)
+ }
+ If( LEqual(Local1, 1)) {
+ Store(1, \_SB.PC13.RR1A.PMES)
+ Store(1, \_SB.PC13.RR1A.PMEP)
+ }
+ If( LEqual(Local1, 2)) {
+ Store(1, \_SB.PC13.RR1B.PMES)
+ Store(1, \_SB.PC13.RR1B.PMEP)
+ }
+ If( LEqual(Local1, 3)) {
+ Store(1, \_SB.PC13.RR1C.PMES)
+ Store(1, \_SB.PC13.RR1C.PMEP)
+ }
+ If( LEqual(Local1, 4)) {
+ Store(1, \_SB.PC13.RR1D.PMES)
+ Store(1, \_SB.PC13.RR1D.PMEP)
+ }
+ If( LEqual(Local1, 5)) {
+ Store(1, \_SB.PC14.RR2A.PMES)
+ Store(1, \_SB.PC14.RR2A.PMEP)
+ }
+ If( LEqual(Local1, 6)) {
+ Store(1, \_SB.PC14.RR2B.PMES)
+ Store(1, \_SB.PC14.RR2B.PMEP)
+ }
+ If( LEqual(Local1, 7)) {
+ Store(1, \_SB.PC14.RR2C.PMES)
+ Store(1, \_SB.PC14.RR2C.PMEP)
+ }
+ If( LEqual(Local1, 8)) {
+ Store(1, \_SB.PC14.RR2D.PMES)
+ Store(1, \_SB.PC14.RR2D.PMEP)
+ }
+ If( LEqual(Local1, 9)) {
+ Store(1, \_SB.PC15.RR3A.PMES)
+ Store(1, \_SB.PC15.RR3A.PMEP)
+ }
+ If( LEqual(Local1, 10)) {
+ Store(1, \_SB.PC15.RR3B.PMES)
+ Store(1, \_SB.PC15.RR3B.PMEP)
+ }
+ If( LEqual(Local1, 11)) {
+ Store(1, \_SB.PC15.RR3C.PMES)
+ Store(1, \_SB.PC15.RR3C.PMEP)
+ }
+ If( LEqual(Local1, 12)) {
+ Store(1, \_SB.PC15.RR3D.PMES)
+ Store(1, \_SB.PC15.RR3D.PMEP)
+ }
+
+ If( LEqual(Local1, 1)) {
+ Store(1, \_SB.PC18.SRP0.PMES)
+ Store(1, \_SB.PC18.SRP0.PMEP)
+ }
+ If( LEqual(Local1, 1)) {
+ Store(1, \_SB.PC19.SR1A.PMES)
+ Store(1, \_SB.PC19.SR1A.PMEP)
+ }
+ If( LEqual(Local1, 2)) {
+ Store(1, \_SB.PC19.SR1B.PMES)
+ Store(1, \_SB.PC19.SR1B.PMEP)
+ }
+ If( LEqual(Local1, 3)) {
+ Store(1, \_SB.PC19.SR1C.PMES)
+ Store(1, \_SB.PC19.SR1C.PMEP)
+ }
+ If( LEqual(Local1, 4)) {
+ Store(1, \_SB.PC19.SR1D.PMES)
+ Store(1, \_SB.PC19.SR1D.PMEP)
+ }
+ If( LEqual(Local1, 5)) {
+ Store(1, \_SB.PC20.SR2A.PMES)
+ Store(1, \_SB.PC20.SR2A.PMEP)
+ }
+ If( LEqual(Local1, 6)) {
+ Store(1, \_SB.PC20.SR2B.PMES)
+ Store(1, \_SB.PC20.SR2B.PMEP)
+ }
+ If( LEqual(Local1, 7)) {
+ Store(1, \_SB.PC20.SR2C.PMES)
+ Store(1, \_SB.PC20.SR2C.PMEP)
+ }
+ If( LEqual(Local1, 8)) {
+ Store(1, \_SB.PC20.SR2D.PMES)
+ Store(1, \_SB.PC20.SR2D.PMEP)
+ }
+ If( LEqual(Local1, 9)) {
+ Store(1, \_SB.PC21.SR3A.PMES)
+ Store(1, \_SB.PC21.SR3A.PMEP)
+ }
+ If( LEqual(Local1, 10)) {
+ Store(1, \_SB.PC21.SR3B.PMES)
+ Store(1, \_SB.PC21.SR3B.PMEP)
+ }
+ If( LEqual(Local1, 11)) {
+ Store(1, \_SB.PC21.SR3C.PMES)
+ Store(1, \_SB.PC21.SR3C.PMEP)
+ }
+ If( LEqual(Local1, 12)) {
+ Store(1, \_SB.PC21.SR3D.PMES)
+ Store(1, \_SB.PC21.SR3D.PMEP)
+ }
+
+ Store(0x01,PEES) //Clear bit 9 of Status
+ Store(0x00,PMEE) //Clear bit 9 of GPE0_EN
+ }
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieRootPortHotPlug.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieRootPortHotPlug.asl new file mode 100644 index 0000000000..e6dc91db33 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieRootPortHotPlug.asl @@ -0,0 +1,692 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+//;************************************************************************;
+//; IMPORTANT NOTE:
+//; Code in this file should be generic/common for any IIO PCIe root port.
+//; DO NOT use hard-coded Bus/Dev/Function # in this file.
+//;
+//;************************************************************************;
+
+
+
+ Name(DBFL, 0) // Debug flag 0/1 = disable/enable debug checkpoints in this file
+
+
+
+ //;************************************************************************;
+ //; This DVPS() method detects if the root port is present and hot-plug capable.
+ //; Input : None
+ //; Output: Non-zero - Root port is present and hot-plug capable
+ //; Zero - otherwise
+ //;************************************************************************;
+ Method(DVPS,0) {
+ // Check if VID/DID = 3C0x_8086 to see if the root port exists
+ If (LNotEqual(VID, 0x8086)) { Return(Zero) }
+ //If( LNotEqual(And(DID, 0xFFF0), 0x3C00)) { Return(Zero) }
+ If( LNotEqual(And(DID, 0xFFF0), 0x2F00)) { Return(Zero) } //HSX
+ // Check the root port to see if slot is implemented and Hot-Plug Capable
+ If(LNot(And(SLIP, HPCP))) { Return(Zero) }
+ Return (One)
+ }
+
+
+ //;************************************************************************;
+ //; This HPEN() method programs "Enable ACPI mode for Hot-plug" bit based on input Arg0
+ //; See IIO PCIe rootport MISCCTRLSTS register 188h[3] definition
+ //; Input : 0/1 bit value to set "Enable ACPI mode for Hot-plug" (IIO PCIe rootport register 188h[3])
+ //; Output: None
+ //;************************************************************************;
+ Method (HPEN, 1, Serialized) {
+
+ DB55(0x71, 0) // debug point
+
+ // get Bus/Dev/Func information of this root port
+ Store(^^_BBN, Local0) // Local0 = Bus# of parent Host bus
+ //Store(_BBN, Local0) // implicit reference to PC00._BBN
+ ShiftRight(_ADR, 16, Local1) // Local1 = self Device #
+ And(_ADR, 0x0000ffff, Local2) // Local2 = self Function #
+
+ // Calculate MMCFG config address of MISCCTRLSTS register at B:D:F:offset 188h
+ //Name (MISR, 0xC0000188)
+ Name (MISR, 0) // create a pointer to MMCFG region space
+ Add(MMBS, 0x188, MISR) // MISR = MMCFG_BASE_ADDR + Offset of MISCCTRLSTS CSR
+ Add(ShiftLeft(Local0, 20), MISR, MISR) // Build bus/dev/func number fields of MISR
+ Add(ShiftLeft(Local1, 15), MISR, MISR)
+ Add(ShiftLeft(Local2, 12), MISR, MISR)
+
+ DB55(0x77, MISR) // debug point
+
+
+ // Create OpRegion for MISCCTRLSTS register at B:D:F:offset 188h
+ OperationRegion (OP37, SystemMemory, MISR, 0x04)
+ Field (OP37, DWordAcc, NoLock, Preserve) {
+ , 3,
+ HGPE, 1, // "Enable ACPI mode for Hot-plug" (register 188h[3])
+ }
+
+ // Program "Enable ACPI mode for Hot-plug" bit to input Arg0
+ Store(Arg0, HGPE)
+ }
+
+ //;************************************************************************;
+ //; This DB55() method is a debug method
+ //; Input : Arg0 Postcode to be sent to IO Port 80h
+ //; Arg1 DWord data to be copied to debug memory location
+ //; in BIOS Data Area (DBA) 40:42
+ //; Output: None
+ //;************************************************************************;
+ Method (DB55, 2, NotSerialized) {
+
+ If (DBFL) { // if debug is enabled
+ Store(Arg0, IO80) // send postcode to port 80h
+ Store(Arg1, MDWD) // store Arg1 to debug memory location
+ Sleep(4000) // stall for 4 seconds
+ }
+ }
+
+ OperationRegion (OP38, SystemMemory, 0x442, 0x04)
+ Field (OP38, AnyAcc, NoLock, Preserve) {
+ MDWD, 32, // dword at BIOS Data Area (BDA) 40:42 (floppy task-file), used as debug memory location
+ }
+
+
+ Method (_INI, 0, NotSerialized) {
+
+ If (LEqual(Zero,DVPS)) {
+ Return // Do nothing if this root port is not "Present and Hot-plugable"
+ }
+ HPEN(1) // No. Enable ACPI Hot-plug events
+ }
+
+
+/* Greencity code
+ OperationRegion (MCTL, SystemMemory, 0xA0048188, 0x04)
+ Field (MCTL, ByteAcc, NoLock, Preserve) {
+ , 3,
+ HGPE, 1,
+ , 7,
+ , 8,
+ , 8
+ }
+
+ Method (_INI, 0, NotSerialized) {
+ Store (0x01, HGPE) //enable GPE message generation for ACPI hotplug support
+ }
+*/
+
+//MCWU Changed ^HP02 to HP02 to avoid re-definition when this file is included under multiple BRxx devices
+ //Name(^HP02, Package(4){0x08, 0x40, 1, 0} )
+ Name(HP02, Package(4){0x08, 0x40, 1, 0} )
+ Method(_HPP, 0) { return(HP02) }
+
+ //
+ // begin hotplug code
+ //
+ Name(SHPC, 0x40) // Slot Hot-plug Capable
+
+ Name(SPDS, 0x040) // Slot Presence Detect State
+
+ Name(MRLS, 0x0) // MRL Closed, Standby Power to slot is on
+ Name(CCOM, 0x010) // Command Complete
+ Name(SPDC, 0x08) // Slot Presence Detect Changes
+ Name(MRLC, 0x04) // Slot MRL Changed
+ Name(SPFD, 0x02) // Slot Power Fault Detected
+ Name(SABP, 0x01) // Slot Attention Button Pressed
+
+ Name(SPOF, 0x10) // Slot Power Off
+ Name(SPON, 0x0F) // Slot Power On Mask
+
+ Name(ALMK, 0x1C) // Slot Atten. LED Mask
+ Name(ALON, 0x01) // Slot Atten. LED On
+ Name(ALBL, 0x02) // Slot Atten LED Blink
+ Name(ALOF, 0x03) // Slot Atten LED Off
+
+ Name(PLMK, 0x13) // Slot Pwr. LED Mask
+ Name(PLON, 0x04) // Slot Pwr. LED On
+ Name(PLBL, 0x08) // Slot Pwr. LED Blink
+ Name(PLOF, 0x0C) // Slot Pwr. LED Off
+
+ //;*************************************
+ //; Bit 3 = Presence Detect Event
+ //; Bit 2 = MRL Sensor Event
+ //; Bit 1 = PWR Fault Event
+ //; Bit 0 = Attention Button Event
+ //;*************************************
+ Name(HPEV, 0xF) // Possible interrupt events (all)
+
+ //;************************************************************************;
+ //;
+ //; PCIe Slot Capabilities Register A4-A7h
+ //; Bit - 31-7 - Not used
+ //; Bit - 6 - Hot-Plug Capable
+ //; Bit - 5 - Hot-Plug Surprise
+ //; Bit - 4 - Power Indicator Present.
+ //; Bit - 3 - Attention Indicator Present.
+ //; Bit - 2 - MRL Sensor Present.
+ //; Bit - 1 - Power Controller Present.
+ //; Bit - 0 - Attention Button Present.
+ //;
+ //; PCIe Slot control Register A8-A9h
+ //;
+ //; Bit - 10 - PWR Control Disable
+ //; Bit - 9:8 - Attn Indicator
+ //; Bit - 7:6 - PWR Indicator
+ //; Bit - 5 - Hot-Plug Interrupt Event Enable
+ //; Bit - 4 - Command Complete Interrupt enable
+ //; Bit - 3 - Presence Detect Changed Interrupt enable
+ //; Bit - 2 - MRL Sensor Changed Interrupt enable
+ //; Bit - 1 - PwrFault Detect Interrupt enable
+ //; Bit - 0 - Attention Button Pressed Interrupt Enable
+ //;
+ //; PCIe Slot Status Registers AA-ADh
+ //;
+ //; Bit - 6 - Presence Detect State.
+ //; Bit - 5 - MRL Sensor State.
+ //; Bit - 4 - Command Completed.
+ //;
+ //; RWC Status Bits
+ //;
+ //; Bit - 3 - Presence Detect Changed.
+ //; Bit - 2 - MRL Sensor Changed.
+ //; Bit - 1 - Power Fault Detected.
+ //; Bit - 0 - Attention Button Pressed.
+ //;************************************************************************;
+
+ OperationRegion(PPA4, PCI_Config, 0x00, 0x0ff)
+ Field(PPA4,ByteAcc,NoLock,Preserve) {
+
+ Offset(0x00), // VenderID/DeviceID register
+ VID, 16, // VID = 0x8086
+ DID, 16, // Device IDs for IIO PCI Express root ports are as follows:
+ // 0x3C00: DMI mode 0x3C01: the DMI port running in PCIe mode
+ // 0x3C02: Port 1a
+ // 0x3C03: Port 1b
+ // 0x3C04: Port 2a
+ // 0x3C05: Port 2b
+ // 0x3C06: Port 2c
+ // 0x3C07: Port 2d
+ // 0x3C08: Port 3a in PCIe mode
+ // 0x3C09: Port 3b
+ // 0x3C0A: Port 3c
+ // 0x3C0B: Port 3d
+ // (0x3C0F: IIO NTB Secondary Endpoint)
+
+ Offset(0x92), // PXPCAP - PCIe CAP Register
+ , 8,
+ SLIP, 1, // bit8 Slot Implemented
+
+ offset(0xA4), // SLTCAP - Slot Capabilities Register
+ ATBP,1, // bit0 Attention Button Present
+ PWCP,1, // bit1 Power Controller Present
+ MRSP,1, // bit2 MRL Sensor Present
+ ATIP,1, // bit3 Attention Indicator Present
+ PWIP,1, // bit4 Power Indicator Present
+ HPSR,1, // bit5 Hot-Plug Surprise
+ HPCP,1, // bit6 Hot-Plug Capable
+
+ offset(0xA8), // SLTCON - PCIE Slot Control Register
+ ABIE,1, // bit0 Attention Button Pressed Interrupt Enable
+ PFIE,1, // bit1 Power Fault Detected Interrupt Enable
+ MSIE,1, // bit2 MRL Sensor Changed Interrupt Enable
+ PDIE,1, // bit3 Presence Detect Changed Interrupt Enable.
+ CCIE,1, // bit4 Command Complete Interrupt Enable.
+ HPIE,1, // bit5 Hot-plug Interrupt Enable.
+ SCTL,5, // bit[10:6] Attn/Power indicator and Power controller.
+
+ offset(0xAA), // SLTSTS - PCIE Slot Status Register
+ SSTS,7, // The status bits in Slot Status Reg
+ ,1,
+}
+
+ OperationRegion(PPA8, PCI_Config, 0x00, 0x0ff)
+ Field(PPA8,ByteAcc,NoLock,Preserve) {
+ Offset(0xA8), // SLTCON - PCIE Slot Control Register
+ ,6,
+ ATID,2, // bit[7:6] Attention Indicator Control.
+ PWID,2, // bit[9:8] Power Indicator Control.
+ PWCC,1, // bit[10] Power Controller Control.
+ ,5,
+ Offset(0xAA), // SLTSTS - PCIE Slot status Register (WRC)
+ ABPS,1, // bit0 Attention Button Pressed Status (RWC)
+ PFDS,1, // bit1 Power Fault Detect Status (RWC)
+ MSCS,1, // bit2 MRL Sensor Changed Status
+ PDCS,1, // bit3 Presence Detect Changed Status
+ CMCS,1, // bit4 Command Complete Status
+ MSSC,1, // bit5 MRL Sensor State
+ PRDS,1, // bit6 Presence Detect State
+ ,1,
+ }
+
+ //;************************************************************************;
+ //; This OSHP (Operating System Hot Plug) method is provided for each HPC
+ //; which is controlled by ACPI. This method disables ACPI access to the
+ //; HPC and restores the normal System Interrupt and Wakeup Signal
+ //; connection.
+ //;************************************************************************;
+ Method(OSHP) { // OS call to unhook Legacy ASL PCI-Express HP code.
+ Store(SSTS, SSTS) // Clear any status
+// Store(0x0, HGPE) // Disable GPE generation
+ HPEN(0) // Disable GPE generation
+ }
+
+ //;************************************************************************;
+ //; Hot Plug Controller Command Method
+ //;
+ //; Input: Arg0 - Command to issue
+ //;
+ //;************************************************************************;
+ Method(HPCC,1) {
+ Store(SCTL, Local0) // get current command state
+ Store(0, Local1) // reset the timeout value
+ If(LNotEqual(Arg0, Local0)) { // see if state is different
+ Store(Arg0, SCTL) // Update the Slot Control
+ While(LAnd (LNot(CMCS), LNotEqual(100, Local1))) { // spin while CMD complete bit is not set,
+ // check for timeout to avoid dead loop
+ Store(0x2C, IO80)
+ Sleep(2) // allow processor time slice
+ Add(Local1, 2, Local1)
+ }
+ Store(0x1, CMCS) // Clear the command complete status
+ }
+ }
+
+ //;************************************************************************;
+ //; Attention Indicator Command
+ //;
+ //; Input: Arg0 - Command to issue
+ //; 1 = ON
+ //; 2 = Blink
+ //; 3 = OFF
+ //;************************************************************************;
+ Method(ATCM,1) {
+ Store(SCTL, Local0) // Get Slot Control
+ And(Local0, ALMK, Local0) // Mask the Attention Indicator Bits
+ If(LEqual(Arg0, 0x1)){ // Attenion indicator "ON?"
+ Or(Local0, ALON, Local0) // Set the Attention Indicator to "ON"
+ }
+ If(LEqual(Arg0, 0x2)){ // Attenion indicator "BLINK?"
+ Or(Local0, ALBL, Local0) // Set the Attention Indicator to "BLINK"
+ }
+ If(LEqual(Arg0, 0x3)){ // Attenion indicator "OFF?"
+ Or(Local0, ALOF, Local0) // Set the Attention Indicator to "OFF"
+ }
+ HPCC(Local0)
+ }
+
+ //;************************************************************************;
+ //; Power Indicator Command
+ //;
+ //; Input: Arg0 - Command to issue
+ //; 1 = ON
+ //; 2 = Blink
+ //; 3 = OFF
+ //;************************************************************************;
+ Method(PWCM,1){
+ Store(SCTL, Local0) // Get Slot Control
+ And(Local0, PLMK, Local0) // Mask the Power Indicator Bits
+ If(LEqual(Arg0, 0x1)){ // Power indicator "ON?"
+ Or(Local0, PLON, Local0) // Set the Power Indicator to "ON"
+ }
+ If(LEqual(Arg0, 0x2)){ // Power indicator "BLINK?"
+ Or(Local0, PLBL, Local0) // Set the Power Indicator to "BLINK"
+ }
+ If(LEqual(Arg0, 0x3)){ // Power indicator "OFF?"
+ Or(Local0, PLOF, Local0) // Set the Power Indicator to "OFF"
+ }
+ HPCC(Local0)
+ }
+
+ //;************************************************************************;
+ //; Power Slot Command
+ //;
+ //; Input: Arg0 - Command to issue
+ //; 1 = Slot Power ON
+ //; 2 = Slot Power Off
+ //;************************************************************************;
+ Method(PWSL,1){
+ Store(SCTL, Local0) // Get Slot Control
+ If(Arg0){ // Power Slot "ON" Arg0 = 1
+ And(Local0, SPON, Local0) // Turns the Power "ON"
+ } Else { // Power Slot "OFF"
+ Or(Local0, SPOF, Local0) // Turns the Power "OFF"
+ }
+ HPCC(Local0)
+ }
+
+ //;************************************************************************;
+ //; _OST Methods to indicate that the device Eject/insert request is
+ //; pending, OS could not complete it
+ //;
+ //; Input: Arg0 - Value used in Notify to OS
+ //; 0x00 - card insert
+ //; 0x03 - card eject
+ //; Arg1 - status of Notify
+ //; 0 - success
+ //; 0x80 - Ejection not supported by OSPM
+ //; 0x81 - Device in use
+ //; 0x82 - Device Busy
+ //; 0x84 - Ejection in progress-pending
+ //;************************************************************************;
+ Method(_OST,3,Serialized) {
+ Switch(And(Arg0,0xFF)) { // Mask to retain low byte
+ Case(0x03) { // Ejection Request
+ Switch(ToInteger(Arg1)) {
+ Case(Package() {0x80, 0x81, 0x82, 0x83}) {
+ //
+ // Ejection Failure for some reason
+ //
+ If (Lnot(PWCC)) { // if slot is powered
+ PWCM(0x1) // Set PowerIndicator to ON
+ Store(0x1,ABIE) // Set AttnBtn Interrupt ON
+ }
+ }
+ }
+ }
+ }
+ } // End _OST
+
+ //;************************************************************************;
+ //; Eject Control Methods to indicate that the device is hot-ejectable and
+ //; should "eject" the device.
+ //;
+ //; Input: Arg0 - Not use.
+ //;
+ //;************************************************************************;
+ Method(EJ02, 1){
+ Store(0xFF, IO80)
+ Store(SCTL, Local0) // Get IOH Port 9/SLot3 Control state
+ if( LNot( LEqual( ATID, 1))) { // Check if Attention LED is not solid "ON"
+ And(Local0, ALMK, Local0) // Mask the Attention Indicator Bits
+ Or(Local0, ALBL, Local0) // Set the Attention Indicator to blink
+ }
+ HPCC(Local0) // issue command
+
+ Store(SCTL, Local0) // Get IOH Port 9/SLot3 Control state
+ Or(Local0, SPOF, Local0) // Set the Power Controller Control to Power Off
+ HPCC(Local0)
+
+ Store(SCTL, Local0) // Get PEXH Port 9/SLot3 Control state
+ Or(Local0, PLOF, Local0) // Set the Power Indicator to Off.
+ HPCC(Local0)
+ } // End of EJ02
+
+ //;************************************************************************;
+ //; PM_PME Wake Handler for Slot 3 only
+ //;
+ //; Input: Arg0 - Slot Number
+ //;
+ //;************************************************************************;
+ Method(PMEH,1){ // Handler for PCI-E PM_PME Wake Event/Interrupt (GPI xxh)
+ If(And(HPEV, SSTS)){ // Check for Hot-Plug Events
+ If(ABPS) {
+ Store (Arg0, IO80) // Send slot number to Port 80
+ Store(0x1, ABPS) // Clear the interrupt status
+ Sleep(200) // delay 200ms
+ }
+ }
+ Return (0xff) // Indicate that this controller did not interrupt
+ } // End of Method PMEH
+
+ //;************************************************************************;
+ //; Hot-Plug Handler for an IIO PCIe root port slot
+ //;
+ //; Input: Arg0 - Slot Numnber (not used)
+ //; Output:
+ //; 0xFF - No hotplug event detected
+ //; 0x03 - Eject Request detected
+ //; 0x00 - Device Presence Changed
+ //;
+ //;************************************************************************;
+ Method(HPEH,1){ // Handler for PCI-E Hot-Plug Event/Interupt Called from \_SB.GPE._L01()
+
+ If (LEqual(Zero,DVPS)) {
+ Return (0xff) // Do nothing if root port is not "Present and Hot-plugable"
+ }
+
+ Store(0x22, IO80)
+ Sleep(100)
+ Store(0,CCIE) // Disable command interrupt
+ If(And(HPEV, SSTS)){ // Check for Hot-Plug Events
+ Store(0x3A, IO80)
+ Sleep(10)
+ Store(PP3H(0x0), Local0) // Call the Slot 3 Hot plug Interrupt Handler
+ Return(Local0) // Return PP2H information
+ }
+ Else{
+ Return (0xff) // Indicate that this controller did not interrupt
+ }
+ Store(0x2F, IO80)
+ Sleep(10)
+ } // End of Method HPEH
+
+ //;************************************************************************;
+ //; Interrut Event Handler
+ //;
+ //; Input: Arg0 - Slot Numnber
+ //;
+ //;************************************************************************;
+ Method(PP3H,1){ // Slot 3 Hot plug Interrupt Handler
+ //
+ // Check for the Atention Button Press, Slot Empty/Presence, Power Controller Control.
+ //
+ Sleep(200) // HW Workaround for AttentionButton Status to stabilise
+ If(ABPS) { // Check if Attention Button Pressed for Device 4
+ If(LNot(PRDS)) { // See if nothing installed (no card in slot)
+ PWSL(0x0) // make sure Power is Off
+ PWCM(0x3) // Set Power Indicator to "OFF"
+ //
+ // Check for MRL here and set attn indicator accordingly
+ //
+ If(LEqual(MSSC,MRLS)) { // Standby power is on - MRL closed
+ ATCM(0x2) // Set Attention Indicator to "BLINK"
+ } else { // Standby power is off - MRL open
+ ATCM(0x3) // set attention indicator "OFF"
+ }
+ Store(0x0, ABIE) // set Attention Button Interrupt to disable
+ Store(0x1, ABPS) // Clear the interrupt status
+ Sleep(200) // delay 200ms
+ Return(0xff) // Attn Button pressed without card in slot. Do nothing
+ }
+ //
+ // Card is present in slot so....
+ //
+ Store(0x0, ABIE) // set Attention Button Interrupt to disable
+ // Attn Btn Interrupt has to be enabled only after an insert oprn
+ Store(0x1, ABPS) // Clear the interrupt status
+ Sleep(200) // delay 200ms
+ //
+ // Check for MRL here - only if SPWR is OFF blink AttnInd and retun 0xff
+ //
+ If(LNot(LEqual(MSSC,MRLS))) { // Standby power is off
+ PWSL(0x0) // make sure Power is Off
+ PWCM(0x3) // Set Power Indicator to "OFF"
+ ATCM(0x2) // Set Attention Indicator to "BLINK"
+ Return(0xff) // Attn Button pressed with card in slot, but MRL open. Do nothing
+ }
+ //Card Present, if StandbyPwr is ON proceed as below with Eject Sequence
+ If(PWCC) { // Slot not Powered
+ PWCM(0x3) // Set Power Indicator to "OFF"
+ ATCM(0x2) // Set Attention Indicator to "BLINK"
+ Return(0xff) // Attn Button pressed with card in slot, MRL closed, Slot not powered. Do nothing
+ } else { // See if Slot is already Powered
+ PWCM(0x2) // Set power Indicator to BLINK
+ Sleep(600) // Wait 100ms
+ Store(600, Local0) // set 5 second accumulator to 0
+ Store(0x1, ABPS) // Clear the interrupt status
+ Sleep(200) // delay 200ms
+ While(LNot(ABPS)) { // check for someone pressing Attention
+ Sleep(200) // Wait 200ms
+ Add(Local0, 200, Local0)
+ If(LEqual(5000, Local0)) { // heck if 5sec has passed without pressing attnetion btn
+ Store(0x1, ABPS) // Clear the interrupt status
+ Sleep(200) // delay 200ms
+ Return (0x3) // continue with Eject request
+ }
+ }
+ PWCM(0x1) // Set power Indicator baCK "ON"
+ Store(0x1, ABPS) // Clear the Attention status
+ Sleep(200) // delay 200ms
+ Store(0x1, ABIE) // set Attention Button Interrupt to enable
+ Return (0xff) // do nothing and abort
+ }
+ } // End if for the Attention Button Hot Plug Interrupt.
+
+ If(PFDS) { // Check if Power Fault Detected
+ Store(0x1, PFDS) // Clear the Power Fault Status
+ PWSL(0x0) // set Power Off
+ PWCM(0x3) // set power indicator to OFF
+ ATCM(0x1) // set attention indicator "ON"
+ Return(0x03) // Eject request.
+ } // End if for the Power Fault Interrupt.
+
+ If(MSCS) { // Check interrupt caused by the MRL Sensor
+ Store(0x1, MSCS) // Clear the MRL Status
+ If(LEqual(MSSC,MRLS)) { // Standby power is on - MRL closed
+ If(PRDS) { // Card is Present
+ // Slot Power is Off, so power up the slot
+ ATCM(0x3) // Set Attention Indicator to off
+ PWCM(0x2) // Set Power Indicator to Blink
+ Sleep(600) // Wait 100ms
+ Store(600, Local0) // set 5 second accumulator to 0
+ Store(0x1, ABPS) // Clear the interrupt status
+ While(LNot(ABPS)) { // check for someone pressing Attention
+ Sleep(200) // Wait 200ms
+ Add(Local0, 200, Local0)
+ If(LEqual(5000, Local0)) { // Check if 5 sec elapsed
+ Store(0x1, ABIE) // Enable Attention button interrupt
+ ATCM(0x3) // set attention indicator "OFF"
+ PWSL(0x1) // Power the Slot
+ Sleep(500) // Wait for .5 Sec for the Power to Stabilize.
+ // Check for the Power Fault Detection
+ If(LNot(PFDS)) { // No Power Fault
+ PWCM(0x1) // Set Power Indicator to "ON"
+ // Or(LVLS, 0x000010000, LVLS) // Enable the Device 4 Slot Clock (GPIO16)
+ // Notify the OS to load the Driver for the card
+ Store(0x00, Local1)
+ Store(0x1, ABIE) // Enable Attention button interrupt
+ } Else { // Power Fault present
+ PWSL(0x0) // set Slot Power Off
+ PWCM(0x3) // set power indicator to OFF
+ ATCM(0x1) // set attention indicator "ON"
+ // And (LVLS, 0x0FFFEFFFF, LVLS) // Disable the Device 4 Slot Clock (GPIO16)
+ Store(0x03, Local1) // Eject request.
+ } // End if for the Slot Power Fault
+ Store(0x1, ABPS) // Clear the Attention status
+ Sleep(200) // delay 200ms
+ Return(Local1)
+ }
+ }
+ //
+ // someone pressed Attention Button
+ //
+ Store(0x1, ABPS) // Clear the Attention status
+ Sleep(200) // delay 200ms
+ PWSL(0x0) // Set Slot Power off
+ PWCM(0x3) // Set Power Indicator back to "OFF"
+ ATCM(02) // Set Attention Indicator to "BLINK"
+ Return(0xff) // leave it off
+ // End of Insert sequence
+ }
+ //MRL is closed, Card is not present
+ PWSL(0x0) // Set Slot Power off
+ PWCM(0x3) // Set Power Indicator back to "OFF"
+ ATCM(02) // Set Attention Indicator to "BLINK"
+ Return(0xff) // leave it off
+ } else { // MRL is open i.e Stdby power is turned off
+ If(PRDS) {
+ //card present MRL switched off
+ ATCM(0x2) // Set Attention Indicator to "BLINK"
+ If(Lnot(PWCC)) { // If slot is powered
+ // This event is not supported and someone has opened the MRL and dumped the power
+ // on the slot with possible pending transactions. This could hose the OS.
+ // Try to Notify the OS to unload the drivers.
+ PWSL(0x0) // Set Slot Power off
+ PWCM(0x3) // Set Power Indicator back to "OFF"
+ Return(0x03) // Eject request.
+ } else { // Slot not powered, MRL is opened, card still in slot - Eject not fully complete
+ Return(0xFF)
+ }
+ }
+ //no card present and Stdby power switched off, turn AI off
+ ATCM(0x3) // Set Attention Indicator to "OFF"
+ Return(0xff) // leave it off
+ } // End of MRL switch open/close state
+ } // End of MRL Sensor State Change
+
+ If(PDCS) { // Check if Presence Detect Changed Status
+ Store(0x1, PDCS) // Clear the Presence Detect Changed Status
+ If(LNot(PRDS)) { // Slot is Empty
+ PWSL(0x0) // Set Slot Power "OFF"
+ PWCM(0x3) // set power indicator to "OFF"
+ If(LEqual(MSSC,MRLS)) { // If Standby power is on
+ ATCM(0x2) // Set Attention Indicator to "Blink"
+ } else {
+ ATCM(0x3) // Set Attention Indicator to "OFF"
+ }
+ Return(0xFF) // Do nothing
+ } Else { // Slot Card is inserted
+ // Irrespective of MRL state blink indicator
+ PWSL(0x0) // Set Slot Power off
+ PWCM(0x3) // Set Power Indicator back to "OFF"
+ ATCM(0x2) // Set Attention Indicator to "Blink"
+ Return(0xFF) // Do nothing
+ }
+ } // End if for the Presence Detect Changed Hot Plug Interrupt.
+ Return(0xff) // should not get here, but do device check if it does.
+ } // End of method PP5H
+ //
+ // End of hotplug code
+ //
+
+ Device(H000) {
+ Name(_ADR, 0x00000000)
+ Name(_SUN, 0x0002) // Slot User Number
+ Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot
+ }
+ Device(H001) {
+ Name(_ADR, 0x00000001)
+ Name(_SUN, 0x0002) // Slot User Number
+ Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot
+ }
+ Device(H002) {
+ Name(_ADR, 0x00000002)
+ Name(_SUN, 0x0002) // Slot User Number
+ Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot
+ }
+ Device(H003) {
+ Name(_ADR, 0x00000003)
+ Name(_SUN, 0x0002) // Slot User Number
+ Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot
+ }
+ Device(H004) {
+ Name(_ADR, 0x00000004)
+ Name(_SUN, 0x0002) // Slot User Number
+ Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot
+ }
+ Device(H005) {
+ Name(_ADR, 0x00000005)
+ Name(_SUN, 0x0002) // Slot User Number
+ Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot
+ }
+ Device(H006) {
+ Name(_ADR, 0x00000006)
+ Name(_SUN, 0x0002) // Slot User Number
+ Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot
+ }
+ Device(H007) {
+ Name(_ADR, 0x00000007)
+ Name(_SUN, 0x0002) // Slot User Number
+ Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot
+ }
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl new file mode 100644 index 0000000000..b6a7188cbb --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl @@ -0,0 +1,38 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+// ITSS
+// Define the needed ITSS registers used by ASL on Interrupt
+// mapping.
+
+scope(\_SB){
+ OperationRegion(ITSS, SystemMemory, 0xfdc43100, 0x208)
+ Field(ITSS, ByteAcc, NoLock, Preserve)
+ {
+ PARC, 8,
+ PBRC, 8,
+ PCRC, 8,
+ PDRC, 8,
+ PERC, 8,
+ PFRC, 8,
+ PGRC, 8,
+ PHRC, 8,
+ Offset(0x200), // Offset 3300h ITSSPRC - ITSS Power Reduction Control
+ , 1,
+ , 1,
+ SCGE, 1, // ITSSPRC[2]: 8254 Static Clock Gating Enable (8254CGE)
+
+ }
+}
+
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Mother.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Mother.asi new file mode 100644 index 0000000000..46abd5706c --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Mother.asi @@ -0,0 +1,208 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Device (DMAC) {
+ Name (_HID, EISAID("PNP0200"))
+ Name (_CRS,ResourceTemplate() {
+ IO(Decode16, 0x0, 0x0, 0, 0x10)
+ IO(Decode16, 0x81, 0x81, 0, 0x3)
+ IO(Decode16, 0x87, 0x87, 0, 0x1)
+ IO(Decode16, 0x89, 0x89, 0, 0x3)
+ IO(Decode16, 0x8f, 0x8f, 0, 0x1)
+ IO(Decode16, 0xc0, 0xc0, 0, 0x20)
+ DMA(Compatibility,NotBusMaster,Transfer8) {4}
+ })
+}
+
+Device (RTC) {
+ Name (_HID,EISAID("PNP0B00"))
+ Name (_CRS,ResourceTemplate() {
+ IO(Decode16,0x70,0x70,0x01,0x02)
+ IO(Decode16,0x74,0x74,0x01,0x04)
+ IRQNoFlags(){8}
+ })
+}
+
+Device (PIC) {
+ Name (_HID,EISAID("PNP0000"))
+ Name (_CRS,ResourceTemplate() {
+ IO(Decode16,0x20,0x20,0x01,0x1E) // length of 1Eh includes all aliases
+ IO(Decode16,0xA0,0xA0,0x01,0x1E)
+ IO(Decode16,0x4D0,0x4D0,0x01,0x02)
+ })
+}
+
+Device (FPU) {
+ Name (_HID,EISAID("PNP0C04"))
+ Name (_CRS,ResourceTemplate() {
+ IO(Decode16,0xF0,0xF0,0x01,0x1)
+ IRQNoFlags(){13}
+ })
+}
+
+Device(TMR)
+{
+ Name(_HID,EISAID("PNP0100"))
+
+ Name(_CRS,ResourceTemplate() {
+ IO(Decode16,0x40,0x40,0x01,0x04)
+ IO(Decode16,0x50,0x50,0x01,0x04) // alias
+ IRQNoFlags(){0}
+ })
+}
+
+Device (SPKR) {
+ Name (_HID,EISAID("PNP0800"))
+ Name (_CRS,ResourceTemplate() {
+ IO(Decode16,0x61,0x61,0x01,0x01)
+ })
+}
+
+//
+// all "PNP0C02" devices- pieces that don't fit anywhere else
+//
+Device(XTRA) {
+ Name(_HID,EISAID("PNP0C02")) // Generic motherboard devices
+ Name(_CRS,
+ ResourceTemplate() {
+ IO(Decode16,0x500,0x500,0x01,0x40) // GPIO space, ICH5
+ IO(Decode16,0x400,0x400,0x01,0x80) // PM IO, ICH5
+ IO(Decode16,0x92,0x92,0x01,0x01) // INIT & Fast A20 port, ICH5
+ //
+ // Resource conflict with COM Port
+ //
+ //IO(Decode16,0x680,0x680,0x01,0x80) // Runtime registers, National SIO
+ IO(Decode16,0x10,0x10,0x01,0x10)
+ IO(Decode16,0x72,0x72,0x01,0x02)
+ IO(Decode16,0x80,0x80,0x01,0x01)
+ IO(Decode16,0x84,0x84,0x01,0x03)
+ IO(Decode16,0x88,0x88,0x01,0x01)
+ IO(Decode16,0x8c,0x8c,0x01,0x03)
+ IO(Decode16,0x90,0x90,0x01,0x10)
+ //
+ // SMBus decode range
+ //
+ IO(Decode16,0x540,0x540,0x01,0x40)
+ //
+ // Pilot Mail Box decode range
+ //
+ IO(Decode16,0x600,0x600,0x01,0x20)
+ //
+ // BMC KCS decode range
+ //
+ IO(Decode16,0xCA0,0xCA0,0x01,0x6)
+ //
+ // Performance Status and control ports decode range
+ //
+ IO(Decode16,0x880,0x880,0x01,0x4)
+
+ //IO Descriptor added for range 800-81f for S501302
+ IO(Decode16,0x800,0x800,0x01,0x20)
+ //IO Descriptor added for range 2F8-2FF for S501706
+ //IO(Decode16,0x2F8,0x2F8,0x01,0x08)
+ //IO(Decode16,0x60,0x60,0x01,0x01)
+ //IO(Decode16,0x64,0x64,0x01,0x01)
+
+ //PCH_ACPI_FLAG: RCBA is not supported in SPT
+ //
+ // RCBA memory range
+ //
+ //Memory32Fixed (ReadOnly, 0xFED1C000, 0x6FFFF) // ICH9 bios spec section 5.10 - reserved memory address space.
+ Memory32Fixed (ReadOnly, 0xFED1C000, 0x24000) // ICH9 bios spec section 5.10 - reserved memory address space.
+ // Leave FED40000-FED45000 for TPM
+ Memory32Fixed (ReadOnly, 0xFED45000, 0x47000) // ICH9 bios spec section 5.10 - reserved memory address space.
+
+ //
+ // FLASH range
+ //
+ Memory32Fixed (ReadOnly, 0xFF000000, 0x1000000) //16MB as per IIO spec
+
+ //
+ // Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF)
+ //
+ Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000)
+
+ //
+ // HECI range, 32 bytes from HECI1_BASE_ADDRESS (0xFE90_0000 to 0xFE90_001F)
+ //
+ //Memory32Fixed (ReadWrite, 0xFE900000, 0x20)
+ Memory32Fixed (ReadWrite, 0xFED12000, 0x10)
+
+ //
+ // HECI range, 32 bytes from HECI2_BASE_ADDRESS (0xFEA0_0000 to 0xFEA0_001F)
+ //
+ //Memory32Fixed (ReadWrite, 0xFEA00000, 0x20)
+ Memory32Fixed (ReadWrite, 0xFED12010, 0x10)
+
+ //
+ // IIO RCBA memory range
+ //
+ Memory32Fixed (ReadOnly, 0xFED1B000, 0x1000)
+ }
+ )
+}
+
+//
+// High Performance Event Timer (HPET)
+//
+Device (HPET) {
+ Name (_HID, EisaId ("PNP0103"))
+
+ Method (_STA, 0, NotSerialized) {
+ If (\HPTE) {
+ Return (0x0F)
+ } Else {
+ Return (0x00)
+ }
+ }
+
+ Name (CRS0, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400)
+ })
+
+ Name (CRS1, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0xFED01000, 0x00000400)
+ })
+
+ Name (CRS2, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0xFED02000, 0x00000400)
+ })
+
+ Name (CRS3, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0xFED03000, 0x00000400)
+ })
+
+ //
+ // Owning control method can't be re-entrant, so _CRS must be Serialized
+ //
+ Method (_CRS, 0, Serialized) {
+ Switch (ToInteger(\HPTB)) {
+ Case (0xFED00000) {
+ Return (CRS0)
+ }
+
+ Case (0xFED01000) {
+ Return (CRS1)
+ }
+
+ Case (0xFED02000) {
+ Return (CRS2)
+ }
+
+ Case (0xFED03000) {
+ Return (CRS3)
+ }
+ }
+ Return (CRS0)
+ }
+}
\ No newline at end of file diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Os.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Os.asi new file mode 100644 index 0000000000..2492a1726c --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Os.asi @@ -0,0 +1,151 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope (\_SB) {
+
+ Name (XCNT, 0)
+ Name (OSYS, 0) // Global variable for type of OS.
+
+ //
+ // Device specific method
+ //
+ Method (_DSM, 4, Serialized) {
+ If (LEqual(Arg0,ToUUID("663E35AF-CC10-41A4-88EA-5470AF055295"))){
+
+ // L1 DIR POINTER
+ Switch (ToInteger(Arg2)) {
+ //
+ //Function 0: Return supported functions, based on revision
+ //
+ Case(0)
+ {
+ Switch (ToInteger(Arg1)) {
+ Case(0) {
+ If (Lequal(EMCA,1))
+ {
+ Return ( Buffer() {0x3} )
+ }
+ Else
+ {
+ Return (Buffer() {0})
+ }
+ }
+ }
+
+ }
+ //
+ // Function 1:
+ //
+ Case(1) {Return (LDIR) }
+ Default { }
+ }
+ }
+
+ Return (Buffer() {0})
+ }
+
+ Method (_INI) {
+
+ If (CondRefOf (_OSI)) {
+
+ If (\_OSI ("Windows 2001.1 SP1")) {
+ Store (5, OSYS) // Windows Server 2003 SP1
+ }
+
+ If (\_OSI ("Windows 2001.1")) {
+ Store (6, OSYS) // Windows Server 2003
+ }
+
+ If (\_OSI ("Windows 2001 SP2")) {
+ Store (7, OSYS) // Windows XP SP2
+ }
+
+ If (\_OSI ("Windows 2001")) {
+ Store (8, OSYS) // Windows XP
+ }
+
+ If (\_OSI ("Windows 2006.1")) {
+ Store (9, OSYS) // Windows Server 2008
+ }
+
+ If (\_OSI ("Windows 2006 SP1")) {
+ Store (10, OSYS) // Windows Vista SP1
+ }
+
+ If (\_OSI ("Windows 2006")) {
+ Store (11, OSYS) // Windows Vista
+ }
+
+ If (\_OSI ("Windows 2009")) {
+ Store (12, OSYS) // Windows Server 2008 R2 & Windows 7
+ }
+
+ If (\_OSI ("Windows 2012")) {
+ Store (13, OSYS) // Windows Server 2012 & Windows 8
+ }
+
+ If (\_OSI ("Windows 2013")) {
+ Store (14, OSYS) // Windows Server 2012 R2 & Windows 8.1
+ }
+
+ If (\_OSI ("Windows 2015")) {
+ Store (15, OSYS) // Windows 10 & Windows Server Technical Preview
+ }
+
+ If (\_OSI ("Windows 2016")) {
+ Store (16, OSYS) // Windows 10, version 1607
+ }
+
+ If (\_OSI ("Windows 2017")) {
+ Store (17, OSYS) // Windows 10, version 1703
+ }
+
+ //
+ // Check Linux also
+ //
+ If (\_OSI ("Linux")) {
+ Store (1, OSYS)
+ }
+
+ If (\_OSI ("FreeBSD")) {
+ Store (2, OSYS)
+ }
+
+ If (\_OSI ("HP-UX")) {
+ Store (3, OSYS)
+ }
+
+ If (\_OSI ("OpenVMS")) {
+ Store (4, OSYS)
+ }
+
+ //
+ // Running WinSvr2012, Win8, or later?
+ //
+ If (LGreaterEqual (\_SB.OSYS, 13)) {
+ //
+ // It is Svr2012 or Win8
+ // Call xHCI device to switch USB ports over
+ // unless it has been done already
+ //
+ If (LEqual (XCNT, 0)) {
+ Store (0x84, IO80)
+ Increment (XCNT)
+ }
+ } Else {
+ Store (\_SB.OSYS, IO80)
+ }
+ }
+ } // End Method (_INI)
+
+} // End Scope (_SB)
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC00.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC00.asi new file mode 100644 index 0000000000..bebf4e0fcb --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC00.asi @@ -0,0 +1,391 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ //
+ // Set this root port to use the correct Proximity Domain
+ //
+ Name(_PXM, 0)
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+#include "Pch.asi"
+#include "PchApic.asi"
+
+
+#define RESOURCE_CHUNK1_OFF 0
+#define RESOURCE_CHUNK2_OFF 16 //(RESOURCE_CHUNK1_OFF + 16)
+#define RESOURCE_CHUNK3_OFF 24 //(RESOURCE_CHUNK2_OFF + 8)
+#define RESOURCE_CHUNK4_OFF 40 //(RESOURCE_CHUNK3_OFF + 16)
+#define RESOURCE_CHUNK5_OFF 56 //(RESOURCE_CHUNK4_OFF + 16)
+#define RESOURCE_CHUNK6_OFF 82 //(RESOURCE_CHUNK5_OFF + 26)
+#define RESOURCE_CHUNK7_OFF 108 //(RESOURCE_CHUNK6_OFF + 26)
+
+#define PciResourceStart Local0
+#define PciResourceLen Local1
+
+ Name(P0RS, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( // Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ IO( // Consumed resource (CF8-CFF)
+ Decode16,
+ 0x0cf8,
+ 0xcf8,
+ 1,
+ 8
+ )
+
+ //RESOURCE_CHUNK3_OFF
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Min
+ 0x0cf7, // Max
+ 0x0000, // Translation
+ 0x0cf8 // Range Length
+ )
+
+ //RESOURCE_CHUNK4_OFF
+ WORDIO( // Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // Descriptor Name
+ )
+
+ //RESOURCE_CHUNK6_OFF
+ DWORDMEMORY( // descriptor for Shadow RAM
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ 0x00000000, // Min (calculated dynamically)
+ 0x00000000, // Max (calculated dynamically)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically)
+ ,
+ ,
+ SRAM // DescriptorName populated so iASL doesn't flag 0 value fields and no tag as error
+ )
+/*
+ //RESOURCE_TPM
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ 0xFED40000, // Min (calculated dynamically)
+ 0xFEDFFFFF, // Max = 4GB - 1MB (fwh + fwh alias...)
+ 0x00000000, // Translation
+ 0x000C0000 // Range Length (calculated dynamically)
+ )
+*/
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable,
+ ReadWrite,0x00,0xFE010000,0xFE010FFF,0x00,0x1000)
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of P0RS Buffer
+
+ OperationRegion(TMEM, PCI_Config, 0x00, 0x100)
+ Field(TMEM, ByteAcc, NoLock, Preserve) {
+ Offset(0x40),
+ , 4,
+ BSEG, 4,
+ PAMS, 48,
+ Offset(0x52),
+ DIM0, 4,
+ DIM1, 4,
+ , 8,
+ DIM2, 4,
+ }
+
+ Name(MTBL, Package(0x10) {
+ 0x0,
+ 0x20,
+ 0x20,
+ 0x30,
+ 0x40,
+ 0x40,
+ 0x60,
+ 0x80,
+ 0x80,
+ 0x80,
+ 0x80,
+ 0xc0,
+ 0x100,
+ 0x100,
+ 0x100,
+ 0x200
+ })
+
+ Name(ERNG, Package(0xd) {
+ 0xc0000,
+ 0xc4000,
+ 0xc8000,
+ 0xcc000,
+ 0xd0000,
+ 0xd4000,
+ 0xd8000,
+ 0xdc000,
+ 0xe0000,
+ 0xe4000,
+ 0xe8000,
+ 0xec000,
+ 0xf0000
+ })
+
+ Name(PAMB, Buffer(0x7) {
+ })
+
+ Method(EROM, 0x0, NotSerialized) {
+ CreateDWordField(P0RS, ^SRAM._MIN, RMIN) // Do not reference hard-coded address
+ CreateDWordField(P0RS, ^SRAM._MAX, RMAX) // Do not reference hard-coded address
+ CreateDWordField(P0RS, ^SRAM._LEN, RLEN) // Do not reference hard-coded address
+ CreateByteField(PAMB, 0x6, BREG)
+ Store(PAMS, PAMB)
+ Store(BSEG, BREG)
+ Store(0x0, RMIN)
+ Store(0x0, RMAX)
+ Store(0x0, RLEN)
+ Store(0x0, Local0)
+ While(LLess(Local0, 0xd))
+ {
+ ShiftRight(Local0, 0x1, Local1)
+ Store(DerefOf(Index(PAMB, Local1, )), Local2)
+ If(And(Local0, 0x1, ))
+ {
+ ShiftRight(Local2, 0x4, Local2)
+ }
+ And(Local2, 0x3, Local2)
+ If(RMIN)
+ {
+ If(Local2)
+ {
+ Add(DerefOf(Index(ERNG, Local0, )), 0x3fff, RMAX)
+ If(LEqual(RMAX, 0xf3fff))
+ {
+ Store(0xfffff, RMAX)
+ }
+ Subtract(RMAX, RMIN, RLEN)
+ Increment(RLEN)
+ }
+ Else
+ {
+ Store(0xc, Local0)
+ }
+ }
+ Else
+ {
+ If(Local2)
+ {
+ Store(DerefOf(Index(ERNG, Local0, )), RMIN)
+ Add(DerefOf(Index(ERNG, Local0, )), 0x3fff, RMAX)
+ If(LEqual(RMAX, 0xf3fff))
+ {
+ Store(0xfffff, RMAX)
+ }
+ Subtract(RMAX, RMIN, RLEN)
+ Increment(RLEN)
+ }
+ Else
+ {
+ }
+ }
+ Increment(Local0)
+ }
+ }
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ EROM()
+ Return(P0RS)
+ }
+
+ //
+ // Memory Riser UID will be in Interger form to support CPU Migration.
+ // First two digits will indicate Memory Device(01) and last two
+ // digits will represent the Memory Riser number.
+ //
+ Device (MHP0) {
+ // Within the IIO, read D5:F1 for Memory HP status
+ Name(_ADR, 0x00050001) // D5:F1
+ Name(_UID, "00-00")
+
+ // MHP0 - Config register for Slot status
+ OperationRegion(MHP0, PCI_Config, 0x00, 0x100)
+ Field(MHP0,ByteAcc,NoLock,Preserve) {
+ Offset(0x0E),
+ STM0,7,
+ }
+ }
+
+ Device (MHP1) {
+ // Within the IIO, read D5:F1 for Memory HP status
+ Name(_ADR, 0x00050001) // D5:F1
+ Name(_UID, "00-01")
+
+ // MHP1 - Config register for Slot status
+ OperationRegion(MHP1, PCI_Config, 0x00, 0x100)
+ Field(MHP1,ByteAcc,NoLock,Preserve) {
+ Offset(0x1E),
+ STM1,7,
+ }
+ }
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC01.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC01.asi new file mode 100644 index 0000000000..aeb0d2ef83 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC01.asi @@ -0,0 +1,261 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ //
+ // Set this root port to use the correct Proximity Domain
+ //
+ Name(_PXM, 0)
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ Store (0xE3, IO80)
+ \_SB.PC01.BR1A.OSHP ()
+ \_SB.PC01.BR1B.OSHP ()
+ \_SB.PC01.BR1C.OSHP ()
+ \_SB.PC01.BR1D.OSHP ()
+
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 0, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Shift for IIO Stack 1
+ ShiftRight(IIOH, 1, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR01, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR01 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR01)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC02.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC02.asi new file mode 100644 index 0000000000..f92d2eea84 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC02.asi @@ -0,0 +1,261 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ //
+ // Set this root port to use the correct Proximity Domain
+ //
+ Name(_PXM, 0)
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ \_SB.PC02.BR2A.OSHP ()
+ \_SB.PC02.BR2B.OSHP ()
+ \_SB.PC02.BR2C.OSHP ()
+ \_SB.PC02.BR2D.OSHP ()
+
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 0, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Shift for IIO Stack 2
+ ShiftRight(IIOH, 2, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR02, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR02 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR02)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC03.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC03.asi new file mode 100644 index 0000000000..466537d014 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC03.asi @@ -0,0 +1,266 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ //
+ // Set this root port to use the correct Proximity Domain
+ //
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(0)
+ } else {
+ Return(1)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ \_SB.PC03.BR3A.OSHP ()
+ \_SB.PC03.BR3B.OSHP ()
+ \_SB.PC03.BR3C.OSHP ()
+ \_SB.PC03.BR3D.OSHP ()
+
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 0, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Shift for IIO Stack 3
+ ShiftRight(IIOH, 3, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR03, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR03 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR03)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC04.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC04.asi new file mode 100644 index 0000000000..2ff1c2f64d --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC04.asi @@ -0,0 +1,238 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ //
+ // Set this root port to use the correct Proximity Domain
+ //
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(0)
+ } else {
+ Return(1)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 0, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Shift for IIO Stack 4
+ ShiftRight(IIOH, 4, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR04, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR04 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR04)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC05.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC05.asi new file mode 100644 index 0000000000..f2b9bce5e3 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC05.asi @@ -0,0 +1,239 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ //
+ // Set this root port to use the correct Proximity Domain
+ //
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(0)
+ } else {
+ Return(1)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 0, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Shift for IIO Stack 5
+ ShiftRight(IIOH, 5, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR05, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR05 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR05)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC06.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC06.asi new file mode 100644 index 0000000000..bc856473bb --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC06.asi @@ -0,0 +1,334 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(1)
+ } else {
+ Return(2)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ \_SB.PC06.QRP0.OSHP ()
+
+
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+
+ // owning control method can't be reentrant, so _DSM must be Serialized
+ Method (_DSM, 4, Serialized) { // Device specific method
+ if(LEqual(Arg0,ToUUID("D8C1A3A6-BE9B-4C9B-91BF-C3CB81FC5DAF"))){
+ Switch(ToInteger(Arg2)) {
+ case(0) {Return ( Buffer() {0x1F} )} // function indexes 1-4 supported
+ case(1) {Return (Buffer() {0x44, 0x52, 0x48, 0x31,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00 } ) } // DRHD buffer containing relavent ATSR structure for I/O Hub n
+
+ case(2) {Return (Buffer() {0x41, 0x54, 0x53, 0x31,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00 } ) }// ATSR buffer containing relavent ATSR structure for I/O Hub n
+ case(3) {Return (Buffer() {0x52, 0x48, 0x53, 0x31,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00 } ) }// RHSA buffer containing relavent ATSR structure for I/O Hub n
+ Default { }
+ }
+ }
+ Return (Buffer() {0})
+ }
+
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 1, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 1 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 8, Local1)
+ // Shift for IIO Stack 0
+ ShiftRight(Local1, 0, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+/* TODO: ifdef does not work here, need to enable this code after PPO
+ // All PCI-Ex ports are dependent on IIOx stack
+ Name(_EDL, Package() {
+ \_SB.PC06.QRP0, \_SB.PC07.QR1A, \_SB.PC07.QR1B, \_SB.PC07.QR1C, \_SB.PC07.QR1D,
+ \_SB.PC08.QR2A, \_SB.PC08.QR2B, \_SB.PC08.QR2C, \_SB.PC08.QR2D,
+ \_SB.PC09.QR3A, \_SB.PC09.QR3B, \_SB.PC09.QR3C, \_SB.PC09.QR3D
+ })
+*/
+ Name(PR06, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR06 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR06)
+ }
+
+ //
+ // Memory Riser UID will be in Interger form to support CPU Migration.
+ // First two digits will indicate Memory Device(01) and last two
+ // digits will represent the Memory Riser number.
+ //
+ Device (MHP0) {
+ // Within the IIO, read D5:F1 for Memory HP status
+ Name(_ADR, 0x00050001) // D5:F1
+ Name(_UID, "01-00")
+
+ // MHP0 - Config register for Slot status
+ OperationRegion(MHP0, PCI_Config, 0xE, 2)
+ Field(MHP0,ByteAcc,NoLock,Preserve) {
+ STM2,7,
+ }
+ }
+
+ Device (MHP1) {
+ // Within the IIO, read D5:F1 for Memory HP status
+ Name(_ADR, 0x00050001) // D5:F1
+ Name(_UID, "01-01")
+
+ // MHP1 - Config register for Slot status
+ OperationRegion(MHP1, PCI_Config, 0x1E, 2)
+ Field(MHP1,ByteAcc,NoLock,Preserve) {
+ STM3,7,
+ }
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC06Ejd.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC06Ejd.asi new file mode 100644 index 0000000000..1921d0e157 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC06Ejd.asi @@ -0,0 +1,15 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ // Eject device if PC06 is removed.
+ Name(_EJD,"\\_SB.PC06") // Dependent on PC06
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC07.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC07.asi new file mode 100644 index 0000000000..50c1269e4e --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC07.asi @@ -0,0 +1,265 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(1)
+ } else {
+ Return(2)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ \_SB.PC07.QR1A.OSHP ()
+ \_SB.PC07.QR1B.OSHP ()
+ \_SB.PC07.QR1C.OSHP ()
+ \_SB.PC07.QR1D.OSHP ()
+
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 1, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 1 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 8, Local1)
+ // Shift for IIO Stack 1
+ ShiftRight(Local1, 1, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR07, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR07 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR07)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC08.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC08.asi new file mode 100644 index 0000000000..18c737a55a --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC08.asi @@ -0,0 +1,268 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(1)
+ } else {
+ Return(2)
+ }
+ }
+
+//
+// Moving _OSC method to respective stack PCXX.asi.
+//
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ \_SB.PC08.QR2A.OSHP ()
+ \_SB.PC08.QR2B.OSHP ()
+ \_SB.PC08.QR2C.OSHP ()
+ \_SB.PC08.QR2D.OSHP ()
+
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 1, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 1 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 8, Local1)
+ // Shift for IIO Stack 2
+ ShiftRight(Local1, 2, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR08, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR08 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR08)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC09.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC09.asi new file mode 100644 index 0000000000..66730a27e9 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC09.asi @@ -0,0 +1,266 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(1)
+ } else {
+ Return(3)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ \_SB.PC09.QR3A.OSHP ()
+ \_SB.PC09.QR3B.OSHP ()
+ \_SB.PC09.QR3C.OSHP ()
+ \_SB.PC09.QR3D.OSHP ()
+
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 1, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 1 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 8, Local1)
+ // Shift for IIO Stack 3
+ ShiftRight(Local1, 3, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR09, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR09 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR09)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC10.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC10.asi new file mode 100644 index 0000000000..a12136c053 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC10.asi @@ -0,0 +1,238 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(1)
+ } else {
+ Return(3)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 1, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 1 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 8, Local1)
+ // Shift for IIO Stack 4
+ ShiftRight(Local1, 4, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR10, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR10 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR10)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC11.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC11.asi new file mode 100644 index 0000000000..efafb7ea99 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC11.asi @@ -0,0 +1,237 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(1)
+ } else {
+ Return(3)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 1, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 1 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 8, Local1)
+ // Shift for IIO Stack 5
+ ShiftRight(Local1, 5, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR11, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR11 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR11)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC12.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC12.asi new file mode 100644 index 0000000000..bd860fe411 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC12.asi @@ -0,0 +1,330 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(2)
+ } else {
+ Return(4)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ \_SB.PC12.RRP0.OSHP ()
+
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+ // owning control method can't be reentrant, so _DSM must be Serialized
+ Method (_DSM, 4, Serialized) { // Device specific method
+ if(LEqual(Arg0,ToUUID("D8C1A3A6-BE9B-4C9B-91BF-C3CB81FC5DAF"))){
+ Switch(ToInteger(Arg2)) {
+ case(0) {Return ( Buffer() {0x1F} )} // function indexes 1-4 supported
+ case(1) {Return (Buffer() {0x44, 0x52, 0x48, 0x32,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00 } ) } // DRHD buffer containing relavent ATSR structure for I/O Hub n
+
+ case(2) {Return (Buffer() {0x41, 0x54, 0x53, 0x32,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00 } ) }// ATSR buffer containing relavent ATSR structure for I/O Hub n
+ case(3) {Return (Buffer() {0x52, 0x48, 0x53, 0x32,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00 } ) }// RHSA buffer containing relavent ATSR structure for I/O Hub n
+ Default { }
+ }
+ }
+ Return (Buffer() {0})
+ }
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 2, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 2 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 16, Local1)
+ // Shift for IIO Stack 0
+ ShiftRight(Local1, 0, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+/* TODO: ifdef does not work here, need to enable this code after PPO
+ // All PCI-Ex ports are dependent on IIO2
+ Name(_EDL, Package() {
+ \_SB.PC12.RRP0, \_SB.PC13.RR1A, \_SB.PC13.RR1B, \_SB.PC13.RR1C, \_SB.PC13.RR1D,
+ \_SB.PC14.RR2A, \_SB.PC14.RR2B, \_SB.PC14.RR2C, \_SB.PC14.RR2D,
+ \_SB.PC15.RR3A, \_SB.PC15.RR3B, \_SB.PC15.RR3C, \_SB.PC15.RR3D
+ })
+*/
+ Name(PR12, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR12 Buffer
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR12)
+ }
+
+ //
+ // Memory Riser UID will be in Interger form to support CPU Migration.
+ // First two digits will indicate Memory Device(01) and last two
+ // digits will represent the Memory Riser number.
+ //
+ Device (MHP0) {
+ // Within the IIO, read D5:F1 for Memory HP status
+ Name(_ADR, 0x00050001) // D5:F1
+ Name(_UID, "02-00")
+
+ // MHP0 - Config register for Slot status
+ OperationRegion(MHP0, PCI_Config, 0xE, 2)
+ Field(MHP0,ByteAcc,NoLock,Preserve) {
+ STM4,7,
+ }
+ }
+
+ Device (MHP1) {
+ // Within the IIO, read D5:F1 for Memory HP status
+ Name(_ADR, 0x00050001) // D5:F1
+ Name(_UID, "02-01")
+
+ // MHP1 - Config register for Slot status
+ OperationRegion(MHP1, PCI_Config, 0x1E, 2)
+ Field(MHP1,ByteAcc,NoLock,Preserve) {
+ STM5,7,
+ }
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC12Ejd.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC12Ejd.asi new file mode 100644 index 0000000000..7a9aedf818 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC12Ejd.asi @@ -0,0 +1,15 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ // Eject device if PC12 is removed.
+ Name(_EJD,"\\_SB.PC12") // Dependent on PC12
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC13.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC13.asi new file mode 100644 index 0000000000..3183a62ff2 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC13.asi @@ -0,0 +1,262 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(2)
+ } else {
+ Return(4)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ \_SB.PC13.RR1A.OSHP ()
+ \_SB.PC13.RR1B.OSHP ()
+ \_SB.PC13.RR1C.OSHP ()
+ \_SB.PC13.RR1D.OSHP ()
+
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 2, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 2 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 16, Local1)
+ // Shift for IIO Stack 1
+ ShiftRight(Local1, 1, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR13, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR13 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR13)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC14.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC14.asi new file mode 100644 index 0000000000..24b1d0e35c --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC14.asi @@ -0,0 +1,265 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(2)
+ } else {
+ Return(4)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ //Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ \_SB.PC14.RR2A.OSHP ()
+ \_SB.PC14.RR2B.OSHP ()
+ \_SB.PC14.RR2C.OSHP ()
+ \_SB.PC14.RR2D.OSHP ()
+
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 2, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 2 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 16, Local1)
+ // Shift for IIO Stack 2
+ ShiftRight(Local1, 2, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR14, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR14 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR14)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC15.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC15.asi new file mode 100644 index 0000000000..77f5aa8185 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC15.asi @@ -0,0 +1,265 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(2)
+ } else {
+ Return(5)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ \_SB.PC15.RR3A.OSHP ()
+ \_SB.PC15.RR3B.OSHP ()
+ \_SB.PC15.RR3C.OSHP ()
+ \_SB.PC15.RR3D.OSHP ()
+
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 2, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 2 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 16, Local1)
+ // Shift for IIO Stack 3
+ ShiftRight(Local1, 3, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR15, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR15 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR15)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC16.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC16.asi new file mode 100644 index 0000000000..1d4e6d89df --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC16.asi @@ -0,0 +1,237 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(2)
+ } else {
+ Return(5)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 2, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 2 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 16, Local1)
+ // Shift for IIO Stack 4
+ ShiftRight(Local1, 4, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR16, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR16 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR16)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC17.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC17.asi new file mode 100644 index 0000000000..4e04769467 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC17.asi @@ -0,0 +1,237 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(2)
+ } else {
+ Return(5)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 2, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 2 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 16, Local1)
+ // Shift for IIO Stack 5
+ ShiftRight(Local1, 5, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR17, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR17 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR17)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC18.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC18.asi new file mode 100644 index 0000000000..ca8f18ecd2 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC18.asi @@ -0,0 +1,348 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(3)
+ } else {
+ Return(6)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ \_SB.PC18.SRP0.OSHP ()
+
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+
+ // owning control method can't be reentrant, so _DSM must be Serialized
+ Method (_DSM, 4, Serialized) { // Device specific method
+ if(LEqual(Arg0,ToUUID("D8C1A3A6-BE9B-4C9B-91BF-C3CB81FC5DAF"))){
+ Switch(ToInteger(Arg2)) {
+ case(0) {Return ( Buffer() {0x1F} )} // function indexes 1-4 supported
+ case(1) {Return (Buffer() {0x44, 0x52, 0x48, 0x33,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00 } ) } // DRHD buffer containing relavent ATSR structure for I/O Hub n
+
+ case(2) {Return (Buffer() {0x41, 0x54, 0x53, 0x33,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00 } ) }// ATSR buffer containing relavent ATSR structure for I/O Hub n
+ case(3) {Return (Buffer() {0x52, 0x48, 0x53, 0x33,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00 } ) }// RHSA buffer containing relavent ATSR structure for I/O Hub n
+ Default { }
+ }
+ }
+ Return (Buffer() {0})
+ }
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 3, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 3 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 24, Local1)
+ // Shift for IIO Stack 0
+ ShiftRight(Local1, 0, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+/* TODO: ifdef does not work here, need to enable this code after PPO
+ // All PCI-Ex ports are dependent on IIO3
+ Name(_EDL, Package() {
+ \_SB.PC18.SRP0, \_SB.PC19.SR1A, \_SB.PC19.SR1B, \_SB.PC19.SR1C, \_SB.PC19.SR1D,
+ \_SB.PC20.SR2A, \_SB.PC20.SR2B, \_SB.PC20.SR2C, \_SB.PC20.SR2D,
+ \_SB.PC21.SR3A, \_SB.PC21.SR3B, \_SB.PC21.SR3C, \_SB.PC21.SR3D
+ })
+
+ Method(_EJ0, 1) {
+ Notify(\_SB.PC18.SRP0, Arg0)
+ Notify(\_SB.PC19.SR1A, Arg0)
+ Notify(\_SB.PC19.SR1B, Arg0)
+ Notify(\_SB.PC19.SR1C, Arg0)
+ Notify(\_SB.PC19.SR1D, Arg0)
+ Notify(\_SB.PC20.SR2A, Arg0)
+ Notify(\_SB.PC20.SR2B, Arg0)
+ Notify(\_SB.PC20.SR2C, Arg0)
+ Notify(\_SB.PC20.SR2D, Arg0)
+ Notify(\_SB.PC21.SR3A, Arg0)
+ Notify(\_SB.PC21.SR3B, Arg0)
+ Notify(\_SB.PC21.SR3C, Arg0)
+ Notify(\_SB.PC21.SR3D, Arg0)
+ \_SB.GSMI(3, 3) //EVENT_IIO_HP, IIO ID
+ }
+*/
+ Name(PR18, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIXH - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR18 Buffer
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR18)
+ }
+
+ //
+ // Memory Riser UID will be in Interger form to support CPU Migration.
+ // First two digits will indicate Memory Device(01) and last two
+ // digits will represent the Memory Riser number.
+ //
+ Device (MHP0) {
+ // Within the IIO, read D5:F1 for Memory HP status
+ Name(_ADR, 0x00050001) // D5:F1
+ Name(_UID, "03-00")
+
+ // MHP0 - Config register for Slot status
+ OperationRegion(MHP0, PCI_Config, 0xE, 2)
+ Field(MHP0,ByteAcc,NoLock,Preserve) {
+ STM6,7,
+ }
+ }
+
+ Device (MHP1) {
+ // Within the IIO, read D5:F1 for Memory HP status
+ Name(_ADR, 0x00050001) // D5:F1
+ Name(_UID, "03-01")
+
+ // MHP1 - Config register for Slot status
+ OperationRegion(MHP1, PCI_Config, 0x1E, 2)
+ Field(MHP1,ByteAcc,NoLock,Preserve) {
+ STM7,7,
+ }
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC18Ejd.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC18Ejd.asi new file mode 100644 index 0000000000..6e0a48b128 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC18Ejd.asi @@ -0,0 +1,15 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ // Eject device if PC18 is removed.
+ Name(_EJD,"\\_SB.PC18") // Dependent on PC18
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC19.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC19.asi new file mode 100644 index 0000000000..121645a3cd --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC19.asi @@ -0,0 +1,265 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(3)
+ } else {
+ Return(6)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ \_SB.PC19.SR1A.OSHP ()
+ \_SB.PC19.SR1B.OSHP ()
+ \_SB.PC19.SR1C.OSHP ()
+ \_SB.PC19.SR1D.OSHP ()
+
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 3, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 3 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 24, Local1)
+ // Shift for IIO Stack
+ ShiftRight(Local1, 1, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR19, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR19 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR19)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC20.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC20.asi new file mode 100644 index 0000000000..fcdb44071b --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC20.asi @@ -0,0 +1,266 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(3)
+ } else {
+ Return(6)
+ }
+ }
+
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ \_SB.PC20.SR2A.OSHP ()
+ \_SB.PC20.SR2B.OSHP ()
+ \_SB.PC20.SR2C.OSHP ()
+ \_SB.PC20.SR2D.OSHP ()
+
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 3, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 3 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 24, Local1)
+ // Shift for IIO Stack
+ ShiftRight(Local1, 2, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR20, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR20 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR20)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC21.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC21.asi new file mode 100644 index 0000000000..3ae6e1c8d8 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC21.asi @@ -0,0 +1,266 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(3)
+ } else {
+ Return(7)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ \_SB.PC21.SR3A.OSHP ()
+ \_SB.PC21.SR3B.OSHP ()
+ \_SB.PC21.SR3C.OSHP ()
+ \_SB.PC21.SR3D.OSHP ()
+
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 3, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 3 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 24, Local1)
+ // Shift for IIO Stack 3
+ ShiftRight(Local1, 3, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR21, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR21 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR21)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC22.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC22.asi new file mode 100644 index 0000000000..e3d64db58c --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC22.asi @@ -0,0 +1,238 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(3)
+ } else {
+ Return(7)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 3, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 3 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 24, Local1)
+ // Shift for IIO Stack 4
+ ShiftRight(Local1, 4, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR22, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR22 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR22)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC23.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC23.asi new file mode 100644 index 0000000000..e64380e4e8 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC23.asi @@ -0,0 +1,238 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(3)
+ } else {
+ Return(7)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 3, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 3 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 24, Local1)
+ // Shift for IIO Stack 5
+ ShiftRight(Local1, 5, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR23, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR23 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR23)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC24.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC24.asi new file mode 100644 index 0000000000..bed4dfbc2b --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC24.asi @@ -0,0 +1,237 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(4)
+ } else {
+ Return(8)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 4, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 4 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 32, Local1)
+ // Shift for IIO Stack 0
+ ShiftRight(Local1, 0, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR24, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR24 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR24)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC25.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC25.asi new file mode 100644 index 0000000000..8c2b3b288c --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC25.asi @@ -0,0 +1,265 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(4)
+ } else {
+ Return(8)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ \_SB.PC25.CR1A.OSHP ()
+ \_SB.PC25.CR1B.OSHP ()
+ \_SB.PC25.CR1C.OSHP ()
+ \_SB.PC25.CR1D.OSHP ()
+
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 4, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 4 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 32, Local1)
+ // Shift for IIO Stack 1
+ ShiftRight(Local1, 1, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR25, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR25 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR25)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC26.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC26.asi new file mode 100644 index 0000000000..95aeb03b0d --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC26.asi @@ -0,0 +1,265 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(4)
+ } else {
+ Return(8)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ \_SB.PC26.CR2A.OSHP ()
+ \_SB.PC26.CR2B.OSHP ()
+ \_SB.PC26.CR2C.OSHP ()
+ \_SB.PC26.CR2D.OSHP ()
+
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 4, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 4 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 32, Local1)
+ // Shift for IIO Stack 2
+ ShiftRight(Local1, 2, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR26, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR26 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR26)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC27.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC27.asi new file mode 100644 index 0000000000..750b4eaa24 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC27.asi @@ -0,0 +1,265 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(4)
+ } else {
+ Return(9)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ \_SB.PC27.CR3A.OSHP ()
+ \_SB.PC27.CR3B.OSHP ()
+ \_SB.PC27.CR3C.OSHP ()
+ \_SB.PC27.CR3D.OSHP ()
+
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 4, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 4 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 32, Local1)
+ // Shift for IIO Stack 3
+ ShiftRight(Local1, 3, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR27, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR27 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR27)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC28.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC28.asi new file mode 100644 index 0000000000..3e8b3b24bd --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC28.asi @@ -0,0 +1,238 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(4)
+ } else {
+ Return(9)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 4, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 4 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 32, Local1)
+ // Shift for IIO Stack 4
+ ShiftRight(Local1, 4, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR28, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR28 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR28)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC29.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC29.asi new file mode 100644 index 0000000000..f10ec64b94 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC29.asi @@ -0,0 +1,238 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(4)
+ } else {
+ Return(9)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 4, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 4 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 32, Local1)
+ // Shift for IIO Stack 5
+ ShiftRight(Local1, 5, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR29, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR29 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR29)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC30.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC30.asi new file mode 100644 index 0000000000..ec46cccc38 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC30.asi @@ -0,0 +1,262 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(5)
+ } else {
+ Return(10)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ \_SB.PC30.TRP0.OSHP ()
+
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 5, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 5 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 40, Local1)
+ // Shift for IIO Stack 0
+ ShiftRight(Local1, 0, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR30, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR30 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR30)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC31.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC31.asi new file mode 100644 index 0000000000..382e75f644 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC31.asi @@ -0,0 +1,265 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(5)
+ } else {
+ Return(10)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ \_SB.PC31.TR1A.OSHP ()
+ \_SB.PC31.TR1B.OSHP ()
+ \_SB.PC31.TR1C.OSHP ()
+ \_SB.PC31.TR1D.OSHP ()
+
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 5, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 5 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 40, Local1)
+ // Shift for IIO Stack 1
+ ShiftRight(Local1, 1, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR31, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR31 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR31)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC32.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC32.asi new file mode 100644 index 0000000000..6c921b52db --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC32.asi @@ -0,0 +1,266 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(5)
+ } else {
+ Return(10)
+ }
+ }
+
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ \_SB.PC32.TR2A.OSHP ()
+ \_SB.PC32.TR2B.OSHP ()
+ \_SB.PC32.TR2C.OSHP ()
+ \_SB.PC32.TR2D.OSHP ()
+
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 5, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 5 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 40, Local1)
+ // Shift for IIO Stack 2
+ ShiftRight(Local1, 2, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR32, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR32 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR32)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC33.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC33.asi new file mode 100644 index 0000000000..39097f45d2 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC33.asi @@ -0,0 +1,266 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(5)
+ } else {
+ Return(11)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ \_SB.PC33.TR3A.OSHP ()
+ \_SB.PC33.TR3B.OSHP ()
+ \_SB.PC33.TR3C.OSHP ()
+ \_SB.PC33.TR3D.OSHP ()
+
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 5, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 5 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 40, Local1)
+ // Shift for IIO Stack 3
+ ShiftRight(Local1, 3, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR33, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR33 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR33)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC34.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC34.asi new file mode 100644 index 0000000000..3335a9f77a --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC34.asi @@ -0,0 +1,238 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(5)
+ } else {
+ Return(11)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 5, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 5 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 40, Local1)
+ // Shift for IIO Stack 4
+ ShiftRight(Local1, 4, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR34, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR34 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR34)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC35.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC35.asi new file mode 100644 index 0000000000..03503ce5ee --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC35.asi @@ -0,0 +1,238 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(5)
+ } else {
+ Return(11)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 5, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 5 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 40, Local1)
+ // Shift for IIO Stack 5
+ ShiftRight(Local1, 5, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR35, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR35 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR35)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC36.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC36.asi new file mode 100644 index 0000000000..606c9132a8 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC36.asi @@ -0,0 +1,263 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(6)
+ } else {
+ Return(12)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ \_SB.PC36.URP0.OSHP ()
+
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 6, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 6 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 48, Local1)
+ // Shift for IIO Stack 0
+ ShiftRight(Local1, 0, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR36, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR36 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR36)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC37.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC37.asi new file mode 100644 index 0000000000..8544b4bb9f --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC37.asi @@ -0,0 +1,265 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(6)
+ } else {
+ Return(12)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ \_SB.PC37.UR1A.OSHP ()
+ \_SB.PC37.UR1B.OSHP ()
+ \_SB.PC37.UR1C.OSHP ()
+ \_SB.PC37.UR1D.OSHP ()
+
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 6, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 6 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 48, Local1)
+ // Shift for IIO Stack 1
+ ShiftRight(Local1, 1, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR37, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR37 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR37)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC38.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC38.asi new file mode 100644 index 0000000000..c64a085a9c --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC38.asi @@ -0,0 +1,266 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(6)
+ } else {
+ Return(12)
+ }
+ }
+
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ \_SB.PC38.UR2A.OSHP ()
+ \_SB.PC38.UR2B.OSHP ()
+ \_SB.PC38.UR2C.OSHP ()
+ \_SB.PC38.UR2D.OSHP ()
+
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 6, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 6 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 48, Local1)
+ // Shift for IIO Stack 2
+ ShiftRight(Local1, 2, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR38, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR38 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR38)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC39.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC39.asi new file mode 100644 index 0000000000..24562e7688 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC39.asi @@ -0,0 +1,266 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(6)
+ } else {
+ Return(13)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ \_SB.PC39.UR3A.OSHP ()
+ \_SB.PC39.UR3B.OSHP ()
+ \_SB.PC39.UR3C.OSHP ()
+ \_SB.PC39.UR3D.OSHP ()
+
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 6, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 6 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 48, Local1)
+ // Shift for IIO Stack 3
+ ShiftRight(Local1, 3, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR39, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR39 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR39)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC40.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC40.asi new file mode 100644 index 0000000000..85b0ded149 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC40.asi @@ -0,0 +1,238 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(6)
+ } else {
+ Return(13)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 6, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 6 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 48, Local1)
+ // Shift for IIO Stack 4
+ ShiftRight(Local1, 4, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR40, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR40 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR40)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC41.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC41.asi new file mode 100644 index 0000000000..a6221b7eba --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC41.asi @@ -0,0 +1,238 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(6)
+ } else {
+ Return(13)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 6, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 6 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 48, Local1)
+ // Shift for IIO Stack 5
+ ShiftRight(Local1, 5, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR41, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR41 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR41)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC42.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC42.asi new file mode 100644 index 0000000000..6da3a3e15a --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC42.asi @@ -0,0 +1,296 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(7)
+ } else {
+ Return(14)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ \_SB.PC42.VRP0.OSHP ()
+
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+
+ // owning control method can't be reentrant, so _DSM must be Serialized
+ Method (_DSM, 4, Serialized) { // Device specific method
+ if(LEqual(Arg0,ToUUID("D8C1A3A6-BE9B-4C9B-91BF-C3CB81FC5DAF"))){
+ Switch(ToInteger(Arg2)) {
+ case(0) {Return ( Buffer() {0x1F} )} // function indexes 1-4 supported
+ case(1) {Return (Buffer() {0x44, 0x52, 0x48, 0x33,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00 } ) } // DRHD buffer containing relavent ATSR structure for I/O Hub n
+
+ case(2) {Return (Buffer() {0x41, 0x54, 0x53, 0x33,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00 } ) }// ATSR buffer containing relavent ATSR structure for I/O Hub n
+ case(3) {Return (Buffer() {0x52, 0x48, 0x53, 0x33,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,
+ 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00 } ) }// RHSA buffer containing relavent ATSR structure for I/O Hub n
+ Default { }
+ }
+ }
+ Return (Buffer() {0})
+ }
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 7, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 7 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 56, Local1)
+ // Shift for IIO Stack 0
+ ShiftRight(Local1, 0, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR42, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR42 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR42)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC43.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC43.asi new file mode 100644 index 0000000000..d56c84d8ea --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC43.asi @@ -0,0 +1,265 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(7)
+ } else {
+ Return(14)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ \_SB.PC43.VR1A.OSHP ()
+ \_SB.PC43.VR1B.OSHP ()
+ \_SB.PC43.VR1C.OSHP ()
+ \_SB.PC43.VR1D.OSHP ()
+
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 7, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 7 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 56, Local1)
+ // Shift for IIO Stack 1
+ ShiftRight(Local1, 1, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR43, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR43 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR43)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC44.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC44.asi new file mode 100644 index 0000000000..2b9eaebf90 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC44.asi @@ -0,0 +1,238 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(7)
+ } else {
+ Return(14)
+ }
+ }
+
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 7, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 7 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 56, Local1)
+ // Shift for IIO Stack 2
+ ShiftRight(Local1, 2, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR44, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR44 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR44)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC45.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC45.asi new file mode 100644 index 0000000000..efd01f1a28 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC45.asi @@ -0,0 +1,238 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(7)
+ } else {
+ Return(15)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 7, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 7 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 56, Local1)
+ // Shift for IIO Stack 3
+ ShiftRight(Local1, 3, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR45, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR45 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR45)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC46.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC46.asi new file mode 100644 index 0000000000..bf845cbb9f --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC46.asi @@ -0,0 +1,238 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(7)
+ } else {
+ Return(15)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 7, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 7 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 56, Local1)
+ // Shift for IIO Stack 4
+ ShiftRight(Local1, 4, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR46, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR46 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR46)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC47.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC47.asi new file mode 100644 index 0000000000..67c41e76e8 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC47.asi @@ -0,0 +1,238 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_PXM) {
+ if (LEqual (CLOD, 0)) {
+ Return(7)
+ } else {
+ Return(15)
+ }
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ } // End _OSC
+
+
+ Method(_STA){
+ // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible
+ ShiftRight(PRBM, 7, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if Socket is present
+ if(LEqual(Local1, 0x1)) {
+ // Account for Socket 7 in bitmap (8 x Socket #)
+ ShiftRight(IIOH, 56, Local1)
+ // Shift for IIO Stack 5
+ ShiftRight(Local1, 5, Local1)
+ And(Local1, 0x1, Local1)
+ // Check if IIO Stack is present
+ if(LEqual(Local1, 0x1)) {
+ // IIOx stack present and logically online
+ Return(0x0F)
+ }
+ }
+ // IIOx stack logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name(PR47, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PR47 Buffer
+
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ Return(PR47)
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Pch.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Pch.asi new file mode 100644 index 0000000000..77c4f1797b --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Pch.asi @@ -0,0 +1,16 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+//
+// I/O controller miscellaneous
+//
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchApic.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchApic.asi new file mode 100644 index 0000000000..8c5787c44c --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchApic.asi @@ -0,0 +1,23 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Device(APIC) {
+ Name (_HID,EISAID("PNP0003")) // APIC resources
+ Name (_CRS, ResourceTemplate() {
+ //
+ // APIC range(0xFEC0_0000 to 0xFECF_FFFF)
+ //
+ Memory32Fixed (ReadOnly, 0xFEC00000, 0x100000) // IO APIC
+ }
+ )
+}
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci1.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci1.asi new file mode 100644 index 0000000000..bb6d1fc8c9 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci1.asi @@ -0,0 +1,97 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Name (OPAC, 0)
+
+OperationRegion(PWKE,PCI_Config,0x54,0x18)
+Field(PWKE,DWordAcc,NoLock,Preserve)
+{
+ , 8,
+ PMEE, 1, // PWR_CNTL_STS.PME_En
+ , 6,
+ PMES, 1, // PWR_CNTL_STS.PME_Sts
+ Offset (0x0E),
+ , 1,
+ PWUC, 10 // Port Wake Up Capability Mask
+}
+
+//
+// Indicate access to OperationRegions is enabled/disabled
+//
+Method (_REG, 2)
+{
+ // If OperationRegion ID = PCI_Config
+ //
+ If (LEqual (Arg0, 2))
+ {
+ // If access is enabled
+ //
+ If (LEqual(Arg1, 1))
+ {
+ // Set local flag
+ //
+ Store (One, OPAC)
+ }
+ Else
+ {
+ // Clear local flag
+ //
+ Store (One, OPAC)
+ }
+ }
+}
+
+//
+// Enable/disable ports on this controller to wake the system
+//
+Method (_PSW,1)
+{
+ If (Arg0)
+ {
+ Store (Ones,PWUC)
+ }
+ Else
+ {
+ Store (0,PWUC)
+ }
+}
+
+//
+// Initialization for this controller
+//
+Method (_INI, 0)
+{
+ // If access to OperationRegion is enabled
+ //
+ If (LEqual (OPAC, One))
+ {
+ Store (1, PMES) // clear PME status
+ Store (0, PMEE) // clear PME enable
+ }
+}
+
+// The CRB leaves the USB ports on in S3/S4 to allow
+// the ability to Wake from USB. Therefore, define
+// the below control methods to state D2 entry during
+// the given S-State.
+
+Method(_S3D,0)
+{
+ Return(2)
+}
+
+Method(_S4D,0)
+{
+ Return(2)
+}
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci2.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci2.asi new file mode 100644 index 0000000000..027a362ee5 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci2.asi @@ -0,0 +1,98 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Name (OPAC, 0)
+
+OperationRegion(PWKE,PCI_Config,0x54,0x18)
+Field(PWKE,DWordAcc,NoLock,Preserve)
+{
+ , 8,
+ PMEE, 1, // PWR_CNTL_STS.PME_En
+ , 6,
+ PMES, 1, // PWR_CNTL_STS.PME_Sts
+ Offset (0x0E),
+ , 1,
+ PWUC, 10 // Port Wake Up Capability Mask
+}
+
+//
+// Indicate access to OperationRegions is enabled/disabled
+//
+Method (_REG, 2)
+{
+ // If OperationRegion ID = PCI_Config
+ //
+ If (LEqual (Arg0, 2))
+ {
+ // If access is enabled
+ //
+ If (LEqual(Arg1, 1))
+ {
+ // Set local flag
+ //
+ Store (One, OPAC)
+ }
+ Else
+ {
+ // Clear local flag
+ //
+ Store (One, OPAC)
+ }
+ }
+}
+
+//
+// Enable/disable ports on this controller to wake the system
+//
+Method (_PSW,1)
+{
+ If (Arg0)
+ {
+ Store (Ones,PWUC)
+ }
+ Else
+ {
+ Store (0,PWUC)
+ }
+}
+
+//
+// Initialization for this controller
+//
+Method (_INI, 0)
+{
+ // If access to OperationRegion is enabled
+ //
+ If (LEqual (OPAC, One))
+ {
+ Store (1, PMES) // clear PME status
+ Store (0, PMEE) // clear PME enable
+ }
+}
+
+// The CRB leaves the USB ports on in S3/S4 to allow
+// the ability to Wake from USB. Therefore, define
+// the below control methods to state D2 entry during
+// the given S-State.
+
+Method(_S3D,0)
+{
+ Return(2)
+}
+
+Method(_S4D,0)
+{
+ Return(2)
+}
+
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchGbe.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchGbe.asl new file mode 100644 index 0000000000..9919367878 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchGbe.asl @@ -0,0 +1,23 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+///
+/// Gbe Ethernet ASL methods and structures
+///
+
+ //
+ // GPE bit 13 indicates wake from this device, can wakeup from S4 state
+ //
+ Method(_PRW, 0) {
+ Return(Package() {13, 4})
+ }
\ No newline at end of file diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchLpc.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchLpc.asi new file mode 100644 index 0000000000..51b4f99d3c --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchLpc.asi @@ -0,0 +1,28 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+//
+// Define bits in LPC bridge config space
+// (\_SB.PCI0.LPC0)
+//
+OperationRegion (LPCB, PCI_Config, 0x00, 0x100)
+Field (LPCB, DWordAcc, NoLock, Preserve)
+{
+ Offset (0xAC),
+ , 16,
+ XSMB, 1 // set when OS routes USB ports to xHCI in SmartAuto mode so next POST will know
+}
+
+#include "IrqLink.asl" // PCI routing control methods
+#include "Mother.asi" // Static motherboard device resource declaration
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchSata.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchSata.asi new file mode 100644 index 0000000000..2fdfd2cb1d --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchSata.asi @@ -0,0 +1,813 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ OperationRegion (IDER,PCI_Config,0x40,0x20)
+ Field (IDER, AnyAcc, NoLock, Preserve)
+ {
+ PFT0 , 1 , // Drive 0 Fast Timing Bank (TIME0)
+ PIE0 , 1 , // Drive 0 IORDY Sample Point Enable (IE0)
+ PPE0 , 1 , // Drive 0 Prefetch/Posting Enable (PPE0)
+ PDE0 , 1 , // Drive 0 DMA Timing Enable (DTE0)
+ PFT1 , 1 , // Drive 1 Fast Timing Bank (TIME1)
+ PIE1 , 1 , // Drive 1 IORDY Sample Point Enable (IE1)
+ PPE1 , 1 , // Drive 1 Prefetch/Posting Enable (PPE1)
+ PDE1 , 1 , // Drive 1 DMA Timing Enable (DTE1)
+ PRT0 , 2 , // Drive 0 Recovery Time (RCT)
+ , 2 , // Reserved
+ PIP0 , 2 , // Drive 0 IORDY Sample Point (ISP)
+ PSIT , 1 , // Drive 1 Timing Register Enable (SITRE)
+ PIDE , 1 , // IDE Decode Enable (IDE)
+ offset (0x2) ,
+ SFT0 , 1 , // Drive 0 Fast Timing Bank (TIME0)
+ SIE0 , 1 , // Drive 0 IORDY Sample Point Enable (IE0)
+ SPE0 , 1 , // Drive 0 Prefetch/Posting Enable (PPE0)
+ SDE0 , 1 , // Drive 0 DMA Timing Enable (DTE0)
+ SFT1 , 1 , // Drive 1 Fast Timing Bank (TIME1)
+ SIE1 , 1 , // Drive 1 IORDY Sample Point Enable (IE1)
+ SPE1 , 1 , // Drive 1 Prefetch/Posting Enable (PPE1)
+ SDE1 , 1 , // Drive 1 DMA Timing Enable (DTE1)
+ SRT0 , 2 , // Drive 0 Recovery Time (RCT)
+ , 2 , // Reserved
+ SIP0 , 2 , // Drive 0 IORDY Sample Point (ISP)
+ SSIT , 1 , // Drive 1 Timing Register Enable (SITRE)
+ SIDE , 1 , // IDE Decode Enable (IDE)
+
+ PRT1 , 2 , // Drive 1 Recovery Time (RCT)
+ PIP1 , 2 , // Drive 1 IORDY Sample Point (ISP)
+ SRT1 , 2 , // Drive 1 Recovery Time (RCT)
+ SIP1 , 2 , // Drive 1 IORDY Sample Point (ISP)
+
+ offset (0x08) ,
+
+ UDM0 , 1 , // Primary Drive 0 Synchronous DMA Mode Enable
+ UDM1 , 1 , // Primary Drive 1 Synchronous DMA Mode Enable
+ UDM2 , 1 , // Secondary Drive 0 Synchronous DMA Mode Enable
+ UDM3 , 1 , // Secondary Drive 1 Synchronous DMA Mode Enable
+
+ offset (0x0A) ,
+
+ PCT0 , 2 , // Primary Drive 0 Cycle Time (PCT0)
+ , 2 , // Reserved
+ PCT1 , 2 , // Primary Drive 1 Cycle Time (PCT1)
+ , 2 , // Reserved
+ SCT0 , 2 , // Secondary Drive 0 Cycle Time (SCT0)
+ , 2 , // Reserved
+ SCT1 , 2 , // Secondary Drive 1 Cycle Time (SCT1)
+
+ offset (0x14) ,
+ PCB0 , 1 , // Primary Drive 0 Base Clock (PCB0)
+ PCB1 , 1 , // Primary Drive 0 Base Clock (PCB0)
+ SCB0 , 1 , // Secondary Drive 1 Base Clock (SCB0)
+ SCB1 , 1 , // Secondary Drive 1 Base Clock (SCB1)
+ PCCR , 2 , // Primary Channel Cable Reporting
+ SCCR , 2 , // Secondary Channel Cable Reporting
+ , 4 , // Reserved
+ PUM0 , 1 , // Primary Drive 0 UDMA 5 Supported
+ PUM1 , 1 , // Primary Drive 1 UDMA 5 Supported
+ SUM0 , 1 , // Secondary Drive 0 UDMA 5 Supported
+ SUM1 , 1 , // Secondary Drive 1 UDMA 5 Supported
+ PSIG , 2 , // PRIM_SIG_MODE
+ SSIG , 2 , // SEC_SIG_MODE
+ }
+
+ //
+ // Get PIO Timing
+ // Arg0 Fast PIO Timing
+ // Arg1 DMA Fast Timing
+ // Arg2 RCT Timing
+ // Arg3 ISP Timing
+ //
+
+ Method(GPIO,4)
+ {
+
+ If (LEqual (Or (Arg0, Arg1) , 0) ) {
+ //
+ // No PIO Timing and DMA Timing support
+ //
+ Return (0xFFFFFFFF)
+
+ } Else {
+ If (And ( LEqual (Arg0, 0) , LEqual (Arg1, 1) ) ) {
+ //
+ // Compatible PIO timing support
+ //
+ Return (900)
+ }
+ }
+
+ //
+ // Using ISP and RCT timing , PCI Clock = 33 Mhz , 30ns per clock
+ //
+ Return (Multiply(30,Subtract(9,Add(Arg2,Arg3))))
+ }
+ //
+ // Get DMA Timing
+ // Arg0 UDMA Supported
+ // Arg1 Ata100
+ // Arg2 Ata66/33
+ // Arg3 Cable report / SATA No mater this input
+ // Arg4 Cycle Timing
+ //
+ Method(GDMA,5)
+ {
+ //
+ // Ultra DMA 66 & 100 need 80 pin conductor
+ //
+ If (LEqual (Arg0, 1)) {
+ //
+ // Ultra DMA Support
+ //
+ If (LEqual (Arg1, 1)) {
+ //
+ // ATA100 80 pin conducter support , Ultra DMA 5 Support
+ //
+ If (LEqual (Arg4, 2)) {
+ Return (15)
+ }
+ Return (20)
+
+ }
+ If (LEqual (Arg2, 1)) {
+ //
+ // ATA66 80 pin conducter support , Base Clock 66Mhz , 15ns per clock
+ //
+ Return (Multiply(15,Subtract(4,Arg4)))
+ }
+ //
+ // Else Ultra DMA33Mhz Supported only,Base Clock 33Mhz , 30ns per clock
+ //
+ Return (Multiply(30,Subtract(4,Arg4)))
+ }
+ // Doesnt support DMA mode
+
+ Return (0xFFFFFFFE)
+ }
+ //
+ // Set Flag
+ // Arg0 IORDY for drive 0
+ // Arg1 Ultra DMA for drive 0
+ // Arg2 IORDY for drive 1
+ // Arg3 Ultra DMA for drive 1
+ // Arg4 indicates chipset can set timing independently for each drive
+ //
+ Method(SFLG, 5)
+ {
+ //
+ // The Chipset always support separate timing setting and always support IORDY
+ //
+ Store (0, Local0)
+ Or (Arg1 ,Local0,Local0)
+ Or (ShiftLeft (Arg0,1) ,Local0, Local0)
+ Or (ShiftLeft (Arg2,3) ,Local0, Local0)
+ Or (ShiftLeft (Arg3,2) ,Local0, Local0)
+ Or (ShiftLeft (Arg4,4) ,Local0, Local0)
+ Return (Local0)
+ }
+ //
+ // Set PIO Timing
+ // Arg0 Timing
+ // Arg1 ATA Device PIO Mode Supported Flag
+ // Arg2 ATA Device PIO Mode Supported Timing
+ //
+ // PIO/Mode Timing
+ // PIO0/Compatible 900 ns
+ // PIO2/SW2 240 ns
+ // PIO3/MW1 180 ns
+ // PIO4/MW2 120 ns
+ //
+
+ Method(SPIO , 3)
+ {
+ Name(PBUF, Buffer(5) { 0x00,0x00,0x00,0x00,0x00})
+ CreateByteField(PBUF, 0, RCT)
+ CreateByteField(PBUF, 1, ISP)
+ CreateByteField(PBUF, 2, FAST)
+ CreateByteField(PBUF, 3, DMAE)
+ CreateByteField(PBUF, 4, PIOT)
+ If (LOr (LEqual (Arg0, 0x0), LEqual (Arg0, 0x0FFFFFFFF)) ) {
+
+ Return (PBUF)
+ }
+ If (LGreater (Arg0, 240)) {
+ //
+ // Compatible timing
+ //
+ Store (1, DMAE) // PIO Mode 0
+ Store (0, PIOT) // Set to PIO Mode 0
+
+ } Else {
+ //
+ // Fast Timing Enable
+ //
+ Store (1, FAST)
+
+ If (And (Arg1, 0x002)) {
+ //
+ // ATA Device Supported PIO Mode Report
+ //
+ If (And (LEqual (Arg0, 120), And( Arg2 , 0x002) ) ) {
+ //
+ // Device support PIO Mode 4
+ //
+ Store (3, RCT) // RCT = 1 CLK
+ Store (2, ISP) // ISP = 3 CLK
+ Store (4, PIOT) // Set to PIO Mode 4
+ } Else {
+ If (And (LLessEqual (Arg0, 180), And( Arg2 , 0x001) ) ) {
+ //
+ // Device support PIO Mode 3
+ //
+ Store (1, RCT) // RCT = 3 CLK
+ Store (2, ISP) // ISP = 3 CLK
+ Store (3, PIOT) // Set to PIO Mode 3
+ } Else {
+ //
+ // PIO Mode 2
+ //
+ Store (0, RCT) // RCT = 4 CLK
+ Store (1, ISP) // ISP = 4 CLK
+ Store (2, PIOT) // Set to PIO Mode 2
+ }
+ }
+ }
+ }
+ Return (PBUF)
+ }
+ //
+ // Set DMA Timing
+ // Arg0 Timing
+ // Arg1 ATA Device PIO Mode Supported Flag
+ // Arg2 ATA Device PIO Mode Supported Timing
+ //
+ // UDMA/Mode Timing
+ // UDMA5 20 ns
+ // UDMA4 30 ns
+ // UDMA3 45 ns
+ // UDMA2 60 ns
+ // UDMA1 90 ns
+ // UDMA0 120 ns
+ //
+
+ Method(SDMA , 3)
+ {
+ Name(PBUF, Buffer(5) { 0x00,0x00,0x00,0x00})
+ CreateByteField(PBUF, 0, PCT)
+ CreateByteField(PBUF, 1, PCB)
+ CreateByteField(PBUF, 2, UDMT) // ATA 100 Support
+ CreateByteField(PBUF, 3, UDME) // Ultra DMA Enable
+ CreateByteField(PBUF, 4, DMAT)
+ If (LOr (LEqual (Arg0, 0x0), LEqual (Arg0, 0x0FFFFFFFF)) ) {
+
+ Return (PBUF)
+ }
+ If (LLessEqual (Arg0, 120)) {
+ //
+ // Ultra DMA Supported
+ //
+ If (And (Arg1, 0x004)) {
+ //
+ // ATA Device Supported UDMA Mode Report
+ //
+ Store (1, UDME)
+ If (And (LEqual (Arg0, 15), And( Arg2 , 0x0040) ) ) {
+ //
+ // Ultra DMA 6
+ //
+ Store (1, UDMT)
+ Store (1, PCB)
+ Store (2, PCT)
+ Store (6, DMAT) // Set to UDMA Mode 6
+ } Else {
+ If (And (LEqual (Arg0, 20), And( Arg2 , 0x0020) ) ) {
+ //
+ // Ultra DMA 5
+ //
+ Store (1, UDMT)
+ Store (1, PCB)
+ Store (1, PCT)
+ Store (5, DMAT) // Set to UDMA Mode 5
+ } Else {
+
+ If (And (LLessEqual (Arg0, 30), And( Arg2 , 0x00010) ) ) {
+ //
+ // Ultra DMA 4
+ //
+ Store (1, PCB)
+ Store (2, PCT)
+ Store (4, DMAT) // Set to UDMA Mode 4
+
+ } Else {
+
+ If (And (LLessEqual (Arg0, 45), And( Arg2 , 0x0008) ) ) {
+ //
+ // Ultra DMA 3
+ //
+ Store (1, PCB)
+ Store (1, PCT)
+ Store (3, DMAT) // Set to UDMA Mode 3
+
+ } Else {
+
+ If (And (LLessEqual (Arg0, 60), And( Arg2 , 0x0004) ) ) {
+ //
+ // Ultra DMA 2
+ //
+ Store (2, PCT)
+ Store (2, DMAT) // Set to UDMA Mode 2
+ } Else {
+
+ If (And (LLessEqual (Arg0, 90), And( Arg2 , 0x0002) ) ) {
+ //
+ // Ultra DMA 1
+ //
+ Store (1, PCT)
+ Store (1, DMAT) // Set to UDMA Mode 1
+ } Else {
+
+ If (And (LLessEqual (Arg0, 120), And( Arg2 , 0x0001) ) ) {
+ //
+ // Ultra DMA 0
+ //
+ Store (0, DMAT) // Set to UDMA Mode 0
+ }
+ }}}}}}
+ }
+ }
+ Return (PBUF)
+ }
+
+
+ //
+ // Primary ide channel
+ //
+ Device(PRID)
+ {
+ Name(_ADR,0)
+ Name(TDM0, 0) // Drive 0 Ultra DMA Type
+ Name(TPI0, 0) // Drive 0 PIO Type
+ Name(TDM1, 0) // Drive 1 Ultra DMA Type
+ Name(TPI1, 0) // Drive 1 PIO Type
+
+ Method(_GTM)
+ {
+ Name(PBUF, Buffer(20) { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00 })
+
+ CreateDwordField(PBUF, 0, PIO0)
+ CreateDwordField(PBUF, 4, DMA0)
+ CreateDwordField(PBUF, 8, PIO1)
+ CreateDwordField(PBUF, 12, DMA1)
+ CreateDwordField(PBUF, 16, FLAG)
+
+ Store ( GPIO (PFT0, PDE0, PRT0, PIP0 ), PIO0)
+ //
+ // Setting the Drive1 PIO Timing, check if we use the same timging for
+ // both Drive0 and Drive1, and if the Drive0 is attached, else use
+ // separate timing
+ //
+
+ If ( And (PSIT, 1) ) {
+ Store ( GPIO (PFT1, PDE1, PRT1, PIP1 ), PIO1)
+ } Else {
+ Store ( GPIO (PFT1, PDE1, PRT0, PIP0 ), PIO1)
+ }
+
+ If (LEqual (PIO0, 0xFFFFFFFF)) {
+ Store(PIO0, DMA0)
+ } Else {
+ Store ( GDMA(UDM0, PUM0, PCB0,And (PCCR ,0x1), PCT0) , DMA0)
+ If ( LGreater ( DMA0, PIO0)) {
+ Store(PIO0, DMA0)
+ }
+ }
+ If (LEqual (PIO1, 0xFFFFFFFF)) {
+ Store(PIO1, DMA1)
+ } Else {
+ Store ( GDMA(UDM1, PUM1, PCB1,And (PCCR ,0x2), PCT1) , DMA1)
+ If ( LGreater ( DMA1, PIO1)) {
+ Store(PIO1, DMA1)
+ }
+ }
+ Store (SFLG (PIE0, UDM0, PIE1, UDM1, 1), FLAG)
+
+ Return (PBUF)
+ }
+
+ Method(_STM,3)
+ {
+ CreateDwordField(Arg0, 0, PIO0)
+ CreateDwordField(Arg0, 4, DMA0)
+ CreateDwordField(Arg0, 8, PIO1)
+ CreateDwordField(Arg0, 12, DMA1)
+ CreateDwordField(Arg0, 16, FLAG)
+
+ //
+ // Device 0 Raw data
+ //
+ CreateWordField(Arg1, 106, RPS0) // word 53
+ CreateWordField(Arg1, 128, IOM0) // word 64
+ CreateWordField(Arg1, 176, DMM0) // Word 88
+
+ //
+ // Device 1 Raw data
+ //
+ CreateWordField(Arg2, 106, RPS1) // word 53
+ CreateWordField(Arg2, 128, IOM1) // word 64
+ CreateWordField(Arg2, 176, DMM1) // Word 88
+
+ Name(IOTM, Buffer(5) { 0x00,0x00,0x00,0x00})
+
+ CreateByteField(IOTM, 0, RCT)
+ CreateByteField(IOTM, 1, ISP)
+ CreateByteField(IOTM, 2, FAST)
+ CreateByteField(IOTM, 3, DMAE)
+ CreateByteField(IOTM, 4, TPIO) // PIO Type
+
+ Name(DMAT, Buffer(5) { 0x00,0x00,0x00,0x00})
+
+ CreateByteField(DMAT, 0, PCT)
+ CreateByteField(DMAT, 1, PCB)
+ CreateByteField(DMAT, 2, UDMT) // ATA 100 Support
+ CreateByteField(DMAT, 3, UDME) // Ultra DMA Enable
+ CreateByteField(DMAT, 4, TDMA) // UDMA Type
+
+ If (And (FLAG , 0x10)) {
+ Store (1, PSIT)
+ }
+
+ Store (SPIO (PIO0,RPS0,IOM0), IOTM)
+
+ If (Or (DMAE, FAST)) {
+ Store (RCT, PRT0)
+ Store (ISP, PIP0)
+ Store (FAST, PFT0)
+ Store (DMAE, PDE0)
+ Store (TPIO, TPI0)
+ }
+ Store (SPIO (PIO1,RPS1,IOM1), IOTM)
+
+ If (Or (DMAE, FAST)) {
+ Store (FAST, PFT1)
+ Store (DMAE, PDE1)
+ Store (TPIO, TPI1)
+ If (And (PSIT,1)) {
+ //
+ // Need set Drive 1 PIO Timing seperate
+ //
+ Store (RCT, PRT1)
+ Store (ISP, PIP1)
+ } Else {
+ Store (RCT, PRT0)
+ Store (ISP, PIP0)
+ }
+ }
+ If (And (FLAG , 0x01)) {
+ Store (SDMA (DMA0,RPS0,DMM0), DMAT)
+ Store (PCT , PCT0)
+ Store (PCB , PCB0)
+ Store (UDME, UDM0)
+ Store (UDMT, PUM0)
+ Store (TDMA, TDM0)
+ } Else {
+ Store (0, UDM0)
+ }
+
+ If (And (FLAG , 0x04)) {
+ Store (SDMA (DMA1,RPS1,DMM1), DMAT)
+ Store (PCT , PCT1)
+ Store (PCB , PCB1)
+ Store (UDME, UDM1)
+ Store (UDMT, PUM1)
+ Store (TDMA, TDM1)
+ } Else {
+ Store (0, UDM1)
+ }
+ //
+ // Check IORDY Support
+ //
+ If (And (FLAG , 0x2)) {
+ Store (1 , PIE0)
+ }
+ If (And (FLAG , 0x8)) {
+ Store (1 , PIE1)
+ }
+
+ }
+ Device(MAST)
+ {
+ Name(_ADR,0)
+ Method(_GTF)
+ {
+ //
+ // Set ATA Device to corresponding Mode
+ //
+ Name(ATA0, Buffer(14)
+ { 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF,
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF })
+
+ CreateByteField(ATA0,1,PIO0) // PIO0 = PIO Mode, Drive 0
+ CreateByteField(ATA0,8,DMA0) // DMA0 = DMA Mode, Drive 0
+
+
+ Store (TPI0, PIO0) // Type we Already get
+
+ Or (PIO0, 0x08 ,PIO0)
+
+ If ( And (UDM0, 1)) {
+ Store (TDM0, DMA0) // Ultra DMA
+ Or (DMA0, 0x40, DMA0)
+ } Else {
+ Store (TPI0, DMA0) // Use PIO Timing
+ If ( LNotEqual (DMA0, 0)) {
+ Subtract(DMA0, 2, DMA0)
+ }
+ Or (DMA0, 0x20, DMA0)
+ }
+ Return (ATA0)
+ }
+ }
+ Device(SLAV)
+ {
+ Name(_ADR,1)
+ Method(_GTF)
+ {
+ //
+ // Set ATA Device to corresponding Mode
+ //
+ Name(ATA1, Buffer(14)
+ { 0x03, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xEF,
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xEF })
+
+ CreateByteField(ATA1,1,PIO1) // PIO0 = PIO Mode, Drive 0
+ CreateByteField(ATA1,8,DMA1) // DMA0 = DMA Mode, Drive 0
+
+ Store (TPI1, PIO1) // Type we Already get
+
+ Or (PIO1, 0x08 ,PIO1)
+
+ If ( And (UDM1, 1)) {
+ Store (TDM1, DMA1) // Ultra DMA
+ Or (DMA1, 0x40, DMA1)
+ } Else {
+ Store (TPI1, DMA1) // Use PIO Timing
+ If ( LNotEqual (DMA1, 0)) {
+ Subtract(DMA1, 2, DMA1)
+ }
+ Or (DMA1, 0x20, DMA1)
+ }
+ Return(ATA1)
+ }
+ }
+ }
+ //
+ // Secondary SATA channel
+ //
+ Device(SECD)
+ {
+ Name(_ADR,1)
+ Name(TDM0, 0)
+ Name(TPI0, 0)
+ Name(TDM1, 0)
+ Name(TPI1, 0)
+
+ Name(DMT1, Buffer(5) { 0x00,0x00,0x00,0x00})
+ Name(DMT2, Buffer(5) { 0x00,0x00,0x00,0x00})
+ Name(POT1, Buffer(5) { 0x00,0x00,0x00,0x00})
+ Name(POT2, Buffer(5) { 0x00,0x00,0x00,0x00})
+
+ Name(STMI, Buffer(20) { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00 })
+
+ Method(_GTM)
+ {
+ Name(PBUF, Buffer(20) { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00 })
+
+ CreateDwordField(PBUF, 0, PIO0)
+ CreateDwordField(PBUF, 4, DMA0)
+ CreateDwordField(PBUF, 8, PIO1)
+ CreateDwordField(PBUF, 12, DMA1)
+ CreateDwordField(PBUF, 16, FLAG)
+
+ Store ( GPIO (SFT0, SDE0, SRT0, SIP0 ), PIO0)
+ //
+ // Setting the Drive1 PIO Timing, check if we use the same timging for
+ // both Drive0 and Drive1, and if the Drive0 is attached, else use
+ // separate timing
+ //
+ If ( And (SSIT, 1) ) {
+ Store ( GPIO (SFT1, SDE1, SRT1, SIP1 ), PIO1)
+ } Else {
+ Store ( GPIO (SFT1, SDE1, SRT0, SIP0 ), PIO1)
+ }
+
+ If (LEqual (PIO0, 0xFFFFFFFF)) {
+ Store(PIO0, DMA0)
+ } Else {
+ Store ( GDMA(UDM2, SUM0, SCB0,And (SCCR ,0x1), SCT0) , DMA0)
+ If ( LGreater ( DMA0, PIO0)) {
+ Store(PIO0, DMA0)
+ }
+ }
+
+ If (LEqual (PIO1, 0xFFFFFFFF)) {
+ Store(PIO1, DMA1)
+ } Else {
+ Store ( GDMA(UDM3, SUM1, SCB1,And (SCCR ,0x2), SCT1) , DMA1)
+ If ( LGreater ( DMA1, PIO1)) {
+ Store(PIO1, DMA1)
+ }
+ }
+
+ Store (SFLG (SIE0, UDM2, SIE1, UDM3, 1), FLAG)
+
+ Return (PBUF)
+ }
+ Method(_STM,3)
+ {
+ CreateDwordField(Arg0, 0, PIO0)
+ CreateDwordField(Arg0, 4, DMA0)
+ CreateDwordField(Arg0, 8, PIO1)
+ CreateDwordField(Arg0, 12, DMA1)
+ CreateDwordField(Arg0, 16, FLAG)
+
+ Store (Arg0, STMI)
+ //
+ // Device 0 Raw data
+ //
+ CreateWordField(Arg1, 106, RPS0) // word 53
+ CreateWordField(Arg1, 128, IOM0) // word 64
+ CreateWordField(Arg1, 176, DMM0) // Word 88
+
+ //
+ // Device 1 Raw data
+ //
+ CreateWordField(Arg2, 106, RPS1) // word 53
+ CreateWordField(Arg2, 128, IOM1) // word 64
+ CreateWordField(Arg2, 176, DMM1) // Word 88
+
+ Name(IOTM, Buffer(5) { 0x00,0x00,0x00,0x00})
+
+ CreateByteField(IOTM, 0, RCT)
+ CreateByteField(IOTM, 1, ISP)
+ CreateByteField(IOTM, 2, FAST)
+ CreateByteField(IOTM, 3, DMAE)
+ CreateByteField(IOTM, 4, TPIO) // PIO Type
+
+ Name(DMAT, Buffer(5) { 0x00,0x00,0x00,0x00})
+
+ CreateByteField(DMAT, 0, PCT)
+ CreateByteField(DMAT, 1, PCB)
+ CreateByteField(DMAT, 2, UDMT) // ATA 100 Support
+ CreateByteField(DMAT, 3, UDME) // Ultra DMA Enable
+ CreateByteField(DMAT, 4, TDMA) // UDMA Type
+
+ If (And (FLAG , 0x10)) {
+ Store (1, SSIT)
+ }
+
+ //
+ // Get Timing and Flag Setting
+ //
+ Store (SPIO (PIO0,RPS0,IOM0), IOTM)
+ //
+ // If no drive0 connect, do nothing to program Drive0 timing
+ //
+ If (Or (DMAE, FAST)) {
+ Store (RCT, SRT0)
+ Store (ISP, SIP0)
+ Store (FAST, SFT0)
+ Store (DMAE, SDE0)
+ Store (TPIO, TPI0)
+ }
+
+ Store (SPIO (PIO1,RPS1,IOM1), IOTM)
+
+ Store (IOTM,POT2)
+
+ If (Or (DMAE, FAST)) {
+ Store (FAST, SFT1)
+ Store (DMAE, SDE1)
+ Store (TPIO, TPI1)
+ If (And (SSIT,1)) {
+ //
+ // Need set Drive 1 PIO Timing separately
+ //
+ Store (RCT, SRT1)
+ Store (ISP, SIP1)
+ } Else {
+ Store (RCT, SRT0)
+ Store (ISP, SIP0)
+ }
+ }
+
+ If (And (FLAG , 0x01)) {
+ Store (SDMA (DMA0,RPS0,DMM0), DMAT)
+ Store (PCT , SCT0)
+ Store (PCB , SCB0)
+ Store (UDME , UDM2)
+ Store (UDMT , SUM0)
+ Store (TDMA, TDM0)
+ } Else {
+ Store (0, UDM2)
+ }
+ If (And (FLAG , 0x04)) {
+ Store (SDMA (DMA1,RPS1,DMM1), DMAT)
+ Store (PCT , SCT1)
+ Store (PCB , SCB1)
+ Store (UDME , UDM3)
+ Store (UDMT , SUM1)
+ Store (TDMA , TDM1)
+ } Else {
+ Store (0, UDM3)
+ }
+ //
+ // Check IORDY Support
+ //
+ If (And (FLAG , 0x2)) {
+ Store (1 , SIE0)
+ }
+ If (And (FLAG , 0x8)) {
+ Store (1 , SIE1)
+ }
+
+ }
+ Device(MAST)
+ {
+ Name(_ADR,0)
+ Method(_GTF)
+ {
+ //
+ // Set ATA Device to corresponding Mode
+ //
+ Name(ATA0, Buffer(14)
+ { 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF,
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF })
+
+ CreateByteField(ATA0,1,PIO0) // PIO0 = PIO Mode, Drive 0
+ CreateByteField(ATA0,8,DMA0) // DMA0 = DMA Mode, Drive 0
+
+ Store (TPI0, PIO0) // Type we Already get
+
+ Or (PIO0, 0x08 ,PIO0)
+
+ If ( And (UDM2, 1)) {
+ Store (TDM0, DMA0) // Ultra DMA
+ Or (DMA0, 0x40, DMA0)
+ } Else {
+ Store (TPI0, DMA0) // Use PIO Timing
+ If ( LNotEqual (DMA0, 0)) {
+ Subtract(DMA0, 2, DMA0)
+ }
+ Or (DMA0, 0x20, DMA0)
+ }
+ Return (ATA0)
+ }
+ }
+ Device(SLAV)
+ {
+ Name(_ADR,1)
+ Method(_GTF)
+ {
+ //
+ // Set ATA Device to corresponding Mode
+ //
+ Name(ATA1, Buffer(14)
+ { 0x03, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xEF,
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xEF })
+
+ CreateByteField(ATA1,1,PIO1) // PIO0 = PIO Mode, Drive 0
+ CreateByteField(ATA1,8,DMA1) // DMA0 = DMA Mode, Drive 0
+
+ Store (TPI1, PIO1) // Type we Already get
+
+ Or (PIO1, 0x08 ,PIO1)
+
+ If ( And (UDM3, 1)) {
+ Store (TDM1, DMA1) // Ultra DMA
+ Or (DMA1, 0x40, DMA1)
+ } Else {
+ Store (TPI1, DMA1) // Use PIO Timing
+ If ( LNotEqual (DMA1, 0)) {
+ Subtract(DMA1, 2, DMA1)
+ }
+ Or (DMA1, 0x20, DMA1)
+ }
+ Return(ATA1)
+ }
+ }
+ }
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchXhci.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchXhci.asi new file mode 100644 index 0000000000..22a4ab5234 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchXhci.asi @@ -0,0 +1,335 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Name (OPAC, Zero)
+Name (XRST, Zero)
+Name (XUSB, Zero)
+
+OperationRegion (XPRT, PCI_Config, 0x74, 0x6C)
+Field (XPRT, DWordAcc, NoLock, Preserve)
+{
+ , 8,
+ PMEE, 1, // PWR_CNTL_STS.PME_En
+ , 6,
+ PMES, 1, // PWR_CNTL_STS.PME_Sts
+ Offset (0x5C),
+ PR2, 32, // XUSB2PR: xHC USB 2.0 Port Routing Register.
+ PR2M, 32, // XUSB2PRM: xHC USB 2.0 Port Routing Mask Register.
+ PR3, 32, // USB3_PSSEN: USB3.0 Port SuperSpeed Enable Register.
+ PR3M, 32 // USB3PRM: USB3.0 Port Routing Mask Register
+}
+
+Method (_PSW,1)
+{
+ If (Arg0)
+ {
+ Store (Ones,PMEE)
+ }
+ Else
+ {
+ Store (0,PMEE)
+ }
+}
+
+
+//
+// Indicate access to OperationRegions is enabled/disabled
+//
+Method (_REG, 2) {
+ //
+ // If OperationRegion ID = PCI_Config
+ //
+ If (LEqual (Arg0, 2)) {
+ //
+ // If access is enabled
+ //
+ If (LEqual(Arg1, 1)) {
+ //
+ // Set local flag
+ //
+ Store (One, OPAC)
+
+ } Else {
+ //
+ // Clear local flag
+ //
+ Store (One, OPAC)
+ }
+ }
+}
+
+//
+// Initialization for this controller
+//
+Method (_INI, 0) {
+ //
+ // If access to OperationRegion is enabled
+ //
+ If (LEqual (OPAC, One)) {
+ Store (1, PMES) // clear PME status
+ Store (0, PMEE) // clear PME enable
+ }
+}
+
+//
+// _OSC for xHCI
+// This method enables XHCI controller if available.
+//
+// Arguments:
+// Arg0 (Integer): Revision ID - should be set to 1
+//
+// Arg1 (Integer): Count of DWords in Arg3
+//
+// Arg2 (Buffer) : Capabilities Buffer
+// DWORD #0 (Status/Error):
+// Bit 0 - Query Support Flag
+// Bit 1 - Always clear(0)
+// Bit 2 - Always clear(0)
+// Bit 3 - Always clear(0)
+//
+// All others - reserved
+//
+// DWORD #1 (Supported):
+// Bit 0 - 1: Switch to xHCI
+//
+// All others - reserved
+//
+// DWORD #2 (Controlled):
+// Bit 0 - 1: Clear Smart Auto state (disable xHCI)
+//
+// All others - reserved
+//
+// Returns:
+// Capabilities Buffer:
+// DWORD #0 (Status):
+// Bit 0 - Reserved (not used)
+//
+// Bit 1 - _OSC failure. Platform Firmware was unable to process the request or query.
+// Capabilities bits may have been masked.
+//
+// Bit 2 - Unrecognized UUID. This bit is set to indicate that the platform firmware
+// does not recognize the UUID passed in _OSC Arg0.
+// Capabilities bits are preserved.
+//
+// Bit 3 - Unrecognized Revision. This bit is set to indicate that the platform firmware
+// does not recognize the Revision ID passed in via Arg1.
+// Capabilities bits beyond those comprehended by the firmware will be masked.
+//
+// Bit 4 - Capabilities Masked. This bit is set to indicate
+// that capabilities bits set by driver software
+// have been cleared by platform firmware.
+//
+// Bit 5 - 0: EHCI controller exposed to OS
+// 1: xHCI controller exposed to OS
+//
+// All others - reserved (return 0)
+//
+// DWORD #1 (Supported):
+// Bit 0 - 0: EHCI supported
+// 1: xHCI supported
+//
+// All others - reserved
+//
+// DWORD #2 (Controlled):
+//
+// All bits - reserved
+//
+
+Method (POSC, 3) {
+
+ Store (0x81, IO80)
+
+ //
+ // Create DWord fields from the Capabilities Buffer
+ //
+ CreateDWordField (Arg2, 0, CDW1) // CDW1 = DWORD that starts at offset 0 of Arg2
+ CreateDWordField (Arg2, 4, CDW2) // CDW2 = DWORD that starts at offset 4 of Arg2
+ CreateDWordField (Arg2, 8, CDW3) // CDW3 = DWORD that starts at offset 8 of Arg2
+
+ //
+ // Are we running a version of Windows that runs the Intel xHCI driver?
+ // i.e. Windows Server 2008 through Windows Server 2008 R2 & Windows 7
+ //
+ If (LAnd (LGreaterEqual (\_SB.OSYS, 9), LLessEqual (\_SB.OSYS, 12))) {
+ //
+ // Running Windows
+ // Check revision is >= 2
+ //
+ If (LLess (Arg0, 2)) {
+ //
+ // Set unknown revision bit
+ //
+ Or (CDW1, 8, CDW1)
+ Store (0x82, IO80)
+ }
+ } Else {
+ //
+ // If the Intel xHCI driver not calling,
+ // then it must be SVOS
+ If (LNotEqual (Arg0, 1)) {
+ //
+ // Set unknown revision bit
+ //
+ Or (CDW1, 8, CDW1)
+ Store (0x82, IO80)
+ }
+ }
+
+ //
+ // Set failure if xHCI is disabled by BIOS
+ //
+ If (LEqual (XHMD, 0)) {
+ Or (CDW1, 2, CDW1)
+ Store (0x83, IO80)
+ }
+
+ //
+ // If no error bits set
+ //
+ If (LEqual (And (CDW1, 0xE), 0)) {
+ //
+ // If not just querying support
+ //
+ If (LNot (And (CDW1, 1))) {
+ //
+ // If uninstaller calling
+ // to switch back to EHCI
+ //
+ If (And (CDW3, 1)) {
+ //
+ // Switch to EHCI
+ //
+ ESEL()
+ Store (0x85, IO80)
+
+ //
+ // And clear ACPINVS variable
+ // that is a copy of USB3.0 setup option
+ // so that we will not re-enable xHCI until
+ // the next reboot
+ //
+ Store (0, XHMD)
+ }
+
+ //
+ // Uninstaller not calling,
+ // OS wants to enable xHCI?
+ //
+ If (And (CDW2, 1)) {
+ //
+ // Switch to xHCI
+ //
+ XSEL(0)
+ Store (0x84, IO80)
+ } Else {
+ //
+ // Switch to EHCI
+ //
+ ESEL()
+ Store (0x85, IO80)
+ }
+ }
+ }
+
+ Return(Arg2)
+}
+
+//
+// Put all ports in XHCI mode
+//
+Method (XSEL, 1, Serialized) {
+ //
+ // If xHCI in auto or smart auto mode
+ // or Arg0 == 1
+ //
+ If ( LOr (LOr (LEqual (XHMD, 2), LEqual (XHMD, 3)), Arg0) ) {
+ //
+ // If xHCI in smart auto mode
+ //
+ If (LEqual (XHMD, 3)) {
+ //
+ // Set B0:D31:F0 ACh[16] to indicate OS has routed ports to xHCI controller
+ //
+ Store (1, \_SB.PC00.LPC0.XSMB)
+ }
+
+ //
+ // Set flags so on Sx resume, we'll know OS has previously
+ // routed ports to xHCI
+ //
+ Store (1, XUSB)
+ Store (1, XRST) // Backup XUSB, cause it might lost in iRST G3 or DeepSx
+
+ //
+ // Enable selected SS ports, route corresponding HS ports to xHCI
+ //
+ Store (0, Local0)
+ And (PR3, 0xFFFFFFC0, Local0)
+ Or (Local0, PR3M, PR3)
+ Store (0, Local0)
+ And (PR2, 0xFFFF8000, Local0)
+ Or (Local0, PR2M, PR2)
+ }
+}
+
+//
+// Put all ports in EHCI mode
+//
+Method (ESEL, 0, Serialized) {
+ //
+ // xHCI in auto or smart auto mode
+ //
+ If (LOr (LEqual (XHMD, 2), LEqual (XHMD, 3))) {
+ //
+ // Disable all SS ports, route all HS ports to EHCI
+ //
+ And (PR3, 0xFFFFFFC0, PR3)
+ And (PR2, 0xFFFF8000, PR2)
+
+ //
+ // Mark as not routed.
+ //
+ Store (0, XUSB)
+ Store (0, XRST)
+ }
+}
+
+Method (XWAK, 0, Serialized) {
+ //
+ // If ports were routed to xHCI before sleep
+ //
+ If (LOr (LEqual (XUSB, 1), LEqual (XRST, 1))) {
+ //
+ // Restore back to xHCI, ignore XHMD
+ //
+ XSEL(1)
+
+ //
+ // And tell OS to re-enumerate xHCI
+ //
+ Notify (\_SB.PC00.XHCI, 0x00)
+ }
+}
+
+//
+// Report what D state the controller is in
+// when the system changes to S3 and S4
+//
+Method(_S3D, 0, NotSerialized) {
+ Return(2)
+}
+
+Method(_S4D, 0, NotSerialized) {
+ Return(2)
+}
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciCrs.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciCrs.asi new file mode 100644 index 0000000000..6b1613b800 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciCrs.asi @@ -0,0 +1,318 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+// Return the proximity domain/node # that this bus is on
+// With this info OSPM will know what memory and I/O resources
+// are under the same IOH
+//
+Name(_PXM, 0)
+
+#define RESOURCE_CHUNK1_OFF 0
+#define RESOURCE_CHUNK2_OFF 16 //(RESOURCE_CHUNK1_OFF + 16)
+#define RESOURCE_CHUNK3_OFF 24 //(RESOURCE_CHUNK2_OFF + 8)
+#define RESOURCE_CHUNK4_OFF 40 //(RESOURCE_CHUNK3_OFF + 16)
+#define RESOURCE_CHUNK5_OFF 56 //(RESOURCE_CHUNK4_OFF + 16)
+#define RESOURCE_CHUNK6_OFF 82 //(RESOURCE_CHUNK5_OFF + 26)
+#define RESOURCE_CHUNK7_OFF 108 //(RESOURCE_CHUNK6_OFF + 26)
+
+#define PciResourceStart Local0
+#define PciResourceLen Local1
+
+Name(PBRS, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity
+ 0x0000, // Min
+ 0x0000, // Max
+ 0x0000, // Translation
+ 0x0000,,, // Range Length = Max-Min+1
+ PB00
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ IO( //Consumed resource (CF8-CFF)
+ Decode16,
+ 0x0cf8,
+ 0xcf8,
+ 1,
+ 8
+ )
+
+ //RESOURCE_CHUNK3_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Min
+ 0x0cf7, // Max
+ 0x0000, // Translation
+ 0x0cf8 // Range Length
+ )
+
+ //RESOURCE_CHUNK4_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x00, // Granularity
+ 0x0000, // Min
+ 0x0000, // Max
+ 0x00, // Translation
+ 0x0000,,, // Range Length
+ PI01
+ )
+
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ 0x000a0000, // Min
+ 0x000bffff, // Max
+ 0x00000000, // Translation
+ 0x00020000 // Range Length
+ )
+
+ //RESOURCE_CHUNK6_OFF
+ DWORDMEMORY( // descriptor for Shadow RAM
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ 0x00000000, // Min (calculated dynamically)
+ 0x00000000, // Max (calculated dynamically)
+ 0x00000000, // Translation
+ 0x00000000,,, // Range Length (calculated dynamically)
+ SDRM
+ )
+
+ //RESOURCE_TPM
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ 0xFED40000, // Min (calculated dynamically)
+ 0xFEDFFFFF, // Max = 4GB - 1MB (fwh + fwh alias...)
+ 0x00000000, // Translation
+ 0x000C0000 // Range Length (calculated dynamically)
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00, // Granularity
+ 0x00000000, // Min (calculated dynamically)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias...)
+ 0x00, // Translation
+ 0x00000000,,, // Range Length (calculated dynamically)
+ PM01
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00, // Granularity
+ 0x00000000000, // Min (calculated dynamically)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias...)
+ 0x00, // Translation
+ 0x00000000000,,, // Range Length (calculated dynamically)
+ PM02
+ )
+}) // end of PBRS Buffer
+
+
+Method(_CRS, 0x0, NotSerialized)
+{
+ //calculate Shadow RAM
+ EROM()
+
+ // Fix up Bus Number Resources
+ CreateWordField(PBRS, ^PB00._MIN, PBMN)
+ Store(BBI0, PBMN)
+ CreateWordField(PBRS, ^PB00._MAX, PBMX) // (MAX bus decoded - 1, assuming Uncore Bus is MAX decoded BUS Number)
+ Store(BBL0, PBMX)
+ CreateWordField(PBRS, ^PB00._LEN, PBLN)
+ Subtract(PBMX, PBMN, PBLN)
+ Add(1, PBLN, PBLN)
+
+ // Fix up 16-bit IO resources
+ CreateWordField(PBRS, ^PI01._MIN, PIMN)
+ Store(IOBA, PIMN)
+ CreateWordField(PBRS, ^PI01._MAX, PIMX)
+ Store(IOLA, PIMX)
+ CreateWordField(PBRS, ^PI01._LEN, PILN)
+ Subtract(PIMX, PIMN, PILN)
+ Add(1, PILN, PILN)
+
+ // Fix up 32-bit Memory resources
+ CreateDWordField(PBRS, ^PM01._MIN, PMMN)
+ Store(MMB0, PMMN)
+ CreateDWordField(PBRS, ^PM01._MAX, PMMX)
+ Store(MML0, PMMX)
+ CreateDWordField(PBRS, ^PM01._LEN, PMLN)
+ Subtract(PMMX, PMMN, PMLN)
+ Add(1, PMLN, PMLN)
+
+ // Fix up 64-bit Memory resources
+// If(LAnd(MMH0, LGreater(OSFL, 8))) {
+ CreateQWordField(PBRS, ^PM02._MIN, P2MN)
+ Store(HMB0, P2MN)
+ CreateQWordField(PBRS, ^PM02._MAX, P2MX)
+ Store(HML0, P2MX)
+ CreateQWordField(PBRS, ^PM02._LEN, P2LN)
+ Subtract(P2MX, P2MN, P2LN)
+ Add(1, P2LN, P2LN)
+// }
+
+ Return(PBRS)
+}
+
+Method(_STA,0) {
+ If (NPB0) {
+ Return(0x0F)
+ }
+ Return(0x00)
+}
+
+OperationRegion(TMEM, PCI_Config, 0x52, 0x3)
+Field(TMEM, ByteAcc, NoLock, Preserve) {
+ DIM0, 4,
+ DIM1, 4,
+ , 8,
+ DIM2, 4
+}
+
+Name(MTBL, Package(0x10) {
+ 0x0,
+ 0x20,
+ 0x20,
+ 0x30,
+ 0x40,
+ 0x40,
+ 0x60,
+ 0x80,
+ 0x80,
+ 0x80,
+ 0x80,
+ 0xc0,
+ 0x100,
+ 0x100,
+ 0x100,
+ 0x200
+})
+
+
+OperationRegion(PAMX, PCI_Config, 0x90, 0x7)
+Field(PAMX, ByteAcc, NoLock, Preserve) {
+ , 4,
+ BSEG, 4,
+ PAMS, 48
+}
+
+Name(ERNG, Package(0xd) {
+ 0xc0000,
+ 0xc4000,
+ 0xc8000,
+ 0xcc000,
+ 0xd0000,
+ 0xd4000,
+ 0xd8000,
+ 0xdc000,
+ 0xe0000,
+ 0xe4000,
+ 0xe8000,
+ 0xec000,
+ 0xf0000
+})
+
+Name(PAMB, Buffer(0x7) {
+})
+
+Method(EROM, 0x0, NotSerialized) {
+ CreateDWordField(PBRS, 0x5c, RMIN)
+ CreateDWordField(PBRS, 0x60, RMAX)
+ CreateDWordField(PBRS, 0x68, RLEN)
+ CreateByteField(PAMB, 0x6, BREG)
+ Store(PAMS, PAMB)
+ Store(BSEG, BREG)
+ Store(0x0, RMIN)
+ Store(0x0, RMAX)
+ Store(0x0, RLEN)
+ Store(0x0, Local0)
+ While(LLess(Local0, 0xd)) {
+ ShiftRight(Local0, 0x1, Local1)
+ Store(DerefOf(Index(PAMB, Local1, )), Local2)
+ If(And(Local0, 0x1, )) {
+ ShiftRight(Local2, 0x4, Local2)
+ }
+ And(Local2, 0x3, Local2)
+ If(RMIN) {
+ If(Local2) {
+ Add(DerefOf(Index(ERNG, Local0, )), 0x3fff, RMAX)
+ If(LEqual(RMAX, 0xf3fff)) {
+ Store(0xfffff, RMAX)
+ }
+ Subtract(RMAX, RMIN, RLEN)
+ Increment(RLEN)
+ } Else {
+ Store(0xc, Local0)
+ }
+ } Else {
+ If(Local2) {
+ Store(DerefOf(Index(ERNG, Local0, )), RMIN)
+ Add(DerefOf(Index(ERNG, Local0, )), 0x3fff, RMAX)
+ If(LEqual(RMAX, 0xf3fff)) {
+ Store(0xfffff, RMAX)
+ }
+ Subtract(RMAX, RMIN, RLEN)
+ Increment(RLEN)
+ } Else {
+ }
+ }
+ Increment(Local0)
+ }
+}
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciIrq.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciIrq.asi new file mode 100644 index 0000000000..b64b70b76a --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciIrq.asi @@ -0,0 +1,461 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+OperationRegion (PRR0, PCI_Config, 0x00, 0x100)
+Field (PRR0, AnyAcc, NoLock, Preserve) {
+ Offset(0x60),
+ PIRA, 8,
+ PIRB, 8,
+ PIRC, 8,
+ PIRD, 8,
+ Offset(0x68),
+ PIRE, 8,
+ PIRF, 8,
+ PIRG, 8,
+ PIRH, 8
+}
+
+Device (LNKA) { // PCI IRQ link A
+ Name (_HID,EISAID("PNP0C0F"))
+ //Name(_UID, 1)
+ Method (_STA,0,NotSerialized) {
+ If(And(PIRA, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xB)
+ } // Don't display
+ }
+
+ Method (_DIS,0,NotSerialized) {
+ Or (PIRA, 0x80, PIRA)
+ }
+
+ Method (_CRS,0,Serialized) {
+ Name (BUF0, ResourceTemplate() {IRQ(Level,ActiveLow,Shared){0}})
+ //
+ // Define references to buffer elements
+ //
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ //
+ // Write current settings into IRQ descriptor
+ //
+ If (And(PIRA, 0x80)) {
+ Store (Zero, Local0)
+ } Else {
+ Store (One,Local0)
+ }
+ //
+ // Shift 1 by value in register 70, Save in buffer
+ //
+ ShiftLeft (Local0,And (PIRA,0x0F),IRQW) // Save in buffer
+ Return (BUF0) // Return Buf0
+ } // End of _CRS method
+
+ Name (_PRS, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
+
+ Method (_SRS,1,NotSerialized) {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+
+ FindSetRightBit(IRQW,Local0) // Set IRQ
+ If (LNotEqual (IRQW,Zero)){
+ And (Local0, 0x7F,Local0)
+ Decrement (Local0)
+ } Else {
+ Or (Local0, 0x80,Local0)
+ }
+ Store (Local0, PIRA)
+ } // End of _SRS Method
+}
+
+Device(LNKB) { // PCI IRQ link B
+ Name (_HID,EISAID("PNP0C0F"))
+ //Name(_UID, 2)
+ Method (_STA,0,NotSerialized) {
+ If (And (PIRB, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xB)
+ } // Don't display
+ }
+
+ Method (_DIS,0,NotSerialized) {
+ Or (PIRB, 0x80,PIRB)
+ }
+
+ Method (_CRS,0,Serialized) {
+ Name(BUF0, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){0}})
+ //
+ // Define references to buffer elements
+ //
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ //
+ // Write current settings into IRQ descriptor
+ //
+ If (And (PIRB, 0x80)) {
+ Store (Zero, Local0)
+ } Else {
+ Store (One,Local0)
+ }
+ //
+ // Shift 1 by value in register 70, Save in buffer
+ //
+ ShiftLeft (Local0,And (PIRB,0x0F),IRQW) // Save in buffer
+ Return (BUF0) // Return Buf0
+ } // End of _CRS method
+
+ Name (_PRS,
+ ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
+
+ Method (_SRS,1,NotSerialized) {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+
+ FindSetRightBit(IRQW,Local0) // Set IRQ
+ If (LNotEqual(IRQW,Zero)) {
+ And (Local0, 0x7F, Local0)
+ Decrement (Local0)
+ } Else {
+ Or (Local0, 0x80, Local0)
+ }
+ Store (Local0, PIRB)
+ } // End of _SRS Method
+}
+
+Device(LNKC) { // PCI IRQ link C
+ Name(_HID, EISAID("PNP0C0F"))
+ //Name(_UID, 3)
+
+ Method (_STA,0,NotSerialized) {
+ If (And (PIRC, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xB)
+ } // Don't display
+ }
+
+ Method (_DIS, 0, NotSerialized) {
+ Or (PIRC, 0x80, PIRC)
+ }
+
+ Method (_CRS, 0, Serialized) {
+ Name (BUF0, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){0}})
+ //
+ // Define references to buffer elements
+ //
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ //
+ // Write current settings into IRQ descriptor
+ //
+ If (And (PIRC, 0x80)) {
+ Store (Zero, Local0)
+ } Else {
+ Store (One,Local0)
+ }
+ //
+ // Shift 1 by value in register 70, Save in buffer
+ //
+ ShiftLeft (Local0,And (PIRC,0x0F),IRQW)
+ Return (BUF0)
+ } // End of _CRS method
+
+ Name (_PRS, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
+
+ Method (_SRS,1,NotSerialized) {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+ FindSetRightBit(IRQW,Local0) // Set IRQ
+ If (LNotEqual (IRQW,Zero)) {
+ And (Local0, 0x7F, Local0)
+ Decrement (Local0)
+ } Else {
+ Or (Local0, 0x80,Local0)
+ }
+ Store (Local0, PIRC)
+ } // End of _SRS Method
+}
+
+Device (LNKD) { // PCI IRQ link D
+ Name (_HID,EISAID ("PNP0C0F"))
+
+ //Name(_UID, 4)
+
+ Method (_STA, 0, NotSerialized) {
+ If (And (PIRD, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xB)
+ } // Don't display
+ }
+
+ Method (_DIS, 0, NotSerialized) {
+ Or(PIRD, 0x80,PIRD)
+ }
+
+ Method (_CRS,0,Serialized) {
+ Name (BUF0, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){0}})
+ //
+ // Define references to buffer elements
+ //
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ //
+ // Write current settings into IRQ descriptor
+ //
+ If (And (PIRD, 0x80)) {
+ Store (Zero, Local0)
+ } Else {
+ Store (One,Local0)
+ }
+ //
+ // Shift 1 by value in register 70, Save in buffer
+ //
+ ShiftLeft (Local0, And (PIRD,0x0F), IRQW)
+ Return (BUF0) // Return Buf0
+ } // End of _CRS method
+
+ Name (_PRS, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
+
+ Method (_SRS,1,NotSerialized) {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+ FindSetRightBit (IRQW, Local0)// Set IRQ
+ If (LNotEqual (IRQW, Zero)) {
+ And (Local0, 0x7F, Local0)
+ Decrement (Local0)
+ } Else {
+ Or (Local0, 0x80, Local0)
+ }
+ Store(Local0, PIRD)
+ } // End of _SRS Method
+}
+
+Device(LNKE) { // PCI IRQ link E
+ Name(_HID,EISAID("PNP0C0F"))
+
+ //Name(_UID, 5)
+
+ Method (_STA,0,NotSerialized) {
+ If (And (PIRE, 0x80)) {
+ Return(0x9)
+ } Else {
+ Return(0xB)
+ } // Don't display
+ }
+
+ Method (_DIS,0,NotSerialized) {
+ Or (PIRE, 0x80, PIRE)
+ }
+
+ Method (_CRS, 0, Serialized) {
+ Name (BUF0, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){0}})
+ //
+ // Define references to buffer elements
+ //
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ //
+ // Write current settings into IRQ descriptor
+ //
+ If (And (PIRE, 0x80)) {
+ Store (Zero, Local0)
+ } Else {
+ Store (One, Local0)
+ }
+ //
+ // Shift 1 by value in register 70, Save in buffer
+ //
+ ShiftLeft (Local0, And (PIRE,0x0F), IRQW)
+ Return (BUF0) // Return Buf0
+ } // End of _CRS method
+
+ Name(_PRS, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
+
+ Method (_SRS,1,NotSerialized) {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+ FindSetRightBit (IRQW, Local0) // Set IRQ
+ If (LNotEqual (IRQW, Zero)) {
+ And (Local0, 0x7F, Local0)
+ Decrement (Local0)
+ } Else {
+ Or (Local0, 0x80, Local0)
+ }
+ Store (Local0, PIRE)
+ } // End of _SRS Method
+}
+
+Device(LNKF) { // PCI IRQ link F
+ Name (_HID,EISAID("PNP0C0F"))
+
+ //Name(_UID, 6)
+
+ Method (_STA,0,Serialized) {
+ If (And (PIRF, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xB)
+ } // Don't display
+ }
+
+ Method (_DIS,0,NotSerialized) {
+ Or (PIRB, 0x80, PIRF)
+ }
+
+ Method (_CRS,0,Serialized) {
+ Name(BUF0, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){0}})
+ //
+ // Define references to buffer elements
+ //
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ //
+ // Write current settings into IRQ descriptor
+ //
+ If (And (PIRF, 0x80)) {
+ Store (Zero, Local0)
+ } Else {
+ Store (One, Local0)
+ }
+ //
+ // Shift 1 by value in register 70, Save in buffer
+ //
+ ShiftLeft (Local0, And (PIRF, 0x0F),IRQW)
+ Return (BUF0)
+ } // End of _CRS method
+
+ Name(_PRS, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
+
+ Method (_SRS,1,NotSerialized) {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+ FindSetRightBit (IRQW,Local0) // Set IRQ
+ If (LNotEqual (IRQW,Zero)) {
+ And (Local0, 0x7F,Local0)
+ Decrement (Local0)
+ } Else {
+ Or (Local0, 0x80, Local0)
+ }
+ Store (Local0, PIRF)
+ } // End of _SRS Method
+}
+
+Device(LNKG) { // PCI IRQ link G
+ Name(_HID,EISAID("PNP0C0F"))
+ //Name(_UID, 7)
+ Method(_STA,0,NotSerialized) {
+ If (And (PIRG, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xB)
+ } // Don't display
+ }
+
+ Method (_DIS, 0, NotSerialized) {
+ Or(PIRG, 0x80,PIRG)
+ }
+
+ Method (_CRS,0,Serialized){
+ Name(BUF0,ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){0}})
+ //
+ // Define references to buffer elements
+ //
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ //
+ // Write current settings into IRQ descriptor
+ //
+ If (And(PIRG, 0x80)) {
+ Store(Zero, Local0)
+ } Else {
+ Store(One,Local0)
+ }
+ //
+ // Shift 1 by value in register 70, Save in buffer
+ //
+ ShiftLeft (Local0,And(PIRG,0x0F),IRQW)
+ Return (BUF0)
+ } // End of _CRS method
+
+ Name (_PRS, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
+
+ Method (_SRS,1,NotSerialized) {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+ FindSetRightBit(IRQW,Local0) // Set IRQ
+ If (LNotEqual (IRQW,Zero)) {
+ And (Local0, 0x7F,Local0)
+ Decrement (Local0)
+ } Else {
+ Or (Local0, 0x80,Local0)
+ }
+ Store (Local0, PIRG)
+ } // End of _SRS Method
+}
+
+Device(LNKH) { // PCI IRQ link H
+ Name (_HID,EISAID("PNP0C0F"))
+
+ //Name(_UID, 8)
+
+ Method (_STA,0,Serialized) {
+ If (And(PIRH, 0x80)) {
+ Return(0x9)
+ } Else {
+ Return(0xB)
+ } // Don't display
+ }
+
+ Method (_DIS,0,NotSerialized) {
+ Or(PIRH, 0x80,PIRH)
+ }
+
+ Method (_CRS,0,Serialized) {
+ Name(BUF0, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){0}})
+ //
+ // Define references to buffer elements
+ //
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ //
+ // Write current settings into IRQ descriptor
+ //
+ If (And (PIRH, 0x80)) {
+ Store (Zero, Local0)
+ } Else {
+ Store (One,Local0)
+ }
+ //
+ // Shift 1 by value in register 70, Save in buffer
+ //
+ ShiftLeft (Local0,And(PIRH,0x0F),IRQW)
+ Return (BUF0)
+ } // End of _CRS method
+
+ Name(_PRS, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
+
+ Method (_SRS,1,NotSerialized) {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+ FindSetRightBit (IRQW,Local0)// Set IRQ
+ If (LNotEqual (IRQW,Zero)) {
+ And (Local0, 0x7F,Local0)
+ Decrement (Local0)
+ } Else {
+ Or (Local0, 0x80,Local0)
+ }
+ Store (Local0, PIRH)
+ }
+}
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHp.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHp.asi new file mode 100644 index 0000000000..3f23c5bd82 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHp.asi @@ -0,0 +1,650 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ //
+ // BIOS parameter
+ // The address will be fixed dynamically during boot.
+ // Will be updated by ACPI platform driver as "FIX8"
+ //
+ OperationRegion (MCTL, SystemMemory, 0x38584946, 0x04)
+ Field (MCTL, ByteAcc, NoLock, Preserve) {
+ , 3,
+ HGPE, 1,
+ , 7,
+ , 8,
+ , 8
+ }
+
+//
+// No longer needed, See PPA4
+//
+// OperationRegion (PSTS, PCI_Config, 0xB0, 0x04)
+// Field (PSTS, ByteAcc, NoLock, Preserve) {
+// , 16,
+// PMES, 1, // PME Status bit 16
+// PMEP, 1, //PME Pending bit 17
+// , 14
+// }
+
+
+ Method (_INI, 0, NotSerialized) {
+ Store (0x01, HGPE) //enable GPE message generation for ACPI hotplug support
+ }
+
+ Name(_HPP, Package(){0x08, 0x40, 1, 0})
+
+ //
+ // begin hotplug code
+ //
+ Name(SHPC, 0x40) // Slot Hot-plug Capable
+
+ Name(SPDS, 0x040) // Slot Presence Detect State
+
+ Name(MRLS, 0x0) // MRL Closed, Standby Power to slot is on
+ Name(CCOM, 0x010) // Command Complete
+ Name(SPDC, 0x08) // Slot Presence Detect Changes
+ Name(MRLC, 0x04) // Slot MRL Changed
+ Name(SPFD, 0x02) // Slot Power Fault Detected
+ Name(SABP, 0x01) // Slot Attention Button Pressed
+
+ Name(SPOF, 0x10) // Slot Power Off
+ Name(SPON, 0x0F) // Slot Power On Mask
+
+ Name(ALMK, 0x1C) // Slot Atten. LED Mask
+ Name(ALON, 0x01) // Slot Atten. LED On
+ Name(ALBL, 0x02) // Slot Atten LED Blink
+ Name(ALOF, 0x03) // Slot Atten LED Off
+
+ Name(PLMK, 0x13) // Slot Pwr. LED Mask
+ Name(PLON, 0x04) // Slot Pwr. LED On
+ Name(PLBL, 0x08) // Slot Pwr. LED Blink
+ Name(PLOF, 0x0C) // Slot Pwr. LED Off
+
+ //;*************************************
+ //; Bit 3 = Presence Detect Event
+ //; Bit 2 = MRL Sensor Event
+ //; Bit 1 = PWR Fault Event
+ //; Bit 0 = Attention Button Event
+ //;*************************************
+ Name(HPEV, 0xF) // Possible interrupt events (all)
+
+ //;************************************************************************;
+ //;
+ //; PCIe Link Control Register A0-A1h
+ //;
+ //; Bit - 4 - Link disable.
+ //;
+ //;************************************************************************;
+//
+// No longer needed, see PPA4
+//
+// OperationRegion(PPA0, PCI_Config, 0xA0, 0x02)
+// Field(PPA0,ByteAcc,NoLock,Preserve) {
+// ,4,
+// LDIS,1, // Link Disable bit4.
+// ,11,
+// }
+
+ //;************************************************************************;
+ //;
+ //; PCIe Slot Capabilities Register A4-A7h
+ //; Bit - 31-5 - Not used
+ //; Bit - 4 - Power Indicator Present.
+ //; Bit - 3 - Attention Indicator Present.
+ //; Bit - 2 - MRL Sensor Present.
+ //; Bit - 1 - Power Controller Present.
+ //; Bit - 0 - Attention Button Present.
+ //;
+ //; PCIe Slot control Register A8-A9h
+ //;
+ //; Bit - 10 - PWR Control Disable
+ //; Bit - 9:8 - Attn Indicator
+ //; Bit - 7:6 - PWR Indicator
+ //; Bit - 5 - Hot-Plug Interrupt Event Enable
+ //; Bit - 4 - Command Complete Interrupt enable
+ //; Bit - 3 - Presence Detect Changed Interrupt enable
+ //; Bit - 2 - MRL Sensor Changed Interrupt enable
+ //; Bit - 1 - PwrFault Detect Interrupt enable
+ //; Bit - 0 - Attention Button Pressed Interrupt Enable
+ //;
+ //; PCIe Slot Status Registers AA-ADh
+ //;
+ //; Bit - 6 - Presence Detect State.
+ //; Bit - 5 - MRL Sensor State.
+ //; Bit - 4 - Command Completed.
+ //;
+ //; RWC Status Bits
+ //;
+ //; Bit - 3 - Presence Detect Changed.
+ //; Bit - 2 - MRL Sensor Changed.
+ //; Bit - 1 - Power Fault Detected.
+ //; Bit - 0 - Attention Button Pressed.
+ //;************************************************************************;
+ OperationRegion(PPA4, PCI_Config, 0x00, 0x100)
+ Field(PPA4,ByteAcc,NoLock,Preserve) {
+ Offset (0xA0), // from PPA0 OpRegion
+ ,4,
+ LDIS,1, // Link Disable bit4.
+ ,11,
+ Offset(0xA4), // A4-A7h PCI Slot Capabilities Register
+ ATBP,1, // Attention Button Present
+ ,1, // Skip Power Controller Present
+ MRSP,1, // MRL Sensor Present
+ ATIP,1, // Attention Indicator Present
+ PWIP,1, // Power Indicator Present
+ ,14,
+ PSNM,13, // Physical Slot Number
+ Offset(0xA8), // PCIE Slot Control Register
+ ABIE,1, // Attention Button Pressed Interrupt Enable
+ PFIE,1, // Power Fault Detected Interrupt Enable
+ MSIE,1, // MRL Sensor Changed Interrupt Enable
+ PDIE,1, // Presence Detect Changed Interrupt Enable.
+ CCIE,1, // Command Complete Interrupt Enable.
+ HPIE,1, // Hot-plug Interrupt Enable.
+ SCTL,5, // Attn/Power indicator and Power controller.
+ ,5, // reserved
+ Offset(0xAA), // PCIE Slot Status Register
+ SSTS,7, // The status bits in Slot Status Reg
+ ,1,
+ Offset (0xB0), // from PSTS OpRegion
+ , 16,
+ PMES, 1, // PME Status bit 16
+ PMEP, 1, // PME Pending bit 17
+ , 14
+ }
+
+ //
+ // These Methods replace the bit field definitions in PPA8
+ // that were bit fields within SCTL
+ //
+ Method (ATID, 0) {
+ Return (And (SCTL, 0x03))
+ }
+
+ Method (PWID, 0) {
+ Return (ShiftRight (And (SCTL, 0x0C), 2))
+ }
+
+ Method (PWCC, 0) {
+ Return (ShiftRight (And (SCTL, 0x10), 4))
+ }
+
+ //
+ // These methods replace the bit fields definitions in PPA8
+ // that were bit fields within SSTS
+ //
+ Method (ABPS, 1) {
+ If (LEqual (Arg0, 1)) {
+ Or (SSTS, 0x01, SSTS)
+ }
+ Return (And (SSTS, 0x01))
+ }
+
+ Method (PFDS, 1) {
+ If (LEqual (Arg0, 1)) {
+ Or (SSTS, 0x02, SSTS)
+ }
+ Return (ShiftRight (And (SSTS, 0x02), 1))
+ }
+
+ Method (MSCS, 1) {
+ If (LEqual (Arg0, 1)) {
+ Or (SSTS, 0x04, SSTS)
+ }
+ Return (ShiftRight (And (SSTS, 0x04), 2))
+ }
+
+ Method (PDCS, 1) {
+ If (LEqual (Arg0, 1)) {
+ Or (SSTS, 0x08, SSTS)
+ }
+ Return (ShiftRight (And (SSTS, 0x08), 3))
+ }
+
+ Method (CMCS, 1) {
+ If (LEqual (Arg0, 1)) {
+ Or (SSTS, 0x10, SSTS)
+ }
+ Return (ShiftRight (And (SSTS, 0x10), 4))
+ }
+
+ Method (MSSC, 1) {
+ If (LEqual (Arg0, 1)) {
+ Or (SSTS, 0x20, SSTS)
+ }
+ Return (ShiftRight (And (SSTS, 0x20), 5))
+ }
+
+ Method (PRDS, 1) {
+ If (LEqual (Arg0, 1)) {
+ Or (SSTS, 0x40, SSTS)
+ }
+ Return (ShiftRight (And (SSTS, 0x40), 6))
+ }
+
+
+// OperationRegion(PPA8, PCI_Config, 0x00, 0x0ff)
+// Field(PPA8,ByteAcc,NoLock,Preserve) {
+// Offset(0xA8), // PCIE Slot Control Register
+// ,6,
+// ATID,2, // Attention Indicator Control.
+// PWID,2, // Power Indicator Control.
+// PWCC,1, // Power Controller Control.
+// ,5,
+// Offset(0xAA), // RWC status
+// ABPS,1, // Attention Button Pressed Status (RWC)
+// PFDS,1, // Power Fault Detect Status (RWC)
+// MSCS,1, // MRL Sensor Changed Status
+// PDCS,1, // Presence Detect Changed Status
+// CMCS,1, // Command Complete Status
+// MSSC,1, // MRL Sensor State
+// PRDS,1, // Presence Detect State
+// ,1,
+// }
+
+ //;************************************************************************;
+ //; This OSHP (Operating System Hot Plug) method is provided for each HPC
+ //; which is controlled by ACPI. This method disables ACPI access to the
+ //; HPC and restores the normal System Interrupt and Wakeup Signal
+ //; connection.
+ //;************************************************************************;
+ Method(OSHP) { // OS call to unhook Legacy ASL PCI-Express HP code.
+ Store(SSTS, SSTS) // Clear any status
+ Store(0x0, HGPE) // Disable GPE generation
+ }
+
+ //;************************************************************************;
+ //; Hot Plug Controller Command Method
+ //;
+ //; Input: Arg0 - Command to issue
+ //;
+ //;************************************************************************;
+ Method(HPCC,1) {
+ Store(SCTL, Local0) // get current command state
+ Store(0, Local1) // reset the timeout value
+ If(LNotEqual(Arg0, Local0)) { // see if state is different
+ Store(Arg0, SCTL) // Update the Slot Control
+ While(LAnd (LNot(CMCS(0)), LNotEqual(100, Local1))) { // spin while CMD complete bit is not set,
+ // check for timeout to avoid dead loop
+ Store(0xFB, IO80)
+ Sleep(2) // allow processor time slice
+ Add(Local1, 2, Local1)
+ }
+ CMCS(1) // Clear the command complete status
+ }
+ }
+
+ //;************************************************************************;
+ //; Attention Indicator Command
+ //;
+ //; Input: Arg0 - Command to issue
+ //; 1 = ON
+ //; 2 = Blink
+ //; 3 = OFF
+ //;************************************************************************;
+ Method(ATCM,1) {
+ Store(SCTL, Local0) // Get Slot Control
+ And(Local0, ALMK, Local0) // Mask the Attention Indicator Bits
+ If(LEqual(Arg0, 0x1)){ // Attenion indicator "ON?"
+ Or(Local0, ALON, Local0) // Set the Attention Indicator to "ON"
+ }
+ If(LEqual(Arg0, 0x2)){ // Attenion indicator "BLINK?"
+ Or(Local0, ALBL, Local0) // Set the Attention Indicator to "BLINK"
+ }
+ If(LEqual(Arg0, 0x3)){ // Attenion indicator "OFF?"
+ Or(Local0, ALOF, Local0) // Set the Attention Indicator to "OFF"
+ }
+ HPCC(Local0)
+ }
+
+ //;************************************************************************;
+ //; Power Indicator Command
+ //;
+ //; Input: Arg0 - Command to issue
+ //; 1 = ON
+ //; 2 = Blink
+ //; 3 = OFF
+ //;************************************************************************;
+ Method(PWCM,1){
+ Store(SCTL, Local0) // Get Slot Control
+ And(Local0, PLMK, Local0) // Mask the Power Indicator Bits
+ If(LEqual(Arg0, 0x1)){ // Power indicator "ON?"
+ Or(Local0, PLON, Local0) // Set the Power Indicator to "ON"
+ }
+ If(LEqual(Arg0, 0x2)){ // Power indicator "BLINK?"
+ Or(Local0, PLBL, Local0) // Set the Power Indicator to "BLINK"
+ }
+ If(LEqual(Arg0, 0x3)){ // Power indicator "OFF?"
+ Or(Local0, PLOF, Local0) // Set the Power Indicator to "OFF"
+ }
+ HPCC(Local0)
+ }
+
+ //;************************************************************************;
+ //; Power Slot Command
+ //;
+ //; Input: Arg0 - Command to issue
+ //; 1 = Slot Power ON
+ //; 2 = Slot Power Off
+ //;************************************************************************;
+ Method(PWSL,1){
+ Store(SCTL, Local0) // Get Slot Control
+ If(Arg0){ // Power Slot "ON" Arg0 = 1
+ And(Local0, SPON, Local0) // Turns the Power "ON"
+ } Else { // Power Slot "OFF"
+ Or(Local0, SPOF, Local0) // Turns the Power "OFF"
+ }
+ HPCC(Local0)
+ }
+
+ //;************************************************************************;
+ //; _OST Methods to indicate that the device Eject/insert request is
+ //; pending, OS could not complete it
+ //;
+ //; Input: Arg0 - Value used in Notify to OS
+ //; 0x00 - card insert
+ //; 0x03 - card eject
+ //; Arg1 - status of Notify
+ //; 0 - success
+ //; 0x80 - Ejection not supported by OSPM
+ //; 0x81 - Device in use
+ //; 0x82 - Device Busy
+ //; 0x84 - Ejection in progress-pending
+ //;************************************************************************;
+ Method(_OST,3,Serialized) {
+ Switch(And(Arg0,0xFF)) { // Mask to retain low byte
+ Case(0x03) { // Ejection Request
+ Switch(ToInteger(Arg1)) {
+ Case(Package() {0x80, 0x81, 0x82, 0x83}) {
+ //
+ // Ejection Failure for some reason
+ //
+ If (Lnot(PWCC())) { // if slot is powered
+ PWCM(0x1) // Set PowerIndicator to ON
+ Store(0x1,ABIE) // Set AttnBtn Interrupt ON
+ }
+ }
+ }
+ }
+ }
+ } // End _OST
+
+ //;************************************************************************;
+ //; Eject Control Methods to indicate that the device is hot-ejectable and
+ //; should "eject" the device.
+ //;
+ //;
+ //;************************************************************************;
+ Method(EJ0L){
+ Store(0xFF, IO80)
+ Store(SCTL, Local0) // Get IIO Port Control state
+ if( LNot( LEqual( ATID(), 1))) { // Check if Attention LED is not solid "ON"
+ And(Local0, ALMK, Local0) // Mask the Attention Indicator Bits
+ Or(Local0, ALBL, Local0) // Set the Attention Indicator to blink
+ }
+ HPCC(Local0) // issue command
+
+ Store(SCTL, Local0) // Get IIO Port Control state
+ Or(Local0, SPOF, Local0) // Set the Power Controller Control to Power Off
+ HPCC(Local0)
+
+ Store(SCTL, Local0) // Get IIO Port Control state
+ Or(Local0, PLOF, Local0) // Set the Power Indicator to Off.
+ HPCC(Local0)
+
+ Store(SCTL, Local0) // Get IIO Port Control state
+ Or(Local0, ALOF, Local0) // Set the Attntion LED to Off.
+ HPCC(Local0)
+
+ } // End of EJ0L
+
+ //;************************************************************************;
+ //; PM_PME Wake Handler for All Slots
+ //;
+ //; Input: Arg0 - Slot Numnber
+ //;
+ //;************************************************************************;
+ Method(PMEH,1){ // Handler for PCI-E PM_PME Wake Event/Interupt (GPI xxh)
+ If(And(HPEV, SSTS)){ // Check for Hot-Plug Events
+ If(ABPS(0)) {
+ Store (Arg0, IO80) // Send slot number to Port 80
+ ABPS(1) // Clear the interrupt status
+ Sleep(200) // delay 200ms
+ }
+ }
+ Return (0xff) // Indicate that this controller did not interrupt
+ } // End of Method PMEH
+
+ //;************************************************************************;
+ //; Hot-Plug Handler for All Slots.
+ //;
+ //; Input: Arg0 - Slot Number
+ //;
+ //;************************************************************************;
+ Method(HPEH,1){ // Handler for PCI-E Hot-Plug Event/Interupt (GPI xxh)
+ Store(0xFE, IO80)
+ Sleep(100)
+ Store(0,CCIE) // Disable command interrupt
+ If(And(HPEV, SSTS)){ // Check for Hot-Plug Events
+ Store(0xFD, IO80)
+ Sleep(10)
+ Store (Arg0, IO80) // Send slot number to Port 80
+ Sleep(10)
+ Store(PPXH(), Local0) // Call Hot plug Interrupt Handler
+ Return(Local0) // Return PPXH information
+ }
+ Else{
+ Return (0xff) // Indicate that this controller did not interrupt
+ }
+ Store(0xFC, IO80)
+ Sleep(10)
+ } // End of Method HPEH
+
+ //;************************************************************************;
+ //; Interrut Event Handler
+ //;
+ //;
+ //;************************************************************************;
+ Method(PPXH){ // Hot plug Interrupt Handler
+ //
+ // Check for the Atention Button Press, Slot Empty/Presence, Power Controller Control.
+ //
+ Sleep(200) // HW Workaround for AttentionButton Status to stabilise
+ If(ABPS(0)) { // Check if Attention Button Pressed
+ If(LNot(PRDS(0))) { // See if nothing installed (no card in slot)
+ Store(0x1, LDIS) // Disable the Link associated with PCI-E port
+ PWSL(0x0) // make sure Power is Off
+ PWCM(0x3) // Set Power Indicator to "OFF"
+ //
+ // Check for MRL here and set attn indicator accordingly
+ //
+ If(LEqual(MSSC(0),MRLS)) { // Standby power is on - MRL closed
+ ATCM(0x2) // Set Attention Indicator to "BLINK"
+ } else { // Standby power is off - MRL open
+ ATCM(0x3) // set attention indicator "OFF"
+ }
+ Store(0x0, ABIE) // set Attention Button Interrupt to disable
+ ABPS(1) // Clear the interrupt status
+ Sleep(200) // delay 200ms
+ Return(0xff) // Attn Button pressed without card in slot. Do nothing
+ }
+ //
+ // Card is present in slot so....
+ //
+ Store(0x0, ABIE) // set Attention Button Interrupt to disable
+ // Attn Btn Interrupt has to be enabled only after an insert oprn
+ ABPS(1) // Clear the interrupt status
+ Sleep(200) // delay 200ms
+ //
+ // Check for MRL here - only if SPWR is OFF blink AttnInd and retun 0xff
+ //
+ //If(LNot(LEqual(MSSC()),MRLS))) { // Standby power is off
+ // PWSL(0x0) // make sure Power is Off
+ // PWCM(0x3) // Set Power Indicator to "OFF"
+ // ATCM(0x2) // Set Attention Indicator to "BLINK"
+ // Return(0xff) // Attn Button pressed with card in slot, but MRL open. Do nothing
+ //}
+ //Card Present, if StandbyPwr is ON proceed as below with Eject Sequence
+ If(PWCC()) { // Slot not Powered
+ PWCM(0x3) // Set Power Indicator to "OFF"
+ ATCM(0x2) // Set Attention Indicator to "BLINK"
+ Return(0xff) // Attn Button pressed with card in slot, MRL closed, Slot not powered. Do nothing
+ } Else { // See if Slot is already Powered
+ PWCM(0x2) // Set power Indicator to BLINK
+ Sleep(600) // Wait 100ms
+ Store(600, Local0) // set 5 second accumulator to 0
+ ABPS(1) // Clear the interrupt status
+ Sleep(200) // delay 200ms
+ While(LNot(ABPS(0))) { // check for someone pressing Attention
+ Sleep(200) // Wait 200ms
+ Add(Local0, 200, Local0)
+ If(LEqual(5000, Local0)) { // heck if 5sec has passed without pressing attnetion btn
+ ABPS(1) // Clear the interrupt status
+ Sleep(200) // delay 200ms
+ Return (0x3) // continue with Eject request
+ }
+ }
+ PWCM(0x1) // Set power Indicator baCK "ON"
+ ABPS(1) // Clear the Attention status
+ Sleep(200) // delay 200ms
+ Store(0x1, ABIE) // set Attention Button Interrupt to enable
+ Return (0xff) // do nothing and abort
+ }
+ } // End if for the Attention Button Hot Plug Interrupt.
+
+ If(PFDS(0)) { // Check if Power Fault Detected
+ PFDS(1) // Clear the Power Fault Status
+ PWSL(0x0) // set Power Off
+ PWCM(0x3) // set power indicator to OFF
+ ATCM(0x1) // set attention indicator "ON"
+ Store(0x1, LDIS) // Disable the Link associated with PCI-E port
+ Return(0x03) // Eject request.
+ } // End if for the Power Fault Interrupt.
+
+ If(MSCS(0)) { // Check interrupt caused by the MRL Sensor
+ MSCS(1) // Clear the MRL Status
+ If(LEqual(MSSC(0),MRLS)) { // Standby power is on - MRL closed
+ If(PRDS(0)) { // Card is Present
+
+ ATCM(0x3) // Set Attention Indicator to off
+ PWCM(0x2) // Set Power Indicator to Blink
+ Sleep(600) // Wait 100ms
+ Store(600, Local0) // set 5 second accumulator to 0
+ ABPS(1) // Clear the interrupt status
+ While(LNot(ABPS(0))) { // check for someone pressing Attention
+ Sleep(200) // Wait 200ms
+ Add(Local0, 200, Local0)
+ If(LEqual(5000, Local0)) { // Check if 5 sec elapsed
+ Store(0x1, ABIE) // Enable Attention button interrupt
+ ATCM(0x3) // set attention indicator "OFF"
+ Store(0x0, LDIS) // Enable the Link associated with PCI-E port
+ PWSL(0x1) // Power the Slot
+ Sleep(500) // Wait for .5 Sec for the Power to Stabilize.
+ // Check for the Power Fault Detection
+ If(LNot(PFDS(0))) { // No Power Fault
+ PWCM(0x1) // Set Power Indicator to "ON"
+ // Or(LVLS, 0x000010000, LVLS) // Enable the Device 4 Slot Clock (GPIO16)
+ // Notify the OS to load the Driver for the card
+ Store(0x00, Local1)
+ Store(0x1, ABIE) // Enable Attention button interrupt
+ } Else { // Power Fault present
+ PWSL(0x0) // set Slot Power Off
+ PWCM(0x3) // set power indicator to OFF
+ ATCM(0x1) // set attention indicator "ON"
+ Store(0x1, LDIS) // Disable the Link associated with PCI-E port
+ // And (LVLS, 0x0FFFEFFFF, LVLS) // Disable the Device 4 Slot Clock (GPIO16)
+ Store(0x03, Local1) // Eject request.
+ } // End if for the Slot Power Fault
+ ABPS(1) // Clear the Attention status
+ Sleep(200) // delay 200ms
+ Return(Local1)
+ }
+ }
+ //
+ // someone pressed Attention Button
+ //
+ ABPS(1) // Clear the Attention status
+ Sleep(200) // delay 200ms
+ PWSL(0x0) // Set Slot Power off
+ PWCM(0x3) // Set Power Indicator back to "OFF"
+ ATCM(02) // Set Attention Indicator to "BLINK"
+ Store(0x1, LDIS) // Disable the Link associated with PCI-E port
+ Return(0xff) // leave it off
+ // End of Insert sequence
+ }
+ //MRL is closed, Card is not present
+ PWSL(0x0) // Set Slot Power off
+ PWCM(0x3) // Set Power Indicator back to "OFF"
+ ATCM(02) // Set Attention Indicator to "BLINK"
+ Store(0x1, LDIS) // Disable the Link associated with PCI-E port
+ Return(0xff) // leave it off
+ } Else { // MRL is open i.e Stdby power is turned off
+ If(PRDS(0)) { //card present MRL switched off
+ ATCM(0x2) // Set Attention Indicator to "BLINK"
+ If(Lnot(PWCC())) { // If slot is powered
+ // This event is not supported and someone has opened the MRL and dumped the power
+ // on the slot with possible pending transactions. This could hose the OS.
+ // Try to Notify the OS to unload the drivers.
+ PWSL(0x0) // Set Slot Power off
+ PWCM(0x3) // Set Power Indicator back to "OFF"
+ Store(0x1, LDIS) // Disable the Link associated with PCI-E port
+ Return(0x03) // Eject request.
+ } Else { // Slot not powered, MRL is opened, card still in slot - Eject not fully complete
+ Return(0xFF)
+ }
+ }
+ //no card present and Stdby power switched off, turn AI off
+ ATCM(0x3) // Set Attention Indicator to "OFF"
+ Return(0xff) // leave it off
+ } // End of MRL switch open/close state
+ } // End of MRL Sensor State Change
+
+ If(PDCS(0)) { // Check if Presence Detect Changed Status
+ PDCS(1) // Clear the Presence Detect Changed Status
+ If(LNot(PRDS(0))) { // Slot is Empty
+ PWSL(0x0) // Set Slot Power "OFF"
+ PWCM(0x3) // set power indicator to "OFF"
+ If(LEqual(MSSC(0),MRLS)) { // If Standby power is on
+ ATCM(0x2) // Set Attention Indicator to "Blink"
+ } else {
+ ATCM(0x3) // Set Attention Indicator to "OFF"
+ }
+ Store(0x1, LDIS) // Disable the Link associated with PCI-E port
+ Return(0xFF) // Do nothing
+ } Else { // Slot Card is inserted
+ // Irrespective of MRL state, do the following
+ Store(0x0, LDIS) // Enable the Link associated with PCI-E port
+ PWSL(0x1) // Set Slot Power ON
+ Sleep(500) // Wait for .5 Sec for the Power to Stabilize.
+ If(LNot(PFDS(0))) { // No Power Fault
+ PWCM(0x1) // Set Power Indicator to "ON"
+ Store(0x00, Local1)
+ Store(0x1, ABIE) // Enable Attention button interrupt
+ ATCM(0x3) // Set Attention Indicator to "OFF"
+ } Else { // Power Fault present
+ PWSL(0x0) // set Slot Power Off
+ PWCM(0x3) // set power indicator to OFF
+ ATCM(0x1) // set attention indicator "ON"
+ Store(0x1, LDIS) // Disable the Link associated with PCI-E port
+ Store(0x03, Local1) // Eject request.
+ } // End if for the Slot Power Fault
+ ABPS(1) // Clear the Attention status
+ Sleep(200) // delay 200ms
+ Return(Local1)
+ }
+ } // End if for the Presence Detect Changed Hot Plug Interrupt.
+ Return(0xff) // should not get here, but do device check if it does.
+ } // End of method PP5H
+ //
+ // End of hotplug code
+ //
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHpDev.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHpDev.asi new file mode 100644 index 0000000000..d9a4565519 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHpDev.asi @@ -0,0 +1,20 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Method(SNUM, 0, Serialized) {
+ Store(PSNM, Local0)
+ Return(Local0)
+ }
+
+ Method(_SUN, 0) { Return(SNUM) } // Slot User Number
+ Method(_EJ0, 1) { EJ0L() } // Remove all power from the slot
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieNonHpDev.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieNonHpDev.asi new file mode 100644 index 0000000000..4f90be3373 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieNonHpDev.asi @@ -0,0 +1,22 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Method(SNUM, 0, Serialized) {
+ Store(PSNM, Local0)
+ Return(Local0)
+ }
+
+ Method(_SUN, 0) {
+ Return(SNUM)
+ } // Slot User Number
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieSeg.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieSeg.asi new file mode 100644 index 0000000000..781d764bb8 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieSeg.asi @@ -0,0 +1,361 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "MaxSocket.h"
+
+ Scope(\) {
+
+ //
+ // \SG00, SG01,... SG07 are defined to contain Segment # for Segment/socket 0, 1, ....
+ //
+ // Create _SEG for each segment/socket
+ //
+
+ //
+ // Debug method for use under BITS
+ // Example: Set SG01 to 5 SSEG(1,5)
+ //
+ Method(SSEG, 2) {
+ If (LEqual(Arg0, 0) ) { Store (Arg1, SG00) }
+ If (LEqual(Arg0, 1) ) { Store (Arg1, SG01) }
+ If (LEqual(Arg0, 2) ) { Store (Arg1, SG02) }
+ If (LEqual(Arg0, 3) ) { Store (Arg1, SG03) }
+ }
+
+
+// ------------------------------------------------------
+// Socket 0 PC00 - PC05 share the same segment number SG00
+// ------------------------------------------------------
+
+ Scope(\_SB.PC00) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG00)
+ }
+ }
+
+ Scope(\_SB.PC01) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG00)
+ }
+ }
+
+ Scope(\_SB.PC02) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG00)
+ }
+ }
+
+ Scope(\_SB.PC03) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG00)
+ }
+ }
+
+ Scope(\_SB.PC04) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG00)
+ }
+ }
+
+ Scope(\_SB.PC05) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG00)
+ }
+ }
+
+// ------------------------------------------------------
+// Socket 1 PC06 - PC11 share the same segment number SG01
+// ------------------------------------------------------
+
+ Scope(\_SB.PC06) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG01)
+ }
+ }
+
+ Scope(\_SB.PC07) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG01)
+ }
+ }
+
+ Scope(\_SB.PC08) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG01)
+ }
+ }
+
+ Scope(\_SB.PC09) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG01)
+ }
+ }
+
+ Scope(\_SB.PC10) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG01)
+ }
+ }
+
+ Scope(\_SB.PC11) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG01)
+ }
+ }
+
+// ------------------------------------------------------
+// Socket 2 PC12 - PC17 share the same segment number SG02
+// ------------------------------------------------------
+
+ Scope(\_SB.PC12) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG02)
+ }
+ }
+
+ Scope(\_SB.PC13) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG02)
+ }
+ }
+
+ Scope(\_SB.PC14) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG02)
+ }
+ }
+
+ Scope(\_SB.PC15) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG02)
+ }
+ }
+
+ Scope(\_SB.PC16) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG02)
+ }
+ }
+
+ Scope(\_SB.PC17) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG02)
+ }
+ }
+
+
+// ------------------------------------------------------
+// Socket 3 PC18 - PC23 share the same segment number SG03
+// ------------------------------------------------------
+
+ Scope(\_SB.PC18) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG03)
+ }
+ }
+
+ Scope(\_SB.PC19) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG03)
+ }
+ }
+
+ Scope(\_SB.PC20) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG03)
+ }
+ }
+
+ Scope(\_SB.PC21) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG03)
+ }
+ }
+
+ Scope(\_SB.PC22) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG03)
+ }
+ }
+
+ Scope(\_SB.PC23) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG03)
+ }
+ }
+
+#if MAX_SOCKET > 4
+
+// ------------------------------------------------------
+// Socket 4 PC24 - PC29 share the same segment number SG03
+// ------------------------------------------------------
+
+ Scope(\_SB.PC24) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG04)
+ }
+ }
+
+ Scope(\_SB.PC25) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG04)
+ }
+ }
+
+ Scope(\_SB.PC26) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG04)
+ }
+ }
+
+ Scope(\_SB.PC27) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG04)
+ }
+ }
+
+ Scope(\_SB.PC28) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG04)
+ }
+ }
+
+ Scope(\_SB.PC29) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG04)
+ }
+ }
+
+// ------------------------------------------------------
+// Socket 5 PC30 - PC35 share the same segment number SG03
+// ------------------------------------------------------
+
+ Scope(\_SB.PC30) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG05)
+ }
+ }
+
+ Scope(\_SB.PC31) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG05)
+ }
+ }
+
+ Scope(\_SB.PC32) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG05)
+ }
+ }
+
+ Scope(\_SB.PC33) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG05)
+ }
+ }
+
+ Scope(\_SB.PC34) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG05)
+ }
+ }
+
+ Scope(\_SB.PC35) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG05)
+ }
+ }
+
+// ------------------------------------------------------
+// Socket 6 PC36 - PC41 share the same segment number SG03
+// ------------------------------------------------------
+
+ Scope(\_SB.PC36) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG06)
+ }
+ }
+
+ Scope(\_SB.PC37) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG06)
+ }
+ }
+
+ Scope(\_SB.PC38) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG06)
+ }
+ }
+
+ Scope(\_SB.PC39) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG06)
+ }
+ }
+
+ Scope(\_SB.PC40) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG06)
+ }
+ }
+
+ Scope(\_SB.PC41) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG06)
+ }
+ }
+
+// ------------------------------------------------------
+// Socket 7 PC42 - PC47 share the same segment number SG03
+// ------------------------------------------------------
+
+ Scope(\_SB.PC42) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG07)
+ }
+ }
+
+ Scope(\_SB.PC43) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG07)
+ }
+ }
+
+ Scope(\_SB.PC44) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG07)
+ }
+ }
+
+ Scope(\_SB.PC45) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG07)
+ }
+ }
+
+ Scope(\_SB.PC46) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG07)
+ }
+ }
+
+ Scope(\_SB.PC47) {
+ Method (_SEG, 0, NotSerialized) {
+ return (SG07)
+ }
+ }
+#endif
+
+} // End Scope(\)
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl new file mode 100644 index 0000000000..69ad6e0382 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl @@ -0,0 +1,85 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+// Interrupt specific registers
+include("Itss.asl")
+//
+// Original file line: 163
+//
+
+Method(ADBG,1,Serialized)
+{
+ Return(0)
+}
+
+//
+// Original file line: 1460
+//
+Scope (\)
+{
+ //
+ // Global Name, returns current Interrupt controller mode;
+ // updated from _PIC control method
+ //
+
+ //
+ // Procedure: GPRW
+ //
+ // Description: Generic Wake up Control Method ("Big brother")
+ // to detect the Max Sleep State available in ASL Name scope
+ // and Return the Package compatible with _PRW format.
+ // Input: Arg0 = bit offset within GPE register space device event will be triggered to.
+ // Arg1 = Max Sleep state, device can resume the System from.
+ // If Arg1 = 0, Update Arg1 with Max _Sx state enabled in the System.
+ // Output: _PRW package
+ //
+ Name(PRWP, Package(){Zero, Zero}) // _PRW Package
+
+ Method(GPRW, 2)
+ {
+ Store(Arg0, Index(PRWP, 0)) // copy GPE#
+ //
+ // SS1-SS4 - enabled in BIOS Setup Sleep states
+ //
+ Store(ShiftLeft(SS1,1),Local0) // S1 ?
+ Or(Local0,ShiftLeft(SS2,2),Local0) // S2 ?
+ Or(Local0,ShiftLeft(SS3,3),Local0) // S3 ?
+ Or(Local0,ShiftLeft(SS4,4),Local0) // S4 ?
+ //
+ // Local0 has a bit mask of enabled Sx(1 based)
+ // bit mask of enabled in BIOS Setup Sleep states(1 based)
+ //
+ If(And(ShiftLeft(1, Arg1), Local0))
+ {
+ //
+ // Requested wake up value (Arg1) is present in Sx list of available Sleep states
+ //
+ Store(Arg1, Index(PRWP, 1)) // copy Sx#
+ }
+ Else
+ {
+ //
+ // Not available -> match Wake up value to the higher Sx state
+ //
+ ShiftRight(Local0, 1, Local0)
+ // If(LOr(LEqual(OSFL, 1), LEqual(OSFL, 2))) { // ??? Win9x
+ // FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 == Max Sx
+ // } Else { // ??? Win2k / XP
+ FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 == Min Sx
+ // }
+ }
+
+ Return(PRWP)
+ }
+}
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGpe.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGpe.asi new file mode 100644 index 0000000000..ec7c3e3315 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGpe.asi @@ -0,0 +1,84 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+// General Purpose Event
+#include "MaxSocket.h"
+
+Scope (\_GPE) {
+
+ //
+ // ME HECI2 SCI handler
+ // Note: This SCI from HECI2 is routed to ICH9 over the DMI and it
+ // sets the DMISCI status bit in TCO block. From there it is routed
+ // to bit6 GPE0 status register.
+ //
+ OperationRegion (TCOS, SystemIO, 0x464, 2) // ICH_ACPI_BASE_ADDRESS + TCO_BASE + R_TCO1_STS
+ Field (TCOS, ByteAcc, NoLock, WriteAsZeros) {
+ Offset (0x1),
+ , 1,
+ DSCI, 1,
+ }
+
+ Method(NTFI, 2){
+ If(And(Arg0, 0x01)){
+ Notify(\_SB.PC06, Arg1)
+ Notify(\_SB.PC07, Arg1)
+ Notify(\_SB.PC08, Arg1)
+ Notify(\_SB.PC09, Arg1)
+ Notify(\_SB.PC10, Arg1)
+ Notify(\_SB.PC11, Arg1)
+ }
+ If(And(Arg0, 0x02)){
+ Notify(\_SB.PC12, Arg1)
+ Notify(\_SB.PC13, Arg1)
+ Notify(\_SB.PC14, Arg1)
+ Notify(\_SB.PC15, Arg1)
+ Notify(\_SB.PC16, Arg1)
+ Notify(\_SB.PC17, Arg1)
+ }
+ If(And(Arg0, 0x04)){
+ Notify(\_SB.PC18, Arg1)
+ Notify(\_SB.PC19, Arg1)
+ Notify(\_SB.PC20, Arg1)
+ Notify(\_SB.PC21, Arg1)
+ Notify(\_SB.PC22, Arg1)
+ Notify(\_SB.PC23, Arg1)
+ }
+ } //End Method NTFI
+
+ // Tell OS to run thru the new status of this device (Software SCI generated from SMM for all Hot plug events)
+ Method (_L62, 0x0, NotSerialized) {
+ if(LEqual(SCI0, 3)) { // Device ejection (Invoked with _EJ0 method called)
+ Store (0, SCI0)
+ } else { // Device check (OS can still reject online request based on resources and capability)
+ NTFI (IIOP, 0)
+ Store (0, MEBC)
+ Store (0, CPHP)
+ Store (0, IIOP)
+ }
+ Store (0, SGPC)
+ Store (1, SGPS)
+
+ }
+
+ // PME supported for Slots, use GPE 9 for PME
+ // Hot plug on all slots for now, change later.
+ // Slot numbers on silk screen might be different than the port number, currently use port numbers.
+ //
+ // IIO PCI_E Slot Hotplug GPE Event
+ //
+ Method (_L61, 0, NotSerialized) {
+ #include "IioPcieHotPlugGpeHandler.asl"
+ }// end of _L01 GPE Method
+
+}// end of _GPE scope.
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformPciTree_WFP.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformPciTree_WFP.asi new file mode 100644 index 0000000000..28344b9aa2 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformPciTree_WFP.asi @@ -0,0 +1,8076 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+Scope (\_SB) {
+
+ Name (PR00, Package() {
+ // [DMI0]: Legacy PCI Express Port 0 on PC00
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [CB0A]: CB3DMA on PC00
+ // [CB0E]: CB3DMA on PC00
+ Package() { 0x0004FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [CB0B]: CB3DMA on PC00
+ // [CB0F]: CB3DMA on PC00
+ Package() { 0x0004FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ // [CB0C]: CB3DMA on PC00
+ // [CB0G]: CB3DMA on PC00
+ Package() { 0x0004FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ // [CB0D]: CB3DMA on PC00
+ // [CB0H]: CB3DMA on PC00
+ Package() { 0x0004FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [IIM0]: IIOMISC on PC00
+ Package() { 0x0005FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0005FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0005FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0005FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [UBX0]: Uncore 0 UBOX Device
+ Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [DISP]: Display Controller
+ Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [IHC1]: HECI #1
+ // [IHC3]: HECI #3
+ Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [IHC2]: HECI #2
+ Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ // [IIDR]: IDE-Redirection (IDE-R)
+ Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ // [IMKT]: Keyboard and Text (KT) Redirection
+ Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [SAT2]: sSATA Host controller 2 on PCH
+ Package() { 0x0011FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [XHCI]: xHCI controller 1 on PCH
+ Package() { 0x0014FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [OTG0]: USB Device Controller (OTG) on PCH
+ Package() { 0x0014FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ // [TERM]: Thermal Subsystem on PCH
+ Package() { 0x0014FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ // [CAMR]: Camera IO Host Controller on PCH
+ Package() { 0x0014FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [HEC1]: HECI #1 on PCH
+ // [HEC3]: HECI #3 on PCH
+ Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [HEC2]: HECI #2 on PCH
+ Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ // [IDER]: ME IDE redirect on PCH
+ Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ // [MEKT]: MEKT on PCH
+ Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [SAT1]: SATA controller 1 on PCH
+ Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [NAN1]: NAND Cycle Router on PCH
+ Package() { 0x0018FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [RP17]: PCIE PCH Root Port #17
+ Package() { 0x001BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [RP18]: PCIE PCH Root Port #18
+ Package() { 0x001BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ // [RP19]: PCIE PCH Root Port #19
+ Package() { 0x001BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ // [RP20]: PCIE PCH Root Port #20
+ Package() { 0x001BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [RP01]: PCIE PCH Root Port #1
+ // [RP05]: PCIE PCH Root Port #5
+ Package() { 0x001CFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [RP02]: PCIE PCH Root Port #2
+ // [RP06]: PCIE PCH Root Port #6
+ Package() { 0x001CFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ // [RP03]: PCIE PCH Root Port #3
+ // [RP07]: PCIE PCH Root Port #7
+ Package() { 0x001CFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ // [RP04]: PCIE PCH Root Port #4
+ // [RP08]: PCIE PCH Root Port #8
+ Package() { 0x001CFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [RP09]: PCIE PCH Root Port #9
+ // [RP13]: PCIE PCH Root Port #13
+ Package() { 0x001DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [RP10]: PCIE PCH Root Port #10
+ // [RP14]: PCIE PCH Root Port #14
+ Package() { 0x001DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ // [RP11]: PCIE PCH Root Port #11
+ // [RP15]: PCIE PCH Root Port #15
+ Package() { 0x001DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ // [RP12]: PCIE PCH Root Port #12
+ // [RP16]: PCIE PCH Root Port #16
+ Package() { 0x001DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [UAR0]: UART #0 on PCH
+ Package() { 0x001EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [UAR1]: UART #1 on PCH
+ Package() { 0x001EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ // [SPI0]: SPI #0 on PCH
+ Package() { 0x001EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ // [SPI1]: SPI #1 on PCH
+ Package() { 0x001EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CAVS]: HD Audio Subsystem Controller on PCH
+ // [SMBS]: SMBus controller on PCH
+ // [GBE1]: GbE Controller on PCH
+ // [NTPK]: Northpeak Controller on PCH
+ Package() { 0x001FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ })
+
+ Name (AR00, Package() {
+ // [DMI0]: Legacy PCI Express Port 0 on PC00
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ // [CB0A]: CB3DMA on PC00
+ // [CB0E]: CB3DMA on PC00
+ Package() { 0x0004FFFF, 0, 0, 16 },
+ // [CB0B]: CB3DMA on PC00
+ // [CB0F]: CB3DMA on PC00
+ Package() { 0x0004FFFF, 1, 0, 17 },
+ // [CB0C]: CB3DMA on PC00
+ // [CB0G]: CB3DMA on PC00
+ Package() { 0x0004FFFF, 2, 0, 18 },
+ // [CB0D]: CB3DMA on PC00
+ // [CB0H]: CB3DMA on PC00
+ Package() { 0x0004FFFF, 3, 0, 19 },
+ // [IIM0]: IIOMISC on PC00
+ Package() { 0x0005FFFF, 0, 0, 16 },
+ Package() { 0x0005FFFF, 1, 0, 17 },
+ Package() { 0x0005FFFF, 2, 0, 18 },
+ Package() { 0x0005FFFF, 3, 0, 19 },
+ // [UBX0]: Uncore 0 UBOX Device
+ Package() { 0x0008FFFF, 0, 0, 16 },
+ Package() { 0x0008FFFF, 1, 0, 17 },
+ Package() { 0x0008FFFF, 2, 0, 18 },
+ Package() { 0x0008FFFF, 3, 0, 19 },
+ // [DISP]: Display Controller
+ Package() { 0x000FFFFF, 0, 0, 16 },
+ // [IHC1]: HECI #1
+ // [IHC3]: HECI #3
+ Package() { 0x0010FFFF, 0, 0, 16 },
+ // [IHC2]: HECI #2
+ Package() { 0x0010FFFF, 1, 0, 17 },
+ // [IIDR]: IDE-Redirection (IDE-R)
+ Package() { 0x0010FFFF, 2, 0, 18 },
+ // [IMKT]: Keyboard and Text (KT) Redirection
+ Package() { 0x0010FFFF, 3, 0, 19 },
+ // [SAT2]: sSATA Host controller 2 on PCH
+ Package() { 0x0011FFFF, 0, 0, 16 },
+ // [XHCI]: xHCI controller 1 on PCH
+ Package() { 0x0014FFFF, 0, 0, 16 },
+ // [OTG0]: USB Device Controller (OTG) on PCH
+ Package() { 0x0014FFFF, 1, 0, 17 },
+ // [TERM]: Thermal Subsystem on PCH
+ Package() { 0x0014FFFF, 2, 0, 18 },
+ // [CAMR]: Camera IO Host Controller on PCH
+ Package() { 0x0014FFFF, 3, 0, 19 },
+ // [HEC1]: HECI #1 on PCH
+ // [HEC3]: HECI #3 on PCH
+ Package() { 0x0016FFFF, 0, 0, 16 },
+ // [HEC2]: HECI #2 on PCH
+ Package() { 0x0016FFFF, 1, 0, 17 },
+ // [IDER]: ME IDE redirect on PCH
+ Package() { 0x0016FFFF, 2, 0, 18 },
+ // [MEKT]: MEKT on PCH
+ Package() { 0x0016FFFF, 3, 0, 19 },
+ // [SAT1]: SATA controller 1 on PCH
+ Package() { 0x0017FFFF, 0, 0, 16 },
+ // [NAN1]: NAND Cycle Router on PCH
+ Package() { 0x0018FFFF, 0, 0, 16 },
+ // [RP17]: PCIE PCH Root Port #17
+ Package() { 0x001BFFFF, 0, 0, 16 },
+ // [RP18]: PCIE PCH Root Port #18
+ Package() { 0x001BFFFF, 1, 0, 17 },
+ // [RP19]: PCIE PCH Root Port #19
+ Package() { 0x001BFFFF, 2, 0, 18 },
+ // [RP20]: PCIE PCH Root Port #20
+ Package() { 0x001BFFFF, 3, 0, 19 },
+ // [RP01]: PCIE PCH Root Port #1
+ // [RP05]: PCIE PCH Root Port #5
+ Package() { 0x001CFFFF, 0, 0, 16 },
+ // [RP02]: PCIE PCH Root Port #2
+ // [RP06]: PCIE PCH Root Port #6
+ Package() { 0x001CFFFF, 1, 0, 17 },
+ // [RP03]: PCIE PCH Root Port #3
+ // [RP07]: PCIE PCH Root Port #7
+ Package() { 0x001CFFFF, 2, 0, 18 },
+ // [RP04]: PCIE PCH Root Port #4
+ // [RP08]: PCIE PCH Root Port #8
+ Package() { 0x001CFFFF, 3, 0, 19 },
+ // [RP09]: PCIE PCH Root Port #9
+ // [RP13]: PCIE PCH Root Port #13
+ Package() { 0x001DFFFF, 0, 0, 16 },
+ // [RP10]: PCIE PCH Root Port #10
+ // [RP14]: PCIE PCH Root Port #14
+ Package() { 0x001DFFFF, 1, 0, 17 },
+ // [RP11]: PCIE PCH Root Port #11
+ // [RP15]: PCIE PCH Root Port #15
+ Package() { 0x001DFFFF, 2, 0, 18 },
+ // [RP12]: PCIE PCH Root Port #12
+ // [RP16]: PCIE PCH Root Port #16
+ Package() { 0x001DFFFF, 3, 0, 19 },
+ // [UAR0]: UART #0 on PCH
+ Package() { 0x001EFFFF, 0, 0, 20 },
+ // [UAR1]: UART #1 on PCH
+ Package() { 0x001EFFFF, 1, 0, 21 },
+ // [SPI0]: SPI #0 on PCH
+ Package() { 0x001EFFFF, 2, 0, 22 },
+ // [SPI1]: SPI #1 on PCH
+ Package() { 0x001EFFFF, 3, 0, 23 },
+ // [CAVS]: HD Audio Subsystem Controller on PCH
+ // [SMBS]: SMBus controller on PCH
+ // [GBE1]: GbE Controller on PCH
+ // [NTPK]: Northpeak Controller on PCH
+ Package() { 0x001FFFFF, 0, 0, 16 },
+ })
+
+ Name (AH00, Package() {
+ // [DMI0]: Legacy PCI Express Port 0 on PC00
+ Package() { 0x0000FFFF, 0, 0, 31 },
+ // [CB0A]: CB3DMA on PC00
+ // [CB0E]: CB3DMA on PC00
+ Package() { 0x0004FFFF, 0, 0, 26 },
+ // [CB0B]: CB3DMA on PC00
+ // [CB0F]: CB3DMA on PC00
+ Package() { 0x0004FFFF, 1, 0, 27 },
+ // [CB0C]: CB3DMA on PC00
+ // [CB0G]: CB3DMA on PC00
+ Package() { 0x0004FFFF, 2, 0, 26 },
+ // [CB0D]: CB3DMA on PC00
+ // [CB0H]: CB3DMA on PC00
+ Package() { 0x0004FFFF, 3, 0, 27 },
+ // [IIM0]: IIOMISC on PC00
+ Package() { 0x0005FFFF, 0, 0, 16 },
+ Package() { 0x0005FFFF, 1, 0, 17 },
+ Package() { 0x0005FFFF, 2, 0, 18 },
+ Package() { 0x0005FFFF, 3, 0, 19 },
+ // [UBX0]: Uncore 0 UBOX Device
+ Package() { 0x0008FFFF, 0, 0, 24 },
+ Package() { 0x0008FFFF, 1, 0, 28 },
+ Package() { 0x0008FFFF, 2, 0, 29 },
+ Package() { 0x0008FFFF, 3, 0, 30 },
+ // [DISP]: Display Controller
+ Package() { 0x000FFFFF, 0, 0, 16 },
+ // [IHC1]: HECI #1
+ // [IHC3]: HECI #3
+ Package() { 0x0010FFFF, 0, 0, 16 },
+ // [IHC2]: HECI #2
+ Package() { 0x0010FFFF, 1, 0, 17 },
+ // [IIDR]: IDE-Redirection (IDE-R)
+ Package() { 0x0010FFFF, 2, 0, 18 },
+ // [IMKT]: Keyboard and Text (KT) Redirection
+ Package() { 0x0010FFFF, 3, 0, 19 },
+ // [SAT2]: sSATA Host controller 2 on PCH
+ Package() { 0x0011FFFF, 0, 0, 16 },
+ // [XHCI]: xHCI controller 1 on PCH
+ Package() { 0x0014FFFF, 0, 0, 16 },
+ // [OTG0]: USB Device Controller (OTG) on PCH
+ Package() { 0x0014FFFF, 1, 0, 17 },
+ // [TERM]: Thermal Subsystem on PCH
+ Package() { 0x0014FFFF, 2, 0, 18 },
+ // [CAMR]: Camera IO Host Controller on PCH
+ Package() { 0x0014FFFF, 3, 0, 19 },
+ // [HEC1]: HECI #1 on PCH
+ // [HEC3]: HECI #3 on PCH
+ Package() { 0x0016FFFF, 0, 0, 16 },
+ // [HEC2]: HECI #2 on PCH
+ Package() { 0x0016FFFF, 1, 0, 17 },
+ // [IDER]: ME IDE redirect on PCH
+ Package() { 0x0016FFFF, 2, 0, 18 },
+ // [MEKT]: MEKT on PCH
+ Package() { 0x0016FFFF, 3, 0, 19 },
+ // [SAT1]: SATA controller 1 on PCH
+ Package() { 0x0017FFFF, 0, 0, 16 },
+ // [NAN1]: NAND Cycle Router on PCH
+ Package() { 0x0018FFFF, 0, 0, 16 },
+ // [RP17]: PCIE PCH Root Port #17
+ Package() { 0x001BFFFF, 0, 0, 16 },
+ // [RP18]: PCIE PCH Root Port #18
+ Package() { 0x001BFFFF, 1, 0, 17 },
+ // [RP19]: PCIE PCH Root Port #19
+ Package() { 0x001BFFFF, 2, 0, 18 },
+ // [RP20]: PCIE PCH Root Port #20
+ Package() { 0x001BFFFF, 3, 0, 19 },
+ // [RP01]: PCIE PCH Root Port #1
+ // [RP05]: PCIE PCH Root Port #5
+ Package() { 0x001CFFFF, 0, 0, 16 },
+ // [RP02]: PCIE PCH Root Port #2
+ // [RP06]: PCIE PCH Root Port #6
+ Package() { 0x001CFFFF, 1, 0, 17 },
+ // [RP03]: PCIE PCH Root Port #3
+ // [RP07]: PCIE PCH Root Port #7
+ Package() { 0x001CFFFF, 2, 0, 18 },
+ // [RP04]: PCIE PCH Root Port #4
+ // [RP08]: PCIE PCH Root Port #8
+ Package() { 0x001CFFFF, 3, 0, 19 },
+ // [RP09]: PCIE PCH Root Port #9
+ // [RP13]: PCIE PCH Root Port #13
+ Package() { 0x001DFFFF, 0, 0, 16 },
+ // [RP10]: PCIE PCH Root Port #10
+ // [RP14]: PCIE PCH Root Port #14
+ Package() { 0x001DFFFF, 1, 0, 17 },
+ // [RP11]: PCIE PCH Root Port #11
+ // [RP15]: PCIE PCH Root Port #15
+ Package() { 0x001DFFFF, 2, 0, 18 },
+ // [RP12]: PCIE PCH Root Port #12
+ // [RP16]: PCIE PCH Root Port #16
+ Package() { 0x001DFFFF, 3, 0, 19 },
+ // [UAR0]: UART #0 on PCH
+ Package() { 0x001EFFFF, 0, 0, 20 },
+ // [UAR1]: UART #1 on PCH
+ Package() { 0x001EFFFF, 1, 0, 21 },
+ // [SPI0]: SPI #0 on PCH
+ Package() { 0x001EFFFF, 2, 0, 22 },
+ // [SPI1]: SPI #1 on PCH
+ Package() { 0x001EFFFF, 3, 0, 23 },
+ // [CAVS]: HD Audio Subsystem Controller on PCH
+ // [SMBS]: SMBus controller on PCH
+ // [GBE1]: GbE Controller on PCH
+ // [NTPK]: Northpeak Controller on PCH
+ Package() { 0x001FFFFF, 0, 0, 16 },
+ })
+
+ Name (PR01, Package() {
+ // [SLTH]: PCIE PCH Slot #17
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR01, Package() {
+ // [SLTH]: PCIE PCH Slot #17
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (PR02, Package() {
+ // [SLTI]: PCIE PCH Slot #18
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKD, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKA, 0 },
+ })
+
+ Name (AR02, Package() {
+ // [SLTI]: PCIE PCH Slot #18
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (PR03, Package() {
+ // [SLTJ]: PCIE PCH Slot #19
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKD, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKB, 0 },
+ })
+
+ Name (AR03, Package() {
+ // [SLTJ]: PCIE PCH Slot #19
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (PR04, Package() {
+ // [SLTK]: PCIE PCH Slot #20
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKD, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKC, 0 },
+ })
+
+ Name (AR04, Package() {
+ // [SLTK]: PCIE PCH Slot #20
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (PR05, Package() {
+ // [SLT1]: PCIE PCH Slot #1
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR05, Package() {
+ // [SLT1]: PCIE PCH Slot #1
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (PR06, Package() {
+ // [SLT2]: PCIE PCH Slot #2
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKD, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKA, 0 },
+ })
+
+ Name (AR06, Package() {
+ // [SLT2]: PCIE PCH Slot #2
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (PR07, Package() {
+ // [SLT3]: PCIE PCH Slot #3
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKD, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKB, 0 },
+ })
+
+ Name (AR07, Package() {
+ // [SLT3]: PCIE PCH Slot #3
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (PR08, Package() {
+ // [SLT4]: PCIE PCH Slot #4
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKD, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKC, 0 },
+ })
+
+ Name (AR08, Package() {
+ // [SLT4]: PCIE PCH Slot #4
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (PR09, Package() {
+ // [SLT5]: PCIE PCH Slot #5
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR09, Package() {
+ // [SLT5]: PCIE PCH Slot #5
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (PR0A, Package() {
+ // [SLT6]: PCIE PCH Slot #6
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKD, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKA, 0 },
+ })
+
+ Name (AR0A, Package() {
+ // [SLT6]: PCIE PCH Slot #6
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (PR0B, Package() {
+ // [SLT7]: PCIE PCH Slot #7
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKD, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKB, 0 },
+ })
+
+ Name (AR0B, Package() {
+ // [SLT7]: PCIE PCH Slot #7
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (PR0C, Package() {
+ // [SLT8]: PCIE PCH Slot #8
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKD, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKC, 0 },
+ })
+
+ Name (AR0C, Package() {
+ // [SLT8]: PCIE PCH Slot #8
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (PR0D, Package() {
+ // [SLT9]: PCIE PCH Slot #9
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR0D, Package() {
+ // [SLT9]: PCIE PCH Slot #9
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (PR0E, Package() {
+ // [SLTA]: PCIE PCH Slot #10
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKD, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKA, 0 },
+ })
+
+ Name (AR0E, Package() {
+ // [SLTA]: PCIE PCH Slot #10
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (PR0F, Package() {
+ // [SLTB]: PCIE PCH Slot #11
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKD, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKB, 0 },
+ })
+
+ Name (AR0F, Package() {
+ // [SLTB]: PCIE PCH Slot #11
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (PR10, Package() {
+ // [SLTC]: PCIE PCH Slot #12
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKD, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKC, 0 },
+ })
+
+ Name (AR10, Package() {
+ // [SLTC]: PCIE PCH Slot #12
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (PR11, Package() {
+ // [SLTD]: PCIE PCH Slot #13
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR11, Package() {
+ // [SLTD]: PCIE PCH Slot #13
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (PR12, Package() {
+ // [SLTE]: PCIE PCH Slot #14
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKD, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKA, 0 },
+ })
+
+ Name (AR12, Package() {
+ // [SLTE]: PCIE PCH Slot #14
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (PR13, Package() {
+ // [SLTF]: PCIE PCH Slot #15
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKD, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKB, 0 },
+ })
+
+ Name (AR13, Package() {
+ // [SLTF]: PCIE PCH Slot #15
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (PR14, Package() {
+ // [SLTG]: PCIE PCH Slot #16
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKD, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKC, 0 },
+ })
+
+ Name (AR14, Package() {
+ // [SLTG]: PCIE PCH Slot #16
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (PR15, Package() {
+ // [BR1A]: PCI Express Port 1A on PC01
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [BR1B]: PCI Express Port 1B on PC01
+ Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [BR1C]: PCI Express Port 1C on PC01
+ Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [BR1D]: PCI Express Port 1D on PC01
+ Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [CHA0]: Uncore 1 CHAUTIL0-7 Device
+ Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CHA1]: Uncore 1 CHAUTIL8-15 Device
+ Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CHA2]: Uncore 1 CHAUTIL16-23 Device
+ Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CHA3]: Uncore 1 CHAUTIL24-27 Device
+ Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CHA4]: Uncore 1 CHASAD0-7 Device
+ Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CHA5]: Uncore 1 CHASAD8-15 Device
+ Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CHA6]: Uncore 1 CHASAD16-23 Device
+ Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CHA7]: Uncore 1 CHASAD24-27 Device
+ Package() { 0x0011FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0011FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0011FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0011FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CMS0]: Uncore 1 CMSCHA0-7 Device
+ Package() { 0x0014FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0014FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0014FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0014FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CMS1]: Uncore 1 CMS0CHA8-15 Device
+ Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CMS2]: Uncore 1 CMS0CHA16-23 Device
+ Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CMS3]: Uncore 1 CMS0CHA24-27 Device
+ Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CDL0]: Uncore 1 CHASADALL Device
+ Package() { 0x001DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x001DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x001DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x001DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [PCU0]: Uncore 1 PCUCR Devices
+ Package() { 0x001EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x001EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x001EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x001EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [VCU0]: Uncore 1 VCUCR Device
+ Package() { 0x001FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x001FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x001FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x001FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR15, Package() {
+ // [BR1A]: PCI Express Port 1A on PC01
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ // [BR1B]: PCI Express Port 1B on PC01
+ Package() { 0x0001FFFF, 0, 0, 16 },
+ // [BR1C]: PCI Express Port 1C on PC01
+ Package() { 0x0002FFFF, 0, 0, 16 },
+ // [BR1D]: PCI Express Port 1D on PC01
+ Package() { 0x0003FFFF, 0, 0, 16 },
+ // [CHA0]: Uncore 1 CHAUTIL0-7 Device
+ Package() { 0x0008FFFF, 0, 0, 16 },
+ Package() { 0x0008FFFF, 1, 0, 17 },
+ Package() { 0x0008FFFF, 2, 0, 18 },
+ Package() { 0x0008FFFF, 3, 0, 19 },
+ // [CHA1]: Uncore 1 CHAUTIL8-15 Device
+ Package() { 0x0009FFFF, 0, 0, 16 },
+ Package() { 0x0009FFFF, 1, 0, 17 },
+ Package() { 0x0009FFFF, 2, 0, 18 },
+ Package() { 0x0009FFFF, 3, 0, 19 },
+ // [CHA2]: Uncore 1 CHAUTIL16-23 Device
+ Package() { 0x000AFFFF, 0, 0, 16 },
+ Package() { 0x000AFFFF, 1, 0, 17 },
+ Package() { 0x000AFFFF, 2, 0, 18 },
+ Package() { 0x000AFFFF, 3, 0, 19 },
+ // [CHA3]: Uncore 1 CHAUTIL24-27 Device
+ Package() { 0x000BFFFF, 0, 0, 16 },
+ Package() { 0x000BFFFF, 1, 0, 17 },
+ Package() { 0x000BFFFF, 2, 0, 18 },
+ Package() { 0x000BFFFF, 3, 0, 19 },
+ // [CHA4]: Uncore 1 CHASAD0-7 Device
+ Package() { 0x000EFFFF, 0, 0, 16 },
+ Package() { 0x000EFFFF, 1, 0, 17 },
+ Package() { 0x000EFFFF, 2, 0, 18 },
+ Package() { 0x000EFFFF, 3, 0, 19 },
+ // [CHA5]: Uncore 1 CHASAD8-15 Device
+ Package() { 0x000FFFFF, 0, 0, 16 },
+ Package() { 0x000FFFFF, 1, 0, 17 },
+ Package() { 0x000FFFFF, 2, 0, 18 },
+ Package() { 0x000FFFFF, 3, 0, 19 },
+ // [CHA6]: Uncore 1 CHASAD16-23 Device
+ Package() { 0x0010FFFF, 0, 0, 16 },
+ Package() { 0x0010FFFF, 1, 0, 17 },
+ Package() { 0x0010FFFF, 2, 0, 18 },
+ Package() { 0x0010FFFF, 3, 0, 19 },
+ // [CHA7]: Uncore 1 CHASAD24-27 Device
+ Package() { 0x0011FFFF, 0, 0, 16 },
+ Package() { 0x0011FFFF, 1, 0, 17 },
+ Package() { 0x0011FFFF, 2, 0, 18 },
+ Package() { 0x0011FFFF, 3, 0, 19 },
+ // [CMS0]: Uncore 1 CMSCHA0-7 Device
+ Package() { 0x0014FFFF, 0, 0, 16 },
+ Package() { 0x0014FFFF, 1, 0, 17 },
+ Package() { 0x0014FFFF, 2, 0, 18 },
+ Package() { 0x0014FFFF, 3, 0, 19 },
+ // [CMS1]: Uncore 1 CMS0CHA8-15 Device
+ Package() { 0x0015FFFF, 0, 0, 16 },
+ Package() { 0x0015FFFF, 1, 0, 17 },
+ Package() { 0x0015FFFF, 2, 0, 18 },
+ Package() { 0x0015FFFF, 3, 0, 19 },
+ // [CMS2]: Uncore 1 CMS0CHA16-23 Device
+ Package() { 0x0016FFFF, 0, 0, 16 },
+ Package() { 0x0016FFFF, 1, 0, 17 },
+ Package() { 0x0016FFFF, 2, 0, 18 },
+ Package() { 0x0016FFFF, 3, 0, 19 },
+ // [CMS3]: Uncore 1 CMS0CHA24-27 Device
+ Package() { 0x0017FFFF, 0, 0, 16 },
+ Package() { 0x0017FFFF, 1, 0, 17 },
+ Package() { 0x0017FFFF, 2, 0, 18 },
+ Package() { 0x0017FFFF, 3, 0, 19 },
+ // [CDL0]: Uncore 1 CHASADALL Device
+ Package() { 0x001DFFFF, 0, 0, 16 },
+ Package() { 0x001DFFFF, 1, 0, 17 },
+ Package() { 0x001DFFFF, 2, 0, 18 },
+ Package() { 0x001DFFFF, 3, 0, 19 },
+ // [PCU0]: Uncore 1 PCUCR Devices
+ Package() { 0x001EFFFF, 0, 0, 16 },
+ Package() { 0x001EFFFF, 1, 0, 17 },
+ Package() { 0x001EFFFF, 2, 0, 18 },
+ Package() { 0x001EFFFF, 3, 0, 19 },
+ // [VCU0]: Uncore 1 VCUCR Device
+ Package() { 0x001FFFFF, 0, 0, 16 },
+ Package() { 0x001FFFFF, 1, 0, 17 },
+ Package() { 0x001FFFFF, 2, 0, 18 },
+ Package() { 0x001FFFFF, 3, 0, 19 },
+ })
+
+ Name (AH15, Package() {
+ // [BR1A]: PCI Express Port 1A on PC01
+ Package() { 0x0000FFFF, 0, 0, 39 },
+ // [BR1B]: PCI Express Port 1B on PC01
+ Package() { 0x0001FFFF, 0, 0, 39 },
+ // [BR1C]: PCI Express Port 1C on PC01
+ Package() { 0x0002FFFF, 0, 0, 39 },
+ // [BR1D]: PCI Express Port 1D on PC01
+ Package() { 0x0003FFFF, 0, 0, 39 },
+ // [CHA0]: Uncore 1 CHAUTIL0-7 Device
+ Package() { 0x0008FFFF, 0, 0, 32 },
+ Package() { 0x0008FFFF, 1, 0, 36 },
+ Package() { 0x0008FFFF, 2, 0, 37 },
+ Package() { 0x0008FFFF, 3, 0, 38 },
+ // [CHA1]: Uncore 1 CHAUTIL8-15 Device
+ Package() { 0x0009FFFF, 0, 0, 32 },
+ Package() { 0x0009FFFF, 1, 0, 36 },
+ Package() { 0x0009FFFF, 2, 0, 37 },
+ Package() { 0x0009FFFF, 3, 0, 38 },
+ // [CHA2]: Uncore 1 CHAUTIL16-23 Device
+ Package() { 0x000AFFFF, 0, 0, 32 },
+ Package() { 0x000AFFFF, 1, 0, 36 },
+ Package() { 0x000AFFFF, 2, 0, 37 },
+ Package() { 0x000AFFFF, 3, 0, 38 },
+ // [CHA3]: Uncore 1 CHAUTIL24-27 Device
+ Package() { 0x000BFFFF, 0, 0, 32 },
+ Package() { 0x000BFFFF, 1, 0, 36 },
+ Package() { 0x000BFFFF, 2, 0, 37 },
+ Package() { 0x000BFFFF, 3, 0, 38 },
+ // [CHA4]: Uncore 1 CHASAD0-7 Device
+ Package() { 0x000EFFFF, 0, 0, 32 },
+ Package() { 0x000EFFFF, 1, 0, 36 },
+ Package() { 0x000EFFFF, 2, 0, 37 },
+ Package() { 0x000EFFFF, 3, 0, 38 },
+ // [CHA5]: Uncore 1 CHASAD8-15 Device
+ Package() { 0x000FFFFF, 0, 0, 32 },
+ Package() { 0x000FFFFF, 1, 0, 36 },
+ Package() { 0x000FFFFF, 2, 0, 37 },
+ Package() { 0x000FFFFF, 3, 0, 38 },
+ // [CHA6]: Uncore 1 CHASAD16-23 Device
+ Package() { 0x0010FFFF, 0, 0, 32 },
+ Package() { 0x0010FFFF, 1, 0, 36 },
+ Package() { 0x0010FFFF, 2, 0, 37 },
+ Package() { 0x0010FFFF, 3, 0, 38 },
+ // [CHA7]: Uncore 1 CHASAD24-27 Device
+ Package() { 0x0011FFFF, 0, 0, 32 },
+ Package() { 0x0011FFFF, 1, 0, 36 },
+ Package() { 0x0011FFFF, 2, 0, 37 },
+ Package() { 0x0011FFFF, 3, 0, 38 },
+ // [CMS0]: Uncore 1 CMSCHA0-7 Device
+ Package() { 0x0014FFFF, 0, 0, 32 },
+ Package() { 0x0014FFFF, 1, 0, 36 },
+ Package() { 0x0014FFFF, 2, 0, 37 },
+ Package() { 0x0014FFFF, 3, 0, 38 },
+ // [CMS1]: Uncore 1 CMS0CHA8-15 Device
+ Package() { 0x0015FFFF, 0, 0, 32 },
+ Package() { 0x0015FFFF, 1, 0, 36 },
+ Package() { 0x0015FFFF, 2, 0, 37 },
+ Package() { 0x0015FFFF, 3, 0, 38 },
+ // [CMS2]: Uncore 1 CMS0CHA16-23 Device
+ Package() { 0x0016FFFF, 0, 0, 32 },
+ Package() { 0x0016FFFF, 1, 0, 36 },
+ Package() { 0x0016FFFF, 2, 0, 37 },
+ Package() { 0x0016FFFF, 3, 0, 38 },
+ // [CMS3]: Uncore 1 CMS0CHA24-27 Device
+ Package() { 0x0017FFFF, 0, 0, 32 },
+ Package() { 0x0017FFFF, 1, 0, 36 },
+ Package() { 0x0017FFFF, 2, 0, 37 },
+ Package() { 0x0017FFFF, 3, 0, 38 },
+ // [CDL0]: Uncore 1 CHASADALL Device
+ Package() { 0x001DFFFF, 0, 0, 32 },
+ Package() { 0x001DFFFF, 1, 0, 36 },
+ Package() { 0x001DFFFF, 2, 0, 37 },
+ Package() { 0x001DFFFF, 3, 0, 38 },
+ // [PCU0]: Uncore 1 PCUCR Devices
+ Package() { 0x001EFFFF, 0, 0, 32 },
+ Package() { 0x001EFFFF, 1, 0, 36 },
+ Package() { 0x001EFFFF, 2, 0, 37 },
+ Package() { 0x001EFFFF, 3, 0, 38 },
+ // [VCU0]: Uncore 1 VCUCR Device
+ Package() { 0x001FFFFF, 0, 0, 32 },
+ Package() { 0x001FFFFF, 1, 0, 36 },
+ Package() { 0x001FFFFF, 2, 0, 37 },
+ Package() { 0x001FFFFF, 3, 0, 38 },
+ })
+
+ Name (PR16, Package() {
+ // [SL01]: PCI Express Slot 1 on 1A on PC01
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR16, Package() {
+ // [SL01]: PCI Express Slot 1 on 1A on PC01
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH16, Package() {
+ // [SL01]: PCI Express Slot 1 on 1A on PC01
+ Package() { 0x0000FFFF, 0, 0, 32 },
+ Package() { 0x0000FFFF, 1, 0, 36 },
+ Package() { 0x0000FFFF, 2, 0, 37 },
+ Package() { 0x0000FFFF, 3, 0, 38 },
+ })
+
+ Name (PR17, Package() {
+ // [SL02]: PCI Express Slot 2 on 1B on PC01
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR17, Package() {
+ // [SL02]: PCI Express Slot 2 on 1B on PC01
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH17, Package() {
+ // [SL02]: PCI Express Slot 2 on 1B on PC01
+ Package() { 0x0000FFFF, 0, 0, 33 },
+ Package() { 0x0000FFFF, 1, 0, 38 },
+ Package() { 0x0000FFFF, 2, 0, 36 },
+ Package() { 0x0000FFFF, 3, 0, 37 },
+ })
+
+ Name (PR18, Package() {
+ // [SL03]: PCI Express Slot 3 on 1C on PC01
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR18, Package() {
+ // [SL03]: PCI Express Slot 3 on 1C on PC01
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH18, Package() {
+ // [SL03]: PCI Express Slot 3 on 1C on PC01
+ Package() { 0x0000FFFF, 0, 0, 34 },
+ Package() { 0x0000FFFF, 1, 0, 37 },
+ Package() { 0x0000FFFF, 2, 0, 38 },
+ Package() { 0x0000FFFF, 3, 0, 36 },
+ })
+
+ Name (PR19, Package() {
+ // [SL04]: PCI Express Slot 4 on 1D on PC01
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR19, Package() {
+ // [SL04]: PCI Express Slot 4 on 1D on PC01
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH19, Package() {
+ // [SL04]: PCI Express Slot 4 on 1D on PC01
+ Package() { 0x0000FFFF, 0, 0, 35 },
+ Package() { 0x0000FFFF, 1, 0, 38 },
+ Package() { 0x0000FFFF, 2, 0, 36 },
+ Package() { 0x0000FFFF, 3, 0, 37 },
+ })
+
+ Name (PR1A, Package() {
+ // [BR2A]: PCI Express Port 2A on PC02
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [BR2B]: PCI Express Port 2B on PC02
+ Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [BR2C]: PCI Express Port 2C on PC02
+ Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [BR2D]: PCI Express Port 2D on PC02
+ Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [M2M0]: Uncore 2 M2MEM0 Device
+ Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [M2M1]: Uncore 2 M2MEM10 Device
+ Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [MCM0]: Uncore 2 MCMAIN Device
+ Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [MCD0]: Uncore 2 MCDECS2 Device
+ Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [MCM1]: Uncore 2 MCMAIN Device
+ Package() { 0x000CFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000CFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000CFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000CFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [MCD1]: Uncore 2 MCDECS12 Device
+ Package() { 0x000DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [UMC0]: Uncore 2 Unicast MC0 DDRIO0 Device
+ Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [UMC1]: Uncore 2 Unicast MC1 DDRIO0 Device
+ Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR1A, Package() {
+ // [BR2A]: PCI Express Port 2A on PC02
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ // [BR2B]: PCI Express Port 2B on PC02
+ Package() { 0x0001FFFF, 0, 0, 16 },
+ // [BR2C]: PCI Express Port 2C on PC02
+ Package() { 0x0002FFFF, 0, 0, 16 },
+ // [BR2D]: PCI Express Port 2D on PC02
+ Package() { 0x0003FFFF, 0, 0, 16 },
+ // [M2M0]: Uncore 2 M2MEM0 Device
+ Package() { 0x0008FFFF, 0, 0, 16 },
+ Package() { 0x0008FFFF, 1, 0, 17 },
+ Package() { 0x0008FFFF, 2, 0, 18 },
+ Package() { 0x0008FFFF, 3, 0, 19 },
+ // [M2M1]: Uncore 2 M2MEM10 Device
+ Package() { 0x0009FFFF, 0, 0, 16 },
+ Package() { 0x0009FFFF, 1, 0, 17 },
+ Package() { 0x0009FFFF, 2, 0, 18 },
+ Package() { 0x0009FFFF, 3, 0, 19 },
+ // [MCM0]: Uncore 2 MCMAIN Device
+ Package() { 0x000AFFFF, 0, 0, 16 },
+ Package() { 0x000AFFFF, 1, 0, 17 },
+ Package() { 0x000AFFFF, 2, 0, 18 },
+ Package() { 0x000AFFFF, 3, 0, 19 },
+ // [MCD0]: Uncore 2 MCDECS2 Device
+ Package() { 0x000BFFFF, 0, 0, 16 },
+ Package() { 0x000BFFFF, 1, 0, 17 },
+ Package() { 0x000BFFFF, 2, 0, 18 },
+ Package() { 0x000BFFFF, 3, 0, 19 },
+ // [MCM1]: Uncore 2 MCMAIN Device
+ Package() { 0x000CFFFF, 0, 0, 16 },
+ Package() { 0x000CFFFF, 1, 0, 17 },
+ Package() { 0x000CFFFF, 2, 0, 18 },
+ Package() { 0x000CFFFF, 3, 0, 19 },
+ // [MCD1]: Uncore 2 MCDECS12 Device
+ Package() { 0x000DFFFF, 0, 0, 16 },
+ Package() { 0x000DFFFF, 1, 0, 17 },
+ Package() { 0x000DFFFF, 2, 0, 18 },
+ Package() { 0x000DFFFF, 3, 0, 19 },
+ // [UMC0]: Uncore 2 Unicast MC0 DDRIO0 Device
+ Package() { 0x0016FFFF, 0, 0, 16 },
+ Package() { 0x0016FFFF, 1, 0, 17 },
+ Package() { 0x0016FFFF, 2, 0, 18 },
+ Package() { 0x0016FFFF, 3, 0, 19 },
+ // [UMC1]: Uncore 2 Unicast MC1 DDRIO0 Device
+ Package() { 0x0017FFFF, 0, 0, 16 },
+ Package() { 0x0017FFFF, 1, 0, 17 },
+ Package() { 0x0017FFFF, 2, 0, 18 },
+ Package() { 0x0017FFFF, 3, 0, 19 },
+ })
+
+ Name (AH1A, Package() {
+ // [BR2A]: PCI Express Port 2A on PC02
+ Package() { 0x0000FFFF, 0, 0, 47 },
+ // [BR2B]: PCI Express Port 2B on PC02
+ Package() { 0x0001FFFF, 0, 0, 47 },
+ // [BR2C]: PCI Express Port 2C on PC02
+ Package() { 0x0002FFFF, 0, 0, 47 },
+ // [BR2D]: PCI Express Port 2D on PC02
+ Package() { 0x0003FFFF, 0, 0, 47 },
+ // [M2M0]: Uncore 2 M2MEM0 Device
+ Package() { 0x0008FFFF, 0, 0, 40 },
+ Package() { 0x0008FFFF, 1, 0, 44 },
+ Package() { 0x0008FFFF, 2, 0, 45 },
+ Package() { 0x0008FFFF, 3, 0, 46 },
+ // [M2M1]: Uncore 2 M2MEM10 Device
+ Package() { 0x0009FFFF, 0, 0, 40 },
+ Package() { 0x0009FFFF, 1, 0, 44 },
+ Package() { 0x0009FFFF, 2, 0, 45 },
+ Package() { 0x0009FFFF, 3, 0, 46 },
+ // [MCM0]: Uncore 2 MCMAIN Device
+ Package() { 0x000AFFFF, 0, 0, 40 },
+ Package() { 0x000AFFFF, 1, 0, 44 },
+ Package() { 0x000AFFFF, 2, 0, 45 },
+ Package() { 0x000AFFFF, 3, 0, 46 },
+ // [MCD0]: Uncore 2 MCDECS2 Device
+ Package() { 0x000BFFFF, 0, 0, 40 },
+ Package() { 0x000BFFFF, 1, 0, 44 },
+ Package() { 0x000BFFFF, 2, 0, 45 },
+ Package() { 0x000BFFFF, 3, 0, 46 },
+ // [MCM1]: Uncore 2 MCMAIN Device
+ Package() { 0x000CFFFF, 0, 0, 40 },
+ Package() { 0x000CFFFF, 1, 0, 44 },
+ Package() { 0x000CFFFF, 2, 0, 45 },
+ Package() { 0x000CFFFF, 3, 0, 46 },
+ // [MCD1]: Uncore 2 MCDECS12 Device
+ Package() { 0x000DFFFF, 0, 0, 40 },
+ Package() { 0x000DFFFF, 1, 0, 44 },
+ Package() { 0x000DFFFF, 2, 0, 45 },
+ Package() { 0x000DFFFF, 3, 0, 46 },
+ // [UMC0]: Uncore 2 Unicast MC0 DDRIO0 Device
+ Package() { 0x0016FFFF, 0, 0, 40 },
+ Package() { 0x0016FFFF, 1, 0, 44 },
+ Package() { 0x0016FFFF, 2, 0, 45 },
+ Package() { 0x0016FFFF, 3, 0, 46 },
+ // [UMC1]: Uncore 2 Unicast MC1 DDRIO0 Device
+ Package() { 0x0017FFFF, 0, 0, 40 },
+ Package() { 0x0017FFFF, 1, 0, 44 },
+ Package() { 0x0017FFFF, 2, 0, 45 },
+ Package() { 0x0017FFFF, 3, 0, 46 },
+ })
+
+ Name (PR1B, Package() {
+ // [SL05]: PCI Express Slot 5 on 2A on PC02
+ // [EPCU]: EVA PCIe Uplink
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR1B, Package() {
+ // [SL05]: PCI Express Slot 5 on 2A on PC02
+ // [EPCU]: EVA PCIe Uplink
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH1B, Package() {
+ // [SL05]: PCI Express Slot 5 on 2A on PC02
+ // [EPCU]: EVA PCIe Uplink
+ Package() { 0x0000FFFF, 0, 0, 40 },
+ Package() { 0x0000FFFF, 1, 0, 44 },
+ Package() { 0x0000FFFF, 2, 0, 45 },
+ Package() { 0x0000FFFF, 3, 0, 46 },
+ })
+
+ Name (PR1C, Package() {
+ // [VSP0]: EVA Virtual Switch Port 0
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [VSP1]: EVA Virtual Switch Port 1
+ Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [VSP2]: EVA Virtual Switch Port 2
+ Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [VSP3]: EVA Virtual Switch Port 3
+ Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ })
+
+ Name (AR1C, Package() {
+ // [VSP0]: EVA Virtual Switch Port 0
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ // [VSP1]: EVA Virtual Switch Port 1
+ Package() { 0x0001FFFF, 0, 0, 16 },
+ // [VSP2]: EVA Virtual Switch Port 2
+ Package() { 0x0002FFFF, 0, 0, 16 },
+ // [VSP3]: EVA Virtual Switch Port 3
+ Package() { 0x0003FFFF, 0, 0, 16 },
+ })
+
+ Name (AH1C, Package() {
+ // [VSP0]: EVA Virtual Switch Port 0
+ Package() { 0x0000FFFF, 0, 0, 40 },
+ Package() { 0x0000FFFF, 1, 0, 44 },
+ Package() { 0x0000FFFF, 2, 0, 45 },
+ Package() { 0x0000FFFF, 3, 0, 46 },
+ // [VSP1]: EVA Virtual Switch Port 1
+ Package() { 0x0001FFFF, 0, 0, 40 },
+ // [VSP2]: EVA Virtual Switch Port 2
+ Package() { 0x0002FFFF, 0, 0, 40 },
+ // [VSP3]: EVA Virtual Switch Port 3
+ Package() { 0x0003FFFF, 0, 0, 40 },
+ })
+
+ Name (PR1D, Package() {
+ // [CPM0]: EVA CPM0
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ })
+
+ Name (AR1D, Package() {
+ // [CPM0]: EVA CPM0
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ })
+
+ Name (AH1D, Package() {
+ // [CPM0]: EVA CPM0
+ Package() { 0x0000FFFF, 0, 0, 40 },
+ })
+
+ Name (PR1E, Package() {
+ // [CPM1]: EVA CPM1
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ })
+
+ Name (AR1E, Package() {
+ // [CPM1]: EVA CPM1
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ })
+
+ Name (AH1E, Package() {
+ // [CPM1]: EVA CPM1
+ Package() { 0x0000FFFF, 0, 0, 41 },
+ })
+
+ Name (PR1F, Package() {
+ // [CPM2]: EVA CPM2
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ })
+
+ Name (AR1F, Package() {
+ // [CPM2]: EVA CPM2
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ })
+
+ Name (AH1F, Package() {
+ // [CPM2]: EVA CPM2
+ Package() { 0x0000FFFF, 0, 0, 45 },
+ })
+
+ Name (PR20, Package() {
+ // [FPK0]: EVA Fort Park 0
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [FPK1]: EVA Fort Park 1
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ // [FPK2]: EVA Fort Park 2
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ // [FPK3]: EVA Fort Park 3
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR20, Package() {
+ // [FPK0]: EVA Fort Park 0
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ // [FPK1]: EVA Fort Park 1
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ // [FPK2]: EVA Fort Park 2
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ // [FPK3]: EVA Fort Park 3
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH20, Package() {
+ // [FPK0]: EVA Fort Park 0
+ Package() { 0x0000FFFF, 0, 0, 46 },
+ // [FPK1]: EVA Fort Park 1
+ Package() { 0x0000FFFF, 1, 0, 46 },
+ // [FPK2]: EVA Fort Park 2
+ Package() { 0x0000FFFF, 2, 0, 46 },
+ // [FPK3]: EVA Fort Park 3
+ Package() { 0x0000FFFF, 3, 0, 46 },
+ })
+
+ Name (PR21, Package() {
+ // [SL06]: PCI Express Slot 6 on 2B on PC02
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR21, Package() {
+ // [SL06]: PCI Express Slot 6 on 2B on PC02
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH21, Package() {
+ // [SL06]: PCI Express Slot 6 on 2B on PC02
+ Package() { 0x0000FFFF, 0, 0, 41 },
+ Package() { 0x0000FFFF, 1, 0, 46 },
+ Package() { 0x0000FFFF, 2, 0, 44 },
+ Package() { 0x0000FFFF, 3, 0, 45 },
+ })
+
+ Name (PR22, Package() {
+ // [SL07]: PCI Express Slot 7 on 2C on PC02
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR22, Package() {
+ // [SL07]: PCI Express Slot 7 on 2C on PC02
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH22, Package() {
+ // [SL07]: PCI Express Slot 7 on 2C on PC02
+ Package() { 0x0000FFFF, 0, 0, 42 },
+ Package() { 0x0000FFFF, 1, 0, 45 },
+ Package() { 0x0000FFFF, 2, 0, 46 },
+ Package() { 0x0000FFFF, 3, 0, 44 },
+ })
+
+ Name (PR23, Package() {
+ // [SL08]: PCI Express Slot 8 on 2D on PC02
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR23, Package() {
+ // [SL08]: PCI Express Slot 8 on 2D on PC02
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH23, Package() {
+ // [SL08]: PCI Express Slot 8 on 2D on PC02
+ Package() { 0x0000FFFF, 0, 0, 43 },
+ Package() { 0x0000FFFF, 1, 0, 46 },
+ Package() { 0x0000FFFF, 2, 0, 44 },
+ Package() { 0x0000FFFF, 3, 0, 45 },
+ })
+
+ Name (PR24, Package() {
+ // [BR3A]: PCI Express Port 3A on PC03
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [BR3B]: PCI Express Port 3B on PC03
+ Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [BR3C]: PCI Express Port 3C on PC03
+ Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [BR3D]: PCI Express Port 3D on PC03
+ Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [KTI0]: KTI0
+ Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [KTI1]: KTI1
+ Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [KTI2]: KTI2
+ Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [M3K0]: M3K0
+ Package() { 0x0012FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0012FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0012FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0012FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [M2U0]: M2U0
+ Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [M2D0]: M2D0
+ Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [M20]: M20
+ Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR24, Package() {
+ // [BR3A]: PCI Express Port 3A on PC03
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ // [BR3B]: PCI Express Port 3B on PC03
+ Package() { 0x0001FFFF, 0, 0, 16 },
+ // [BR3C]: PCI Express Port 3C on PC03
+ Package() { 0x0002FFFF, 0, 0, 16 },
+ // [BR3D]: PCI Express Port 3D on PC03
+ Package() { 0x0003FFFF, 0, 0, 16 },
+ // [KTI0]: KTI0
+ Package() { 0x000EFFFF, 0, 0, 16 },
+ Package() { 0x000EFFFF, 1, 0, 17 },
+ Package() { 0x000EFFFF, 2, 0, 18 },
+ Package() { 0x000EFFFF, 3, 0, 19 },
+ // [KTI1]: KTI1
+ Package() { 0x000FFFFF, 0, 0, 16 },
+ Package() { 0x000FFFFF, 1, 0, 17 },
+ Package() { 0x000FFFFF, 2, 0, 18 },
+ Package() { 0x000FFFFF, 3, 0, 19 },
+ // [KTI2]: KTI2
+ Package() { 0x0010FFFF, 0, 0, 16 },
+ Package() { 0x0010FFFF, 1, 0, 17 },
+ Package() { 0x0010FFFF, 2, 0, 18 },
+ Package() { 0x0010FFFF, 3, 0, 19 },
+ // [M3K0]: M3K0
+ Package() { 0x0012FFFF, 0, 0, 16 },
+ Package() { 0x0012FFFF, 1, 0, 17 },
+ Package() { 0x0012FFFF, 2, 0, 18 },
+ Package() { 0x0012FFFF, 3, 0, 19 },
+ // [M2U0]: M2U0
+ Package() { 0x0015FFFF, 0, 0, 16 },
+ Package() { 0x0015FFFF, 1, 0, 17 },
+ Package() { 0x0015FFFF, 2, 0, 18 },
+ Package() { 0x0015FFFF, 3, 0, 19 },
+ // [M2D0]: M2D0
+ Package() { 0x0016FFFF, 0, 0, 16 },
+ Package() { 0x0016FFFF, 1, 0, 17 },
+ Package() { 0x0016FFFF, 2, 0, 18 },
+ Package() { 0x0016FFFF, 3, 0, 19 },
+ // [M20]: M20
+ Package() { 0x0017FFFF, 0, 0, 16 },
+ Package() { 0x0017FFFF, 1, 0, 17 },
+ Package() { 0x0017FFFF, 2, 0, 18 },
+ Package() { 0x0017FFFF, 3, 0, 19 },
+ })
+
+ Name (AH24, Package() {
+ // [BR3A]: PCI Express Port 3A on PC03
+ Package() { 0x0000FFFF, 0, 0, 55 },
+ // [BR3B]: PCI Express Port 3B on PC03
+ Package() { 0x0001FFFF, 0, 0, 55 },
+ // [BR3C]: PCI Express Port 3C on PC03
+ Package() { 0x0002FFFF, 0, 0, 55 },
+ // [BR3D]: PCI Express Port 3D on PC03
+ Package() { 0x0003FFFF, 0, 0, 55 },
+ // [KTI0]: KTI0
+ Package() { 0x000EFFFF, 0, 0, 48 },
+ Package() { 0x000EFFFF, 1, 0, 52 },
+ Package() { 0x000EFFFF, 2, 0, 53 },
+ Package() { 0x000EFFFF, 3, 0, 54 },
+ // [KTI1]: KTI1
+ Package() { 0x000FFFFF, 0, 0, 48 },
+ Package() { 0x000FFFFF, 1, 0, 52 },
+ Package() { 0x000FFFFF, 2, 0, 53 },
+ Package() { 0x000FFFFF, 3, 0, 54 },
+ // [KTI2]: KTI2
+ Package() { 0x0010FFFF, 0, 0, 48 },
+ Package() { 0x0010FFFF, 1, 0, 52 },
+ Package() { 0x0010FFFF, 2, 0, 53 },
+ Package() { 0x0010FFFF, 3, 0, 54 },
+ // [M3K0]: M3K0
+ Package() { 0x0012FFFF, 0, 0, 48 },
+ Package() { 0x0012FFFF, 1, 0, 52 },
+ Package() { 0x0012FFFF, 2, 0, 53 },
+ Package() { 0x0012FFFF, 3, 0, 54 },
+ // [M2U0]: M2U0
+ Package() { 0x0015FFFF, 0, 0, 48 },
+ Package() { 0x0015FFFF, 1, 0, 52 },
+ Package() { 0x0015FFFF, 2, 0, 53 },
+ Package() { 0x0015FFFF, 3, 0, 54 },
+ // [M2D0]: M2D0
+ Package() { 0x0016FFFF, 0, 0, 48 },
+ Package() { 0x0016FFFF, 1, 0, 52 },
+ Package() { 0x0016FFFF, 2, 0, 53 },
+ Package() { 0x0016FFFF, 3, 0, 54 },
+ // [M20]: M20
+ Package() { 0x0017FFFF, 0, 0, 48 },
+ Package() { 0x0017FFFF, 1, 0, 52 },
+ Package() { 0x0017FFFF, 2, 0, 53 },
+ Package() { 0x0017FFFF, 3, 0, 54 },
+ })
+
+ Name (PR25, Package() {
+ // [SL09]: PCI Express Slot 9 on 3A on PC03
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR25, Package() {
+ // [SL09]: PCI Express Slot 9 on 3A on PC03
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH25, Package() {
+ // [SL09]: PCI Express Slot 9 on 3A on PC03
+ Package() { 0x0000FFFF, 0, 0, 48 },
+ Package() { 0x0000FFFF, 1, 0, 52 },
+ Package() { 0x0000FFFF, 2, 0, 53 },
+ Package() { 0x0000FFFF, 3, 0, 54 },
+ })
+
+ Name (PR26, Package() {
+ // [SL0A]: PCI Express Slot 10 on 3B on PC03
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR26, Package() {
+ // [SL0A]: PCI Express Slot 10 on 3B on PC03
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH26, Package() {
+ // [SL0A]: PCI Express Slot 10 on 3B on PC03
+ Package() { 0x0000FFFF, 0, 0, 49 },
+ Package() { 0x0000FFFF, 1, 0, 54 },
+ Package() { 0x0000FFFF, 2, 0, 52 },
+ Package() { 0x0000FFFF, 3, 0, 53 },
+ })
+
+ Name (PR27, Package() {
+ // [SL0B]: PCI Express Slot 11 on 3C on PC03
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR27, Package() {
+ // [SL0B]: PCI Express Slot 11 on 3C on PC03
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH27, Package() {
+ // [SL0B]: PCI Express Slot 11 on 3C on PC03
+ Package() { 0x0000FFFF, 0, 0, 50 },
+ Package() { 0x0000FFFF, 1, 0, 53 },
+ Package() { 0x0000FFFF, 2, 0, 54 },
+ Package() { 0x0000FFFF, 3, 0, 52 },
+ })
+
+ Name (PR28, Package() {
+ // [SL0C]: PCI Express Slot 12 on 3D on PC03
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR28, Package() {
+ // [SL0C]: PCI Express Slot 12 on 3D on PC03
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH28, Package() {
+ // [SL0C]: PCI Express Slot 12 on 3D on PC03
+ Package() { 0x0000FFFF, 0, 0, 51 },
+ Package() { 0x0000FFFF, 1, 0, 54 },
+ Package() { 0x0000FFFF, 2, 0, 52 },
+ Package() { 0x0000FFFF, 3, 0, 53 },
+ })
+
+ Name (PR29, Package() {
+ // [MCP0]: PCI Express Port 4 on PC04
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ })
+
+ Name (AR29, Package() {
+ // [MCP0]: PCI Express Port 4 on PC04
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ })
+
+ Name (AH29, Package() {
+ // [MCP0]: PCI Express Port 4 on PC04
+ Package() { 0x0000FFFF, 0, 0, 63 },
+ })
+
+ Name (PR2A, Package() {
+ // [SL0D]: PCI Express Slot 13 on 4 on PC04
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR2A, Package() {
+ // [SL0D]: PCI Express Slot 13 on 4 on PC04
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH2A, Package() {
+ // [SL0D]: PCI Express Slot 13 on 4 on PC04
+ Package() { 0x0000FFFF, 0, 0, 56 },
+ Package() { 0x0000FFFF, 1, 0, 60 },
+ Package() { 0x0000FFFF, 2, 0, 61 },
+ Package() { 0x0000FFFF, 3, 0, 62 },
+ })
+
+ Name (PR2B, Package() {
+ // [MCP1]: PCI Express Port 5 on PC05
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ })
+
+ Name (AR2B, Package() {
+ // [MCP1]: PCI Express Port 5 on PC05
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ })
+
+ Name (AH2B, Package() {
+ // [MCP1]: PCI Express Port 5 on PC05
+ Package() { 0x0000FFFF, 0, 0, 71 },
+ })
+
+ Name (PR2C, Package() {
+ // [SL0E]: PCI Express Slot 14 on 5 on PC05
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR2C, Package() {
+ // [SL0E]: PCI Express Slot 14 on 5 on PC05
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH2C, Package() {
+ // [SL0E]: PCI Express Slot 14 on 5 on PC05
+ Package() { 0x0000FFFF, 0, 0, 64 },
+ Package() { 0x0000FFFF, 1, 0, 68 },
+ Package() { 0x0000FFFF, 2, 0, 69 },
+ Package() { 0x0000FFFF, 3, 0, 70 },
+ })
+
+ Name (PR2D, Package() {
+ // [QRP0]: PCI Express Port 0 on PC06
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [CB1B]: CB3DMA on PC06
+ // [CB1F]: CB3DMA on PC06
+ Package() { 0x0004FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ // [CB1C]: CB3DMA on PC06
+ // [CB1G]: CB3DMA on PC06
+ Package() { 0x0004FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ // [CB1D]: CB3DMA on PC06
+ // [CB1H]: CB3DMA on PC06
+ Package() { 0x0004FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CB1E]: CB3DMA on PC06
+ // [CB1A]: CB3DMA on PC06
+ Package() { 0x0004FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [IIM1]: IIOMISC on PC01
+ Package() { 0x0005FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0005FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0005FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0005FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [UBX1]: Uncore 4 UBOX Device
+ Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR2D, Package() {
+ // [QRP0]: PCI Express Port 0 on PC06
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ // [CB1B]: CB3DMA on PC06
+ // [CB1F]: CB3DMA on PC06
+ Package() { 0x0004FFFF, 1, 0, 17 },
+ // [CB1C]: CB3DMA on PC06
+ // [CB1G]: CB3DMA on PC06
+ Package() { 0x0004FFFF, 2, 0, 18 },
+ // [CB1D]: CB3DMA on PC06
+ // [CB1H]: CB3DMA on PC06
+ Package() { 0x0004FFFF, 3, 0, 19 },
+ // [CB1E]: CB3DMA on PC06
+ // [CB1A]: CB3DMA on PC06
+ Package() { 0x0004FFFF, 0, 0, 16 },
+ // [IIM1]: IIOMISC on PC01
+ Package() { 0x0005FFFF, 0, 0, 16 },
+ Package() { 0x0005FFFF, 1, 0, 17 },
+ Package() { 0x0005FFFF, 2, 0, 18 },
+ Package() { 0x0005FFFF, 3, 0, 19 },
+ // [UBX1]: Uncore 4 UBOX Device
+ Package() { 0x0008FFFF, 0, 0, 16 },
+ Package() { 0x0008FFFF, 1, 0, 17 },
+ Package() { 0x0008FFFF, 2, 0, 18 },
+ Package() { 0x0008FFFF, 3, 0, 19 },
+ })
+
+ Name (AH2D, Package() {
+ // [QRP0]: PCI Express Port 0 on PC06
+ Package() { 0x0000FFFF, 0, 0, 79 },
+ // [CB1B]: CB3DMA on PC06
+ // [CB1F]: CB3DMA on PC06
+ Package() { 0x0004FFFF, 1, 0, 75 },
+ // [CB1C]: CB3DMA on PC06
+ // [CB1G]: CB3DMA on PC06
+ Package() { 0x0004FFFF, 2, 0, 74 },
+ // [CB1D]: CB3DMA on PC06
+ // [CB1H]: CB3DMA on PC06
+ Package() { 0x0004FFFF, 3, 0, 75 },
+ // [CB1E]: CB3DMA on PC06
+ // [CB1A]: CB3DMA on PC06
+ Package() { 0x0004FFFF, 0, 0, 74 },
+ // [IIM1]: IIOMISC on PC01
+ Package() { 0x0005FFFF, 0, 0, 16 },
+ Package() { 0x0005FFFF, 1, 0, 17 },
+ Package() { 0x0005FFFF, 2, 0, 18 },
+ Package() { 0x0005FFFF, 3, 0, 19 },
+ // [UBX1]: Uncore 4 UBOX Device
+ Package() { 0x0008FFFF, 0, 0, 72 },
+ Package() { 0x0008FFFF, 1, 0, 76 },
+ Package() { 0x0008FFFF, 2, 0, 77 },
+ Package() { 0x0008FFFF, 3, 0, 78 },
+ })
+
+ Name (PR2E, Package() {
+ // [SL0F]: PCI Express Slot 15 on P0 on PC06
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR2E, Package() {
+ // [SL0F]: PCI Express Slot 15 on P0 on PC06
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH2E, Package() {
+ // [SL0F]: PCI Express Slot 15 on P0 on PC06
+ Package() { 0x0000FFFF, 0, 0, 72 },
+ Package() { 0x0000FFFF, 1, 0, 76 },
+ Package() { 0x0000FFFF, 2, 0, 77 },
+ Package() { 0x0000FFFF, 3, 0, 78 },
+ })
+
+ Name (PR2F, Package() {
+ // [QR1A]: PCI Express Port 1A on PC07
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [QR1B]: PCI Express Port 1B on PC07
+ Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [QR1C]: PCI Express Port 1C on PC07
+ Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [QR1D]: PCI Express Port 1D on PC07
+ Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [CHB0]: Uncore 5 CHAUTIL0-7 Device
+ Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CHB1]: Uncore 5 CHAUTIL8-15 Device
+ Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CHB2]: Uncore 5 CHAUTIL16-23 Device
+ Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CHB3]: Uncore 5 CHAUTIL24-27 Device
+ Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CHB4]: Uncore 5 CHASAD0-7 Device
+ Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CHB5]: Uncore 5 CHASAD8-15 Device
+ Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CHB6]: Uncore 5 CHASAD16-23 Device
+ Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CHB7]: Uncore 5 CHASAD24-27 Device
+ Package() { 0x0011FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0011FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0011FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0011FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CMS4]: Uncore 5 CMSCHA0-7 Device
+ Package() { 0x0014FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0014FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0014FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0014FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CMS5]: Uncore 5 CMS0CHA8-15 Device
+ Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CMS6]: Uncore 5 CMS0CHA16-23 Device
+ Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CMS7]: Uncore 5 CMS0CHA24-27 Device
+ Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CDL1]: Uncore 5 CHASADALL Device
+ Package() { 0x001DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x001DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x001DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x001DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [PCU1]: Uncore 5 PCUCR Devices
+ Package() { 0x001EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x001EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x001EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x001EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [VCU1]: Uncore 5 VCUCR Device
+ Package() { 0x001FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x001FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x001FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x001FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR2F, Package() {
+ // [QR1A]: PCI Express Port 1A on PC07
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ // [QR1B]: PCI Express Port 1B on PC07
+ Package() { 0x0001FFFF, 0, 0, 16 },
+ // [QR1C]: PCI Express Port 1C on PC07
+ Package() { 0x0002FFFF, 0, 0, 16 },
+ // [QR1D]: PCI Express Port 1D on PC07
+ Package() { 0x0003FFFF, 0, 0, 16 },
+ // [CHB0]: Uncore 5 CHAUTIL0-7 Device
+ Package() { 0x0008FFFF, 0, 0, 16 },
+ Package() { 0x0008FFFF, 1, 0, 17 },
+ Package() { 0x0008FFFF, 2, 0, 18 },
+ Package() { 0x0008FFFF, 3, 0, 19 },
+ // [CHB1]: Uncore 5 CHAUTIL8-15 Device
+ Package() { 0x0009FFFF, 0, 0, 16 },
+ Package() { 0x0009FFFF, 1, 0, 17 },
+ Package() { 0x0009FFFF, 2, 0, 18 },
+ Package() { 0x0009FFFF, 3, 0, 19 },
+ // [CHB2]: Uncore 5 CHAUTIL16-23 Device
+ Package() { 0x000AFFFF, 0, 0, 16 },
+ Package() { 0x000AFFFF, 1, 0, 17 },
+ Package() { 0x000AFFFF, 2, 0, 18 },
+ Package() { 0x000AFFFF, 3, 0, 19 },
+ // [CHB3]: Uncore 5 CHAUTIL24-27 Device
+ Package() { 0x000BFFFF, 0, 0, 16 },
+ Package() { 0x000BFFFF, 1, 0, 17 },
+ Package() { 0x000BFFFF, 2, 0, 18 },
+ Package() { 0x000BFFFF, 3, 0, 19 },
+ // [CHB4]: Uncore 5 CHASAD0-7 Device
+ Package() { 0x000EFFFF, 0, 0, 16 },
+ Package() { 0x000EFFFF, 1, 0, 17 },
+ Package() { 0x000EFFFF, 2, 0, 18 },
+ Package() { 0x000EFFFF, 3, 0, 19 },
+ // [CHB5]: Uncore 5 CHASAD8-15 Device
+ Package() { 0x000FFFFF, 0, 0, 16 },
+ Package() { 0x000FFFFF, 1, 0, 17 },
+ Package() { 0x000FFFFF, 2, 0, 18 },
+ Package() { 0x000FFFFF, 3, 0, 19 },
+ // [CHB6]: Uncore 5 CHASAD16-23 Device
+ Package() { 0x0010FFFF, 0, 0, 16 },
+ Package() { 0x0010FFFF, 1, 0, 17 },
+ Package() { 0x0010FFFF, 2, 0, 18 },
+ Package() { 0x0010FFFF, 3, 0, 19 },
+ // [CHB7]: Uncore 5 CHASAD24-27 Device
+ Package() { 0x0011FFFF, 0, 0, 16 },
+ Package() { 0x0011FFFF, 1, 0, 17 },
+ Package() { 0x0011FFFF, 2, 0, 18 },
+ Package() { 0x0011FFFF, 3, 0, 19 },
+ // [CMS4]: Uncore 5 CMSCHA0-7 Device
+ Package() { 0x0014FFFF, 0, 0, 16 },
+ Package() { 0x0014FFFF, 1, 0, 17 },
+ Package() { 0x0014FFFF, 2, 0, 18 },
+ Package() { 0x0014FFFF, 3, 0, 19 },
+ // [CMS5]: Uncore 5 CMS0CHA8-15 Device
+ Package() { 0x0015FFFF, 0, 0, 16 },
+ Package() { 0x0015FFFF, 1, 0, 17 },
+ Package() { 0x0015FFFF, 2, 0, 18 },
+ Package() { 0x0015FFFF, 3, 0, 19 },
+ // [CMS6]: Uncore 5 CMS0CHA16-23 Device
+ Package() { 0x0016FFFF, 0, 0, 16 },
+ Package() { 0x0016FFFF, 1, 0, 17 },
+ Package() { 0x0016FFFF, 2, 0, 18 },
+ Package() { 0x0016FFFF, 3, 0, 19 },
+ // [CMS7]: Uncore 5 CMS0CHA24-27 Device
+ Package() { 0x0017FFFF, 0, 0, 16 },
+ Package() { 0x0017FFFF, 1, 0, 17 },
+ Package() { 0x0017FFFF, 2, 0, 18 },
+ Package() { 0x0017FFFF, 3, 0, 19 },
+ // [CDL1]: Uncore 5 CHASADALL Device
+ Package() { 0x001DFFFF, 0, 0, 16 },
+ Package() { 0x001DFFFF, 1, 0, 17 },
+ Package() { 0x001DFFFF, 2, 0, 18 },
+ Package() { 0x001DFFFF, 3, 0, 19 },
+ // [PCU1]: Uncore 5 PCUCR Devices
+ Package() { 0x001EFFFF, 0, 0, 16 },
+ Package() { 0x001EFFFF, 1, 0, 17 },
+ Package() { 0x001EFFFF, 2, 0, 18 },
+ Package() { 0x001EFFFF, 3, 0, 19 },
+ // [VCU1]: Uncore 5 VCUCR Device
+ Package() { 0x001FFFFF, 0, 0, 16 },
+ Package() { 0x001FFFFF, 1, 0, 17 },
+ Package() { 0x001FFFFF, 2, 0, 18 },
+ Package() { 0x001FFFFF, 3, 0, 19 },
+ })
+
+ Name (AH2F, Package() {
+ // [QR1A]: PCI Express Port 1A on PC07
+ Package() { 0x0000FFFF, 0, 0, 87 },
+ // [QR1B]: PCI Express Port 1B on PC07
+ Package() { 0x0001FFFF, 0, 0, 87 },
+ // [QR1C]: PCI Express Port 1C on PC07
+ Package() { 0x0002FFFF, 0, 0, 87 },
+ // [QR1D]: PCI Express Port 1D on PC07
+ Package() { 0x0003FFFF, 0, 0, 87 },
+ // [CHB0]: Uncore 5 CHAUTIL0-7 Device
+ Package() { 0x0008FFFF, 0, 0, 80 },
+ Package() { 0x0008FFFF, 1, 0, 84 },
+ Package() { 0x0008FFFF, 2, 0, 85 },
+ Package() { 0x0008FFFF, 3, 0, 86 },
+ // [CHB1]: Uncore 5 CHAUTIL8-15 Device
+ Package() { 0x0009FFFF, 0, 0, 80 },
+ Package() { 0x0009FFFF, 1, 0, 84 },
+ Package() { 0x0009FFFF, 2, 0, 85 },
+ Package() { 0x0009FFFF, 3, 0, 86 },
+ // [CHB2]: Uncore 5 CHAUTIL16-23 Device
+ Package() { 0x000AFFFF, 0, 0, 80 },
+ Package() { 0x000AFFFF, 1, 0, 84 },
+ Package() { 0x000AFFFF, 2, 0, 85 },
+ Package() { 0x000AFFFF, 3, 0, 86 },
+ // [CHB3]: Uncore 5 CHAUTIL24-27 Device
+ Package() { 0x000BFFFF, 0, 0, 80 },
+ Package() { 0x000BFFFF, 1, 0, 84 },
+ Package() { 0x000BFFFF, 2, 0, 85 },
+ Package() { 0x000BFFFF, 3, 0, 86 },
+ // [CHB4]: Uncore 5 CHASAD0-7 Device
+ Package() { 0x000EFFFF, 0, 0, 80 },
+ Package() { 0x000EFFFF, 1, 0, 84 },
+ Package() { 0x000EFFFF, 2, 0, 85 },
+ Package() { 0x000EFFFF, 3, 0, 86 },
+ // [CHB5]: Uncore 5 CHASAD8-15 Device
+ Package() { 0x000FFFFF, 0, 0, 80 },
+ Package() { 0x000FFFFF, 1, 0, 84 },
+ Package() { 0x000FFFFF, 2, 0, 85 },
+ Package() { 0x000FFFFF, 3, 0, 86 },
+ // [CHB6]: Uncore 5 CHASAD16-23 Device
+ Package() { 0x0010FFFF, 0, 0, 80 },
+ Package() { 0x0010FFFF, 1, 0, 84 },
+ Package() { 0x0010FFFF, 2, 0, 85 },
+ Package() { 0x0010FFFF, 3, 0, 86 },
+ // [CHB7]: Uncore 5 CHASAD24-27 Device
+ Package() { 0x0011FFFF, 0, 0, 80 },
+ Package() { 0x0011FFFF, 1, 0, 84 },
+ Package() { 0x0011FFFF, 2, 0, 85 },
+ Package() { 0x0011FFFF, 3, 0, 86 },
+ // [CMS4]: Uncore 5 CMSCHA0-7 Device
+ Package() { 0x0014FFFF, 0, 0, 80 },
+ Package() { 0x0014FFFF, 1, 0, 84 },
+ Package() { 0x0014FFFF, 2, 0, 85 },
+ Package() { 0x0014FFFF, 3, 0, 86 },
+ // [CMS5]: Uncore 5 CMS0CHA8-15 Device
+ Package() { 0x0015FFFF, 0, 0, 80 },
+ Package() { 0x0015FFFF, 1, 0, 84 },
+ Package() { 0x0015FFFF, 2, 0, 85 },
+ Package() { 0x0015FFFF, 3, 0, 86 },
+ // [CMS6]: Uncore 5 CMS0CHA16-23 Device
+ Package() { 0x0016FFFF, 0, 0, 80 },
+ Package() { 0x0016FFFF, 1, 0, 84 },
+ Package() { 0x0016FFFF, 2, 0, 85 },
+ Package() { 0x0016FFFF, 3, 0, 86 },
+ // [CMS7]: Uncore 5 CMS0CHA24-27 Device
+ Package() { 0x0017FFFF, 0, 0, 80 },
+ Package() { 0x0017FFFF, 1, 0, 84 },
+ Package() { 0x0017FFFF, 2, 0, 85 },
+ Package() { 0x0017FFFF, 3, 0, 86 },
+ // [CDL1]: Uncore 5 CHASADALL Device
+ Package() { 0x001DFFFF, 0, 0, 80 },
+ Package() { 0x001DFFFF, 1, 0, 84 },
+ Package() { 0x001DFFFF, 2, 0, 85 },
+ Package() { 0x001DFFFF, 3, 0, 86 },
+ // [PCU1]: Uncore 5 PCUCR Devices
+ Package() { 0x001EFFFF, 0, 0, 80 },
+ Package() { 0x001EFFFF, 1, 0, 84 },
+ Package() { 0x001EFFFF, 2, 0, 85 },
+ Package() { 0x001EFFFF, 3, 0, 86 },
+ // [VCU1]: Uncore 5 VCUCR Device
+ Package() { 0x001FFFFF, 0, 0, 80 },
+ Package() { 0x001FFFFF, 1, 0, 84 },
+ Package() { 0x001FFFFF, 2, 0, 85 },
+ Package() { 0x001FFFFF, 3, 0, 86 },
+ })
+
+ Name (PR30, Package() {
+ // [SL10]: PCI Express Slot 16 on 1A on PC07
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR30, Package() {
+ // [SL10]: PCI Express Slot 16 on 1A on PC07
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH30, Package() {
+ // [SL10]: PCI Express Slot 16 on 1A on PC07
+ Package() { 0x0000FFFF, 0, 0, 80 },
+ Package() { 0x0000FFFF, 1, 0, 84 },
+ Package() { 0x0000FFFF, 2, 0, 85 },
+ Package() { 0x0000FFFF, 3, 0, 86 },
+ })
+
+ Name (PR31, Package() {
+ // [SL11]: PCI Express Slot 17 on 1B on PC07
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR31, Package() {
+ // [SL11]: PCI Express Slot 17 on 1B on PC07
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH31, Package() {
+ // [SL11]: PCI Express Slot 17 on 1B on PC07
+ Package() { 0x0000FFFF, 0, 0, 81 },
+ Package() { 0x0000FFFF, 1, 0, 86 },
+ Package() { 0x0000FFFF, 2, 0, 84 },
+ Package() { 0x0000FFFF, 3, 0, 85 },
+ })
+
+ Name (PR32, Package() {
+ // [SL12]: PCI Express Slot 18 on 1C on PC07
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR32, Package() {
+ // [SL12]: PCI Express Slot 18 on 1C on PC07
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH32, Package() {
+ // [SL12]: PCI Express Slot 18 on 1C on PC07
+ Package() { 0x0000FFFF, 0, 0, 82 },
+ Package() { 0x0000FFFF, 1, 0, 85 },
+ Package() { 0x0000FFFF, 2, 0, 86 },
+ Package() { 0x0000FFFF, 3, 0, 84 },
+ })
+
+ Name (PR33, Package() {
+ // [SL13]: PCI Express Slot 19 on 1D on PC07
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR33, Package() {
+ // [SL13]: PCI Express Slot 19 on 1D on PC07
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH33, Package() {
+ // [SL13]: PCI Express Slot 19 on 1D on PC07
+ Package() { 0x0000FFFF, 0, 0, 83 },
+ Package() { 0x0000FFFF, 1, 0, 86 },
+ Package() { 0x0000FFFF, 2, 0, 84 },
+ Package() { 0x0000FFFF, 3, 0, 85 },
+ })
+
+ Name (PR34, Package() {
+ // [QR2A]: PCI Express Port 2A on PC08
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [QR2B]: PCI Express Port 2B on PC08
+ Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [QR2C]: PCI Express Port 2C on PC08
+ Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [QR2D]: PCI Express Port 2D on PC08
+ Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [M2M2]: Uncore 6 M2MEM0 Device
+ Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [M2M3]: Uncore 6 M2MEM10 Device
+ Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [MCM2]: Uncore 6 MCMAIN Device
+ Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [MCD2]: Uncore 6 MCDECS2 Device
+ Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [MCM3]: Uncore 6 MCMAIN Device
+ Package() { 0x000CFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000CFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000CFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000CFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [MCD3]: Uncore 6 MCDECS12 Device
+ Package() { 0x000DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [UMC2]: Uncore 6 Unicast MC0 DDRIO0 Device
+ Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [UMC3]: Uncore 6 Unicast MC1 DDRIO0 Device
+ Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR34, Package() {
+ // [QR2A]: PCI Express Port 2A on PC08
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ // [QR2B]: PCI Express Port 2B on PC08
+ Package() { 0x0001FFFF, 0, 0, 16 },
+ // [QR2C]: PCI Express Port 2C on PC08
+ Package() { 0x0002FFFF, 0, 0, 16 },
+ // [QR2D]: PCI Express Port 2D on PC08
+ Package() { 0x0003FFFF, 0, 0, 16 },
+ // [M2M2]: Uncore 6 M2MEM0 Device
+ Package() { 0x0008FFFF, 0, 0, 16 },
+ Package() { 0x0008FFFF, 1, 0, 17 },
+ Package() { 0x0008FFFF, 2, 0, 18 },
+ Package() { 0x0008FFFF, 3, 0, 19 },
+ // [M2M3]: Uncore 6 M2MEM10 Device
+ Package() { 0x0009FFFF, 0, 0, 16 },
+ Package() { 0x0009FFFF, 1, 0, 17 },
+ Package() { 0x0009FFFF, 2, 0, 18 },
+ Package() { 0x0009FFFF, 3, 0, 19 },
+ // [MCM2]: Uncore 6 MCMAIN Device
+ Package() { 0x000AFFFF, 0, 0, 16 },
+ Package() { 0x000AFFFF, 1, 0, 17 },
+ Package() { 0x000AFFFF, 2, 0, 18 },
+ Package() { 0x000AFFFF, 3, 0, 19 },
+ // [MCD2]: Uncore 6 MCDECS2 Device
+ Package() { 0x000BFFFF, 0, 0, 16 },
+ Package() { 0x000BFFFF, 1, 0, 17 },
+ Package() { 0x000BFFFF, 2, 0, 18 },
+ Package() { 0x000BFFFF, 3, 0, 19 },
+ // [MCM3]: Uncore 6 MCMAIN Device
+ Package() { 0x000CFFFF, 0, 0, 16 },
+ Package() { 0x000CFFFF, 1, 0, 17 },
+ Package() { 0x000CFFFF, 2, 0, 18 },
+ Package() { 0x000CFFFF, 3, 0, 19 },
+ // [MCD3]: Uncore 6 MCDECS12 Device
+ Package() { 0x000DFFFF, 0, 0, 16 },
+ Package() { 0x000DFFFF, 1, 0, 17 },
+ Package() { 0x000DFFFF, 2, 0, 18 },
+ Package() { 0x000DFFFF, 3, 0, 19 },
+ // [UMC2]: Uncore 6 Unicast MC0 DDRIO0 Device
+ Package() { 0x0016FFFF, 0, 0, 16 },
+ Package() { 0x0016FFFF, 1, 0, 17 },
+ Package() { 0x0016FFFF, 2, 0, 18 },
+ Package() { 0x0016FFFF, 3, 0, 19 },
+ // [UMC3]: Uncore 6 Unicast MC1 DDRIO0 Device
+ Package() { 0x0017FFFF, 0, 0, 16 },
+ Package() { 0x0017FFFF, 1, 0, 17 },
+ Package() { 0x0017FFFF, 2, 0, 18 },
+ Package() { 0x0017FFFF, 3, 0, 19 },
+ })
+
+ Name (AH34, Package() {
+ // [QR2A]: PCI Express Port 2A on PC08
+ Package() { 0x0000FFFF, 0, 0, 95 },
+ // [QR2B]: PCI Express Port 2B on PC08
+ Package() { 0x0001FFFF, 0, 0, 95 },
+ // [QR2C]: PCI Express Port 2C on PC08
+ Package() { 0x0002FFFF, 0, 0, 95 },
+ // [QR2D]: PCI Express Port 2D on PC08
+ Package() { 0x0003FFFF, 0, 0, 95 },
+ // [M2M2]: Uncore 6 M2MEM0 Device
+ Package() { 0x0008FFFF, 0, 0, 88 },
+ Package() { 0x0008FFFF, 1, 0, 92 },
+ Package() { 0x0008FFFF, 2, 0, 93 },
+ Package() { 0x0008FFFF, 3, 0, 94 },
+ // [M2M3]: Uncore 6 M2MEM10 Device
+ Package() { 0x0009FFFF, 0, 0, 88 },
+ Package() { 0x0009FFFF, 1, 0, 92 },
+ Package() { 0x0009FFFF, 2, 0, 93 },
+ Package() { 0x0009FFFF, 3, 0, 94 },
+ // [MCM2]: Uncore 6 MCMAIN Device
+ Package() { 0x000AFFFF, 0, 0, 88 },
+ Package() { 0x000AFFFF, 1, 0, 92 },
+ Package() { 0x000AFFFF, 2, 0, 93 },
+ Package() { 0x000AFFFF, 3, 0, 94 },
+ // [MCD2]: Uncore 6 MCDECS2 Device
+ Package() { 0x000BFFFF, 0, 0, 88 },
+ Package() { 0x000BFFFF, 1, 0, 92 },
+ Package() { 0x000BFFFF, 2, 0, 93 },
+ Package() { 0x000BFFFF, 3, 0, 94 },
+ // [MCM3]: Uncore 6 MCMAIN Device
+ Package() { 0x000CFFFF, 0, 0, 88 },
+ Package() { 0x000CFFFF, 1, 0, 92 },
+ Package() { 0x000CFFFF, 2, 0, 93 },
+ Package() { 0x000CFFFF, 3, 0, 94 },
+ // [MCD3]: Uncore 6 MCDECS12 Device
+ Package() { 0x000DFFFF, 0, 0, 88 },
+ Package() { 0x000DFFFF, 1, 0, 92 },
+ Package() { 0x000DFFFF, 2, 0, 93 },
+ Package() { 0x000DFFFF, 3, 0, 94 },
+ // [UMC2]: Uncore 6 Unicast MC0 DDRIO0 Device
+ Package() { 0x0016FFFF, 0, 0, 88 },
+ Package() { 0x0016FFFF, 1, 0, 92 },
+ Package() { 0x0016FFFF, 2, 0, 93 },
+ Package() { 0x0016FFFF, 3, 0, 94 },
+ // [UMC3]: Uncore 6 Unicast MC1 DDRIO0 Device
+ Package() { 0x0017FFFF, 0, 0, 88 },
+ Package() { 0x0017FFFF, 1, 0, 92 },
+ Package() { 0x0017FFFF, 2, 0, 93 },
+ Package() { 0x0017FFFF, 3, 0, 94 },
+ })
+
+ Name (PR35, Package() {
+ // [SL14]: PCI Express Slot 20 on 2A on PC08
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR35, Package() {
+ // [SL14]: PCI Express Slot 20 on 2A on PC08
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH35, Package() {
+ // [SL14]: PCI Express Slot 20 on 2A on PC08
+ Package() { 0x0000FFFF, 0, 0, 88 },
+ Package() { 0x0000FFFF, 1, 0, 92 },
+ Package() { 0x0000FFFF, 2, 0, 93 },
+ Package() { 0x0000FFFF, 3, 0, 94 },
+ })
+
+ Name (PR36, Package() {
+ // [SL15]: PCI Express Slot 21 on 2B on PC08
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR36, Package() {
+ // [SL15]: PCI Express Slot 21 on 2B on PC08
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH36, Package() {
+ // [SL15]: PCI Express Slot 21 on 2B on PC08
+ Package() { 0x0000FFFF, 0, 0, 89 },
+ Package() { 0x0000FFFF, 1, 0, 94 },
+ Package() { 0x0000FFFF, 2, 0, 92 },
+ Package() { 0x0000FFFF, 3, 0, 93 },
+ })
+
+ Name (PR37, Package() {
+ // [SL16]: PCI Express Slot 22 on 2C on PC08
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR37, Package() {
+ // [SL16]: PCI Express Slot 22 on 2C on PC08
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH37, Package() {
+ // [SL16]: PCI Express Slot 22 on 2C on PC08
+ Package() { 0x0000FFFF, 0, 0, 90 },
+ Package() { 0x0000FFFF, 1, 0, 93 },
+ Package() { 0x0000FFFF, 2, 0, 94 },
+ Package() { 0x0000FFFF, 3, 0, 92 },
+ })
+
+ Name (PR38, Package() {
+ // [SL17]: PCI Express Slot 23 on 2D on PC08
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR38, Package() {
+ // [SL17]: PCI Express Slot 23 on 2D on PC08
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH38, Package() {
+ // [SL17]: PCI Express Slot 23 on 2D on PC08
+ Package() { 0x0000FFFF, 0, 0, 91 },
+ Package() { 0x0000FFFF, 1, 0, 94 },
+ Package() { 0x0000FFFF, 2, 0, 92 },
+ Package() { 0x0000FFFF, 3, 0, 93 },
+ })
+
+ Name (PR39, Package() {
+ // [QR3A]: PCI Express Port 3A on PC09
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [QR3B]: PCI Express Port 3B on PC09
+ Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [QR3C]: PCI Express Port 3C on PC09
+ Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [QR3D]: PCI Express Port 3D on PC09
+ Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [KTI3]: Uncore 7 KTI3
+ Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [KTI4]: Uncore 7 KTI4
+ Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [KTI5]: Uncore 7 KTI5
+ Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [M3K1]: Uncore 7 M3K1
+ Package() { 0x0012FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0012FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0012FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0012FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [M2U1]: Uncore 7 M2U1
+ Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [M2D1]: Uncore 7 M2D1
+ Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [M21]: Uncore 7 M21
+ Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR39, Package() {
+ // [QR3A]: PCI Express Port 3A on PC09
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ // [QR3B]: PCI Express Port 3B on PC09
+ Package() { 0x0001FFFF, 0, 0, 16 },
+ // [QR3C]: PCI Express Port 3C on PC09
+ Package() { 0x0002FFFF, 0, 0, 16 },
+ // [QR3D]: PCI Express Port 3D on PC09
+ Package() { 0x0003FFFF, 0, 0, 16 },
+ // [KTI3]: Uncore 7 KTI3
+ Package() { 0x000EFFFF, 0, 0, 16 },
+ Package() { 0x000EFFFF, 1, 0, 17 },
+ Package() { 0x000EFFFF, 2, 0, 18 },
+ Package() { 0x000EFFFF, 3, 0, 19 },
+ // [KTI4]: Uncore 7 KTI4
+ Package() { 0x000FFFFF, 0, 0, 16 },
+ Package() { 0x000FFFFF, 1, 0, 17 },
+ Package() { 0x000FFFFF, 2, 0, 18 },
+ Package() { 0x000FFFFF, 3, 0, 19 },
+ // [KTI5]: Uncore 7 KTI5
+ Package() { 0x0010FFFF, 0, 0, 16 },
+ Package() { 0x0010FFFF, 1, 0, 17 },
+ Package() { 0x0010FFFF, 2, 0, 18 },
+ Package() { 0x0010FFFF, 3, 0, 19 },
+ // [M3K1]: Uncore 7 M3K1
+ Package() { 0x0012FFFF, 0, 0, 16 },
+ Package() { 0x0012FFFF, 1, 0, 17 },
+ Package() { 0x0012FFFF, 2, 0, 18 },
+ Package() { 0x0012FFFF, 3, 0, 19 },
+ // [M2U1]: Uncore 7 M2U1
+ Package() { 0x0015FFFF, 0, 0, 16 },
+ Package() { 0x0015FFFF, 1, 0, 17 },
+ Package() { 0x0015FFFF, 2, 0, 18 },
+ Package() { 0x0015FFFF, 3, 0, 19 },
+ // [M2D1]: Uncore 7 M2D1
+ Package() { 0x0016FFFF, 0, 0, 16 },
+ Package() { 0x0016FFFF, 1, 0, 17 },
+ Package() { 0x0016FFFF, 2, 0, 18 },
+ Package() { 0x0016FFFF, 3, 0, 19 },
+ // [M21]: Uncore 7 M21
+ Package() { 0x0017FFFF, 0, 0, 16 },
+ Package() { 0x0017FFFF, 1, 0, 17 },
+ Package() { 0x0017FFFF, 2, 0, 18 },
+ Package() { 0x0017FFFF, 3, 0, 19 },
+ })
+
+ Name (AH39, Package() {
+ // [QR3A]: PCI Express Port 3A on PC09
+ Package() { 0x0000FFFF, 0, 0, 103 },
+ // [QR3B]: PCI Express Port 3B on PC09
+ Package() { 0x0001FFFF, 0, 0, 103 },
+ // [QR3C]: PCI Express Port 3C on PC09
+ Package() { 0x0002FFFF, 0, 0, 103 },
+ // [QR3D]: PCI Express Port 3D on PC09
+ Package() { 0x0003FFFF, 0, 0, 103 },
+ // [KTI3]: Uncore 7 KTI3
+ Package() { 0x000EFFFF, 0, 0, 96 },
+ Package() { 0x000EFFFF, 1, 0, 100 },
+ Package() { 0x000EFFFF, 2, 0, 101 },
+ Package() { 0x000EFFFF, 3, 0, 102 },
+ // [KTI4]: Uncore 7 KTI4
+ Package() { 0x000FFFFF, 0, 0, 96 },
+ Package() { 0x000FFFFF, 1, 0, 100 },
+ Package() { 0x000FFFFF, 2, 0, 101 },
+ Package() { 0x000FFFFF, 3, 0, 102 },
+ // [KTI5]: Uncore 7 KTI5
+ Package() { 0x0010FFFF, 0, 0, 96 },
+ Package() { 0x0010FFFF, 1, 0, 100 },
+ Package() { 0x0010FFFF, 2, 0, 101 },
+ Package() { 0x0010FFFF, 3, 0, 102 },
+ // [M3K1]: Uncore 7 M3K1
+ Package() { 0x0012FFFF, 0, 0, 96 },
+ Package() { 0x0012FFFF, 1, 0, 100 },
+ Package() { 0x0012FFFF, 2, 0, 101 },
+ Package() { 0x0012FFFF, 3, 0, 102 },
+ // [M2U1]: Uncore 7 M2U1
+ Package() { 0x0015FFFF, 0, 0, 96 },
+ Package() { 0x0015FFFF, 1, 0, 100 },
+ Package() { 0x0015FFFF, 2, 0, 101 },
+ Package() { 0x0015FFFF, 3, 0, 102 },
+ // [M2D1]: Uncore 7 M2D1
+ Package() { 0x0016FFFF, 0, 0, 96 },
+ Package() { 0x0016FFFF, 1, 0, 100 },
+ Package() { 0x0016FFFF, 2, 0, 101 },
+ Package() { 0x0016FFFF, 3, 0, 102 },
+ // [M21]: Uncore 7 M21
+ Package() { 0x0017FFFF, 0, 0, 96 },
+ Package() { 0x0017FFFF, 1, 0, 100 },
+ Package() { 0x0017FFFF, 2, 0, 101 },
+ Package() { 0x0017FFFF, 3, 0, 102 },
+ })
+
+ Name (PR3A, Package() {
+ // [SL18]: PCI Express Slot 24 on 3A on PC09
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR3A, Package() {
+ // [SL18]: PCI Express Slot 24 on 3A on PC09
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH3A, Package() {
+ // [SL18]: PCI Express Slot 24 on 3A on PC09
+ Package() { 0x0000FFFF, 0, 0, 96 },
+ Package() { 0x0000FFFF, 1, 0, 100 },
+ Package() { 0x0000FFFF, 2, 0, 101 },
+ Package() { 0x0000FFFF, 3, 0, 102 },
+ })
+
+ Name (PR3B, Package() {
+ // [SL19]: PCI Express Slot 25 on 3B on PC09
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR3B, Package() {
+ // [SL19]: PCI Express Slot 25 on 3B on PC09
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH3B, Package() {
+ // [SL19]: PCI Express Slot 25 on 3B on PC09
+ Package() { 0x0000FFFF, 0, 0, 97 },
+ Package() { 0x0000FFFF, 1, 0, 102 },
+ Package() { 0x0000FFFF, 2, 0, 100 },
+ Package() { 0x0000FFFF, 3, 0, 101 },
+ })
+
+ Name (PR3C, Package() {
+ // [SL1A]: PCI Express Slot 26 on 3C on PC09
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR3C, Package() {
+ // [SL1A]: PCI Express Slot 26 on 3C on PC09
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH3C, Package() {
+ // [SL1A]: PCI Express Slot 26 on 3C on PC09
+ Package() { 0x0000FFFF, 0, 0, 98 },
+ Package() { 0x0000FFFF, 1, 0, 101 },
+ Package() { 0x0000FFFF, 2, 0, 102 },
+ Package() { 0x0000FFFF, 3, 0, 100 },
+ })
+
+ Name (PR3D, Package() {
+ // [SL1B]: PCI Express Slot 27 on 3D on PC09
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR3D, Package() {
+ // [SL1B]: PCI Express Slot 27 on 3D on PC09
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH3D, Package() {
+ // [SL1B]: PCI Express Slot 27 on 3D on PC09
+ Package() { 0x0000FFFF, 0, 0, 99 },
+ Package() { 0x0000FFFF, 1, 0, 102 },
+ Package() { 0x0000FFFF, 2, 0, 100 },
+ Package() { 0x0000FFFF, 3, 0, 101 },
+ })
+
+ Name (PR3E, Package() {
+ // [MCP2]: PCI Express Port 13 on PC10
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ })
+
+ Name (AR3E, Package() {
+ // [MCP2]: PCI Express Port 13 on PC10
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ })
+
+ Name (AH3E, Package() {
+ // [MCP2]: PCI Express Port 13 on PC10
+ Package() { 0x0000FFFF, 0, 0, 111 },
+ })
+
+ Name (PR3F, Package() {
+ // [SL1C]: PCI Express Slot 28 on 4 on PC10
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR3F, Package() {
+ // [SL1C]: PCI Express Slot 28 on 4 on PC10
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH3F, Package() {
+ // [SL1C]: PCI Express Slot 28 on 4 on PC10
+ Package() { 0x0000FFFF, 0, 0, 104 },
+ Package() { 0x0000FFFF, 1, 0, 108 },
+ Package() { 0x0000FFFF, 2, 0, 109 },
+ Package() { 0x0000FFFF, 3, 0, 110 },
+ })
+
+ Name (PR40, Package() {
+ // [MCP3]: PCI Express Port 14 on PC11
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ })
+
+ Name (AR40, Package() {
+ // [MCP3]: PCI Express Port 14 on PC11
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ })
+
+ Name (AH40, Package() {
+ // [MCP3]: PCI Express Port 14 on PC11
+ Package() { 0x0000FFFF, 0, 0, 119 },
+ })
+
+ Name (PR41, Package() {
+ // [SL1D]: PCI Express Slot 29 on 5 on PC11
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR41, Package() {
+ // [SL1D]: PCI Express Slot 29 on 5 on PC11
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH41, Package() {
+ // [SL1D]: PCI Express Slot 29 on 5 on PC11
+ Package() { 0x0000FFFF, 0, 0, 112 },
+ Package() { 0x0000FFFF, 1, 0, 116 },
+ Package() { 0x0000FFFF, 2, 0, 117 },
+ Package() { 0x0000FFFF, 3, 0, 118 },
+ })
+
+ Name (PR42, Package() {
+ // [RRP0]: PCI Express Port 0 on PC12
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [CB2B]: CB3DMA on PC12
+ // [CB2F]: CB3DMA on PC12
+ Package() { 0x0004FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ // [CB2C]: CB3DMA on PC12
+ // [CB2G]: CB3DMA on PC12
+ Package() { 0x0004FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ // [CB2D]: CB3DMA on PC12
+ // [CB2H]: CB3DMA on PC12
+ Package() { 0x0004FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CB2E]: CB3DMA on PC12
+ // [CB2A]: CB3DMA on PC12
+ Package() { 0x0004FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [IIM2]: IIOMISC on PC02
+ Package() { 0x0005FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0005FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0005FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0005FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [UBX2]: Uncore 8 UBOX Device
+ Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR42, Package() {
+ // [RRP0]: PCI Express Port 0 on PC12
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ // [CB2B]: CB3DMA on PC12
+ // [CB2F]: CB3DMA on PC12
+ Package() { 0x0004FFFF, 1, 0, 17 },
+ // [CB2C]: CB3DMA on PC12
+ // [CB2G]: CB3DMA on PC12
+ Package() { 0x0004FFFF, 2, 0, 18 },
+ // [CB2D]: CB3DMA on PC12
+ // [CB2H]: CB3DMA on PC12
+ Package() { 0x0004FFFF, 3, 0, 19 },
+ // [CB2E]: CB3DMA on PC12
+ // [CB2A]: CB3DMA on PC12
+ Package() { 0x0004FFFF, 0, 0, 16 },
+ // [IIM2]: IIOMISC on PC02
+ Package() { 0x0005FFFF, 0, 0, 16 },
+ Package() { 0x0005FFFF, 1, 0, 17 },
+ Package() { 0x0005FFFF, 2, 0, 18 },
+ Package() { 0x0005FFFF, 3, 0, 19 },
+ // [UBX2]: Uncore 8 UBOX Device
+ Package() { 0x0008FFFF, 0, 0, 16 },
+ Package() { 0x0008FFFF, 1, 0, 17 },
+ Package() { 0x0008FFFF, 2, 0, 18 },
+ Package() { 0x0008FFFF, 3, 0, 19 },
+ })
+
+ Name (AH42, Package() {
+ // [RRP0]: PCI Express Port 0 on PC12
+ Package() { 0x0000FFFF, 0, 0, 127 },
+ // [CB2B]: CB3DMA on PC12
+ // [CB2F]: CB3DMA on PC12
+ Package() { 0x0004FFFF, 1, 0, 123 },
+ // [CB2C]: CB3DMA on PC12
+ // [CB2G]: CB3DMA on PC12
+ Package() { 0x0004FFFF, 2, 0, 122 },
+ // [CB2D]: CB3DMA on PC12
+ // [CB2H]: CB3DMA on PC12
+ Package() { 0x0004FFFF, 3, 0, 123 },
+ // [CB2E]: CB3DMA on PC12
+ // [CB2A]: CB3DMA on PC12
+ Package() { 0x0004FFFF, 0, 0, 122 },
+ // [IIM2]: IIOMISC on PC02
+ Package() { 0x0005FFFF, 0, 0, 16 },
+ Package() { 0x0005FFFF, 1, 0, 17 },
+ Package() { 0x0005FFFF, 2, 0, 18 },
+ Package() { 0x0005FFFF, 3, 0, 19 },
+ // [UBX2]: Uncore 8 UBOX Device
+ Package() { 0x0008FFFF, 0, 0, 120 },
+ Package() { 0x0008FFFF, 1, 0, 124 },
+ Package() { 0x0008FFFF, 2, 0, 125 },
+ Package() { 0x0008FFFF, 3, 0, 126 },
+ })
+
+ Name (PR43, Package() {
+ // [SL1E]: PCI Express Slot 30 on P0 on PC12
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR43, Package() {
+ // [SL1E]: PCI Express Slot 30 on P0 on PC12
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH43, Package() {
+ // [SL1E]: PCI Express Slot 30 on P0 on PC12
+ Package() { 0x0000FFFF, 0, 0, 120 },
+ Package() { 0x0000FFFF, 1, 0, 124 },
+ Package() { 0x0000FFFF, 2, 0, 125 },
+ Package() { 0x0000FFFF, 3, 0, 126 },
+ })
+
+ Name (PR44, Package() {
+ // [RR1A]: PCI Express Port 1A on PC13
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [RR1B]: PCI Express Port 1B on PC13
+ Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [RR1C]: PCI Express Port 1C on PC13
+ Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [RR1D]: PCI Express Port 1D on PC13
+ Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [CHC0]: Uncore 9 CHAUTIL0-7 Device
+ Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CHC1]: Uncore 9 CHAUTIL8-15 Device
+ Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CHC2]: Uncore 9 CHAUTIL16-23 Device
+ Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CHC3]: Uncore 9 CHAUTIL24-27 Device
+ Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CHC4]: Uncore 9 CHASAD0-7 Device
+ Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CHC5]: Uncore 9 CHASAD8-15 Device
+ Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CHC6]: Uncore 9 CHASAD16-23 Device
+ Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CHC7]: Uncore 9 CHASAD24-27 Device
+ Package() { 0x0011FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0011FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0011FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0011FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CMS8]: Uncore 9 CMSCHA0-7 Device
+ Package() { 0x0014FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0014FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0014FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0014FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CMS9]: Uncore 9 CMS0CHA8-15 Device
+ Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CDL2]: Uncore 9 CHASADALL Device
+ Package() { 0x001DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x001DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x001DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x001DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [PCU2]: Uncore 9 PCUCR Devices
+ Package() { 0x001EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x001EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x001EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x001EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [VCU2]: Uncore 9 VCUCR Device
+ Package() { 0x001FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x001FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x001FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x001FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR44, Package() {
+ // [RR1A]: PCI Express Port 1A on PC13
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ // [RR1B]: PCI Express Port 1B on PC13
+ Package() { 0x0001FFFF, 0, 0, 16 },
+ // [RR1C]: PCI Express Port 1C on PC13
+ Package() { 0x0002FFFF, 0, 0, 16 },
+ // [RR1D]: PCI Express Port 1D on PC13
+ Package() { 0x0003FFFF, 0, 0, 16 },
+ // [CHC0]: Uncore 9 CHAUTIL0-7 Device
+ Package() { 0x0008FFFF, 0, 0, 16 },
+ Package() { 0x0008FFFF, 1, 0, 17 },
+ Package() { 0x0008FFFF, 2, 0, 18 },
+ Package() { 0x0008FFFF, 3, 0, 19 },
+ // [CHC1]: Uncore 9 CHAUTIL8-15 Device
+ Package() { 0x0009FFFF, 0, 0, 16 },
+ Package() { 0x0009FFFF, 1, 0, 17 },
+ Package() { 0x0009FFFF, 2, 0, 18 },
+ Package() { 0x0009FFFF, 3, 0, 19 },
+ // [CHC2]: Uncore 9 CHAUTIL16-23 Device
+ Package() { 0x000AFFFF, 0, 0, 16 },
+ Package() { 0x000AFFFF, 1, 0, 17 },
+ Package() { 0x000AFFFF, 2, 0, 18 },
+ Package() { 0x000AFFFF, 3, 0, 19 },
+ // [CHC3]: Uncore 9 CHAUTIL24-27 Device
+ Package() { 0x000BFFFF, 0, 0, 16 },
+ Package() { 0x000BFFFF, 1, 0, 17 },
+ Package() { 0x000BFFFF, 2, 0, 18 },
+ Package() { 0x000BFFFF, 3, 0, 19 },
+ // [CHC4]: Uncore 9 CHASAD0-7 Device
+ Package() { 0x000EFFFF, 0, 0, 16 },
+ Package() { 0x000EFFFF, 1, 0, 17 },
+ Package() { 0x000EFFFF, 2, 0, 18 },
+ Package() { 0x000EFFFF, 3, 0, 19 },
+ // [CHC5]: Uncore 9 CHASAD8-15 Device
+ Package() { 0x000FFFFF, 0, 0, 16 },
+ Package() { 0x000FFFFF, 1, 0, 17 },
+ Package() { 0x000FFFFF, 2, 0, 18 },
+ Package() { 0x000FFFFF, 3, 0, 19 },
+ // [CHC6]: Uncore 9 CHASAD16-23 Device
+ Package() { 0x0010FFFF, 0, 0, 16 },
+ Package() { 0x0010FFFF, 1, 0, 17 },
+ Package() { 0x0010FFFF, 2, 0, 18 },
+ Package() { 0x0010FFFF, 3, 0, 19 },
+ // [CHC7]: Uncore 9 CHASAD24-27 Device
+ Package() { 0x0011FFFF, 0, 0, 16 },
+ Package() { 0x0011FFFF, 1, 0, 17 },
+ Package() { 0x0011FFFF, 2, 0, 18 },
+ Package() { 0x0011FFFF, 3, 0, 19 },
+ // [CMS8]: Uncore 9 CMSCHA0-7 Device
+ Package() { 0x0014FFFF, 0, 0, 16 },
+ Package() { 0x0014FFFF, 1, 0, 17 },
+ Package() { 0x0014FFFF, 2, 0, 18 },
+ Package() { 0x0014FFFF, 3, 0, 19 },
+ // [CMS9]: Uncore 9 CMS0CHA8-15 Device
+ Package() { 0x0015FFFF, 0, 0, 16 },
+ Package() { 0x0015FFFF, 1, 0, 17 },
+ Package() { 0x0015FFFF, 2, 0, 18 },
+ Package() { 0x0015FFFF, 3, 0, 19 },
+ // [CDL2]: Uncore 9 CHASADALL Device
+ Package() { 0x001DFFFF, 0, 0, 16 },
+ Package() { 0x001DFFFF, 1, 0, 17 },
+ Package() { 0x001DFFFF, 2, 0, 18 },
+ Package() { 0x001DFFFF, 3, 0, 19 },
+ // [PCU2]: Uncore 9 PCUCR Devices
+ Package() { 0x001EFFFF, 0, 0, 16 },
+ Package() { 0x001EFFFF, 1, 0, 17 },
+ Package() { 0x001EFFFF, 2, 0, 18 },
+ Package() { 0x001EFFFF, 3, 0, 19 },
+ // [VCU2]: Uncore 9 VCUCR Device
+ Package() { 0x001FFFFF, 0, 0, 16 },
+ Package() { 0x001FFFFF, 1, 0, 17 },
+ Package() { 0x001FFFFF, 2, 0, 18 },
+ Package() { 0x001FFFFF, 3, 0, 19 },
+ })
+
+ Name (AH44, Package() {
+ // [RR1A]: PCI Express Port 1A on PC13
+ Package() { 0x0000FFFF, 0, 0, 135 },
+ // [RR1B]: PCI Express Port 1B on PC13
+ Package() { 0x0001FFFF, 0, 0, 135 },
+ // [RR1C]: PCI Express Port 1C on PC13
+ Package() { 0x0002FFFF, 0, 0, 135 },
+ // [RR1D]: PCI Express Port 1D on PC13
+ Package() { 0x0003FFFF, 0, 0, 135 },
+ // [CHC0]: Uncore 9 CHAUTIL0-7 Device
+ Package() { 0x0008FFFF, 0, 0, 128 },
+ Package() { 0x0008FFFF, 1, 0, 132 },
+ Package() { 0x0008FFFF, 2, 0, 133 },
+ Package() { 0x0008FFFF, 3, 0, 134 },
+ // [CHC1]: Uncore 9 CHAUTIL8-15 Device
+ Package() { 0x0009FFFF, 0, 0, 128 },
+ Package() { 0x0009FFFF, 1, 0, 132 },
+ Package() { 0x0009FFFF, 2, 0, 133 },
+ Package() { 0x0009FFFF, 3, 0, 134 },
+ // [CHC2]: Uncore 9 CHAUTIL16-23 Device
+ Package() { 0x000AFFFF, 0, 0, 128 },
+ Package() { 0x000AFFFF, 1, 0, 132 },
+ Package() { 0x000AFFFF, 2, 0, 133 },
+ Package() { 0x000AFFFF, 3, 0, 134 },
+ // [CHC3]: Uncore 9 CHAUTIL24-27 Device
+ Package() { 0x000BFFFF, 0, 0, 128 },
+ Package() { 0x000BFFFF, 1, 0, 132 },
+ Package() { 0x000BFFFF, 2, 0, 133 },
+ Package() { 0x000BFFFF, 3, 0, 134 },
+ // [CHC4]: Uncore 9 CHASAD0-7 Device
+ Package() { 0x000EFFFF, 0, 0, 128 },
+ Package() { 0x000EFFFF, 1, 0, 132 },
+ Package() { 0x000EFFFF, 2, 0, 133 },
+ Package() { 0x000EFFFF, 3, 0, 134 },
+ // [CHC5]: Uncore 9 CHASAD8-15 Device
+ Package() { 0x000FFFFF, 0, 0, 128 },
+ Package() { 0x000FFFFF, 1, 0, 132 },
+ Package() { 0x000FFFFF, 2, 0, 133 },
+ Package() { 0x000FFFFF, 3, 0, 134 },
+ // [CHC6]: Uncore 9 CHASAD16-23 Device
+ Package() { 0x0010FFFF, 0, 0, 128 },
+ Package() { 0x0010FFFF, 1, 0, 132 },
+ Package() { 0x0010FFFF, 2, 0, 133 },
+ Package() { 0x0010FFFF, 3, 0, 134 },
+ // [CHC7]: Uncore 9 CHASAD24-27 Device
+ Package() { 0x0011FFFF, 0, 0, 128 },
+ Package() { 0x0011FFFF, 1, 0, 132 },
+ Package() { 0x0011FFFF, 2, 0, 133 },
+ Package() { 0x0011FFFF, 3, 0, 134 },
+ // [CMS8]: Uncore 9 CMSCHA0-7 Device
+ Package() { 0x0014FFFF, 0, 0, 128 },
+ Package() { 0x0014FFFF, 1, 0, 132 },
+ Package() { 0x0014FFFF, 2, 0, 133 },
+ Package() { 0x0014FFFF, 3, 0, 134 },
+ // [CMS9]: Uncore 9 CMS0CHA8-15 Device
+ Package() { 0x0015FFFF, 0, 0, 128 },
+ Package() { 0x0015FFFF, 1, 0, 132 },
+ Package() { 0x0015FFFF, 2, 0, 133 },
+ Package() { 0x0015FFFF, 3, 0, 134 },
+ // [CDL2]: Uncore 9 CHASADALL Device
+ Package() { 0x001DFFFF, 0, 0, 128 },
+ Package() { 0x001DFFFF, 1, 0, 132 },
+ Package() { 0x001DFFFF, 2, 0, 133 },
+ Package() { 0x001DFFFF, 3, 0, 134 },
+ // [PCU2]: Uncore 9 PCUCR Devices
+ Package() { 0x001EFFFF, 0, 0, 128 },
+ Package() { 0x001EFFFF, 1, 0, 132 },
+ Package() { 0x001EFFFF, 2, 0, 133 },
+ Package() { 0x001EFFFF, 3, 0, 134 },
+ // [VCU2]: Uncore 9 VCUCR Device
+ Package() { 0x001FFFFF, 0, 0, 128 },
+ Package() { 0x001FFFFF, 1, 0, 132 },
+ Package() { 0x001FFFFF, 2, 0, 133 },
+ Package() { 0x001FFFFF, 3, 0, 134 },
+ })
+
+ Name (PR45, Package() {
+ // [SL1F]: PCI Express Slot 31 on 1A on PC13
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR45, Package() {
+ // [SL1F]: PCI Express Slot 31 on 1A on PC13
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH45, Package() {
+ // [SL1F]: PCI Express Slot 31 on 1A on PC13
+ Package() { 0x0000FFFF, 0, 0, 128 },
+ Package() { 0x0000FFFF, 1, 0, 132 },
+ Package() { 0x0000FFFF, 2, 0, 133 },
+ Package() { 0x0000FFFF, 3, 0, 134 },
+ })
+
+ Name (PR46, Package() {
+ // [SL20]: PCI Express Slot 32 on 1B on PC13
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR46, Package() {
+ // [SL20]: PCI Express Slot 32 on 1B on PC13
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH46, Package() {
+ // [SL20]: PCI Express Slot 32 on 1B on PC13
+ Package() { 0x0000FFFF, 0, 0, 129 },
+ Package() { 0x0000FFFF, 1, 0, 134 },
+ Package() { 0x0000FFFF, 2, 0, 132 },
+ Package() { 0x0000FFFF, 3, 0, 133 },
+ })
+
+ Name (PR47, Package() {
+ // [SL21]: PCI Express Slot 33 on 1C on PC13
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR47, Package() {
+ // [SL21]: PCI Express Slot 33 on 1C on PC13
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH47, Package() {
+ // [SL21]: PCI Express Slot 33 on 1C on PC13
+ Package() { 0x0000FFFF, 0, 0, 130 },
+ Package() { 0x0000FFFF, 1, 0, 133 },
+ Package() { 0x0000FFFF, 2, 0, 134 },
+ Package() { 0x0000FFFF, 3, 0, 132 },
+ })
+
+ Name (PR48, Package() {
+ // [SL22]: PCI Express Slot 34 on 1D on PC13
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR48, Package() {
+ // [SL22]: PCI Express Slot 34 on 1D on PC13
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH48, Package() {
+ // [SL22]: PCI Express Slot 34 on 1D on PC13
+ Package() { 0x0000FFFF, 0, 0, 131 },
+ Package() { 0x0000FFFF, 1, 0, 134 },
+ Package() { 0x0000FFFF, 2, 0, 132 },
+ Package() { 0x0000FFFF, 3, 0, 133 },
+ })
+
+ Name (PR49, Package() {
+ // [RR2A]: PCI Express Port 2A on PC14
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [RR2B]: PCI Express Port 2B on PC14
+ Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [RR2C]: PCI Express Port 2C on PC14
+ Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [RR2D]: PCI Express Port 2D on PC14
+ Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [M2M4]: Uncore 10 M2MEM0 Device
+ Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [M2M5]: Uncore 10 M2MEM10 Device
+ Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [MCM4]: Uncore 10 MCMAIN Device
+ Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [MCD4]: Uncore 10 MCDECS2 Device
+ Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [MCM5]: Uncore 10 MCMAIN Device
+ Package() { 0x000CFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000CFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000CFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000CFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [MCD5]: Uncore 10 MCDECS12 Device
+ Package() { 0x000DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [UMC4]: Uncore 10 Unicast MC0 DDRIO0 Device
+ Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [UMC5]: Uncore 10 Unicast MC1 DDRIO0 Device
+ Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR49, Package() {
+ // [RR2A]: PCI Express Port 2A on PC14
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ // [RR2B]: PCI Express Port 2B on PC14
+ Package() { 0x0001FFFF, 0, 0, 16 },
+ // [RR2C]: PCI Express Port 2C on PC14
+ Package() { 0x0002FFFF, 0, 0, 16 },
+ // [RR2D]: PCI Express Port 2D on PC14
+ Package() { 0x0003FFFF, 0, 0, 16 },
+ // [M2M4]: Uncore 10 M2MEM0 Device
+ Package() { 0x0008FFFF, 0, 0, 16 },
+ Package() { 0x0008FFFF, 1, 0, 17 },
+ Package() { 0x0008FFFF, 2, 0, 18 },
+ Package() { 0x0008FFFF, 3, 0, 19 },
+ // [M2M5]: Uncore 10 M2MEM10 Device
+ Package() { 0x0009FFFF, 0, 0, 16 },
+ Package() { 0x0009FFFF, 1, 0, 17 },
+ Package() { 0x0009FFFF, 2, 0, 18 },
+ Package() { 0x0009FFFF, 3, 0, 19 },
+ // [MCM4]: Uncore 10 MCMAIN Device
+ Package() { 0x000AFFFF, 0, 0, 16 },
+ Package() { 0x000AFFFF, 1, 0, 17 },
+ Package() { 0x000AFFFF, 2, 0, 18 },
+ Package() { 0x000AFFFF, 3, 0, 19 },
+ // [MCD4]: Uncore 10 MCDECS2 Device
+ Package() { 0x000BFFFF, 0, 0, 16 },
+ Package() { 0x000BFFFF, 1, 0, 17 },
+ Package() { 0x000BFFFF, 2, 0, 18 },
+ Package() { 0x000BFFFF, 3, 0, 19 },
+ // [MCM5]: Uncore 10 MCMAIN Device
+ Package() { 0x000CFFFF, 0, 0, 16 },
+ Package() { 0x000CFFFF, 1, 0, 17 },
+ Package() { 0x000CFFFF, 2, 0, 18 },
+ Package() { 0x000CFFFF, 3, 0, 19 },
+ // [MCD5]: Uncore 10 MCDECS12 Device
+ Package() { 0x000DFFFF, 0, 0, 16 },
+ Package() { 0x000DFFFF, 1, 0, 17 },
+ Package() { 0x000DFFFF, 2, 0, 18 },
+ Package() { 0x000DFFFF, 3, 0, 19 },
+ // [UMC4]: Uncore 10 Unicast MC0 DDRIO0 Device
+ Package() { 0x0016FFFF, 0, 0, 16 },
+ Package() { 0x0016FFFF, 1, 0, 17 },
+ Package() { 0x0016FFFF, 2, 0, 18 },
+ Package() { 0x0016FFFF, 3, 0, 19 },
+ // [UMC5]: Uncore 10 Unicast MC1 DDRIO0 Device
+ Package() { 0x0017FFFF, 0, 0, 16 },
+ Package() { 0x0017FFFF, 1, 0, 17 },
+ Package() { 0x0017FFFF, 2, 0, 18 },
+ Package() { 0x0017FFFF, 3, 0, 19 },
+ })
+
+ Name (AH49, Package() {
+ // [RR2A]: PCI Express Port 2A on PC14
+ Package() { 0x0000FFFF, 0, 0, 143 },
+ // [RR2B]: PCI Express Port 2B on PC14
+ Package() { 0x0001FFFF, 0, 0, 143 },
+ // [RR2C]: PCI Express Port 2C on PC14
+ Package() { 0x0002FFFF, 0, 0, 143 },
+ // [RR2D]: PCI Express Port 2D on PC14
+ Package() { 0x0003FFFF, 0, 0, 143 },
+ // [M2M4]: Uncore 10 M2MEM0 Device
+ Package() { 0x0008FFFF, 0, 0, 136 },
+ Package() { 0x0008FFFF, 1, 0, 140 },
+ Package() { 0x0008FFFF, 2, 0, 141 },
+ Package() { 0x0008FFFF, 3, 0, 142 },
+ // [M2M5]: Uncore 10 M2MEM10 Device
+ Package() { 0x0009FFFF, 0, 0, 136 },
+ Package() { 0x0009FFFF, 1, 0, 140 },
+ Package() { 0x0009FFFF, 2, 0, 141 },
+ Package() { 0x0009FFFF, 3, 0, 142 },
+ // [MCM4]: Uncore 10 MCMAIN Device
+ Package() { 0x000AFFFF, 0, 0, 136 },
+ Package() { 0x000AFFFF, 1, 0, 140 },
+ Package() { 0x000AFFFF, 2, 0, 141 },
+ Package() { 0x000AFFFF, 3, 0, 142 },
+ // [MCD4]: Uncore 10 MCDECS2 Device
+ Package() { 0x000BFFFF, 0, 0, 136 },
+ Package() { 0x000BFFFF, 1, 0, 140 },
+ Package() { 0x000BFFFF, 2, 0, 141 },
+ Package() { 0x000BFFFF, 3, 0, 142 },
+ // [MCM5]: Uncore 10 MCMAIN Device
+ Package() { 0x000CFFFF, 0, 0, 136 },
+ Package() { 0x000CFFFF, 1, 0, 140 },
+ Package() { 0x000CFFFF, 2, 0, 141 },
+ Package() { 0x000CFFFF, 3, 0, 142 },
+ // [MCD5]: Uncore 10 MCDECS12 Device
+ Package() { 0x000DFFFF, 0, 0, 136 },
+ Package() { 0x000DFFFF, 1, 0, 140 },
+ Package() { 0x000DFFFF, 2, 0, 141 },
+ Package() { 0x000DFFFF, 3, 0, 142 },
+ // [UMC4]: Uncore 10 Unicast MC0 DDRIO0 Device
+ Package() { 0x0016FFFF, 0, 0, 136 },
+ Package() { 0x0016FFFF, 1, 0, 140 },
+ Package() { 0x0016FFFF, 2, 0, 141 },
+ Package() { 0x0016FFFF, 3, 0, 142 },
+ // [UMC5]: Uncore 10 Unicast MC1 DDRIO0 Device
+ Package() { 0x0017FFFF, 0, 0, 136 },
+ Package() { 0x0017FFFF, 1, 0, 140 },
+ Package() { 0x0017FFFF, 2, 0, 141 },
+ Package() { 0x0017FFFF, 3, 0, 142 },
+ })
+
+ Name (PR4A, Package() {
+ // [SL23]: PCI Express Slot 35 on 2A on PC14
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR4A, Package() {
+ // [SL23]: PCI Express Slot 35 on 2A on PC14
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH4A, Package() {
+ // [SL23]: PCI Express Slot 35 on 2A on PC14
+ Package() { 0x0000FFFF, 0, 0, 136 },
+ Package() { 0x0000FFFF, 1, 0, 140 },
+ Package() { 0x0000FFFF, 2, 0, 141 },
+ Package() { 0x0000FFFF, 3, 0, 142 },
+ })
+
+ Name (PR4B, Package() {
+ // [SL24]: PCI Express Slot 36 on 2B on PC14
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR4B, Package() {
+ // [SL24]: PCI Express Slot 36 on 2B on PC14
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH4B, Package() {
+ // [SL24]: PCI Express Slot 36 on 2B on PC14
+ Package() { 0x0000FFFF, 0, 0, 137 },
+ Package() { 0x0000FFFF, 1, 0, 142 },
+ Package() { 0x0000FFFF, 2, 0, 140 },
+ Package() { 0x0000FFFF, 3, 0, 141 },
+ })
+
+ Name (PR4C, Package() {
+ // [SL25]: PCI Express Slot 37 on 2C on PC14
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR4C, Package() {
+ // [SL25]: PCI Express Slot 37 on 2C on PC14
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH4C, Package() {
+ // [SL25]: PCI Express Slot 37 on 2C on PC14
+ Package() { 0x0000FFFF, 0, 0, 138 },
+ Package() { 0x0000FFFF, 1, 0, 141 },
+ Package() { 0x0000FFFF, 2, 0, 142 },
+ Package() { 0x0000FFFF, 3, 0, 140 },
+ })
+
+ Name (PR4D, Package() {
+ // [SL26]: PCI Express Slot 38 on 2D on PC14
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR4D, Package() {
+ // [SL26]: PCI Express Slot 38 on 2D on PC14
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH4D, Package() {
+ // [SL26]: PCI Express Slot 38 on 2D on PC14
+ Package() { 0x0000FFFF, 0, 0, 139 },
+ Package() { 0x0000FFFF, 1, 0, 142 },
+ Package() { 0x0000FFFF, 2, 0, 140 },
+ Package() { 0x0000FFFF, 3, 0, 141 },
+ })
+
+ Name (PR4E, Package() {
+ // [RR3A]: PCI Express Port 3A on PC15
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [RR3B]: PCI Express Port 3B on PC15
+ Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [RR3C]: PCI Express Port 3C on PC15
+ Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [RR3D]: PCI Express Port 3D on PC15
+ Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [KTI6]: Uncore 11 KTI6
+ Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [KTI7]: Uncore 11 KTI7
+ Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [KTI8]: Uncore 11 KTI8
+ Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [M3K2]: Uncore 11 M3K2
+ Package() { 0x0012FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0012FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0012FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0012FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [M2U2]: Uncore 11 M2U2
+ Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [M2D2]: Uncore 11 M2D2
+ Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [M22]: Uncore 11 M22
+ Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR4E, Package() {
+ // [RR3A]: PCI Express Port 3A on PC15
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ // [RR3B]: PCI Express Port 3B on PC15
+ Package() { 0x0001FFFF, 0, 0, 16 },
+ // [RR3C]: PCI Express Port 3C on PC15
+ Package() { 0x0002FFFF, 0, 0, 16 },
+ // [RR3D]: PCI Express Port 3D on PC15
+ Package() { 0x0003FFFF, 0, 0, 16 },
+ // [KTI6]: Uncore 11 KTI6
+ Package() { 0x000EFFFF, 0, 0, 16 },
+ Package() { 0x000EFFFF, 1, 0, 17 },
+ Package() { 0x000EFFFF, 2, 0, 18 },
+ Package() { 0x000EFFFF, 3, 0, 19 },
+ // [KTI7]: Uncore 11 KTI7
+ Package() { 0x000FFFFF, 0, 0, 16 },
+ Package() { 0x000FFFFF, 1, 0, 17 },
+ Package() { 0x000FFFFF, 2, 0, 18 },
+ Package() { 0x000FFFFF, 3, 0, 19 },
+ // [KTI8]: Uncore 11 KTI8
+ Package() { 0x0010FFFF, 0, 0, 16 },
+ Package() { 0x0010FFFF, 1, 0, 17 },
+ Package() { 0x0010FFFF, 2, 0, 18 },
+ Package() { 0x0010FFFF, 3, 0, 19 },
+ // [M3K2]: Uncore 11 M3K2
+ Package() { 0x0012FFFF, 0, 0, 16 },
+ Package() { 0x0012FFFF, 1, 0, 17 },
+ Package() { 0x0012FFFF, 2, 0, 18 },
+ Package() { 0x0012FFFF, 3, 0, 19 },
+ // [M2U2]: Uncore 11 M2U2
+ Package() { 0x0015FFFF, 0, 0, 16 },
+ Package() { 0x0015FFFF, 1, 0, 17 },
+ Package() { 0x0015FFFF, 2, 0, 18 },
+ Package() { 0x0015FFFF, 3, 0, 19 },
+ // [M2D2]: Uncore 11 M2D2
+ Package() { 0x0016FFFF, 0, 0, 16 },
+ Package() { 0x0016FFFF, 1, 0, 17 },
+ Package() { 0x0016FFFF, 2, 0, 18 },
+ Package() { 0x0016FFFF, 3, 0, 19 },
+ // [M22]: Uncore 11 M22
+ Package() { 0x0017FFFF, 0, 0, 16 },
+ Package() { 0x0017FFFF, 1, 0, 17 },
+ Package() { 0x0017FFFF, 2, 0, 18 },
+ Package() { 0x0017FFFF, 3, 0, 19 },
+ })
+
+ Name (AH4E, Package() {
+ // [RR3A]: PCI Express Port 3A on PC15
+ Package() { 0x0000FFFF, 0, 0, 151 },
+ // [RR3B]: PCI Express Port 3B on PC15
+ Package() { 0x0001FFFF, 0, 0, 151 },
+ // [RR3C]: PCI Express Port 3C on PC15
+ Package() { 0x0002FFFF, 0, 0, 151 },
+ // [RR3D]: PCI Express Port 3D on PC15
+ Package() { 0x0003FFFF, 0, 0, 151 },
+ // [KTI6]: Uncore 11 KTI6
+ Package() { 0x000EFFFF, 0, 0, 144 },
+ Package() { 0x000EFFFF, 1, 0, 148 },
+ Package() { 0x000EFFFF, 2, 0, 149 },
+ Package() { 0x000EFFFF, 3, 0, 150 },
+ // [KTI7]: Uncore 11 KTI7
+ Package() { 0x000FFFFF, 0, 0, 144 },
+ Package() { 0x000FFFFF, 1, 0, 148 },
+ Package() { 0x000FFFFF, 2, 0, 149 },
+ Package() { 0x000FFFFF, 3, 0, 150 },
+ // [KTI8]: Uncore 11 KTI8
+ Package() { 0x0010FFFF, 0, 0, 144 },
+ Package() { 0x0010FFFF, 1, 0, 148 },
+ Package() { 0x0010FFFF, 2, 0, 149 },
+ Package() { 0x0010FFFF, 3, 0, 150 },
+ // [M3K2]: Uncore 11 M3K2
+ Package() { 0x0012FFFF, 0, 0, 144 },
+ Package() { 0x0012FFFF, 1, 0, 148 },
+ Package() { 0x0012FFFF, 2, 0, 149 },
+ Package() { 0x0012FFFF, 3, 0, 150 },
+ // [M2U2]: Uncore 11 M2U2
+ Package() { 0x0015FFFF, 0, 0, 144 },
+ Package() { 0x0015FFFF, 1, 0, 148 },
+ Package() { 0x0015FFFF, 2, 0, 149 },
+ Package() { 0x0015FFFF, 3, 0, 150 },
+ // [M2D2]: Uncore 11 M2D2
+ Package() { 0x0016FFFF, 0, 0, 144 },
+ Package() { 0x0016FFFF, 1, 0, 148 },
+ Package() { 0x0016FFFF, 2, 0, 149 },
+ Package() { 0x0016FFFF, 3, 0, 150 },
+ // [M22]: Uncore 11 M22
+ Package() { 0x0017FFFF, 0, 0, 144 },
+ Package() { 0x0017FFFF, 1, 0, 148 },
+ Package() { 0x0017FFFF, 2, 0, 149 },
+ Package() { 0x0017FFFF, 3, 0, 150 },
+ })
+
+ Name (PR4F, Package() {
+ // [SL27]: PCI Express Slot 39 on 3A on PC15
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR4F, Package() {
+ // [SL27]: PCI Express Slot 39 on 3A on PC15
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH4F, Package() {
+ // [SL27]: PCI Express Slot 39 on 3A on PC15
+ Package() { 0x0000FFFF, 0, 0, 144 },
+ Package() { 0x0000FFFF, 1, 0, 148 },
+ Package() { 0x0000FFFF, 2, 0, 149 },
+ Package() { 0x0000FFFF, 3, 0, 150 },
+ })
+
+ Name (PR50, Package() {
+ // [SL28]: PCI Express Slot 40 on 3B on PC15
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR50, Package() {
+ // [SL28]: PCI Express Slot 40 on 3B on PC15
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH50, Package() {
+ // [SL28]: PCI Express Slot 40 on 3B on PC15
+ Package() { 0x0000FFFF, 0, 0, 145 },
+ Package() { 0x0000FFFF, 1, 0, 150 },
+ Package() { 0x0000FFFF, 2, 0, 148 },
+ Package() { 0x0000FFFF, 3, 0, 149 },
+ })
+
+ Name (PR51, Package() {
+ // [SL29]: PCI Express Slot 41 on 3C on PC15
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR51, Package() {
+ // [SL29]: PCI Express Slot 41 on 3C on PC15
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH51, Package() {
+ // [SL29]: PCI Express Slot 41 on 3C on PC15
+ Package() { 0x0000FFFF, 0, 0, 146 },
+ Package() { 0x0000FFFF, 1, 0, 149 },
+ Package() { 0x0000FFFF, 2, 0, 150 },
+ Package() { 0x0000FFFF, 3, 0, 148 },
+ })
+
+ Name (PR52, Package() {
+ // [SL2A]: PCI Express Slot 42 on 3D on PC15
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR52, Package() {
+ // [SL2A]: PCI Express Slot 42 on 3D on PC15
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH52, Package() {
+ // [SL2A]: PCI Express Slot 42 on 3D on PC15
+ Package() { 0x0000FFFF, 0, 0, 147 },
+ Package() { 0x0000FFFF, 1, 0, 150 },
+ Package() { 0x0000FFFF, 2, 0, 148 },
+ Package() { 0x0000FFFF, 3, 0, 149 },
+ })
+
+ Name (PR53, Package() {
+ // [MCP4]: PCI Express Port 4 on PC16
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ })
+
+ Name (AR53, Package() {
+ // [MCP4]: PCI Express Port 4 on PC16
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ })
+
+ Name (AH53, Package() {
+ // [MCP4]: PCI Express Port 4 on PC16
+ Package() { 0x0000FFFF, 0, 0, 159 },
+ })
+
+ Name (PR54, Package() {
+ // [SL2B]: PCI Express Slot 43 on 4 on PC16
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR54, Package() {
+ // [SL2B]: PCI Express Slot 43 on 4 on PC16
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH54, Package() {
+ // [SL2B]: PCI Express Slot 43 on 4 on PC16
+ Package() { 0x0000FFFF, 0, 0, 152 },
+ Package() { 0x0000FFFF, 1, 0, 156 },
+ Package() { 0x0000FFFF, 2, 0, 157 },
+ Package() { 0x0000FFFF, 3, 0, 158 },
+ })
+
+ Name (PR55, Package() {
+ // [MCP5]: PCI Express Port 5 on PC17
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ })
+
+ Name (AR55, Package() {
+ // [MCP5]: PCI Express Port 5 on PC17
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ })
+
+ Name (AH55, Package() {
+ // [MCP5]: PCI Express Port 5 on PC17
+ Package() { 0x0000FFFF, 0, 0, 167 },
+ })
+
+ Name (PR56, Package() {
+ // [SL2C]: PCI Express Slot 44 on 4 on PC17
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR56, Package() {
+ // [SL2C]: PCI Express Slot 44 on 4 on PC17
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH56, Package() {
+ // [SL2C]: PCI Express Slot 44 on 4 on PC17
+ Package() { 0x0000FFFF, 0, 0, 160 },
+ Package() { 0x0000FFFF, 1, 0, 164 },
+ Package() { 0x0000FFFF, 2, 0, 165 },
+ Package() { 0x0000FFFF, 3, 0, 166 },
+ })
+
+ Name (PR57, Package() {
+ // [SRP0]: PCI Express Port 0 on PC18
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [CB3B]: CB3DMA on PC18
+ // [CB3F]: CB3DMA on PC18
+ Package() { 0x0004FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ // [CB3C]: CB3DMA on PC18
+ // [CB3G]: CB3DMA on PC18
+ Package() { 0x0004FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ // [CB3D]: CB3DMA on PC18
+ // [CB3H]: CB3DMA on PC18
+ Package() { 0x0004FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CB3E]: CB3DMA on PC18
+ // [CB3A]: CB3DMA on PC18
+ Package() { 0x0004FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [IIM3]: IIOMISC on PC03
+ Package() { 0x0005FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0005FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0005FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0005FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [UBX3]: Uncore 12 UBOX Device
+ Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR57, Package() {
+ // [SRP0]: PCI Express Port 0 on PC18
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ // [CB3B]: CB3DMA on PC18
+ // [CB3F]: CB3DMA on PC18
+ Package() { 0x0004FFFF, 1, 0, 17 },
+ // [CB3C]: CB3DMA on PC18
+ // [CB3G]: CB3DMA on PC18
+ Package() { 0x0004FFFF, 2, 0, 18 },
+ // [CB3D]: CB3DMA on PC18
+ // [CB3H]: CB3DMA on PC18
+ Package() { 0x0004FFFF, 3, 0, 19 },
+ // [CB3E]: CB3DMA on PC18
+ // [CB3A]: CB3DMA on PC18
+ Package() { 0x0004FFFF, 0, 0, 16 },
+ // [IIM3]: IIOMISC on PC03
+ Package() { 0x0005FFFF, 0, 0, 16 },
+ Package() { 0x0005FFFF, 1, 0, 17 },
+ Package() { 0x0005FFFF, 2, 0, 18 },
+ Package() { 0x0005FFFF, 3, 0, 19 },
+ // [UBX3]: Uncore 12 UBOX Device
+ Package() { 0x0008FFFF, 0, 0, 16 },
+ Package() { 0x0008FFFF, 1, 0, 17 },
+ Package() { 0x0008FFFF, 2, 0, 18 },
+ Package() { 0x0008FFFF, 3, 0, 19 },
+ })
+
+ Name (AH57, Package() {
+ // [SRP0]: PCI Express Port 0 on PC18
+ Package() { 0x0000FFFF, 0, 0, 175 },
+ // [CB3B]: CB3DMA on PC18
+ // [CB3F]: CB3DMA on PC18
+ Package() { 0x0004FFFF, 1, 0, 171 },
+ // [CB3C]: CB3DMA on PC18
+ // [CB3G]: CB3DMA on PC18
+ Package() { 0x0004FFFF, 2, 0, 170 },
+ // [CB3D]: CB3DMA on PC18
+ // [CB3H]: CB3DMA on PC18
+ Package() { 0x0004FFFF, 3, 0, 171 },
+ // [CB3E]: CB3DMA on PC18
+ // [CB3A]: CB3DMA on PC18
+ Package() { 0x0004FFFF, 0, 0, 170 },
+ // [IIM3]: IIOMISC on PC03
+ Package() { 0x0005FFFF, 0, 0, 16 },
+ Package() { 0x0005FFFF, 1, 0, 17 },
+ Package() { 0x0005FFFF, 2, 0, 18 },
+ Package() { 0x0005FFFF, 3, 0, 19 },
+ // [UBX3]: Uncore 12 UBOX Device
+ Package() { 0x0008FFFF, 0, 0, 168 },
+ Package() { 0x0008FFFF, 1, 0, 172 },
+ Package() { 0x0008FFFF, 2, 0, 173 },
+ Package() { 0x0008FFFF, 3, 0, 174 },
+ })
+
+ Name (PR58, Package() {
+ // [SL2D]: PCI Express Slot 45 on P0 on PC18
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR58, Package() {
+ // [SL2D]: PCI Express Slot 45 on P0 on PC18
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH58, Package() {
+ // [SL2D]: PCI Express Slot 45 on P0 on PC18
+ Package() { 0x0000FFFF, 0, 0, 168 },
+ Package() { 0x0000FFFF, 1, 0, 172 },
+ Package() { 0x0000FFFF, 2, 0, 173 },
+ Package() { 0x0000FFFF, 3, 0, 174 },
+ })
+
+ Name (PR59, Package() {
+ // [SR1A]: PCI Express Port 1A on PC19
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [SR1B]: PCI Express Port 1B on PC19
+ Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [SR1C]: PCI Express Port 1C on PC19
+ Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [SR1D]: PCI Express Port 1D on PC19
+ Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [CHD0]: Uncore 13 CHAUTIL0-7 Device
+ Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CHD1]: Uncore 13 CHAUTIL8-15 Device
+ Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CHD2]: Uncore 13 CHAUTIL16-23 Device
+ Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CHD3]: Uncore 13 CHAUTIL24-27 Device
+ Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CHD4]: Uncore 13 CHASAD0-7 Device
+ Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CHD5]: Uncore 13 CHASAD8-15 Device
+ Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CHD6]: Uncore 13 CHASAD16-23 Device
+ Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CHD7]: Uncore 13 CHASAD24-27 Device
+ Package() { 0x0011FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0011FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0011FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0011FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CM12]: Uncore 13 CMSCHA0-7 Device
+ Package() { 0x0014FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0014FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0014FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0014FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CM13]: Uncore 13 CMS0CHA8-15 Device
+ Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CM14]: Uncore 13 CMS0CHA16-23 Device
+ Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CM15]: Uncore 13 CMS0CHA24-27 Device
+ Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [CDL3]: Uncore 13 CHASADALL Device
+ Package() { 0x001DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x001DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x001DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x001DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [PCU3]: Uncore 13 PCUCR Devices
+ Package() { 0x001EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x001EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x001EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x001EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [VCU3]: Uncore 13 VCUCR Device
+ Package() { 0x001FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x001FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x001FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x001FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR59, Package() {
+ // [SR1A]: PCI Express Port 1A on PC19
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ // [SR1B]: PCI Express Port 1B on PC19
+ Package() { 0x0001FFFF, 0, 0, 16 },
+ // [SR1C]: PCI Express Port 1C on PC19
+ Package() { 0x0002FFFF, 0, 0, 16 },
+ // [SR1D]: PCI Express Port 1D on PC19
+ Package() { 0x0003FFFF, 0, 0, 16 },
+ // [CHD0]: Uncore 13 CHAUTIL0-7 Device
+ Package() { 0x0008FFFF, 0, 0, 16 },
+ Package() { 0x0008FFFF, 1, 0, 17 },
+ Package() { 0x0008FFFF, 2, 0, 18 },
+ Package() { 0x0008FFFF, 3, 0, 19 },
+ // [CHD1]: Uncore 13 CHAUTIL8-15 Device
+ Package() { 0x0009FFFF, 0, 0, 16 },
+ Package() { 0x0009FFFF, 1, 0, 17 },
+ Package() { 0x0009FFFF, 2, 0, 18 },
+ Package() { 0x0009FFFF, 3, 0, 19 },
+ // [CHD2]: Uncore 13 CHAUTIL16-23 Device
+ Package() { 0x000AFFFF, 0, 0, 16 },
+ Package() { 0x000AFFFF, 1, 0, 17 },
+ Package() { 0x000AFFFF, 2, 0, 18 },
+ Package() { 0x000AFFFF, 3, 0, 19 },
+ // [CHD3]: Uncore 13 CHAUTIL24-27 Device
+ Package() { 0x000BFFFF, 0, 0, 16 },
+ Package() { 0x000BFFFF, 1, 0, 17 },
+ Package() { 0x000BFFFF, 2, 0, 18 },
+ Package() { 0x000BFFFF, 3, 0, 19 },
+ // [CHD4]: Uncore 13 CHASAD0-7 Device
+ Package() { 0x000EFFFF, 0, 0, 16 },
+ Package() { 0x000EFFFF, 1, 0, 17 },
+ Package() { 0x000EFFFF, 2, 0, 18 },
+ Package() { 0x000EFFFF, 3, 0, 19 },
+ // [CHD5]: Uncore 13 CHASAD8-15 Device
+ Package() { 0x000FFFFF, 0, 0, 16 },
+ Package() { 0x000FFFFF, 1, 0, 17 },
+ Package() { 0x000FFFFF, 2, 0, 18 },
+ Package() { 0x000FFFFF, 3, 0, 19 },
+ // [CHD6]: Uncore 13 CHASAD16-23 Device
+ Package() { 0x0010FFFF, 0, 0, 16 },
+ Package() { 0x0010FFFF, 1, 0, 17 },
+ Package() { 0x0010FFFF, 2, 0, 18 },
+ Package() { 0x0010FFFF, 3, 0, 19 },
+ // [CHD7]: Uncore 13 CHASAD24-27 Device
+ Package() { 0x0011FFFF, 0, 0, 16 },
+ Package() { 0x0011FFFF, 1, 0, 17 },
+ Package() { 0x0011FFFF, 2, 0, 18 },
+ Package() { 0x0011FFFF, 3, 0, 19 },
+ // [CM12]: Uncore 13 CMSCHA0-7 Device
+ Package() { 0x0014FFFF, 0, 0, 16 },
+ Package() { 0x0014FFFF, 1, 0, 17 },
+ Package() { 0x0014FFFF, 2, 0, 18 },
+ Package() { 0x0014FFFF, 3, 0, 19 },
+ // [CM13]: Uncore 13 CMS0CHA8-15 Device
+ Package() { 0x0015FFFF, 0, 0, 16 },
+ Package() { 0x0015FFFF, 1, 0, 17 },
+ Package() { 0x0015FFFF, 2, 0, 18 },
+ Package() { 0x0015FFFF, 3, 0, 19 },
+ // [CM14]: Uncore 13 CMS0CHA16-23 Device
+ Package() { 0x0016FFFF, 0, 0, 16 },
+ Package() { 0x0016FFFF, 1, 0, 17 },
+ Package() { 0x0016FFFF, 2, 0, 18 },
+ Package() { 0x0016FFFF, 3, 0, 19 },
+ // [CM15]: Uncore 13 CMS0CHA24-27 Device
+ Package() { 0x0017FFFF, 0, 0, 16 },
+ Package() { 0x0017FFFF, 1, 0, 17 },
+ Package() { 0x0017FFFF, 2, 0, 18 },
+ Package() { 0x0017FFFF, 3, 0, 19 },
+ // [CDL3]: Uncore 13 CHASADALL Device
+ Package() { 0x001DFFFF, 0, 0, 16 },
+ Package() { 0x001DFFFF, 1, 0, 17 },
+ Package() { 0x001DFFFF, 2, 0, 18 },
+ Package() { 0x001DFFFF, 3, 0, 19 },
+ // [PCU3]: Uncore 13 PCUCR Devices
+ Package() { 0x001EFFFF, 0, 0, 16 },
+ Package() { 0x001EFFFF, 1, 0, 17 },
+ Package() { 0x001EFFFF, 2, 0, 18 },
+ Package() { 0x001EFFFF, 3, 0, 19 },
+ // [VCU3]: Uncore 13 VCUCR Device
+ Package() { 0x001FFFFF, 0, 0, 16 },
+ Package() { 0x001FFFFF, 1, 0, 17 },
+ Package() { 0x001FFFFF, 2, 0, 18 },
+ Package() { 0x001FFFFF, 3, 0, 19 },
+ })
+
+ Name (AH59, Package() {
+ // [SR1A]: PCI Express Port 1A on PC19
+ Package() { 0x0000FFFF, 0, 0, 183 },
+ // [SR1B]: PCI Express Port 1B on PC19
+ Package() { 0x0001FFFF, 0, 0, 183 },
+ // [SR1C]: PCI Express Port 1C on PC19
+ Package() { 0x0002FFFF, 0, 0, 183 },
+ // [SR1D]: PCI Express Port 1D on PC19
+ Package() { 0x0003FFFF, 0, 0, 183 },
+ // [CHD0]: Uncore 13 CHAUTIL0-7 Device
+ Package() { 0x0008FFFF, 0, 0, 176 },
+ Package() { 0x0008FFFF, 1, 0, 180 },
+ Package() { 0x0008FFFF, 2, 0, 181 },
+ Package() { 0x0008FFFF, 3, 0, 182 },
+ // [CHD1]: Uncore 13 CHAUTIL8-15 Device
+ Package() { 0x0009FFFF, 0, 0, 176 },
+ Package() { 0x0009FFFF, 1, 0, 180 },
+ Package() { 0x0009FFFF, 2, 0, 181 },
+ Package() { 0x0009FFFF, 3, 0, 182 },
+ // [CHD2]: Uncore 13 CHAUTIL16-23 Device
+ Package() { 0x000AFFFF, 0, 0, 176 },
+ Package() { 0x000AFFFF, 1, 0, 180 },
+ Package() { 0x000AFFFF, 2, 0, 181 },
+ Package() { 0x000AFFFF, 3, 0, 182 },
+ // [CHD3]: Uncore 13 CHAUTIL24-27 Device
+ Package() { 0x000BFFFF, 0, 0, 176 },
+ Package() { 0x000BFFFF, 1, 0, 180 },
+ Package() { 0x000BFFFF, 2, 0, 181 },
+ Package() { 0x000BFFFF, 3, 0, 182 },
+ // [CHD4]: Uncore 13 CHASAD0-7 Device
+ Package() { 0x000EFFFF, 0, 0, 176 },
+ Package() { 0x000EFFFF, 1, 0, 180 },
+ Package() { 0x000EFFFF, 2, 0, 181 },
+ Package() { 0x000EFFFF, 3, 0, 182 },
+ // [CHD5]: Uncore 13 CHASAD8-15 Device
+ Package() { 0x000FFFFF, 0, 0, 176 },
+ Package() { 0x000FFFFF, 1, 0, 180 },
+ Package() { 0x000FFFFF, 2, 0, 181 },
+ Package() { 0x000FFFFF, 3, 0, 182 },
+ // [CHD6]: Uncore 13 CHASAD16-23 Device
+ Package() { 0x0010FFFF, 0, 0, 176 },
+ Package() { 0x0010FFFF, 1, 0, 180 },
+ Package() { 0x0010FFFF, 2, 0, 181 },
+ Package() { 0x0010FFFF, 3, 0, 182 },
+ // [CHD7]: Uncore 13 CHASAD24-27 Device
+ Package() { 0x0011FFFF, 0, 0, 176 },
+ Package() { 0x0011FFFF, 1, 0, 180 },
+ Package() { 0x0011FFFF, 2, 0, 181 },
+ Package() { 0x0011FFFF, 3, 0, 182 },
+ // [CM12]: Uncore 13 CMSCHA0-7 Device
+ Package() { 0x0014FFFF, 0, 0, 176 },
+ Package() { 0x0014FFFF, 1, 0, 180 },
+ Package() { 0x0014FFFF, 2, 0, 181 },
+ Package() { 0x0014FFFF, 3, 0, 182 },
+ // [CM13]: Uncore 13 CMS0CHA8-15 Device
+ Package() { 0x0015FFFF, 0, 0, 176 },
+ Package() { 0x0015FFFF, 1, 0, 180 },
+ Package() { 0x0015FFFF, 2, 0, 181 },
+ Package() { 0x0015FFFF, 3, 0, 182 },
+ // [CM14]: Uncore 13 CMS0CHA16-23 Device
+ Package() { 0x0016FFFF, 0, 0, 176 },
+ Package() { 0x0016FFFF, 1, 0, 180 },
+ Package() { 0x0016FFFF, 2, 0, 181 },
+ Package() { 0x0016FFFF, 3, 0, 182 },
+ // [CM15]: Uncore 13 CMS0CHA24-27 Device
+ Package() { 0x0017FFFF, 0, 0, 176 },
+ Package() { 0x0017FFFF, 1, 0, 180 },
+ Package() { 0x0017FFFF, 2, 0, 181 },
+ Package() { 0x0017FFFF, 3, 0, 182 },
+ // [CDL3]: Uncore 13 CHASADALL Device
+ Package() { 0x001DFFFF, 0, 0, 176 },
+ Package() { 0x001DFFFF, 1, 0, 180 },
+ Package() { 0x001DFFFF, 2, 0, 181 },
+ Package() { 0x001DFFFF, 3, 0, 182 },
+ // [PCU3]: Uncore 13 PCUCR Devices
+ Package() { 0x001EFFFF, 0, 0, 176 },
+ Package() { 0x001EFFFF, 1, 0, 180 },
+ Package() { 0x001EFFFF, 2, 0, 181 },
+ Package() { 0x001EFFFF, 3, 0, 182 },
+ // [VCU3]: Uncore 13 VCUCR Device
+ Package() { 0x001FFFFF, 0, 0, 176 },
+ Package() { 0x001FFFFF, 1, 0, 180 },
+ Package() { 0x001FFFFF, 2, 0, 181 },
+ Package() { 0x001FFFFF, 3, 0, 182 },
+ })
+
+ Name (PR5A, Package() {
+ // [SL2E]: PCI Express Slot 46 on 1A on PC19
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR5A, Package() {
+ // [SL2E]: PCI Express Slot 46 on 1A on PC19
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH5A, Package() {
+ // [SL2E]: PCI Express Slot 46 on 1A on PC19
+ Package() { 0x0000FFFF, 0, 0, 176 },
+ Package() { 0x0000FFFF, 1, 0, 180 },
+ Package() { 0x0000FFFF, 2, 0, 181 },
+ Package() { 0x0000FFFF, 3, 0, 182 },
+ })
+
+ Name (PR5B, Package() {
+ // [SL2F]: PCI Express Slot 47 on 1B on PC19
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR5B, Package() {
+ // [SL2F]: PCI Express Slot 47 on 1B on PC19
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH5B, Package() {
+ // [SL2F]: PCI Express Slot 47 on 1B on PC19
+ Package() { 0x0000FFFF, 0, 0, 177 },
+ Package() { 0x0000FFFF, 1, 0, 182 },
+ Package() { 0x0000FFFF, 2, 0, 180 },
+ Package() { 0x0000FFFF, 3, 0, 181 },
+ })
+
+ Name (PR5C, Package() {
+ // [SL30]: PCI Express Slot 48 on 1C on PC19
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR5C, Package() {
+ // [SL30]: PCI Express Slot 48 on 1C on PC19
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH5C, Package() {
+ // [SL30]: PCI Express Slot 48 on 1C on PC19
+ Package() { 0x0000FFFF, 0, 0, 178 },
+ Package() { 0x0000FFFF, 1, 0, 181 },
+ Package() { 0x0000FFFF, 2, 0, 182 },
+ Package() { 0x0000FFFF, 3, 0, 180 },
+ })
+
+ Name (PR5D, Package() {
+ // [SL31]: PCI Express Slot 49 on 1D on PC19
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR5D, Package() {
+ // [SL31]: PCI Express Slot 49 on 1D on PC19
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH5D, Package() {
+ // [SL31]: PCI Express Slot 49 on 1D on PC19
+ Package() { 0x0000FFFF, 0, 0, 179 },
+ Package() { 0x0000FFFF, 1, 0, 182 },
+ Package() { 0x0000FFFF, 2, 0, 180 },
+ Package() { 0x0000FFFF, 3, 0, 181 },
+ })
+
+ Name (PR5E, Package() {
+ // [SR2A]: PCI Express Port 2A on PC20
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [SR2B]: PCI Express Port 2B on PC20
+ Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [SR2C]: PCI Express Port 2C on PC20
+ Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [SR2D]: PCI Express Port 2D on PC20
+ Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [M2M6]: Uncore 14 M2MEM0 Device
+ Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [M2M7]: Uncore 14 M2MEM10 Device
+ Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [MCM6]: Uncore 14 MCMAIN Device
+ Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [MCD6]: Uncore 14 MCDECS2 Device
+ Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [MCM7]: Uncore 14 MCMAIN Device
+ Package() { 0x000CFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000CFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000CFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000CFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [MCD7]: Uncore 14 MCDECS12 Device
+ Package() { 0x000DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [UMC6]: Uncore 14 Unicast MC0 DDRIO0 Device
+ Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [UMC7]: Uncore 14 Unicast MC1 DDRIO0 Device
+ Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR5E, Package() {
+ // [SR2A]: PCI Express Port 2A on PC20
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ // [SR2B]: PCI Express Port 2B on PC20
+ Package() { 0x0001FFFF, 0, 0, 16 },
+ // [SR2C]: PCI Express Port 2C on PC20
+ Package() { 0x0002FFFF, 0, 0, 16 },
+ // [SR2D]: PCI Express Port 2D on PC20
+ Package() { 0x0003FFFF, 0, 0, 16 },
+ // [M2M6]: Uncore 14 M2MEM0 Device
+ Package() { 0x0008FFFF, 0, 0, 16 },
+ Package() { 0x0008FFFF, 1, 0, 17 },
+ Package() { 0x0008FFFF, 2, 0, 18 },
+ Package() { 0x0008FFFF, 3, 0, 19 },
+ // [M2M7]: Uncore 14 M2MEM10 Device
+ Package() { 0x0009FFFF, 0, 0, 16 },
+ Package() { 0x0009FFFF, 1, 0, 17 },
+ Package() { 0x0009FFFF, 2, 0, 18 },
+ Package() { 0x0009FFFF, 3, 0, 19 },
+ // [MCM6]: Uncore 14 MCMAIN Device
+ Package() { 0x000AFFFF, 0, 0, 16 },
+ Package() { 0x000AFFFF, 1, 0, 17 },
+ Package() { 0x000AFFFF, 2, 0, 18 },
+ Package() { 0x000AFFFF, 3, 0, 19 },
+ // [MCD6]: Uncore 14 MCDECS2 Device
+ Package() { 0x000BFFFF, 0, 0, 16 },
+ Package() { 0x000BFFFF, 1, 0, 17 },
+ Package() { 0x000BFFFF, 2, 0, 18 },
+ Package() { 0x000BFFFF, 3, 0, 19 },
+ // [MCM7]: Uncore 14 MCMAIN Device
+ Package() { 0x000CFFFF, 0, 0, 16 },
+ Package() { 0x000CFFFF, 1, 0, 17 },
+ Package() { 0x000CFFFF, 2, 0, 18 },
+ Package() { 0x000CFFFF, 3, 0, 19 },
+ // [MCD7]: Uncore 14 MCDECS12 Device
+ Package() { 0x000DFFFF, 0, 0, 16 },
+ Package() { 0x000DFFFF, 1, 0, 17 },
+ Package() { 0x000DFFFF, 2, 0, 18 },
+ Package() { 0x000DFFFF, 3, 0, 19 },
+ // [UMC6]: Uncore 14 Unicast MC0 DDRIO0 Device
+ Package() { 0x0016FFFF, 0, 0, 16 },
+ Package() { 0x0016FFFF, 1, 0, 17 },
+ Package() { 0x0016FFFF, 2, 0, 18 },
+ Package() { 0x0016FFFF, 3, 0, 19 },
+ // [UMC7]: Uncore 14 Unicast MC1 DDRIO0 Device
+ Package() { 0x0017FFFF, 0, 0, 16 },
+ Package() { 0x0017FFFF, 1, 0, 17 },
+ Package() { 0x0017FFFF, 2, 0, 18 },
+ Package() { 0x0017FFFF, 3, 0, 19 },
+ })
+
+ Name (AH5E, Package() {
+ // [SR2A]: PCI Express Port 2A on PC20
+ Package() { 0x0000FFFF, 0, 0, 191 },
+ // [SR2B]: PCI Express Port 2B on PC20
+ Package() { 0x0001FFFF, 0, 0, 191 },
+ // [SR2C]: PCI Express Port 2C on PC20
+ Package() { 0x0002FFFF, 0, 0, 191 },
+ // [SR2D]: PCI Express Port 2D on PC20
+ Package() { 0x0003FFFF, 0, 0, 191 },
+ // [M2M6]: Uncore 14 M2MEM0 Device
+ Package() { 0x0008FFFF, 0, 0, 184 },
+ Package() { 0x0008FFFF, 1, 0, 188 },
+ Package() { 0x0008FFFF, 2, 0, 189 },
+ Package() { 0x0008FFFF, 3, 0, 190 },
+ // [M2M7]: Uncore 14 M2MEM10 Device
+ Package() { 0x0009FFFF, 0, 0, 184 },
+ Package() { 0x0009FFFF, 1, 0, 188 },
+ Package() { 0x0009FFFF, 2, 0, 189 },
+ Package() { 0x0009FFFF, 3, 0, 190 },
+ // [MCM6]: Uncore 14 MCMAIN Device
+ Package() { 0x000AFFFF, 0, 0, 184 },
+ Package() { 0x000AFFFF, 1, 0, 188 },
+ Package() { 0x000AFFFF, 2, 0, 189 },
+ Package() { 0x000AFFFF, 3, 0, 190 },
+ // [MCD6]: Uncore 14 MCDECS2 Device
+ Package() { 0x000BFFFF, 0, 0, 184 },
+ Package() { 0x000BFFFF, 1, 0, 188 },
+ Package() { 0x000BFFFF, 2, 0, 189 },
+ Package() { 0x000BFFFF, 3, 0, 190 },
+ // [MCM7]: Uncore 14 MCMAIN Device
+ Package() { 0x000CFFFF, 0, 0, 184 },
+ Package() { 0x000CFFFF, 1, 0, 188 },
+ Package() { 0x000CFFFF, 2, 0, 189 },
+ Package() { 0x000CFFFF, 3, 0, 190 },
+ // [MCD7]: Uncore 14 MCDECS12 Device
+ Package() { 0x000DFFFF, 0, 0, 184 },
+ Package() { 0x000DFFFF, 1, 0, 188 },
+ Package() { 0x000DFFFF, 2, 0, 189 },
+ Package() { 0x000DFFFF, 3, 0, 190 },
+ // [UMC6]: Uncore 14 Unicast MC0 DDRIO0 Device
+ Package() { 0x0016FFFF, 0, 0, 184 },
+ Package() { 0x0016FFFF, 1, 0, 188 },
+ Package() { 0x0016FFFF, 2, 0, 189 },
+ Package() { 0x0016FFFF, 3, 0, 190 },
+ // [UMC7]: Uncore 14 Unicast MC1 DDRIO0 Device
+ Package() { 0x0017FFFF, 0, 0, 184 },
+ Package() { 0x0017FFFF, 1, 0, 188 },
+ Package() { 0x0017FFFF, 2, 0, 189 },
+ Package() { 0x0017FFFF, 3, 0, 190 },
+ })
+
+ Name (PR5F, Package() {
+ // [SL32]: PCI Express Slot 50 on 2A on PC20
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR5F, Package() {
+ // [SL32]: PCI Express Slot 50 on 2A on PC20
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH5F, Package() {
+ // [SL32]: PCI Express Slot 50 on 2A on PC20
+ Package() { 0x0000FFFF, 0, 0, 184 },
+ Package() { 0x0000FFFF, 1, 0, 188 },
+ Package() { 0x0000FFFF, 2, 0, 189 },
+ Package() { 0x0000FFFF, 3, 0, 190 },
+ })
+
+ Name (PR60, Package() {
+ // [SL33]: PCI Express Slot 51 on 2B on PC20
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR60, Package() {
+ // [SL33]: PCI Express Slot 51 on 2B on PC20
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH60, Package() {
+ // [SL33]: PCI Express Slot 51 on 2B on PC20
+ Package() { 0x0000FFFF, 0, 0, 185 },
+ Package() { 0x0000FFFF, 1, 0, 190 },
+ Package() { 0x0000FFFF, 2, 0, 188 },
+ Package() { 0x0000FFFF, 3, 0, 189 },
+ })
+
+ Name (PR61, Package() {
+ // [SL34]: PCI Express Slot 52 on 2C on PC20
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR61, Package() {
+ // [SL34]: PCI Express Slot 52 on 2C on PC20
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH61, Package() {
+ // [SL34]: PCI Express Slot 52 on 2C on PC20
+ Package() { 0x0000FFFF, 0, 0, 186 },
+ Package() { 0x0000FFFF, 1, 0, 189 },
+ Package() { 0x0000FFFF, 2, 0, 190 },
+ Package() { 0x0000FFFF, 3, 0, 188 },
+ })
+
+ Name (PR62, Package() {
+ // [SL35]: PCI Express Slot 53 on 2D on PC20
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR62, Package() {
+ // [SL35]: PCI Express Slot 53 on 2D on PC20
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH62, Package() {
+ // [SL35]: PCI Express Slot 53 on 2D on PC20
+ Package() { 0x0000FFFF, 0, 0, 187 },
+ Package() { 0x0000FFFF, 1, 0, 190 },
+ Package() { 0x0000FFFF, 2, 0, 188 },
+ Package() { 0x0000FFFF, 3, 0, 189 },
+ })
+
+ Name (PR63, Package() {
+ // [SR3A]: PCI Express Port 3A on PC21
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [SR3B]: PCI Express Port 3B on PC21
+ Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [SR3C]: PCI Express Port 3C on PC21
+ Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [SR3D]: PCI Express Port 3D on PC21
+ Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ // [KTI9]: Uncore 15 KTI9
+ Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [KT10]: Uncore 15 KT10
+ Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [KT11]: Uncore 15 KT11
+ Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [M3K3]: Uncore 15 M3K3
+ Package() { 0x0012FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0012FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0012FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0012FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [M2U3]: Uncore 15 M2U3
+ Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [M2D3]: Uncore 15 M2D3
+ Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ // [M23]: Uncore 15 M23
+ Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR63, Package() {
+ // [SR3A]: PCI Express Port 3A on PC21
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ // [SR3B]: PCI Express Port 3B on PC21
+ Package() { 0x0001FFFF, 0, 0, 16 },
+ // [SR3C]: PCI Express Port 3C on PC21
+ Package() { 0x0002FFFF, 0, 0, 16 },
+ // [SR3D]: PCI Express Port 3D on PC21
+ Package() { 0x0003FFFF, 0, 0, 16 },
+ // [KTI9]: Uncore 15 KTI9
+ Package() { 0x000EFFFF, 0, 0, 16 },
+ Package() { 0x000EFFFF, 1, 0, 17 },
+ Package() { 0x000EFFFF, 2, 0, 18 },
+ Package() { 0x000EFFFF, 3, 0, 19 },
+ // [KT10]: Uncore 15 KT10
+ Package() { 0x000FFFFF, 0, 0, 16 },
+ Package() { 0x000FFFFF, 1, 0, 17 },
+ Package() { 0x000FFFFF, 2, 0, 18 },
+ Package() { 0x000FFFFF, 3, 0, 19 },
+ // [KT11]: Uncore 15 KT11
+ Package() { 0x0010FFFF, 0, 0, 16 },
+ Package() { 0x0010FFFF, 1, 0, 17 },
+ Package() { 0x0010FFFF, 2, 0, 18 },
+ Package() { 0x0010FFFF, 3, 0, 19 },
+ // [M3K3]: Uncore 15 M3K3
+ Package() { 0x0012FFFF, 0, 0, 16 },
+ Package() { 0x0012FFFF, 1, 0, 17 },
+ Package() { 0x0012FFFF, 2, 0, 18 },
+ Package() { 0x0012FFFF, 3, 0, 19 },
+ // [M2U3]: Uncore 15 M2U3
+ Package() { 0x0015FFFF, 0, 0, 16 },
+ Package() { 0x0015FFFF, 1, 0, 17 },
+ Package() { 0x0015FFFF, 2, 0, 18 },
+ Package() { 0x0015FFFF, 3, 0, 19 },
+ // [M2D3]: Uncore 15 M2D3
+ Package() { 0x0016FFFF, 0, 0, 16 },
+ Package() { 0x0016FFFF, 1, 0, 17 },
+ Package() { 0x0016FFFF, 2, 0, 18 },
+ Package() { 0x0016FFFF, 3, 0, 19 },
+ // [M23]: Uncore 15 M23
+ Package() { 0x0017FFFF, 0, 0, 16 },
+ Package() { 0x0017FFFF, 1, 0, 17 },
+ Package() { 0x0017FFFF, 2, 0, 18 },
+ Package() { 0x0017FFFF, 3, 0, 19 },
+ })
+
+ Name (AH63, Package() {
+ // [SR3A]: PCI Express Port 3A on PC21
+ Package() { 0x0000FFFF, 0, 0, 199 },
+ // [SR3B]: PCI Express Port 3B on PC21
+ Package() { 0x0001FFFF, 0, 0, 199 },
+ // [SR3C]: PCI Express Port 3C on PC21
+ Package() { 0x0002FFFF, 0, 0, 199 },
+ // [SR3D]: PCI Express Port 3D on PC21
+ Package() { 0x0003FFFF, 0, 0, 199 },
+ // [KTI9]: Uncore 15 KTI9
+ Package() { 0x000EFFFF, 0, 0, 192 },
+ Package() { 0x000EFFFF, 1, 0, 196 },
+ Package() { 0x000EFFFF, 2, 0, 197 },
+ Package() { 0x000EFFFF, 3, 0, 198 },
+ // [KT10]: Uncore 15 KT10
+ Package() { 0x000FFFFF, 0, 0, 192 },
+ Package() { 0x000FFFFF, 1, 0, 196 },
+ Package() { 0x000FFFFF, 2, 0, 197 },
+ Package() { 0x000FFFFF, 3, 0, 198 },
+ // [KT11]: Uncore 15 KT11
+ Package() { 0x0010FFFF, 0, 0, 192 },
+ Package() { 0x0010FFFF, 1, 0, 196 },
+ Package() { 0x0010FFFF, 2, 0, 197 },
+ Package() { 0x0010FFFF, 3, 0, 198 },
+ // [M3K3]: Uncore 15 M3K3
+ Package() { 0x0012FFFF, 0, 0, 192 },
+ Package() { 0x0012FFFF, 1, 0, 196 },
+ Package() { 0x0012FFFF, 2, 0, 197 },
+ Package() { 0x0012FFFF, 3, 0, 198 },
+ // [M2U3]: Uncore 15 M2U3
+ Package() { 0x0015FFFF, 0, 0, 192 },
+ Package() { 0x0015FFFF, 1, 0, 196 },
+ Package() { 0x0015FFFF, 2, 0, 197 },
+ Package() { 0x0015FFFF, 3, 0, 198 },
+ // [M2D3]: Uncore 15 M2D3
+ Package() { 0x0016FFFF, 0, 0, 192 },
+ Package() { 0x0016FFFF, 1, 0, 196 },
+ Package() { 0x0016FFFF, 2, 0, 197 },
+ Package() { 0x0016FFFF, 3, 0, 198 },
+ // [M23]: Uncore 15 M23
+ Package() { 0x0017FFFF, 0, 0, 192 },
+ Package() { 0x0017FFFF, 1, 0, 196 },
+ Package() { 0x0017FFFF, 2, 0, 197 },
+ Package() { 0x0017FFFF, 3, 0, 198 },
+ })
+
+ Name (PR64, Package() {
+ // [SL36]: PCI Express Slot 54 on 3A on PC21
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR64, Package() {
+ // [SL36]: PCI Express Slot 54 on 3A on PC21
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH64, Package() {
+ // [SL36]: PCI Express Slot 54 on 3A on PC21
+ Package() { 0x0000FFFF, 0, 0, 192 },
+ Package() { 0x0000FFFF, 1, 0, 196 },
+ Package() { 0x0000FFFF, 2, 0, 197 },
+ Package() { 0x0000FFFF, 3, 0, 198 },
+ })
+
+ Name (PR65, Package() {
+ // [SL37]: PCI Express Slot 55 on 3B on PC21
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR65, Package() {
+ // [SL37]: PCI Express Slot 55 on 3B on PC21
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH65, Package() {
+ // [SL37]: PCI Express Slot 55 on 3B on PC21
+ Package() { 0x0000FFFF, 0, 0, 193 },
+ Package() { 0x0000FFFF, 1, 0, 198 },
+ Package() { 0x0000FFFF, 2, 0, 196 },
+ Package() { 0x0000FFFF, 3, 0, 197 },
+ })
+
+ Name (PR66, Package() {
+ // [SL38]: PCI Express Slot 56 on 3C on PC21
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR66, Package() {
+ // [SL38]: PCI Express Slot 56 on 3C on PC21
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH66, Package() {
+ // [SL38]: PCI Express Slot 56 on 3C on PC21
+ Package() { 0x0000FFFF, 0, 0, 194 },
+ Package() { 0x0000FFFF, 1, 0, 197 },
+ Package() { 0x0000FFFF, 2, 0, 198 },
+ Package() { 0x0000FFFF, 3, 0, 196 },
+ })
+
+ Name (PR67, Package() {
+ // [SL39]: PCI Express Slot 57 on 3D on PC21
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR67, Package() {
+ // [SL39]: PCI Express Slot 57 on 3D on PC21
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH67, Package() {
+ // [SL39]: PCI Express Slot 57 on 3D on PC21
+ Package() { 0x0000FFFF, 0, 0, 195 },
+ Package() { 0x0000FFFF, 1, 0, 198 },
+ Package() { 0x0000FFFF, 2, 0, 196 },
+ Package() { 0x0000FFFF, 3, 0, 197 },
+ })
+
+ Name (PR68, Package() {
+ // [MCP6]: PCI Express Port 4 on PC22
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ })
+
+ Name (AR68, Package() {
+ // [MCP6]: PCI Express Port 4 on PC22
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ })
+
+ Name (AH68, Package() {
+ // [MCP6]: PCI Express Port 4 on PC22
+ Package() { 0x0000FFFF, 0, 0, 207 },
+ })
+
+ Name (PR69, Package() {
+ // [SL3A]: PCI Express Slot 58 on 4 on PC22
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR69, Package() {
+ // [SL3A]: PCI Express Slot 58 on 4 on PC22
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH69, Package() {
+ // [SL3A]: PCI Express Slot 58 on 4 on PC22
+ Package() { 0x0000FFFF, 0, 0, 200 },
+ Package() { 0x0000FFFF, 1, 0, 204 },
+ Package() { 0x0000FFFF, 2, 0, 205 },
+ Package() { 0x0000FFFF, 3, 0, 206 },
+ })
+
+ Name (PR6A, Package() {
+ // [MCP7]: PCI Express Port 5 on PC23
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ })
+
+ Name (AR6A, Package() {
+ // [MCP7]: PCI Express Port 5 on PC23
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ })
+
+ Name (AH6A, Package() {
+ // [MCP7]: PCI Express Port 5 on PC23
+ Package() { 0x0000FFFF, 0, 0, 215 },
+ })
+
+ Name (PR6B, Package() {
+ // [SL3B]: PCI Express Slot 59 on 4 on PC23
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR6B, Package() {
+ // [SL3B]: PCI Express Slot 59 on 4 on PC23
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AH6B, Package() {
+ // [SL3B]: PCI Express Slot 59 on 4 on PC23
+ Package() { 0x0000FFFF, 0, 0, 208 },
+ Package() { 0x0000FFFF, 1, 0, 212 },
+ Package() { 0x0000FFFF, 2, 0, 213 },
+ Package() { 0x0000FFFF, 3, 0, 214 },
+ })
+
+ Name (PR6C, Package() {
+ // [FPG0]: FPGA Device
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ })
+
+ Name (AR6C, Package() {
+ // [FPG0]: FPGA Device
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ })
+
+ Name (PR6D, Package() {
+ // [FPG1]: FPGA Device
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ })
+
+ Name (AR6D, Package() {
+ // [FPG1]: FPGA Device
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ })
+
+ Name (PR6E, Package() {
+ // [FPG2]: FPGA Device
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ })
+
+ Name (AR6E, Package() {
+ // [FPG2]: FPGA Device
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ })
+
+ Name (PR6F, Package() {
+ // [FPG3]: FPGA Device
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR6F, Package() {
+ // [FPG3]: FPGA Device
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (PR70, Package() {
+ // [FKT0]: FPGA Device
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ })
+
+ Name (AR70, Package() {
+ // [FKT0]: FPGA Device
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ })
+
+ Name (PR71, Package() {
+ // [FKT1]: FPGA Device
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ })
+
+ Name (AR71, Package() {
+ // [FKT1]: FPGA Device
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ })
+
+ Name (PR72, Package() {
+ // [FKT2]: FPGA Device
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ })
+
+ Name (AR72, Package() {
+ // [FKT2]: FPGA Device
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ })
+
+ Name (PR73, Package() {
+ // [FKT3]: FPGA Device
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (AR73, Package() {
+ // [FKT3]: FPGA Device
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ // Socket 0 Root bridge (Stack 0)
+ Device (PC00) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x00)
+ Method (_BBN, 0, NotSerialized) {
+ return (BB00)
+ }
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR00)
+ }
+ If (LEqual(AP00, One)) {
+ Return (AH00)
+ }
+ Return (AR00)
+ }
+
+ #include "PC00.asi"
+ #include "HostBus.asl"
+
+ // Legacy PCI Express Port 0 on PC00
+ Device (DMI0) {
+ Name (_ADR, 0x00000000)
+ }
+
+ // CB3DMA on PC00
+ Device (CB0A) {
+ Name (_ADR, 0x00040000)
+ }
+
+ // CB3DMA on PC00
+ Device (CB0B) {
+ Name (_ADR, 0x00040001)
+ }
+
+ // CB3DMA on PC00
+ Device (CB0C) {
+ Name (_ADR, 0x00040002)
+ }
+
+ // CB3DMA on PC00
+ Device (CB0D) {
+ Name (_ADR, 0x00040003)
+ }
+
+ // CB3DMA on PC00
+ Device (CB0E) {
+ Name (_ADR, 0x00040004)
+ }
+
+ // CB3DMA on PC00
+ Device (CB0F) {
+ Name (_ADR, 0x00040005)
+ }
+
+ // CB3DMA on PC00
+ Device (CB0G) {
+ Name (_ADR, 0x00040006)
+ }
+
+ // CB3DMA on PC00
+ Device (CB0H) {
+ Name (_ADR, 0x00040007)
+ }
+
+ // IIOMISC on PC00
+ Device (IIM0) {
+ Name (_ADR, 0x00050000)
+ }
+
+ // Uncore 0 UBOX Device
+ Device (UBX0) {
+ Name (_ADR, 0x00080000)
+ }
+
+ // High definition Audio Controller
+ Device (ALZA) {
+ Name (_ADR, 0x000E0000)
+ }
+
+ // Display Controller
+ Device (DISP) {
+ Name (_ADR, 0x000F0000)
+ }
+
+ // HECI #1
+ Device (IHC1) {
+ Name (_ADR, 0x00100000)
+ }
+
+ // HECI #2
+ Device (IHC2) {
+ Name (_ADR, 0x00100001)
+ }
+
+ // IDE-Redirection (IDE-R)
+ Device (IIDR) {
+ Name (_ADR, 0x00100002)
+ }
+
+ // Keyboard and Text (KT) Redirection
+ Device (IMKT) {
+ Name (_ADR, 0x00100003)
+ }
+
+ // HECI #3
+ Device (IHC3) {
+ Name (_ADR, 0x00100004)
+ }
+
+ // MROM 0 function function
+ Device (MRO0) {
+ Name (_ADR, 0x00110000)
+ }
+
+ // MROM 1 function function
+ Device (MRO1) {
+ Name (_ADR, 0x00110001)
+ }
+
+ // sSATA Host controller 2 on PCH
+ Device (SAT2) {
+ Name (_ADR, 0x00110005)
+ }
+
+ // xHCI controller 1 on PCH
+ Device (XHCI) {
+ Name (_ADR, 0x00140000)
+ }
+
+ // USB Device Controller (OTG) on PCH
+ Device (OTG0) {
+ Name (_ADR, 0x00140001)
+ }
+
+ // Thermal Subsystem on PCH
+ Device (TERM) {
+ Name (_ADR, 0x00140002)
+ }
+
+ // Camera IO Host Controller on PCH
+ Device (CAMR) {
+ Name (_ADR, 0x00140003)
+ }
+
+ // Northpeak Phantom (ACPI) Function on PCH
+ Device (NTHP) {
+ Name (_ADR, 0x00140004)
+ }
+
+ // HECI #1 on PCH
+ Device (HEC1) {
+ Name (_ADR, 0x00160000)
+ }
+
+ // HECI #2 on PCH
+ Device (HEC2) {
+ Name (_ADR, 0x00160001)
+ }
+
+ // ME IDE redirect on PCH
+ Device (IDER) {
+ Name (_ADR, 0x00160002)
+ }
+
+ // MEKT on PCH
+ Device (MEKT) {
+ Name (_ADR, 0x00160003)
+ }
+
+ // HECI #3 on PCH
+ Device (HEC3) {
+ Name (_ADR, 0x00160004)
+ }
+
+ // SATA controller 1 on PCH
+ Device (SAT1) {
+ Name (_ADR, 0x00170000)
+ }
+
+ // NAND Cycle Router on PCH
+ Device (NAN1) {
+ Name (_ADR, 0x00180000)
+ }
+
+ // PCIE PCH Root Port #17
+ Device (RP17) {
+ #include "RP17_ADR.asl"
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR01)
+ }
+ Return (AR01)
+ }
+
+ // PCIE PCH Slot #17
+ Device (SLTH) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // PCIE PCH Root Port #18
+ Device (RP18) {
+ #include "RP18_ADR.asl"
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR02)
+ }
+ Return (AR02)
+ }
+
+ // PCIE PCH Slot #18
+ Device (SLTI) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // PCIE PCH Root Port #19
+ Device (RP19) {
+ #include "RP19_ADR.asl"
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR03)
+ }
+ Return (AR03)
+ }
+
+ // PCIE PCH Slot #19
+ Device (SLTJ) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // PCIE PCH Root Port #20
+ Device (RP20) {
+ #include "RP20_ADR.asl"
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR04)
+ }
+ Return (AR04)
+ }
+
+ // PCIE PCH Slot #20
+ Device (SLTK) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // PCIE PCH Root Port #1
+ Device (RP01) {
+ #include "RP01_ADR.asl"
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR05)
+ }
+ Return (AR05)
+ }
+ }
+
+ // PCIE PCH Root Port #2
+ Device (RP02) {
+ #include "RP02_ADR.asl"
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR06)
+ }
+ Return (AR06)
+ }
+ }
+
+ // PCIE PCH Root Port #3
+ Device (RP03) {
+ #include "RP03_ADR.asl"
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR07)
+ }
+ Return (AR07)
+ }
+ }
+
+ // PCIE PCH Root Port #4
+ Device (RP04) {
+ #include "RP04_ADR.asl"
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR08)
+ }
+ Return (AR08)
+ }
+ }
+
+ // PCIE PCH Root Port #5
+ Device (RP05) {
+ #include "RP05_ADR.asl"
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR09)
+ }
+ Return (AR09)
+ }
+ }
+
+ // PCIE PCH Root Port #6
+ Device (RP06) {
+ #include "RP06_ADR.asl"
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR0A)
+ }
+ Return (AR0A)
+ }
+ }
+
+ // PCIE PCH Root Port #7
+ Device (RP07) {
+ #include "RP07_ADR.asl"
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR0B)
+ }
+ Return (AR0B)
+ }
+ }
+
+ // PCIE PCH Root Port #8
+ Device (RP08) {
+ #include "RP08_ADR.asl"
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR0C)
+ }
+ Return (AR0C)
+ }
+ }
+
+ // PCIE PCH Root Port #9
+ Device (RP09) {
+ #include "RP09_ADR.asl"
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR0D)
+ }
+ Return (AR0D)
+ }
+
+ // PCIE PCH Slot #9
+ Device (SLT9) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // PCIE PCH Root Port #10
+ Device (RP10) {
+ #include "RP10_ADR.asl"
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR0E)
+ }
+ Return (AR0E)
+ }
+
+ // PCIE PCH Slot #10
+ Device (SLTA) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // PCIE PCH Root Port #11
+ Device (RP11) {
+ #include "RP11_ADR.asl"
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR0F)
+ }
+ Return (AR0F)
+ }
+
+ // PCIE PCH Slot #11
+ Device (SLTB) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // PCIE PCH Root Port #12
+ Device (RP12) {
+ #include "RP12_ADR.asl"
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR10)
+ }
+ Return (AR10)
+ }
+
+ // PCIE PCH Slot #12
+ Device (SLTC) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // PCIE PCH Root Port #13
+ Device (RP13) {
+ #include "RP13_ADR.asl"
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR11)
+ }
+ Return (AR11)
+ }
+
+ // PCIE PCH Slot #13
+ Device (SLTD) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // PCIE PCH Root Port #14
+ Device (RP14) {
+ #include "RP14_ADR.asl"
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR12)
+ }
+ Return (AR12)
+ }
+
+ // PCIE PCH Slot #14
+ Device (SLTE) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // PCIE PCH Root Port #15
+ Device (RP15) {
+ #include "RP15_ADR.asl"
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR13)
+ }
+ Return (AR13)
+ }
+
+ // PCIE PCH Slot #15
+ Device (SLTF) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // PCIE PCH Root Port #16
+ Device (RP16) {
+ #include "RP16_ADR.asl"
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR14)
+ }
+ Return (AR14)
+ }
+
+ // PCIE PCH Slot #16
+ Device (SLTG) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // UART #0 on PCH
+ Device (UAR0) {
+ Name (_ADR, 0x001E0000)
+ }
+
+ // UART #1 on PCH
+ Device (UAR1) {
+ Name (_ADR, 0x001E0001)
+ }
+
+ // SPI #0 on PCH
+ Device (SPI0) {
+ Name (_ADR, 0x001E0002)
+ }
+
+ // SPI #1 on PCH
+ Device (SPI1) {
+ Name (_ADR, 0x001E0003)
+ }
+
+ // ISA Bridge on PCH
+ Device (LPC0) {
+ Name (_ADR, 0x001F0000)
+
+ #include "PchLpc.asi"
+ }
+
+ // Power Management Controller on PCH
+ Device (PMC1) {
+ Name (_ADR, 0x001F0002)
+ }
+
+ // HD Audio Subsystem Controller on PCH
+ Device (CAVS) {
+ Name (_ADR, 0x001F0003)
+ }
+
+ // SMBus controller on PCH
+ Device (SMBS) {
+ Name (_ADR, 0x001F0004)
+ }
+
+ // SPI controller on PCH
+ Device (SPIC) {
+ Name (_ADR, 0x001F0005)
+ }
+
+ // GbE Controller on PCH
+ Device (GBE1) {
+ Name (_ADR, 0x001F0006)
+ }
+
+ // Northpeak Controller on PCH
+ Device (NTPK) {
+ Name (_ADR, 0x001F0007)
+ }
+ }
+
+ // Socket 0 Root bridge (Stack 1)
+ Device (PC01) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x01)
+ Method (_BBN, 0, NotSerialized) {
+ return (BB01)
+ }
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR15)
+ }
+ If (LEqual(AP01, One)) {
+ Return (AH15)
+ }
+ Return (AR15)
+ }
+
+ #include "PC01.asi"
+
+ // PCI Express Port 1A on PC01
+ Device (BR1A) {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR16)
+ }
+ If (LEqual(AP01, One)) {
+ Return (AH16)
+ }
+ Return (AR16)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+ }
+
+ // PCI Express Port 1B on PC01
+ Device (BR1B) {
+ Name (_ADR, 0x00010000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR17)
+ }
+ If (LEqual(AP01, One)) {
+ Return (AH17)
+ }
+ Return (AR17)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+ }
+
+ // PCI Express Port 1C on PC01
+ Device (BR1C) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR18)
+ }
+ If (LEqual(AP01, One)) {
+ Return (AH18)
+ }
+ Return (AR18)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+ }
+
+ // PCI Express Port 1D on PC01
+ Device (BR1D) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR19)
+ }
+ If (LEqual(AP01, One)) {
+ Return (AH19)
+ }
+ Return (AR19)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+ }
+
+ // Uncore 1 CHAUTIL0-7 Device
+ Device (CHA0) {
+ Name (_ADR, 0x00080000)
+ }
+
+ // Uncore 1 CHAUTIL8-15 Device
+ Device (CHA1) {
+ Name (_ADR, 0x00090000)
+ }
+
+ // Uncore 1 CHAUTIL16-23 Device
+ Device (CHA2) {
+ Name (_ADR, 0x000A0000)
+ }
+
+ // Uncore 1 CHAUTIL24-27 Device
+ Device (CHA3) {
+ Name (_ADR, 0x000B0000)
+ }
+
+ // Uncore 1 CHASAD0-7 Device
+ Device (CHA4) {
+ Name (_ADR, 0x000E0000)
+ }
+
+ // Uncore 1 CHASAD8-15 Device
+ Device (CHA5) {
+ Name (_ADR, 0x000F0000)
+ }
+
+ // Uncore 1 CHASAD16-23 Device
+ Device (CHA6) {
+ Name (_ADR, 0x00100000)
+ }
+
+ // Uncore 1 CHASAD24-27 Device
+ Device (CHA7) {
+ Name (_ADR, 0x00110000)
+ }
+
+ // Uncore 1 CMSCHA0-7 Device
+ Device (CMS0) {
+ Name (_ADR, 0x00140000)
+ }
+
+ // Uncore 1 CMS0CHA8-15 Device
+ Device (CMS1) {
+ Name (_ADR, 0x00150000)
+ }
+
+ // Uncore 1 CMS0CHA16-23 Device
+ Device (CMS2) {
+ Name (_ADR, 0x00160000)
+ }
+
+ // Uncore 1 CMS0CHA24-27 Device
+ Device (CMS3) {
+ Name (_ADR, 0x00170000)
+ }
+
+ // Uncore 1 CHASADALL Device
+ Device (CDL0) {
+ Name (_ADR, 0x001D0000)
+ }
+
+ // Uncore 1 PCUCR Devices
+ Device (PCU0) {
+ Name (_ADR, 0x001E0000)
+ }
+
+ // Uncore 1 VCUCR Device
+ Device (VCU0) {
+ Name (_ADR, 0x001F0000)
+ }
+ }
+
+ // Socket 0 Root bridge (Stack 2)
+ Device (PC02) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x02)
+ Method (_BBN, 0, NotSerialized) {
+ return (BB02)
+ }
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR1A)
+ }
+ If (LEqual(AP02, One)) {
+ Return (AH1A)
+ }
+ Return (AR1A)
+ }
+
+ #include "PC02.asi"
+
+ // PCI Express Port 2A on PC02
+ Device (BR2A) {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR1B)
+ }
+ If (LEqual(AP02, One)) {
+ Return (AH1B)
+ }
+ Return (AR1B)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+
+ // EVA PCIe Uplink
+ Device (EPCU) {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x0B, 0x00})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR1C)
+ }
+ If (LEqual(AP02, One)) {
+ Return (AH1C)
+ }
+ Return (AR1C)
+ }
+
+ // EVA Virtual Switch Port 0
+ Device (VSP0) {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x0B, 0x00})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR1D)
+ }
+ If (LEqual(AP02, One)) {
+ Return (AH1D)
+ }
+ Return (AR1D)
+ }
+
+ // EVA CPM0
+ Device (CPM0) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // EVA Virtual Switch Port 1
+ Device (VSP1) {
+ Name (_ADR, 0x00010000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x0B, 0x00})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR1E)
+ }
+ If (LEqual(AP02, One)) {
+ Return (AH1E)
+ }
+ Return (AR1E)
+ }
+
+ // EVA CPM1
+ Device (CPM1) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // EVA Virtual Switch Port 2
+ Device (VSP2) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x0B, 0x00})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR1F)
+ }
+ If (LEqual(AP02, One)) {
+ Return (AH1F)
+ }
+ Return (AR1F)
+ }
+
+ // EVA CPM2
+ Device (CPM2) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // EVA Virtual Switch Port 3
+ Device (VSP3) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x0B, 0x00})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR20)
+ }
+ If (LEqual(AP02, One)) {
+ Return (AH20)
+ }
+ Return (AR20)
+ }
+
+ // EVA Fort Park 0
+ Device (FPK0) {
+ Name (_ADR, 0x00000000)
+ }
+
+ // EVA Fort Park 1
+ Device (FPK1) {
+ Name (_ADR, 0x00000001)
+ }
+
+ // EVA Fort Park 2
+ Device (FPK2) {
+ Name (_ADR, 0x00000002)
+ }
+
+ // EVA Fort Park 3
+ Device (FPK3) {
+ Name (_ADR, 0x00000003)
+ }
+ }
+ }
+ }
+
+ // PCI Express Port 2B on PC02
+ Device (BR2B) {
+ Name (_ADR, 0x00010000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR21)
+ }
+ If (LEqual(AP02, One)) {
+ Return (AH21)
+ }
+ Return (AR21)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+ }
+
+ // PCI Express Port 2C on PC02
+ Device (BR2C) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR22)
+ }
+ If (LEqual(AP02, One)) {
+ Return (AH22)
+ }
+ Return (AR22)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+ }
+
+ // PCI Express Port 2D on PC02
+ Device (BR2D) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR23)
+ }
+ If (LEqual(AP02, One)) {
+ Return (AH23)
+ }
+ Return (AR23)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+ }
+
+ // Uncore 2 M2MEM0 Device
+ Device (M2M0) {
+ Name (_ADR, 0x00080000)
+ }
+
+ // Uncore 2 M2MEM10 Device
+ Device (M2M1) {
+ Name (_ADR, 0x00090000)
+ }
+
+ // Uncore 2 MCMAIN Device
+ Device (MCM0) {
+ Name (_ADR, 0x000A0000)
+ }
+
+ // Uncore 2 MCDECS2 Device
+ Device (MCD0) {
+ Name (_ADR, 0x000B0000)
+ }
+
+ // Uncore 2 MCMAIN Device
+ Device (MCM1) {
+ Name (_ADR, 0x000C0000)
+ }
+
+ // Uncore 2 MCDECS12 Device
+ Device (MCD1) {
+ Name (_ADR, 0x000D0000)
+ }
+
+ // Uncore 2 Unicast MC0 DDRIO0 Device
+ Device (UMC0) {
+ Name (_ADR, 0x00160000)
+ }
+
+ // Uncore 2 Unicast MC1 DDRIO0 Device
+ Device (UMC1) {
+ Name (_ADR, 0x00170000)
+ }
+ }
+
+ // Socket 0 Root bridge (Stack 3)
+ Device (PC03) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x03)
+ Method (_BBN, 0, NotSerialized) {
+ return (BB03)
+ }
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR24)
+ }
+ If (LEqual(AP03, One)) {
+ Return (AH24)
+ }
+ Return (AR24)
+ }
+
+ #include "PC03.asi"
+
+ // PCI Express Port 3A on PC03
+ Device (BR3A) {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR25)
+ }
+ If (LEqual(AP03, One)) {
+ Return (AH25)
+ }
+ Return (AR25)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+ }
+
+ // PCI Express Port 3B on PC03
+ Device (BR3B) {
+ Name (_ADR, 0x00010000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR26)
+ }
+ If (LEqual(AP03, One)) {
+ Return (AH26)
+ }
+ Return (AR26)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+ }
+
+ // PCI Express Port 3C on PC03
+ Device (BR3C) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR27)
+ }
+ If (LEqual(AP03, One)) {
+ Return (AH27)
+ }
+ Return (AR27)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+ }
+
+ // PCI Express Port 3D on PC03
+ Device (BR3D) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR28)
+ }
+ If (LEqual(AP03, One)) {
+ Return (AH28)
+ }
+ Return (AR28)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+ }
+
+ // KTI0
+ Device (KTI0) {
+ Name (_ADR, 0x000E0000)
+ }
+
+ // KTI1
+ Device (KTI1) {
+ Name (_ADR, 0x000F0000)
+ }
+
+ // KTI2
+ Device (KTI2) {
+ Name (_ADR, 0x00100000)
+ }
+
+ // M3K0
+ Device (M3K0) {
+ Name (_ADR, 0x00120000)
+ }
+
+ // M2U0
+ Device (M2U0) {
+ Name (_ADR, 0x00150000)
+ }
+
+ // M2D0
+ Device (M2D0) {
+ Name (_ADR, 0x00160000)
+ }
+
+ // M20
+ Device (M20) {
+ Name (_ADR, 0x00170000)
+ }
+ }
+
+ // Socket 0 Root bridge (Stack 4)
+ Device (PC04) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x04)
+ Method (_BBN, 0, NotSerialized) {
+ return (BB04)
+ }
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR29)
+ }
+ If (LEqual(AP04, One)) {
+ Return (AH29)
+ }
+ Return (AR29)
+ }
+
+ #include "PC04.asi"
+
+ // PCI Express Port 4 on PC04
+ Device (MCP0) {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR2A)
+ }
+ If (LEqual(AP04, One)) {
+ Return (AH2A)
+ }
+ Return (AR2A)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ }
+ }
+
+ // Socket 0 Root bridge (Stack 5)
+ Device (PC05) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x05)
+ Method (_BBN, 0, NotSerialized) {
+ return (BB05)
+ }
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR2B)
+ }
+ If (LEqual(AP05, One)) {
+ Return (AH2B)
+ }
+ Return (AR2B)
+ }
+
+ #include "PC05.asi"
+
+ // PCI Express Port 5 on PC05
+ Device (MCP1) {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR2C)
+ }
+ If (LEqual(AP05, One)) {
+ Return (AH2C)
+ }
+ Return (AR2C)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ }
+ }
+
+ // Socket 1 Root bridge (Stack 0)
+ Device (PC06) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x06)
+ Method (_BBN, 0, NotSerialized) {
+ return (BB06)
+ }
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR2D)
+ }
+ If (LEqual(AP06, One)) {
+ Return (AH2D)
+ }
+ Return (AR2D)
+ }
+
+ #include "PC06.asi"
+ #include "Sck1Ejd.asi"
+
+ // PCI Express Port 0 on PC06
+ Device (QRP0) {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR2E)
+ }
+ If (LEqual(AP06, One)) {
+ Return (AH2E)
+ }
+ Return (AR2E)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC06Ejd.asi"
+ }
+
+ // CB3DMA on PC06
+ Device (CB1B) {
+ Name (_ADR, 0x00040001)
+ }
+
+ // CB3DMA on PC06
+ Device (CB1C) {
+ Name (_ADR, 0x00040002)
+ }
+
+ // CB3DMA on PC06
+ Device (CB1D) {
+ Name (_ADR, 0x00040003)
+ }
+
+ // CB3DMA on PC06
+ Device (CB1E) {
+ Name (_ADR, 0x00040004)
+ }
+
+ // CB3DMA on PC06
+ Device (CB1F) {
+ Name (_ADR, 0x00040005)
+ }
+
+ // CB3DMA on PC06
+ Device (CB1G) {
+ Name (_ADR, 0x00040006)
+ }
+
+ // CB3DMA on PC06
+ Device (CB1H) {
+ Name (_ADR, 0x00040007)
+ }
+
+ // IIOMISC on PC01
+ Device (IIM1) {
+ Name (_ADR, 0x00050000)
+ }
+
+ // Uncore 4 UBOX Device
+ Device (UBX1) {
+ Name (_ADR, 0x00080000)
+ }
+
+ // CB3DMA on PC06
+ Device (CB1A) {
+ Name (_ADR, 0x00040000)
+ }
+ }
+
+ // Socket 1 Root bridge (Stack 1)
+ Device (PC07) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x07)
+ Method (_BBN, 0, NotSerialized) {
+ return (BB07)
+ }
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR2F)
+ }
+ If (LEqual(AP07, One)) {
+ Return (AH2F)
+ }
+ Return (AR2F)
+ }
+
+ #include "PC07.asi"
+ #include "Sck1Ejd.asi"
+
+ // PCI Express Port 1A on PC07
+ Device (QR1A) {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR30)
+ }
+ If (LEqual(AP07, One)) {
+ Return (AH30)
+ }
+ Return (AR30)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC06Ejd.asi"
+ }
+
+ // PCI Express Port 1B on PC07
+ Device (QR1B) {
+ Name (_ADR, 0x00010000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR31)
+ }
+ If (LEqual(AP07, One)) {
+ Return (AH31)
+ }
+ Return (AR31)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC06Ejd.asi"
+ }
+
+ // PCI Express Port 1C on PC07
+ Device (QR1C) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR32)
+ }
+ If (LEqual(AP07, One)) {
+ Return (AH32)
+ }
+ Return (AR32)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC06Ejd.asi"
+ }
+
+ // PCI Express Port 1D on PC07
+ Device (QR1D) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR33)
+ }
+ If (LEqual(AP07, One)) {
+ Return (AH33)
+ }
+ Return (AR33)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC06Ejd.asi"
+ }
+
+ // Uncore 5 CHAUTIL0-7 Device
+ Device (CHB0) {
+ Name (_ADR, 0x00080000)
+ }
+
+ // Uncore 5 CHAUTIL8-15 Device
+ Device (CHB1) {
+ Name (_ADR, 0x00090000)
+ }
+
+ // Uncore 5 CHAUTIL16-23 Device
+ Device (CHB2) {
+ Name (_ADR, 0x000A0000)
+ }
+
+ // Uncore 5 CHAUTIL24-27 Device
+ Device (CHB3) {
+ Name (_ADR, 0x000B0000)
+ }
+
+ // Uncore 5 CHASAD0-7 Device
+ Device (CHB4) {
+ Name (_ADR, 0x000E0000)
+ }
+
+ // Uncore 5 CHASAD8-15 Device
+ Device (CHB5) {
+ Name (_ADR, 0x000F0000)
+ }
+
+ // Uncore 5 CHASAD16-23 Device
+ Device (CHB6) {
+ Name (_ADR, 0x00100000)
+ }
+
+ // Uncore 5 CHASAD24-27 Device
+ Device (CHB7) {
+ Name (_ADR, 0x00110000)
+ }
+
+ // Uncore 5 CMSCHA0-7 Device
+ Device (CMS4) {
+ Name (_ADR, 0x00140000)
+ }
+
+ // Uncore 5 CMS0CHA8-15 Device
+ Device (CMS5) {
+ Name (_ADR, 0x00150000)
+ }
+
+ // Uncore 5 CMS0CHA16-23 Device
+ Device (CMS6) {
+ Name (_ADR, 0x00160000)
+ }
+
+ // Uncore 5 CMS0CHA24-27 Device
+ Device (CMS7) {
+ Name (_ADR, 0x00170000)
+ }
+
+ // Uncore 5 CHASADALL Device
+ Device (CDL1) {
+ Name (_ADR, 0x001D0000)
+ }
+
+ // Uncore 5 PCUCR Devices
+ Device (PCU1) {
+ Name (_ADR, 0x001E0000)
+ }
+
+ // Uncore 5 VCUCR Device
+ Device (VCU1) {
+ Name (_ADR, 0x001F0000)
+ }
+ }
+
+ // Socket 1 Root bridge (Stack 2)
+ Device (PC08) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x08)
+ Method (_BBN, 0, NotSerialized) {
+ return (BB08)
+ }
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR34)
+ }
+ If (LEqual(AP08, One)) {
+ Return (AH34)
+ }
+ Return (AR34)
+ }
+
+ #include "PC08.asi"
+ #include "Sck1Ejd.asi"
+
+ // PCI Express Port 2A on PC08
+ Device (QR2A) {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR35)
+ }
+ If (LEqual(AP08, One)) {
+ Return (AH35)
+ }
+ Return (AR35)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC06Ejd.asi"
+ }
+
+ // PCI Express Port 2B on PC08
+ Device (QR2B) {
+ Name (_ADR, 0x00010000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR36)
+ }
+ If (LEqual(AP08, One)) {
+ Return (AH36)
+ }
+ Return (AR36)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC06Ejd.asi"
+ }
+
+ // PCI Express Port 2C on PC08
+ Device (QR2C) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR37)
+ }
+ If (LEqual(AP08, One)) {
+ Return (AH37)
+ }
+ Return (AR37)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC06Ejd.asi"
+ }
+
+ // PCI Express Port 2D on PC08
+ Device (QR2D) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR38)
+ }
+ If (LEqual(AP08, One)) {
+ Return (AH38)
+ }
+ Return (AR38)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC06Ejd.asi"
+ }
+
+ // Uncore 6 M2MEM0 Device
+ Device (M2M2) {
+ Name (_ADR, 0x00080000)
+ }
+
+ // Uncore 6 M2MEM10 Device
+ Device (M2M3) {
+ Name (_ADR, 0x00090000)
+ }
+
+ // Uncore 6 MCMAIN Device
+ Device (MCM2) {
+ Name (_ADR, 0x000A0000)
+ }
+
+ // Uncore 6 MCDECS2 Device
+ Device (MCD2) {
+ Name (_ADR, 0x000B0000)
+ }
+
+ // Uncore 6 MCMAIN Device
+ Device (MCM3) {
+ Name (_ADR, 0x000C0000)
+ }
+
+ // Uncore 6 MCDECS12 Device
+ Device (MCD3) {
+ Name (_ADR, 0x000D0000)
+ }
+
+ // Uncore 6 Unicast MC0 DDRIO0 Device
+ Device (UMC2) {
+ Name (_ADR, 0x00160000)
+ }
+
+ // Uncore 6 Unicast MC1 DDRIO0 Device
+ Device (UMC3) {
+ Name (_ADR, 0x00170000)
+ }
+ }
+
+ // Socket 1 Root bridge (Stack 3)
+ Device (PC09) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x09)
+ Method (_BBN, 0, NotSerialized) {
+ return (BB09)
+ }
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR39)
+ }
+ If (LEqual(AP09, One)) {
+ Return (AH39)
+ }
+ Return (AR39)
+ }
+
+ #include "PC09.asi"
+ #include "Sck1Ejd.asi"
+
+ // PCI Express Port 3A on PC09
+ Device (QR3A) {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR3A)
+ }
+ If (LEqual(AP09, One)) {
+ Return (AH3A)
+ }
+ Return (AR3A)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC06Ejd.asi"
+ }
+
+ // PCI Express Port 3B on PC09
+ Device (QR3B) {
+ Name (_ADR, 0x00010000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR3B)
+ }
+ If (LEqual(AP09, One)) {
+ Return (AH3B)
+ }
+ Return (AR3B)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC06Ejd.asi"
+ }
+
+ // PCI Express Port 3C on PC09
+ Device (QR3C) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR3C)
+ }
+ If (LEqual(AP09, One)) {
+ Return (AH3C)
+ }
+ Return (AR3C)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC06Ejd.asi"
+ }
+
+ // PCI Express Port 3D on PC09
+ Device (QR3D) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR3D)
+ }
+ If (LEqual(AP09, One)) {
+ Return (AH3D)
+ }
+ Return (AR3D)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC06Ejd.asi"
+ }
+
+ // Uncore 7 KTI3
+ Device (KTI3) {
+ Name (_ADR, 0x000E0000)
+ }
+
+ // Uncore 7 KTI4
+ Device (KTI4) {
+ Name (_ADR, 0x000F0000)
+ }
+
+ // Uncore 7 KTI5
+ Device (KTI5) {
+ Name (_ADR, 0x00100000)
+ }
+
+ // Uncore 7 M3K1
+ Device (M3K1) {
+ Name (_ADR, 0x00120000)
+ }
+
+ // Uncore 7 M2U1
+ Device (M2U1) {
+ Name (_ADR, 0x00150000)
+ }
+
+ // Uncore 7 M2D1
+ Device (M2D1) {
+ Name (_ADR, 0x00160000)
+ }
+
+ // Uncore 7 M21
+ Device (M21) {
+ Name (_ADR, 0x00170000)
+ }
+ }
+
+ // Socket 1 Root bridge (Stack 4)
+ Device (PC10) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x0A)
+ Method (_BBN, 0, NotSerialized) {
+ return (BB10)
+ }
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR3E)
+ }
+ If (LEqual(AP10, One)) {
+ Return (AH3E)
+ }
+ Return (AR3E)
+ }
+
+ #include "PC10.asi"
+ #include "Sck1Ejd.asi"
+
+ // PCI Express Port 13 on PC10
+ Device (MCP2) {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR3F)
+ }
+ If (LEqual(AP10, One)) {
+ Return (AH3F)
+ }
+ Return (AR3F)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC06Ejd.asi"
+ }
+ }
+
+ // Socket 1 Root bridge (Stack 5)
+ Device (PC11) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x0B)
+ Method (_BBN, 0, NotSerialized) {
+ return (BB11)
+ }
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR40)
+ }
+ If (LEqual(AP11, One)) {
+ Return (AH40)
+ }
+ Return (AR40)
+ }
+
+ #include "PC11.asi"
+ #include "Sck1Ejd.asi"
+
+ // PCI Express Port 14 on PC11
+ Device (MCP3) {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR41)
+ }
+ If (LEqual(AP11, One)) {
+ Return (AH41)
+ }
+ Return (AR41)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC06Ejd.asi"
+ }
+ }
+
+ // Socket 2 Root bridge (Stack 0)
+ Device (PC12) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x0C)
+ Method (_BBN, 0, NotSerialized) {
+ return (BB12)
+ }
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR42)
+ }
+ If (LEqual(AP12, One)) {
+ Return (AH42)
+ }
+ Return (AR42)
+ }
+
+ #include "PC12.asi"
+ #include "Sck2Ejd.asi"
+
+ // PCI Express Port 0 on PC12
+ Device (RRP0) {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR43)
+ }
+ If (LEqual(AP12, One)) {
+ Return (AH43)
+ }
+ Return (AR43)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC12Ejd.asi"
+ }
+
+ // CB3DMA on PC12
+ Device (CB2B) {
+ Name (_ADR, 0x00040001)
+ }
+
+ // CB3DMA on PC12
+ Device (CB2C) {
+ Name (_ADR, 0x00040002)
+ }
+
+ // CB3DMA on PC12
+ Device (CB2D) {
+ Name (_ADR, 0x00040003)
+ }
+
+ // CB3DMA on PC12
+ Device (CB2E) {
+ Name (_ADR, 0x00040004)
+ }
+
+ // CB3DMA on PC12
+ Device (CB2F) {
+ Name (_ADR, 0x00040005)
+ }
+
+ // CB3DMA on PC12
+ Device (CB2G) {
+ Name (_ADR, 0x00040006)
+ }
+
+ // CB3DMA on PC12
+ Device (CB2H) {
+ Name (_ADR, 0x00040007)
+ }
+
+ // IIOMISC on PC02
+ Device (IIM2) {
+ Name (_ADR, 0x00050000)
+ }
+
+ // Uncore 8 UBOX Device
+ Device (UBX2) {
+ Name (_ADR, 0x00080000)
+ }
+
+ // CB3DMA on PC12
+ Device (CB2A) {
+ Name (_ADR, 0x00040000)
+ }
+ }
+
+ // Socket 2 Root bridge (Stack 1)
+ Device (PC13) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x0D)
+ Method (_BBN, 0, NotSerialized) {
+ return (BB13)
+ }
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR44)
+ }
+ If (LEqual(AP13, One)) {
+ Return (AH44)
+ }
+ Return (AR44)
+ }
+
+ #include "PC13.asi"
+ #include "Sck2Ejd.asi"
+
+ // PCI Express Port 1A on PC13
+ Device (RR1A) {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR45)
+ }
+ If (LEqual(AP13, One)) {
+ Return (AH45)
+ }
+ Return (AR45)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC12Ejd.asi"
+ }
+
+ // PCI Express Port 1B on PC13
+ Device (RR1B) {
+ Name (_ADR, 0x00010000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR46)
+ }
+ If (LEqual(AP13, One)) {
+ Return (AH46)
+ }
+ Return (AR46)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC12Ejd.asi"
+ }
+
+ // PCI Express Port 1C on PC13
+ Device (RR1C) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR47)
+ }
+ If (LEqual(AP13, One)) {
+ Return (AH47)
+ }
+ Return (AR47)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC12Ejd.asi"
+ }
+
+ // PCI Express Port 1D on PC13
+ Device (RR1D) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR48)
+ }
+ If (LEqual(AP13, One)) {
+ Return (AH48)
+ }
+ Return (AR48)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC12Ejd.asi"
+ }
+
+ // Uncore 9 CHAUTIL0-7 Device
+ Device (CHC0) {
+ Name (_ADR, 0x00080000)
+ }
+
+ // Uncore 9 CHAUTIL8-15 Device
+ Device (CHC1) {
+ Name (_ADR, 0x00090000)
+ }
+
+ // Uncore 9 CHAUTIL16-23 Device
+ Device (CHC2) {
+ Name (_ADR, 0x000A0000)
+ }
+
+ // Uncore 9 CHAUTIL24-27 Device
+ Device (CHC3) {
+ Name (_ADR, 0x000B0000)
+ }
+
+ // Uncore 9 CHASAD0-7 Device
+ Device (CHC4) {
+ Name (_ADR, 0x000E0000)
+ }
+
+ // Uncore 9 CHASAD8-15 Device
+ Device (CHC5) {
+ Name (_ADR, 0x000F0000)
+ }
+
+ // Uncore 9 CHASAD16-23 Device
+ Device (CHC6) {
+ Name (_ADR, 0x00100000)
+ }
+
+ // Uncore 9 CHASAD24-27 Device
+ Device (CHC7) {
+ Name (_ADR, 0x00110000)
+ }
+
+ // Uncore 9 CMSCHA0-7 Device
+ Device (CMS8) {
+ Name (_ADR, 0x00140000)
+ }
+
+ // Uncore 9 CMS0CHA8-15 Device
+ Device (CMS9) {
+ Name (_ADR, 0x00150000)
+ }
+
+ // Uncore 9 CHASADALL Device
+ Device (CDL2) {
+ Name (_ADR, 0x001D0000)
+ }
+
+ // Uncore 9 PCUCR Devices
+ Device (PCU2) {
+ Name (_ADR, 0x001E0000)
+ }
+
+ // Uncore 9 VCUCR Device
+ Device (VCU2) {
+ Name (_ADR, 0x001F0000)
+ }
+ }
+
+ // Socket 2 Root bridge (Stack 2)
+ Device (PC14) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x0E)
+ Method (_BBN, 0, NotSerialized) {
+ return (BB14)
+ }
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR49)
+ }
+ If (LEqual(AP14, One)) {
+ Return (AH49)
+ }
+ Return (AR49)
+ }
+
+ #include "PC14.asi"
+ #include "Sck2Ejd.asi"
+
+ // PCI Express Port 2A on PC14
+ Device (RR2A) {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR4A)
+ }
+ If (LEqual(AP14, One)) {
+ Return (AH4A)
+ }
+ Return (AR4A)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC12Ejd.asi"
+ }
+
+ // PCI Express Port 2B on PC14
+ Device (RR2B) {
+ Name (_ADR, 0x00010000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR4B)
+ }
+ If (LEqual(AP14, One)) {
+ Return (AH4B)
+ }
+ Return (AR4B)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC12Ejd.asi"
+ }
+
+ // PCI Express Port 2C on PC14
+ Device (RR2C) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR4C)
+ }
+ If (LEqual(AP14, One)) {
+ Return (AH4C)
+ }
+ Return (AR4C)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC12Ejd.asi"
+ }
+
+ // PCI Express Port 2D on PC14
+ Device (RR2D) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR4D)
+ }
+ If (LEqual(AP14, One)) {
+ Return (AH4D)
+ }
+ Return (AR4D)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC12Ejd.asi"
+ }
+
+ // Uncore 10 M2MEM0 Device
+ Device (M2M4) {
+ Name (_ADR, 0x00080000)
+ }
+
+ // Uncore 10 M2MEM10 Device
+ Device (M2M5) {
+ Name (_ADR, 0x00090000)
+ }
+
+ // Uncore 10 MCMAIN Device
+ Device (MCM4) {
+ Name (_ADR, 0x000A0000)
+ }
+
+ // Uncore 10 MCDECS2 Device
+ Device (MCD4) {
+ Name (_ADR, 0x000B0000)
+ }
+
+ // Uncore 10 MCMAIN Device
+ Device (MCM5) {
+ Name (_ADR, 0x000C0000)
+ }
+
+ // Uncore 10 MCDECS12 Device
+ Device (MCD5) {
+ Name (_ADR, 0x000D0000)
+ }
+
+ // Uncore 10 Unicast MC0 DDRIO0 Device
+ Device (UMC4) {
+ Name (_ADR, 0x00160000)
+ }
+
+ // Uncore 10 Unicast MC1 DDRIO0 Device
+ Device (UMC5) {
+ Name (_ADR, 0x00170000)
+ }
+ }
+
+ // Socket 2 Root bridge (Stack 3)
+ Device (PC15) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x0F)
+ Method (_BBN, 0, NotSerialized) {
+ return (BB15)
+ }
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR4E)
+ }
+ If (LEqual(AP15, One)) {
+ Return (AH4E)
+ }
+ Return (AR4E)
+ }
+
+ #include "PC15.asi"
+ #include "Sck2Ejd.asi"
+
+ // PCI Express Port 3A on PC15
+ Device (RR3A) {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR4F)
+ }
+ If (LEqual(AP15, One)) {
+ Return (AH4F)
+ }
+ Return (AR4F)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC12Ejd.asi"
+ }
+
+ // PCI Express Port 3B on PC15
+ Device (RR3B) {
+ Name (_ADR, 0x00010000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR50)
+ }
+ If (LEqual(AP15, One)) {
+ Return (AH50)
+ }
+ Return (AR50)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC12Ejd.asi"
+ }
+
+ // PCI Express Port 3C on PC15
+ Device (RR3C) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR51)
+ }
+ If (LEqual(AP15, One)) {
+ Return (AH51)
+ }
+ Return (AR51)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC12Ejd.asi"
+ }
+
+ // PCI Express Port 3D on PC15
+ Device (RR3D) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR52)
+ }
+ If (LEqual(AP15, One)) {
+ Return (AH52)
+ }
+ Return (AR52)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC12Ejd.asi"
+ }
+
+ // Uncore 11 KTI6
+ Device (KTI6) {
+ Name (_ADR, 0x000E0000)
+ }
+
+ // Uncore 11 KTI7
+ Device (KTI7) {
+ Name (_ADR, 0x000F0000)
+ }
+
+ // Uncore 11 KTI8
+ Device (KTI8) {
+ Name (_ADR, 0x00100000)
+ }
+
+ // Uncore 11 M3K2
+ Device (M3K2) {
+ Name (_ADR, 0x00120000)
+ }
+
+ // Uncore 11 M2U2
+ Device (M2U2) {
+ Name (_ADR, 0x00150000)
+ }
+
+ // Uncore 11 M2D2
+ Device (M2D2) {
+ Name (_ADR, 0x00160000)
+ }
+
+ // Uncore 11 M22
+ Device (M22) {
+ Name (_ADR, 0x00170000)
+ }
+ }
+
+ // Socket 2 Root bridge (Stack 4)
+ Device (PC16) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x10)
+ Method (_BBN, 0, NotSerialized) {
+ return (BB16)
+ }
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR53)
+ }
+ If (LEqual(AP16, One)) {
+ Return (AH53)
+ }
+ Return (AR53)
+ }
+
+ #include "PC16.asi"
+ #include "Sck2Ejd.asi"
+
+ // PCI Express Port 4 on PC16
+ Device (MCP4) {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR54)
+ }
+ If (LEqual(AP16, One)) {
+ Return (AH54)
+ }
+ Return (AR54)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC12Ejd.asi"
+ }
+ }
+
+ // Socket 2 Root bridge (Stack 5)
+ Device (PC17) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x11)
+ Method (_BBN, 0, NotSerialized) {
+ return (BB17)
+ }
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR55)
+ }
+ If (LEqual(AP17, One)) {
+ Return (AH55)
+ }
+ Return (AR55)
+ }
+
+ #include "PC17.asi"
+ #include "Sck2Ejd.asi"
+
+ // PCI Express Port 5 on PC17
+ Device (MCP5) {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR56)
+ }
+ If (LEqual(AP17, One)) {
+ Return (AH56)
+ }
+ Return (AR56)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC12Ejd.asi"
+ }
+ }
+
+ // Socket 3 Root bridge (Stack 0)
+ Device (PC18) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x12)
+ Method (_BBN, 0, NotSerialized) {
+ return (BB18)
+ }
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR57)
+ }
+ If (LEqual(AP18, One)) {
+ Return (AH57)
+ }
+ Return (AR57)
+ }
+
+ #include "PC18.asi"
+ #include "Sck3Ejd.asi"
+
+ // PCI Express Port 0 on PC18
+ Device (SRP0) {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR58)
+ }
+ If (LEqual(AP18, One)) {
+ Return (AH58)
+ }
+ Return (AR58)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC18Ejd.asi"
+ }
+
+ // CB3DMA on PC18
+ Device (CB3B) {
+ Name (_ADR, 0x00040001)
+ }
+
+ // CB3DMA on PC18
+ Device (CB3C) {
+ Name (_ADR, 0x00040002)
+ }
+
+ // CB3DMA on PC18
+ Device (CB3D) {
+ Name (_ADR, 0x00040003)
+ }
+
+ // CB3DMA on PC18
+ Device (CB3E) {
+ Name (_ADR, 0x00040004)
+ }
+
+ // CB3DMA on PC18
+ Device (CB3F) {
+ Name (_ADR, 0x00040005)
+ }
+
+ // CB3DMA on PC18
+ Device (CB3G) {
+ Name (_ADR, 0x00040006)
+ }
+
+ // CB3DMA on PC18
+ Device (CB3H) {
+ Name (_ADR, 0x00040007)
+ }
+
+ // IIOMISC on PC03
+ Device (IIM3) {
+ Name (_ADR, 0x00050000)
+ }
+
+ // Uncore 12 UBOX Device
+ Device (UBX3) {
+ Name (_ADR, 0x00080000)
+ }
+
+ // CB3DMA on PC18
+ Device (CB3A) {
+ Name (_ADR, 0x00040000)
+ }
+ }
+
+ // Socket 3 Root bridge (Stack 1)
+ Device (PC19) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x13)
+ Method (_BBN, 0, NotSerialized) {
+ return (BB19)
+ }
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR59)
+ }
+ If (LEqual(AP19, One)) {
+ Return (AH59)
+ }
+ Return (AR59)
+ }
+
+ #include "PC19.asi"
+ #include "Sck3Ejd.asi"
+
+ // PCI Express Port 1A on PC19
+ Device (SR1A) {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR5A)
+ }
+ If (LEqual(AP19, One)) {
+ Return (AH5A)
+ }
+ Return (AR5A)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC18Ejd.asi"
+ }
+
+ // PCI Express Port 1B on PC19
+ Device (SR1B) {
+ Name (_ADR, 0x00010000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR5B)
+ }
+ If (LEqual(AP19, One)) {
+ Return (AH5B)
+ }
+ Return (AR5B)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC18Ejd.asi"
+ }
+
+ // PCI Express Port 1C on PC19
+ Device (SR1C) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR5C)
+ }
+ If (LEqual(AP19, One)) {
+ Return (AH5C)
+ }
+ Return (AR5C)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC18Ejd.asi"
+ }
+
+ // PCI Express Port 1D on PC19
+ Device (SR1D) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR5D)
+ }
+ If (LEqual(AP19, One)) {
+ Return (AH5D)
+ }
+ Return (AR5D)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC18Ejd.asi"
+ }
+
+ // Uncore 13 CHAUTIL0-7 Device
+ Device (CHD0) {
+ Name (_ADR, 0x00080000)
+ }
+
+ // Uncore 13 CHAUTIL8-15 Device
+ Device (CHD1) {
+ Name (_ADR, 0x00090000)
+ }
+
+ // Uncore 13 CHAUTIL16-23 Device
+ Device (CHD2) {
+ Name (_ADR, 0x000A0000)
+ }
+
+ // Uncore 13 CHAUTIL24-27 Device
+ Device (CHD3) {
+ Name (_ADR, 0x000B0000)
+ }
+
+ // Uncore 13 CHASAD0-7 Device
+ Device (CHD4) {
+ Name (_ADR, 0x000E0000)
+ }
+
+ // Uncore 13 CHASAD8-15 Device
+ Device (CHD5) {
+ Name (_ADR, 0x000F0000)
+ }
+
+ // Uncore 13 CHASAD16-23 Device
+ Device (CHD6) {
+ Name (_ADR, 0x00100000)
+ }
+
+ // Uncore 13 CHASAD24-27 Device
+ Device (CHD7) {
+ Name (_ADR, 0x00110000)
+ }
+
+ // Uncore 13 CMSCHA0-7 Device
+ Device (CM12) {
+ Name (_ADR, 0x00140000)
+ }
+
+ // Uncore 13 CMS0CHA8-15 Device
+ Device (CM13) {
+ Name (_ADR, 0x00150000)
+ }
+
+ // Uncore 13 CMS0CHA16-23 Device
+ Device (CM14) {
+ Name (_ADR, 0x00160000)
+ }
+
+ // Uncore 13 CMS0CHA24-27 Device
+ Device (CM15) {
+ Name (_ADR, 0x00170000)
+ }
+
+ // Uncore 13 CHASADALL Device
+ Device (CDL3) {
+ Name (_ADR, 0x001D0000)
+ }
+
+ // Uncore 13 PCUCR Devices
+ Device (PCU3) {
+ Name (_ADR, 0x001E0000)
+ }
+
+ // Uncore 13 VCUCR Device
+ Device (VCU3) {
+ Name (_ADR, 0x001F0000)
+ }
+ }
+
+ // Socket 3 Root bridge (Stack 2)
+ Device (PC20) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x14)
+ Method (_BBN, 0, NotSerialized) {
+ return (BB20)
+ }
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR5E)
+ }
+ If (LEqual(AP20, One)) {
+ Return (AH5E)
+ }
+ Return (AR5E)
+ }
+
+ #include "PC20.asi"
+ #include "Sck3Ejd.asi"
+
+ // PCI Express Port 2A on PC20
+ Device (SR2A) {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR5F)
+ }
+ If (LEqual(AP20, One)) {
+ Return (AH5F)
+ }
+ Return (AR5F)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC18Ejd.asi"
+ }
+
+ // PCI Express Port 2B on PC20
+ Device (SR2B) {
+ Name (_ADR, 0x00010000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR60)
+ }
+ If (LEqual(AP20, One)) {
+ Return (AH60)
+ }
+ Return (AR60)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC18Ejd.asi"
+ }
+
+ // PCI Express Port 2C on PC20
+ Device (SR2C) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR61)
+ }
+ If (LEqual(AP20, One)) {
+ Return (AH61)
+ }
+ Return (AR61)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC18Ejd.asi"
+ }
+
+ // PCI Express Port 2D on PC20
+ Device (SR2D) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR62)
+ }
+ If (LEqual(AP20, One)) {
+ Return (AH62)
+ }
+ Return (AR62)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC18Ejd.asi"
+ }
+
+ // Uncore 14 M2MEM0 Device
+ Device (M2M6) {
+ Name (_ADR, 0x00080000)
+ }
+
+ // Uncore 14 M2MEM10 Device
+ Device (M2M7) {
+ Name (_ADR, 0x00090000)
+ }
+
+ // Uncore 14 MCMAIN Device
+ Device (MCM6) {
+ Name (_ADR, 0x000A0000)
+ }
+
+ // Uncore 14 MCDECS2 Device
+ Device (MCD6) {
+ Name (_ADR, 0x000B0000)
+ }
+
+ // Uncore 14 MCMAIN Device
+ Device (MCM7) {
+ Name (_ADR, 0x000C0000)
+ }
+
+ // Uncore 14 MCDECS12 Device
+ Device (MCD7) {
+ Name (_ADR, 0x000D0000)
+ }
+
+ // Uncore 14 Unicast MC0 DDRIO0 Device
+ Device (UMC6) {
+ Name (_ADR, 0x00160000)
+ }
+
+ // Uncore 14 Unicast MC1 DDRIO0 Device
+ Device (UMC7) {
+ Name (_ADR, 0x00170000)
+ }
+ }
+
+ // Socket 3 Root bridge (Stack 3)
+ Device (PC21) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x15)
+ Method (_BBN, 0, NotSerialized) {
+ return (BB21)
+ }
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR63)
+ }
+ If (LEqual(AP21, One)) {
+ Return (AH63)
+ }
+ Return (AR63)
+ }
+
+ #include "PC21.asi"
+ #include "Sck3Ejd.asi"
+
+ // PCI Express Port 3A on PC21
+ Device (SR3A) {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR64)
+ }
+ If (LEqual(AP21, One)) {
+ Return (AH64)
+ }
+ Return (AR64)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC18Ejd.asi"
+ }
+
+ // PCI Express Port 3B on PC21
+ Device (SR3B) {
+ Name (_ADR, 0x00010000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR65)
+ }
+ If (LEqual(AP21, One)) {
+ Return (AH65)
+ }
+ Return (AR65)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC18Ejd.asi"
+ }
+
+ // PCI Express Port 3C on PC21
+ Device (SR3C) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR66)
+ }
+ If (LEqual(AP21, One)) {
+ Return (AH66)
+ }
+ Return (AR66)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC18Ejd.asi"
+ }
+
+ // PCI Express Port 3D on PC21
+ Device (SR3D) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR67)
+ }
+ If (LEqual(AP21, One)) {
+ Return (AH67)
+ }
+ Return (AR67)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC18Ejd.asi"
+ }
+
+ // Uncore 15 KTI9
+ Device (KTI9) {
+ Name (_ADR, 0x000E0000)
+ }
+
+ // Uncore 15 KT10
+ Device (KT10) {
+ Name (_ADR, 0x000F0000)
+ }
+
+ // Uncore 15 KT11
+ Device (KT11) {
+ Name (_ADR, 0x00100000)
+ }
+
+ // Uncore 15 M3K3
+ Device (M3K3) {
+ Name (_ADR, 0x00120000)
+ }
+
+ // Uncore 15 M2U3
+ Device (M2U3) {
+ Name (_ADR, 0x00150000)
+ }
+
+ // Uncore 15 M2D3
+ Device (M2D3) {
+ Name (_ADR, 0x00160000)
+ }
+
+ // Uncore 15 M23
+ Device (M23) {
+ Name (_ADR, 0x00170000)
+ }
+ }
+
+ // Socket 3 Root bridge (Stack 4)
+ Device (PC22) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x16)
+ Method (_BBN, 0, NotSerialized) {
+ return (BB22)
+ }
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR68)
+ }
+ If (LEqual(AP22, One)) {
+ Return (AH68)
+ }
+ Return (AR68)
+ }
+
+ #include "PC22.asi"
+ #include "Sck3Ejd.asi"
+
+ // PCI Express Port 4 on PC22
+ Device (MCP6) {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR69)
+ }
+ If (LEqual(AP22, One)) {
+ Return (AH69)
+ }
+ Return (AR69)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC18Ejd.asi"
+ }
+ }
+
+ // Socket 3 Root bridge (Stack 5)
+ Device (PC23) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x17)
+ Method (_BBN, 0, NotSerialized) {
+ return (BB23)
+ }
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR6A)
+ }
+ If (LEqual(AP23, One)) {
+ Return (AH6A)
+ }
+ Return (AR6A)
+ }
+
+ #include "PC23.asi"
+ #include "Sck3Ejd.asi"
+
+ // PCI Express Port 5 on PC23
+ Device (MCP7) {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR6B)
+ }
+ If (LEqual(AP23, One)) {
+ Return (AH6B)
+ }
+ Return (AR6B)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC18Ejd.asi"
+
+ }
+ }
+}
+
+Scope (\_GPE) {
+ // [BR1A]: PCI Express Port 1A on PC01
+ // [BR1B]: PCI Express Port 1B on PC01
+ // [BR1C]: PCI Express Port 1C on PC01
+ // [BR1D]: PCI Express Port 1D on PC01
+ // [BR2A]: PCI Express Port 2A on PC02
+ // [BR2B]: PCI Express Port 2B on PC02
+ // [BR2C]: PCI Express Port 2C on PC02
+ // [BR2D]: PCI Express Port 2D on PC02
+ // [BR3A]: PCI Express Port 3A on PC03
+ // [BR3B]: PCI Express Port 3B on PC03
+ // [BR3C]: PCI Express Port 3C on PC03
+ // [BR3D]: PCI Express Port 3D on PC03
+ // [MCP0]: PCI Express Port 4 on PC04
+ // [MCP1]: PCI Express Port 5 on PC05
+ // [QRP0]: PCI Express Port 0 on PC06
+ // [QR1A]: PCI Express Port 1A on PC07
+ // [QR1B]: PCI Express Port 1B on PC07
+ // [QR1C]: PCI Express Port 1C on PC07
+ // [QR1D]: PCI Express Port 1D on PC07
+ // [QR2A]: PCI Express Port 2A on PC08
+ // [QR2B]: PCI Express Port 2B on PC08
+ // [QR2C]: PCI Express Port 2C on PC08
+ // [QR2D]: PCI Express Port 2D on PC08
+ // [QR3A]: PCI Express Port 3A on PC09
+ // [QR3B]: PCI Express Port 3B on PC09
+ // [QR3C]: PCI Express Port 3C on PC09
+ // [QR3D]: PCI Express Port 3D on PC09
+ // [MCP2]: PCI Express Port 13 on PC10
+ // [MCP3]: PCI Express Port 14 on PC11
+ // [RRP0]: PCI Express Port 0 on PC12
+ // [RR1A]: PCI Express Port 1A on PC13
+ // [RR1B]: PCI Express Port 1B on PC13
+ // [RR1C]: PCI Express Port 1C on PC13
+ // [RR1D]: PCI Express Port 1D on PC13
+ // [RR2A]: PCI Express Port 2A on PC14
+ // [RR2B]: PCI Express Port 2B on PC14
+ // [RR2C]: PCI Express Port 2C on PC14
+ // [RR2D]: PCI Express Port 2D on PC14
+ // [RR3A]: PCI Express Port 3A on PC15
+ // [RR3B]: PCI Express Port 3B on PC15
+ // [RR3C]: PCI Express Port 3C on PC15
+ // [RR3D]: PCI Express Port 3D on PC15
+ // [MCP4]: PCI Express Port 4 on PC16
+ // [MCP5]: PCI Express Port 5 on PC17
+ // [SRP0]: PCI Express Port 0 on PC18
+ // [SR1A]: PCI Express Port 1A on PC19
+ // [SR1B]: PCI Express Port 1B on PC19
+ // [SR1C]: PCI Express Port 1C on PC19
+ // [SR1D]: PCI Express Port 1D on PC19
+ // [SR2A]: PCI Express Port 2A on PC20
+ // [SR2B]: PCI Express Port 2B on PC20
+ // [SR2C]: PCI Express Port 2C on PC20
+ // [SR2D]: PCI Express Port 2D on PC20
+ // [SR3A]: PCI Express Port 3A on PC21
+ // [SR3B]: PCI Express Port 3B on PC21
+ // [SR3C]: PCI Express Port 3C on PC21
+ // [SR3D]: PCI Express Port 3D on PC21
+ // [MCP6]: PCI Express Port 4 on PC22
+ // [MCP7]: PCI Express Port 5 on PC23
+ Method (_L09, 0x0, NotSerialized) {
+ #include "Gpe.asl"
+ Notify (\_SB.PC01.BR1A, 0x02)
+ Notify (\_SB.PC01.BR1B, 0x02)
+ Notify (\_SB.PC01.BR1C, 0x02)
+ Notify (\_SB.PC01.BR1D, 0x02)
+ Notify (\_SB.PC02.BR2A, 0x02)
+ Notify (\_SB.PC02.BR2B, 0x02)
+ Notify (\_SB.PC02.BR2C, 0x02)
+ Notify (\_SB.PC02.BR2D, 0x02)
+ Notify (\_SB.PC03.BR3A, 0x02)
+ Notify (\_SB.PC03.BR3B, 0x02)
+ Notify (\_SB.PC03.BR3C, 0x02)
+ Notify (\_SB.PC03.BR3D, 0x02)
+ Notify (\_SB.PC04.MCP0, 0x02)
+ Notify (\_SB.PC05.MCP1, 0x02)
+ Notify (\_SB.PC06.QRP0, 0x02)
+ Notify (\_SB.PC07.QR1A, 0x02)
+ Notify (\_SB.PC07.QR1B, 0x02)
+ Notify (\_SB.PC07.QR1C, 0x02)
+ Notify (\_SB.PC07.QR1D, 0x02)
+ Notify (\_SB.PC08.QR2A, 0x02)
+ Notify (\_SB.PC08.QR2B, 0x02)
+ Notify (\_SB.PC08.QR2C, 0x02)
+ Notify (\_SB.PC08.QR2D, 0x02)
+ Notify (\_SB.PC09.QR3A, 0x02)
+ Notify (\_SB.PC09.QR3B, 0x02)
+ Notify (\_SB.PC09.QR3C, 0x02)
+ Notify (\_SB.PC09.QR3D, 0x02)
+ Notify (\_SB.PC10.MCP2, 0x02)
+ Notify (\_SB.PC11.MCP3, 0x02)
+ Notify (\_SB.PC12.RRP0, 0x02)
+ Notify (\_SB.PC13.RR1A, 0x02)
+ Notify (\_SB.PC13.RR1B, 0x02)
+ Notify (\_SB.PC13.RR1C, 0x02)
+ Notify (\_SB.PC13.RR1D, 0x02)
+ Notify (\_SB.PC14.RR2A, 0x02)
+ Notify (\_SB.PC14.RR2B, 0x02)
+ Notify (\_SB.PC14.RR2C, 0x02)
+ Notify (\_SB.PC14.RR2D, 0x02)
+ Notify (\_SB.PC15.RR3A, 0x02)
+ Notify (\_SB.PC15.RR3B, 0x02)
+ Notify (\_SB.PC15.RR3C, 0x02)
+ Notify (\_SB.PC15.RR3D, 0x02)
+ Notify (\_SB.PC16.MCP4, 0x02)
+ Notify (\_SB.PC17.MCP5, 0x02)
+ Notify (\_SB.PC18.SRP0, 0x02)
+ Notify (\_SB.PC19.SR1A, 0x02)
+ Notify (\_SB.PC19.SR1B, 0x02)
+ Notify (\_SB.PC19.SR1C, 0x02)
+ Notify (\_SB.PC19.SR1D, 0x02)
+ Notify (\_SB.PC20.SR2A, 0x02)
+ Notify (\_SB.PC20.SR2B, 0x02)
+ Notify (\_SB.PC20.SR2C, 0x02)
+ Notify (\_SB.PC20.SR2D, 0x02)
+ Notify (\_SB.PC21.SR3A, 0x02)
+ Notify (\_SB.PC21.SR3B, 0x02)
+ Notify (\_SB.PC21.SR3C, 0x02)
+ Notify (\_SB.PC21.SR3D, 0x02)
+ Notify (\_SB.PC22.MCP6, 0x02)
+ Notify (\_SB.PC23.MCP7, 0x02)
+ }
+
+ // [EPCU]: EVA PCIe Uplink
+ // [VSP0]: EVA Virtual Switch Port 0
+ // [VSP1]: EVA Virtual Switch Port 1
+ // [VSP2]: EVA Virtual Switch Port 2
+ // [VSP3]: EVA Virtual Switch Port 3
+ Method (_L0B, 0x0, NotSerialized) {
+ Notify (\_SB.PC02.BR2A.EPCU, 0x02)
+ Notify (\_SB.PC02.BR2A.EPCU.VSP0, 0x02)
+ Notify (\_SB.PC02.BR2A.EPCU.VSP1, 0x02)
+ Notify (\_SB.PC02.BR2A.EPCU.VSP2, 0x02)
+ Notify (\_SB.PC02.BR2A.EPCU.VSP3, 0x02)
+ }
+
+}
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck1Ejd.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck1Ejd.asi new file mode 100644 index 0000000000..4bb04b1e23 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck1Ejd.asi @@ -0,0 +1,15 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ // Eject device if SCK1 is removed.
+ Name(_EJD,"\\_SB.SCK1") // Dependent on SCK1
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck2Ejd.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck2Ejd.asi new file mode 100644 index 0000000000..46da40ef3f --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck2Ejd.asi @@ -0,0 +1,15 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ // Eject device if SCK2 is removed.
+ Name(_EJD,"\\_SB.SCK2") // Dependent on SCK2
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck3Ejd.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck3Ejd.asi new file mode 100644 index 0000000000..2c8608960b --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck3Ejd.asi @@ -0,0 +1,15 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ // Eject device if SCK3 is removed.
+ Name(_EJD,"\\_SB.SCK3") // Dependent on SCK3
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore0.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore0.asi new file mode 100644 index 0000000000..c07eb6d288 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore0.asi @@ -0,0 +1,39 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (PRU0, Package() {
+ Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }
+ })
+
+ Name (ARU0, Package() {
+ Package() { 0x0008FFFF, 0, 0, 16 },
+ Package() { 0x0008FFFF, 1, 0, 17 },
+ Package() { 0x0008FFFF, 2, 0, 18 },
+ Package() { 0x0008FFFF, 3, 0, 19 }
+ })
+
+
+ Device (UNC0) {
+ Name (_UID, "UNCORE0")
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PRU0)
+ }
+ Return (ARU0)
+ }
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore1.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore1.asi new file mode 100644 index 0000000000..f404ff64c0 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore1.asi @@ -0,0 +1,181 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (PRU1, Package() {
+ Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+
+ Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x0011FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0011FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0011FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0011FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x0014FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0014FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0014FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0014FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x001DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x001DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x001DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x001DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x001EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x001EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x001EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x001EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x001FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x001FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x001FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x001FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+ })
+
+ Name (ARU1, Package() {
+ Package() { 0x0008FFFF, 0, 0, 16 },
+ Package() { 0x0008FFFF, 1, 0, 17 },
+ Package() { 0x0008FFFF, 2, 0, 18 },
+ Package() { 0x0008FFFF, 3, 0, 19 },
+
+ Package() { 0x0009FFFF, 0, 0, 16 },
+ Package() { 0x0009FFFF, 1, 0, 17 },
+ Package() { 0x0009FFFF, 2, 0, 18 },
+ Package() { 0x0009FFFF, 3, 0, 19 },
+
+ Package() { 0x000AFFFF, 0, 0, 16 },
+ Package() { 0x000AFFFF, 1, 0, 17 },
+ Package() { 0x000AFFFF, 2, 0, 18 },
+ Package() { 0x000AFFFF, 3, 0, 19 },
+
+ Package() { 0x000BFFFF, 0, 0, 16 },
+ Package() { 0x000BFFFF, 1, 0, 17 },
+ Package() { 0x000BFFFF, 2, 0, 18 },
+ Package() { 0x000BFFFF, 3, 0, 19 },
+
+ Package() { 0x000EFFFF, 0, 0, 16 },
+ Package() { 0x000EFFFF, 1, 0, 17 },
+ Package() { 0x000EFFFF, 2, 0, 18 },
+ Package() { 0x000EFFFF, 3, 0, 19 },
+
+ Package() { 0x000FFFFF, 0, 0, 16 },
+ Package() { 0x000FFFFF, 1, 0, 17 },
+ Package() { 0x000FFFFF, 2, 0, 18 },
+ Package() { 0x000FFFFF, 3, 0, 19 },
+
+ Package() { 0x0010FFFF, 0, 0, 16 },
+ Package() { 0x0010FFFF, 1, 0, 17 },
+ Package() { 0x0010FFFF, 2, 0, 18 },
+ Package() { 0x0010FFFF, 3, 0, 19 },
+
+ Package() { 0x0011FFFF, 0, 0, 16 },
+ Package() { 0x0011FFFF, 1, 0, 17 },
+ Package() { 0x0011FFFF, 2, 0, 18 },
+ Package() { 0x0011FFFF, 3, 0, 19 },
+
+ Package() { 0x0014FFFF, 0, 0, 16 },
+ Package() { 0x0014FFFF, 1, 0, 17 },
+ Package() { 0x0014FFFF, 2, 0, 18 },
+ Package() { 0x0014FFFF, 3, 0, 19 },
+
+ Package() { 0x0015FFFF, 0, 0, 16 },
+ Package() { 0x0015FFFF, 1, 0, 17 },
+ Package() { 0x0015FFFF, 2, 0, 18 },
+ Package() { 0x0015FFFF, 3, 0, 19 },
+
+ Package() { 0x0016FFFF, 0, 0, 16 },
+ Package() { 0x0016FFFF, 1, 0, 17 },
+ Package() { 0x0016FFFF, 2, 0, 18 },
+ Package() { 0x0016FFFF, 3, 0, 19 },
+
+ Package() { 0x0017FFFF, 0, 0, 16 },
+ Package() { 0x0017FFFF, 1, 0, 17 },
+ Package() { 0x0017FFFF, 2, 0, 18 },
+ Package() { 0x0017FFFF, 3, 0, 19 },
+
+ Package() { 0x001DFFFF, 0, 0, 16 },
+ Package() { 0x001DFFFF, 1, 0, 17 },
+ Package() { 0x001DFFFF, 2, 0, 18 },
+ Package() { 0x001DFFFF, 3, 0, 19 },
+
+ Package() { 0x001EFFFF, 0, 0, 16 },
+ Package() { 0x001EFFFF, 1, 0, 17 },
+ Package() { 0x001EFFFF, 2, 0, 18 },
+ Package() { 0x001EFFFF, 3, 0, 19 },
+
+ Package() { 0x001FFFFF, 0, 0, 16 },
+ Package() { 0x001FFFFF, 1, 0, 17 },
+ Package() { 0x001FFFFF, 2, 0, 18 },
+ Package() { 0x001FFFFF, 3, 0, 19 },
+ })
+
+ //
+ // Devices 8 - 31 on PStack
+ //
+ Device (UNC1) {
+ Name (_UID, "UNCORE1")
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PRU1)
+ }
+ Return (ARU1)
+ }
+ }
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore2.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore2.asi new file mode 100644 index 0000000000..577a3c2537 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore2.asi @@ -0,0 +1,131 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (PRU2, Package() {
+ //
+ // PCIe2 PortA/NTB
+ //
+ Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x000CFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000CFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000CFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000CFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x000DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+
+ Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ })
+
+ Name (ARU2, Package() {
+ //
+ // PCIe2 PortA/NTB
+ //
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+
+ Package() { 0x0008FFFF, 0, 0, 16 },
+ Package() { 0x0008FFFF, 1, 0, 17 },
+ Package() { 0x0008FFFF, 2, 0, 18 },
+ Package() { 0x0008FFFF, 3, 0, 19 },
+
+ Package() { 0x0009FFFF, 0, 0, 16 },
+ Package() { 0x0009FFFF, 1, 0, 17 },
+ Package() { 0x0009FFFF, 2, 0, 18 },
+ Package() { 0x0009FFFF, 3, 0, 19 },
+
+ Package() { 0x000AFFFF, 0, 0, 16 },
+ Package() { 0x000AFFFF, 1, 0, 17 },
+ Package() { 0x000AFFFF, 2, 0, 18 },
+ Package() { 0x000AFFFF, 3, 0, 19 },
+
+ Package() { 0x000BFFFF, 0, 0, 16 },
+ Package() { 0x000BFFFF, 1, 0, 17 },
+ Package() { 0x000BFFFF, 2, 0, 18 },
+ Package() { 0x000BFFFF, 3, 0, 19 },
+
+ Package() { 0x000CFFFF, 0, 0, 16 },
+ Package() { 0x000CFFFF, 1, 0, 17 },
+ Package() { 0x000CFFFF, 2, 0, 18 },
+ Package() { 0x000CFFFF, 3, 0, 19 },
+
+ Package() { 0x000DFFFF, 0, 0, 16 },
+ Package() { 0x000DFFFF, 1, 0, 17 },
+ Package() { 0x000DFFFF, 2, 0, 18 },
+ Package() { 0x000DFFFF, 3, 0, 19 },
+
+
+ Package() { 0x0016FFFF, 0, 0, 16 },
+ Package() { 0x0016FFFF, 1, 0, 17 },
+ Package() { 0x0016FFFF, 2, 0, 18 },
+ Package() { 0x0016FFFF, 3, 0, 19 },
+
+ Package() { 0x0017FFFF, 0, 0, 16 },
+ Package() { 0x0017FFFF, 1, 0, 17 },
+ Package() { 0x0017FFFF, 2, 0, 18 },
+ Package() { 0x0017FFFF, 3, 0, 19 },
+
+ })
+
+ //
+ // Devices 8 - 31 on each stack
+ //
+ Device (UNC2) {
+ Name (_UID, "UNCORE2")
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PRU2)
+ }
+ Return (ARU2)
+ }
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore3.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore3.asi new file mode 100644 index 0000000000..7f20255d04 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore3.asi @@ -0,0 +1,104 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name (PRU3, Package() {
+
+ Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+
+ Package() { 0x0012FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0012FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0012FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0012FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
+ Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
+ Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
+ Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
+
+ })
+
+ Name (ARU3, Package() {
+ Package() { 0x000EFFFF, 0, 0, 16 },
+ Package() { 0x000EFFFF, 1, 0, 17 },
+ Package() { 0x000EFFFF, 2, 0, 18 },
+ Package() { 0x000EFFFF, 3, 0, 19 },
+
+ Package() { 0x000FFFFF, 0, 0, 16 },
+ Package() { 0x000FFFFF, 1, 0, 17 },
+ Package() { 0x000FFFFF, 2, 0, 18 },
+ Package() { 0x000FFFFF, 3, 0, 19 },
+
+ Package() { 0x0010FFFF, 0, 0, 16 },
+ Package() { 0x0010FFFF, 1, 0, 17 },
+ Package() { 0x0010FFFF, 2, 0, 18 },
+ Package() { 0x0010FFFF, 3, 0, 19 },
+
+ Package() { 0x0012FFFF, 0, 0, 16 },
+ Package() { 0x0012FFFF, 1, 0, 17 },
+ Package() { 0x0012FFFF, 2, 0, 18 },
+ Package() { 0x0012FFFF, 3, 0, 19 },
+
+ Package() { 0x0015FFFF, 0, 0, 16 },
+ Package() { 0x0015FFFF, 1, 0, 17 },
+ Package() { 0x0015FFFF, 2, 0, 18 },
+ Package() { 0x0015FFFF, 3, 0, 19 },
+
+ Package() { 0x0016FFFF, 0, 0, 16 },
+ Package() { 0x0016FFFF, 1, 0, 17 },
+ Package() { 0x0016FFFF, 2, 0, 18 },
+ Package() { 0x0016FFFF, 3, 0, 19 },
+
+ Package() { 0x0017FFFF, 0, 0, 16 },
+ Package() { 0x0017FFFF, 1, 0, 17 },
+ Package() { 0x0017FFFF, 2, 0, 18 },
+ Package() { 0x0017FFFF, 3, 0, 19 },
+ })
+
+ //
+ // Devices 8 - 31 on each stack
+ //
+ Device (UNC3) {
+ Name (_UID, "UNCORE3")
+ Name (_ADR, 0x00000000)
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PRU3)
+ }
+ Return (ARU3)
+ }
+ }
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/WFPPlatform.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/WFPPlatform.asl new file mode 100644 index 0000000000..d995817140 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/WFPPlatform.asl @@ -0,0 +1,195 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+DefinitionBlock ("WFPPlatform.asl","DSDT",2,"INTEL","PLATWFP ",3)
+{
+
+ #include "CommonPlatform.asi"
+ #include "PlatformPciTree_WFP.asi"
+ #include "AMLUPD.asl"
+ #include "DSDT.ASL"
+ #include "Pch.asl" //This is in another package (PchPkg)
+ #include "Platform.asl"
+ #include "PlatformGpe.asi"
+ #include "PcieSeg.asi"
+
+ Scope (\_SB.PC00.XHCI.RHUB) {
+
+
+
+ //
+ // Method for creating generic _PLD buffers
+ // _PLD contains lots of data, but for purpose of internal validation we care only about
+ // ports' visibility and pairing (this requires group position)
+ // so these are the only 2 configurable parameters (User Visible, Group Position)
+ //
+ Method(GPLD, 2, Serialized) {
+ Name(PCKG, Package() { Buffer(0x10) {} } )
+ CreateField(DerefOf(Index(PCKG,0)), 0, 7, REV)
+ Store(1,REV)
+ CreateField(DerefOf(Index(PCKG,0)), 64, 1, VISI)
+ Store(Arg0, VISI)
+ CreateField(DerefOf(Index(PCKG,0)), 87, 8, GPOS)
+ Store(Arg1, GPOS)
+
+
+ return (PCKG)
+ }
+
+ //
+ // Method for creating generic _UPC buffers
+ // Similar to _PLD, for internal testing we only care about 1 parameter (port connectable)
+ //
+ Method(GUPC, 1, Serialized) {
+ Name(PCKG, Package(4) { 0, 0xFF, 0, 0 } )
+ Store(Arg0,Index(PCKG,0))
+
+
+ return (PCKG)
+ }
+
+
+
+ } //end scope RHUB
+
+ Scope (\_SB.PC00.XHCI.RHUB.HS01) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,1)) } //Rear Panel A [CONN27] - Upper - usb2 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.HS02) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,2)) } //Rear Panel A [CONN27] - Center - usb2 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.HS03) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,3)) } //Rear Panel A [CONN27] - Bottom - usb2 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.HS04) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,4)) } //Internal A1 [CONN9] - Right - usb2 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.HS05) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,5)) } //Front Panel [CONN20] - Right - usb2 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.HS06) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,6)) } //Front Panel [CONN20] - Left - usb2 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.HS07) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,7)) } //Internal Type A3 [CONN4] - ? - usb2 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.HS08) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,8)) } //Internal Type A3 [CONN4] - ? - usb2 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.HS09) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,9)) } //Jacksonville [CONN22] - Bottom - usb2 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.HS10) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,10)) } //Usb daughter card [CONN14] - ? - usb2 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.HS11) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(0,11)) } //Jacksonville [CONN22] - Center - usb2 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.HS12) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(0,12)) } //Usb daughter card [CONN14] - ? - usb2 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.HS13) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,13)) } //Internal A1 [CONN4] - Left - usb2 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.HS14) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,14)) } //Usb daughter card [CONN14] - ? - usb2 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.USR1) {
+ Method(_UPC) { Return (GUPC(0)) }
+ Method(_PLD) { Return (GPLD(0,0)) }
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.USR2) {
+ Method(_UPC) { Return (GUPC(0)) }
+ Method(_PLD) { Return (GPLD(0,0)) }
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.SS01) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,1)) } //Rear Panel A [CONN27] - Upper - usb3 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.SS02) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,2)) } //Rear Panel A [CONN27] - Center - usb3 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.SS03) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,3)) } //Rear Panel A [CONN27] - Bottom - usb3 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.SS04) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,4)) } //Internal A1 [CONN9] - Right - usb3 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.SS05) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,5)) } //Front Panel [CONN20] - Right - usb3 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.SS06) {
+ Method(_UPC) { Return (GUPC(1)) }
+ Method(_PLD) { Return (GPLD(1,6)) } //Front Panel [CONN20] - Left - usb3 port
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.SS07) {
+ Method(_UPC) { Return (GUPC(0)) }
+ Method(_PLD) { Return (GPLD(0,0)) } //N/A
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.SS08) {
+ Method(_UPC) { Return (GUPC(0)) }
+ Method(_PLD) { Return (GPLD(0,0)) } //N/A
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.SS09) {
+ Method(_UPC) { Return (GUPC(0)) }
+ Method(_PLD) { Return (GPLD(0,0)) } //N/A
+ }
+
+ Scope (\_SB.PC00.XHCI.RHUB.SS10) {
+ Method(_UPC) { Return (GUPC(0)) }
+ Method(_PLD) { Return (GPLD(0,0)) } //N/A
+ }
+
+} // end of DSDT
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