diff options
Diffstat (limited to 'Silicon/AMD/Styx/AcpiTables')
| -rw-r--r-- | Silicon/AMD/Styx/AcpiTables/AcpiAml.inf | 29 | ||||
| -rw-r--r-- | Silicon/AMD/Styx/AcpiTables/AcpiTables.inf | 90 | ||||
| -rw-r--r-- | Silicon/AMD/Styx/AcpiTables/Csrt.c | 107 | ||||
| -rw-r--r-- | Silicon/AMD/Styx/AcpiTables/Dbg2.c | 114 | ||||
| -rw-r--r-- | Silicon/AMD/Styx/AcpiTables/Dsdt.asl | 817 | ||||
| -rw-r--r-- | Silicon/AMD/Styx/AcpiTables/Dsdt.c | 192 | ||||
| -rw-r--r-- | Silicon/AMD/Styx/AcpiTables/Fadt.c | 104 | ||||
| -rw-r--r-- | Silicon/AMD/Styx/AcpiTables/Gtdt.c | 189 | ||||
| -rw-r--r-- | Silicon/AMD/Styx/AcpiTables/Iort.c | 375 | ||||
| -rw-r--r-- | Silicon/AMD/Styx/AcpiTables/Madt.c | 336 | ||||
| -rw-r--r-- | Silicon/AMD/Styx/AcpiTables/Mcfg.c | 51 | ||||
| -rw-r--r-- | Silicon/AMD/Styx/AcpiTables/Spcr.c | 124 |
12 files changed, 2528 insertions, 0 deletions
diff --git a/Silicon/AMD/Styx/AcpiTables/AcpiAml.inf b/Silicon/AMD/Styx/AcpiTables/AcpiAml.inf new file mode 100644 index 0000000000..08a7aabe82 --- /dev/null +++ b/Silicon/AMD/Styx/AcpiTables/AcpiAml.inf @@ -0,0 +1,29 @@ +#/** @file
+#
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AcpiAml
+ FILE_GUID = 2df2a2ee-5f34-4dea-b4b6-da724e455f33
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Dsdt.asl
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/AMD/Styx/AmdStyx.dec
+
diff --git a/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf b/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf new file mode 100644 index 0000000000..cfffc73894 --- /dev/null +++ b/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf @@ -0,0 +1,90 @@ +#/** @file
+# Sample ACPI Platform Driver
+#
+# Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+#/**
+#
+# Derived from:
+# MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AmdStyxAcpiLib
+ FILE_GUID = 74850e9e-371c-43af-b1fe-794d61505ad0
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = AmdStyxAcpiLib
+
+[Sources]
+ Gtdt.c
+ Fadt.c
+ Dbg2.c
+ Spcr.c
+ Madt.c
+ Mcfg.c
+ Csrt.c
+ Dsdt.c
+ Iort.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec
+ Silicon/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+ PcdLib
+ DebugLib
+ UefiBootServicesTableLib
+
+[Protocols]
+ gAmdMpCoreInfoProtocolGuid ## CONSUMED
+
+[Pcd]
+ gAmdStyxTokenSpaceGuid.PcdSocCoreCount
+ gAmdStyxTokenSpaceGuid.PcdSocCpuId
+ gAmdStyxTokenSpaceGuid.PcdEthMacA
+ gAmdStyxTokenSpaceGuid.PcdEthMacB
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+ gAmdStyxTokenSpaceGuid.PcdSerialDbgRegisterBase
+ gAmdStyxTokenSpaceGuid.PcdGicVersion
+ gAmdStyxTokenSpaceGuid.PcdGicHypervisorInterruptInterfaceBase
+ gAmdStyxTokenSpaceGuid.PcdGicVirtualInterruptInterfaceBase
+ gAmdStyxTokenSpaceGuid.PcdGicVirtualMaintenanceInterrupt
+ gAmdStyxTokenSpaceGuid.PcdGicVirtualRegisterInterfaceBase
+ gAmdStyxTokenSpaceGuid.PcdGicMSIFrameBase
+ gAmdStyxTokenSpaceGuid.PcdCntControlBase
+ gAmdStyxTokenSpaceGuid.PcdCntReadBase
+ gAmdStyxTokenSpaceGuid.PcdCntCTLBase
+ gAmdStyxTokenSpaceGuid.PcdCntBase0
+ gAmdStyxTokenSpaceGuid.PcdCntEL0Base0
+ gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogRefreshBase
+ gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogControlBase
+ gAmdStyxTokenSpaceGuid.PcdSbsaWakeUpGSIV
+ gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogGSIV
+ gAmdStyxTokenSpaceGuid.PcdSocCoresPerCluster
+ gAmdStyxTokenSpaceGuid.PcdPsciOsSupport
+ gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport
+ gAmdStyxTokenSpaceGuid.PcdParkingProtocolVersion
+ gAmdStyxTokenSpaceGuid.PcdSata1PortCount
+
+[Depex]
+ gAmdMpCoreInfoProtocolGuid
diff --git a/Silicon/AMD/Styx/AcpiTables/Csrt.c b/Silicon/AMD/Styx/AcpiTables/Csrt.c new file mode 100644 index 0000000000..f25f90da53 --- /dev/null +++ b/Silicon/AMD/Styx/AcpiTables/Csrt.c @@ -0,0 +1,107 @@ +/** @file
+
+ ACPI Memory mapped configuration space base address Description Table (MCFG).
+ Implementation based on PCI Firmware Specification Revision 3.0 final draft,
+ downloadable at http://www.pcisig.com/home
+
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+
+ This program and the accompanying materials are licensed and
+ made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the
+ license may be found at http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+
+//
+// CSRT for ARM_CCN504 (L3 CACHE)
+//
+#define AMD_ACPI_ARM_CCN504_CSRT_REVISION 0
+#define AMD_ACPI_ARM_CCN504_VENDOR_ID SIGNATURE_32('A','R','M','H')
+#define AMD_ACPI_ARM_CCN504_DEVICE_ID 0x510
+#define AMD_ACPI_ARM_CCN504_RESOURCE_TYPE 0x04
+#define AMD_ACPI_ARM_CCN504_DESC_VERSION 1
+#define AMD_ACPI_ARM_CCN504_HNF_COUNT 8
+#define AMD_ACPI_ARM_CCN504_BASE_ADDR 0xE8000000ULL
+#define AMD_ACPI_ARM_CCN504_CACHE_SIZE 0x00800000ULL
+
+//
+// Ensure proper (byte-packed) structure formats
+//
+#pragma pack(push, 1)
+
+typedef struct {
+ UINT32 Version;
+ UINT8 HnfRegionCount;
+ UINT8 Reserved[3];
+ UINT64 BaseAddress;
+ UINT64 CacheSize;
+} AMD_ACPI_ARM_CCN504_CSRT_DEVICE_DESCRIPTOR;
+
+typedef struct {
+ UINT32 Length;
+ UINT16 ResourceType;
+ UINT16 ResourceSubtype;
+ UINT32 UID;
+ AMD_ACPI_ARM_CCN504_CSRT_DEVICE_DESCRIPTOR Ccn504Desc;
+} AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_DESCRIPTOR;
+
+typedef struct {
+ UINT32 Length;
+ UINT32 VendorId;
+ UINT32 SubvendorId;
+ UINT16 DeviceId;
+ UINT16 SubdeviceId;
+ UINT16 Revision;
+ UINT8 Reserved[2];
+ UINT32 SharedInfoLength;
+ AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_DESCRIPTOR RsrcDesc;
+} AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_GROUP;
+
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_GROUP RsrcGroup;
+} AMD_ACPI_ARM_CCN504_CORE_SYSTEM_RESOURCE_TABLE;
+
+
+AMD_ACPI_ARM_CCN504_CORE_SYSTEM_RESOURCE_TABLE AcpiCsrt = {
+ AMD_ACPI_HEADER (EFI_ACPI_5_1_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE,
+ AMD_ACPI_ARM_CCN504_CORE_SYSTEM_RESOURCE_TABLE,
+ AMD_ACPI_ARM_CCN504_CSRT_REVISION),
+ { sizeof (AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_GROUP), // UINT32 RsrcGroup.Length
+ AMD_ACPI_ARM_CCN504_VENDOR_ID, // UINT32 RsrcGroup.VendorId
+ 0, // UINT32 RsrcGroup.SubvendorId
+ AMD_ACPI_ARM_CCN504_DEVICE_ID, // UINT16 RsrcGroup.DeviceId
+ 0, // UINT16 RsrcGroup.SubdeviceId
+ 0, // UINT16 RsrcGroup.Revision
+ { 0 }, // UINT8 RsrcGroup.Reserved[]
+ 0, // UINT32 RsrcGroup.SharedInfoLength
+ { sizeof (AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_DESCRIPTOR), // UINT32 RsrcDesc.Length
+ AMD_ACPI_ARM_CCN504_RESOURCE_TYPE, // UINT16 RsrcDesc.ResourceType
+ 0, // UINT16 RsrcDesc.ResourceSubtype
+ 0, // UINT32 RsrcDesc.UID
+ { AMD_ACPI_ARM_CCN504_DESC_VERSION, // UINT32 Ccn504Desc.Version
+ AMD_ACPI_ARM_CCN504_HNF_COUNT, // UINT8 Ccn504Desc.HnfRegionCount
+ { 0 }, // UINT8 Ccn504Desc.Reserved[]
+ AMD_ACPI_ARM_CCN504_BASE_ADDR, // UINT64 Ccn504Desc.BaseAddress
+ AMD_ACPI_ARM_CCN504_CACHE_SIZE, // UINT64 Ccn504Desc.CacheSize
+ },
+ },
+ },
+};
+
+#pragma pack(pop)
+
+
+EFI_ACPI_DESCRIPTION_HEADER *
+CsrtHeader (
+ VOID
+ )
+{
+ return &AcpiCsrt.Header;
+}
diff --git a/Silicon/AMD/Styx/AcpiTables/Dbg2.c b/Silicon/AMD/Styx/AcpiTables/Dbg2.c new file mode 100644 index 0000000000..5d6cf82dba --- /dev/null +++ b/Silicon/AMD/Styx/AcpiTables/Dbg2.c @@ -0,0 +1,114 @@ +/** @file
+
+ Microsoft Debug Port Table 2 (DBG2)
+ © 2012 Microsoft. All rights reserved.<BR>
+ http://go.microsoft.com/fwlink/p/?linkid=403551
+
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+#include <IndustryStandard/DebugPort2Table.h>
+
+#pragma pack(push, 1)
+
+#define EFI_ACPI_DBG2_REVISION 0
+#define DBG2_NUM_DEBUG_PORTS 1
+#define DBG2_NUMBER_OF_GENERIC_ADDRESS_REGISTERS 1
+#define DBG2_NAMESPACESTRING_FIELD_SIZE 8
+#define DBG2_OEM_DATA_FIELD_SIZE 0
+#define DBG2_OEM_DATA_FIELD_OFFSET 0
+
+#define DBG2_DEBUG_PORT_SUBTYPE_PL011 0x0003 // Sub type for Pl011
+#define DBG2_DEBUG_PORT_SUBTYPE_UEFI 0x0007 // Sub type for UEFI Debug Port
+#define PL011_UART_LENGTH 0x1000
+
+#define NAME_STR_UART1 {'C', 'O', 'M', '1', '\0', '\0', '\0', '\0'}
+#define NAME_STR_UEFI {'U', 'E', 'F', 'I', '\0', '\0', '\0', '\0'}
+
+
+typedef struct {
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister;
+ UINT32 AddressSize;
+ UINT8 NameSpaceString[DBG2_NAMESPACESTRING_FIELD_SIZE];
+} DBG2_DEBUG_DEVICE_INFORMATION;
+
+typedef struct {
+ EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Description;
+ DBG2_DEBUG_DEVICE_INFORMATION Dbg2DeviceInfo[DBG2_NUM_DEBUG_PORTS];
+} DBG2_TABLE;
+
+
+#define DBG2_DEBUG_PORT_DDI(NumReg, SubType, UartBase, UartAddrLen, UartNameStr) { \
+ { \
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, /* UINT8 Revision; */ \
+ sizeof (DBG2_DEBUG_DEVICE_INFORMATION), /* UINT16 Length; */ \
+ NumReg, /* UINT8 NumberofGenericAddressRegisters; */ \
+ DBG2_NAMESPACESTRING_FIELD_SIZE, /* UINT16 NameSpaceStringLength; */ \
+ OFFSET_OF(DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString), /* UINT16 NameSpaceStringOffset; */ \
+ DBG2_OEM_DATA_FIELD_SIZE, /* UINT16 OemDataLength; */ \
+ DBG2_OEM_DATA_FIELD_OFFSET, /* UINT16 OemDataOffset; */ \
+ EFI_ACPI_DBG2_PORT_TYPE_SERIAL, /* UINT16 Port Type; */ \
+ SubType, /* UINT16 Port Subtype; */ \
+ {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, /* UINT8 Reserved[2]; */ \
+ OFFSET_OF(DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister), /* UINT16 BaseAddressRegister Offset; */ \
+ OFFSET_OF(DBG2_DEBUG_DEVICE_INFORMATION, AddressSize) /* UINT16 AddressSize Offset; */ \
+ }, \
+ AMD_GASN (UartBase), /* EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister */ \
+ UartAddrLen, /* UINT32 AddressSize */ \
+ UartNameStr /* UINT8 NameSpaceString[MAX_DBG2_NAME_LEN] */ \
+ }
+
+
+STATIC DBG2_TABLE AcpiDbg2 = {
+ {
+ AMD_ACPI_HEADER (EFI_ACPI_5_0_DEBUG_PORT_2_TABLE_SIGNATURE,
+ DBG2_TABLE,
+ EFI_ACPI_DBG2_REVISION),
+ OFFSET_OF(DBG2_TABLE, Dbg2DeviceInfo),
+ DBG2_NUM_DEBUG_PORTS // UINT32 NumberDbgDeviceInfo
+ },
+ {
+ /*
+ * Kernel Debug Port
+ */
+#if (DBG2_NUM_DEBUG_PORTS > 0)
+ DBG2_DEBUG_PORT_DDI(DBG2_NUMBER_OF_GENERIC_ADDRESS_REGISTERS,
+ DBG2_DEBUG_PORT_SUBTYPE_PL011,
+ FixedPcdGet64(PcdSerialDbgRegisterBase),
+ PL011_UART_LENGTH,
+ NAME_STR_UART1),
+#endif
+ /*
+ * UEFI Debug Port
+ */
+#if (DBG2_NUM_DEBUG_PORTS > 1)
+ DBG2_DEBUG_PORT_DDI(0,
+ DBG2_DEBUG_PORT_SUBTYPE_UEFI,
+ 0,
+ 0,
+ NAME_STR_UEFI),
+#endif
+ }
+};
+
+#pragma pack(pop)
+
+EFI_ACPI_DESCRIPTION_HEADER *
+Dbg2Header (
+ VOID
+ )
+{
+ return &AcpiDbg2.Description.Header;
+}
+
diff --git a/Silicon/AMD/Styx/AcpiTables/Dsdt.asl b/Silicon/AMD/Styx/AcpiTables/Dsdt.asl new file mode 100644 index 0000000000..4741bb487c --- /dev/null +++ b/Silicon/AMD/Styx/AcpiTables/Dsdt.asl @@ -0,0 +1,817 @@ +/** @file
+
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+
+ Derived from:
+ ArmPlatformPkg/ArmJunoPkg/AcpiTables/Dsdt.asl
+
+**/
+
+DefinitionBlock ("DSDT.aml", "DSDT", 2, "AMDINC", "SEATTLE ", 3)
+{
+ Scope (_SB)
+ {
+ Device (CPU0)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x000) // _UID: Unique ID
+ }
+#if (NUM_CORES > 1)
+ Device (CPU1)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x001) // _UID: Unique ID
+ }
+#endif
+#if (NUM_CORES > 2)
+ Device (CPU2)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x100) // _UID: Unique ID
+ }
+#endif
+#if (NUM_CORES > 3)
+ Device (CPU3)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x101) // _UID: Unique ID
+ }
+#endif
+#if (NUM_CORES > 4)
+ Device (CPU4)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x200) // _UID: Unique ID
+ }
+#endif
+#if (NUM_CORES > 5)
+ Device (CPU5)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x201) // _UID: Unique ID
+ }
+#endif
+#if (NUM_CORES > 6)
+ Device (CPU6)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x300) // _UID: Unique ID
+ }
+#endif
+#if (NUM_CORES > 7)
+ Device (CPU7)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x301) // _UID: Unique ID
+ }
+#endif
+
+ Device (AHC0)
+ {
+ Name (_HID, "AMDI0600") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_CLS, Package (0x03) // _CLS: Class Code
+ {
+ 0x01,
+ 0x06,
+ 0x01
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0300000, // Address Base (MMIO)
+ 0x00010000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE0000078, // Address Base (SGPIO)
+ 0x00000001, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000183, }
+ })
+ }
+
+ Device (AHC1)
+ {
+ Name (_HID, "AMDI0600") // _HID: Hardware ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_CLS, Package (0x03) // _CLS: Class Code
+ {
+ 0x01,
+ 0x06,
+ 0x01
+ })
+ Method (_STA)
+ {
+ Return (0x0F)
+ }
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0D00000, // Address Base (MMIO)
+ 0x00010000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE000007C, // Address Base (SGPIO)
+ 0x00000001, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000182, }
+ })
+ }
+
+#if DO_XGBE
+ Device (ETH0)
+ {
+ Name (_HID, "AMDI8001") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0700000, // Address Base (XGMAC)
+ 0x00010000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE0780000, // Address Base (XPCS)
+ 0x00080000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE1240800, // Address Base (SERDES_RxTx)
+ 0x00000400, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE1250000, // Address Base (SERDES_IR_1)
+ 0x00000060, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE12500F8, // Address Base (SERDES_IR_2)
+ 0x00000004, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000165, } // XGMAC
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x0000017A, } // DMA0
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x0000017B, } // DMA1
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x0000017C, } // DMA2
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x0000017D, } // DMA3
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000163, } // XPCS
+ })
+ Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package (0x02) {"mac-address", Package (0x06) {0x02, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5}},
+ Package (0x02) {"phy-mode", "xgmii"},
+ Package (0x02) {"amd,speed-set", 0x00},
+ Package (0x02) {"amd,dma-freq", 0x0EE6B280},
+ Package (0x02) {"amd,ptp-freq", 0x0EE6B280},
+ Package (0x02) {"amd,serdes-blwc", Package (0x03) {1, 1, 0}},
+ Package (0x02) {"amd,serdes-cdr-rate", Package (0x03) {2, 2, 7}},
+ Package (0x02) {"amd,serdes-pq-skew", Package (0x03) {10, 10, 18}},
+ Package (0x02) {"amd,serdes-tx-amp", Package (0x03) {15, 15, 10}},
+ Package (0x02) {"amd,serdes-dfe-tap-config", Package (0x03) {3, 3, 1}},
+ Package (0x02) {"amd,serdes-dfe-tap-enable", Package (0x03) {0, 0, 127}},
+ Package (0x02) {"amd,per-channel-interrupt", 0x01}
+ }
+ })
+ }
+
+ Device (ETH1)
+ {
+ Name (_HID, "AMDI8001") // _HID: Hardware ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0900000, // Address Base (XGMAC)
+ 0x00010000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE0980000, // Address Base (XPCS)
+ 0x00080000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE1240C00, // Address Base (SERDES_RxTx)
+ 0x00000400, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE1250080, // Address Base (SERDES_IR_1)
+ 0x00000060, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE12500FC, // Address Base (SERDES_IR_2)
+ 0x00000004, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000164, } // XGMAC
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x00000175, } // DMA0
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x00000176, } // DMA1
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x00000177, } // DMA2
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x00000178, } // DMA3
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000162, } // XPCS
+ })
+ Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package (0x02) {"mac-address", Package (0x06) {0x02, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5}},
+ Package (0x02) {"phy-mode", "xgmii"},
+ Package (0x02) {"amd,speed-set", 0x00},
+ Package (0x02) {"amd,dma-freq", 0x0EE6B280},
+ Package (0x02) {"amd,ptp-freq", 0x0EE6B280},
+ Package (0x02) {"amd,serdes-blwc", Package (0x03) {1, 1, 0}},
+ Package (0x02) {"amd,serdes-cdr-rate", Package (0x03) {2, 2, 7}},
+ Package (0x02) {"amd,serdes-pq-skew", Package (0x03) {10, 10, 18}},
+ Package (0x02) {"amd,serdes-tx-amp", Package (0x03) {15, 15, 10}},
+ Package (0x02) {"amd,serdes-dfe-tap-config", Package (0x03) {3, 3, 1}},
+ Package (0x02) {"amd,serdes-dfe-tap-enable", Package (0x03) {0, 0, 127}},
+ Package (0x02) {"amd,per-channel-interrupt", 0x01}
+ }
+ })
+ }
+#endif // DO_XGBE
+
+ Device (SPI0)
+ {
+ Name (_HID, "AMDI0500") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE1020000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000016A, }
+ })
+ }
+
+ Device (SPI1)
+ {
+ Name (_HID, "AMDI0500") // _HID: Hardware ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE1030000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000169, }
+ })
+
+ Device(SDC0)
+ {
+ Name(_HID, "AMDI0501") // SD Card/MMC slot
+ Name(_CRS, ResourceTemplate()
+ {
+ SPISerialBus(1, // DeviceSelection
+ PolarityLow, // DeviceSelectionPolarity
+ FourWireMode, // WireMode
+ 8, // DataBitLength
+ ControllerInitiated, // SlaveMode
+ 20000000, // ConnectionSpeed
+ ClockPolarityLow, // ClockPolarity
+ ClockPhaseFirst, // ClockPhase
+ "\\SB.SPI1", // ResourceSource
+ 0, // ResourceSourceIndex
+ ResourceConsumer, // ResourceUsage
+ ) // SPISerialBus()
+
+ // SD Card “Detect” signal
+ GpioInt(Edge, ActiveBoth, ExclusiveAndWake, PullDown, , "\\_SB.GIO1") {6}
+ }) // ResourceTemplate()
+
+ } // Device()
+ }
+
+ Device (COM1)
+ {
+ Name (_HID, "AMDI0511") // _HID: Hardware ID
+ Name (_CID, "ARMH0011") // _CID: Compatible ID
+ Name (_ADR, 0xE1010000) // _ADR: Address
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE1010000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000168, }
+ })
+ }
+
+ Device (GIO0)
+ {
+ Name (_HID, "AMDI0400") // _HID: Hardware ID
+ Name (_CID, "ARMH0061") // _CID: Compatible ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0080000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000189, }
+ })
+ }
+
+ Device (GIO1)
+ {
+ Name (_HID, "AMDI0400") // _HID: Hardware ID
+ Name (_CID, "ARMH0061") // _CID: Compatible ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE1050000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000186, }
+ })
+ }
+
+ Device (GIO2)
+ {
+ Name (_HID, "AMDI0400") // _HID: Hardware ID
+ Name (_CID, "ARMH0061") // _CID: Compatible ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Method (_STA)
+ {
+ Return (0x0F)
+ }
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0020000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000018E, }
+ })
+ }
+
+ Device (GIO3)
+ {
+ Name (_HID, "AMDI0400") // _HID: Hardware ID
+ Name (_CID, "ARMH0061") // _CID: Compatible ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Method (_STA)
+ {
+ Return (0x0F)
+ }
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0030000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000018D, }
+ })
+ }
+
+ Device (I2C0)
+ {
+ Name (_HID, "AMDI0510") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE1000000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000185, }
+ })
+
+ Method (SSCN, 0, NotSerialized)
+ {
+ Return (Package (0x03)
+ {
+ 0x0430,
+ 0x04E1,
+ 0x00
+ })
+ }
+
+ Method (FMCN, 0, NotSerialized)
+ {
+ Return (Package (0x03)
+ {
+ 0x00DE,
+ 0x018F,
+ 0x00
+ })
+ }
+ }
+
+ Device (I2C1)
+ {
+ Name (_HID, "AMDI0510") // _HID: Hardware ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0050000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000174, }
+ })
+
+ Method (SSCN, 0, NotSerialized)
+ {
+ Return (Package (0x03)
+ {
+ 0x0430,
+ 0x04E1,
+ 0x00
+ })
+ }
+
+ Method (FMCN, 0, NotSerialized)
+ {
+ Return (Package (0x03)
+ {
+ 0x00DE,
+ 0x018F,
+ 0x00
+ })
+ }
+ }
+
+ Device (CCP0)
+ {
+ Name (_HID, "AMDI0C00") // _HID: Hardware ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0100000, // Address Base
+ 0x00010000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000023, }
+ })
+
+ Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package (0x02) {"amd,zlib-support", 1}
+ }
+ })
+ }
+
+#if DO_KCS
+ //
+ // IPMI/KCS
+ //
+ Device (KCS0)
+ {
+ Name (_HID, "AMDI0300")
+ Name (_CID, "IPI0001")
+ Name (_STR, Unicode("IPMI_KCS"))
+ Name (_UID, 0)
+ Name (_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xE0010000, 0x1) // KCS Data In/Out
+ Memory32Fixed(ReadWrite, 0xE0010004, 0x1) // KCS Control/Status
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,,,) { 421 } // GSIV
+ })
+ Method (_IFT) { // Interface Type
+ Return ( 0x01) // IPMI KCS
+ }
+
+ Method (_SRV) { // Spec Revision
+ Return (0x200) // IPMI Spec v2.0
+ }
+ }
+#endif // DO_KCS
+
+ //
+ // PCIe Root Bus
+ //
+ Device (PCI0)
+ {
+ Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
+ Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
+ Name (_SEG, 0x00) // _SEG: PCI Segment
+ Name (_BBN, 0x00) // _BBN: BIOS Bus Number
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_PRT, Package () // _PRT: PCI Routing Table
+ {
+ // INTA of the bridge device itself
+ Package () { 0x2FFFF, 0x0, 0x0, 0x140 }
+ })
+
+ Device (EXP1)
+ {
+ Name (_ADR, 0x20001) // _ADR: Address
+ Name (_PRT, Package () // _PRT: PCI Routing Table
+ {
+ Package () { 0xFFFF, 0x0, 0x0, 0x140 },
+ Package () { 0xFFFF, 0x1, 0x0, 0x141 },
+ Package () { 0xFFFF, 0x2, 0x0, 0x142 },
+ Package () { 0xFFFF, 0x3, 0x0, 0x143 }
+ }) // _PRT
+ }
+ Device (EXP2)
+ {
+ Name (_ADR, 0x20002) // _ADR: Address
+ Name (_PRT, Package () // _PRT: PCI Routing Table
+ {
+ Package () { 0xFFFF, 0x0, 0x0, 0x144 },
+ Package () { 0xFFFF, 0x1, 0x0, 0x145 },
+ Package () { 0xFFFF, 0x2, 0x0, 0x146 },
+ Package () { 0xFFFF, 0x3, 0x0, 0x147 }
+ }) // _PRT
+ }
+ Device (EXP3)
+ {
+ Name (_ADR, 0x20003) // _ADR: Address
+ Name (_PRT, Package () // _PRT: PCI Routing Table
+ {
+ Package () { 0xFFFF, 0x0, 0x0, 0x148 },
+ Package () { 0xFFFF, 0x1, 0x0, 0x149 },
+ Package () { 0xFFFF, 0x2, 0x0, 0x14A },
+ Package () { 0xFFFF, 0x3, 0x0, 0x14B }
+ }) // _PRT
+ }
+
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x007F, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0080, // Length
+ )
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x40000000, // Range Minimum
+ 0x5FFFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x20000000 // Length
+ )
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x60000000, // Range Minimum
+ 0x7FFFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x20000000 // Length
+ )
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x80000000, // Range Minimum
+ 0x9FFFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x20000000 // Length
+ )
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0xA0000000, // Range Minimum
+ 0xBFFFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x20000000 // Length
+ )
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000100000000, // Range Minimum
+ 0x00000001FFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000100000000 // Length
+ )
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000200000000, // Range Minimum
+ 0x00000003FFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000200000000 // Length
+ )
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000400000000, // Range Minimum
+ 0x00000007FFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000400000000 // Length
+ )
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000800000000, // Range Minimum
+ 0x0000000FFFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000800000000 // Length
+ )
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000001000000000, // Range Minimum
+ 0x0000001FFFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000001000000000 // Length
+ )
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000002000000000, // Range Minimum
+ 0x0000003FFFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000002000000000 // Length
+ )
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000004000000000, // Range Minimum
+ 0x0000007FFFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000004000000000 // Length
+ )
+ DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x00000000, // Granularity
+ 0x00000000, // Range Minimum
+ 0x0000FFFF, // Range Maximum
+ 0xEFFF0000, // Translation Address
+ 0x00010000, // Length
+ ,
+ ,
+ ,
+ TypeTranslation
+ )
+ })
+ Return (RBUF) /* \_SB_.PCI0._CRS.RBUF */
+ } // Method(_CRS)
+
+ Device (RES0)
+ {
+ Name (_HID, "PNP0C02")
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0xF0000000, 0x8000000)
+ })
+ }
+ Name (SUPP, 0x00)
+ Name (CTRL, 0x00)
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ CreateDWordField (Arg3, 0x00, CDW1)
+ If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ Store (CDW2, SUPP) /* \_SB_.PCI0.SUPP */
+ Store (CDW3, CTRL) /* \_SB_.PCI0.CTRL */
+ If (LNotEqual (And (SUPP, 0x16), 0x16))
+ {
+ And (CTRL, 0x1E, CTRL) /* \_SB_.PCI0.CTRL */
+ }
+
+ And (CTRL, 0x1D, CTRL) /* \_SB_.PCI0.CTRL */
+ If (LNotEqual (Arg1, One))
+ {
+ Or (CDW1, 0x08, CDW1) /* \_SB_.PCI0._OSC.CDW1 */
+ }
+
+ If (LNotEqual (CDW3, CTRL))
+ {
+ Or (CDW1, 0x10, CDW1) /* \_SB_.PCI0._OSC.CDW1 */
+ }
+
+ Store (CTRL, CDW3) /* \_SB_.PCI0._OSC.CDW3 */
+ Return (Arg3)
+ }
+ Else
+ {
+ Or (CDW1, 0x04, CDW1) /* \_SB_.PCI0._OSC.CDW1 */
+ Return (Arg3)
+ }
+ } // Method(_OSC)
+
+ //
+ // Device-Specific Methods
+ //
+ Method(_DSM, 0x4, NotSerialized) {
+ If (LEqual(Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
+ switch (ToInteger(Arg2)) {
+ //
+ // Function 0: Return supported functions
+ //
+ case(0) {
+ Return (Buffer() {0xFF})
+ }
+
+ //
+ // Function 1: Return PCIe Slot Information
+ //
+ case(1) {
+ Return (Package(2) {
+ One, // Success
+ Package(3) {
+ 0x1, // x1 PCIe link
+ 0x1, // PCI express card slot
+ 0x1 // WAKE# signal supported
+ }
+ })
+ }
+
+ //
+ // Function 2: Return PCIe Slot Number.
+ //
+ case(2) {
+ Return (Package(1) {
+ Package(4) {
+ 2, // Source ID
+ 4, // Token ID: ID refers to a slot
+ 0, // Start bit of the field to use.
+ 7 // End bit of the field to use.
+ }
+ })
+ }
+
+ //
+ // Function 3: Return Vendor-specific Token ID Strings.
+ //
+ case(3) {
+ Return (Package(0) {})
+ }
+
+ //
+ // Function 4: Return PCI Bus Capabilities
+ //
+ case(4) {
+ Return (Package(2) {
+ One, // Success
+ Buffer() {
+ 1,0, // Version
+ 0,0, // Status, 0:Success
+ 24,0,0,0, // Length
+ 1,0, // PCI
+ 16,0, // Length
+ 0, // Attributes
+ 0x0D, // Current Speed/Mode
+ 0x3F,0, // Supported Speeds/Modes
+ 0, // Voltage
+ 0,0,0,0,0,0,0 // Reserved
+ }
+ })
+ }
+
+ //
+ // Function 5: Return Ignore PCI Boot Configuration
+ //
+ case(5) {
+ Return (Package(1) {1})
+ }
+
+ //
+ // Function 6: Return LTR Maximum Latency
+ //
+ case(6) {
+ Return (Package(4) {
+ Package(1){0}, // Maximum Snoop Latency Scale
+ Package(1){0}, // Maximum Snoop Latency Value
+ Package(1){0}, // Maximum No-Snoop Latency Scale
+ Package(1){0} // Maximum No-Snoop Latency Value
+ })
+ }
+
+ //
+ // Function 7: Return PCI Express Naming
+ //
+ case(7) {
+ Return (Package(2) {
+ Package(1) {0},
+ Package(1) {Unicode("PCI0")}
+ })
+ }
+
+ //
+ // Not supported
+ //
+ default {
+ }
+ }
+ }
+ Return (Buffer(){0})
+ } // Method(_DSM)
+
+ //
+ // Root-Complex 0
+ //
+ Device (RP0)
+ {
+ Name (_ADR, 0xF0000000) // _ADR: Bus 0, Dev 0, Func 0
+ }
+ }
+ }
+}
+
diff --git a/Silicon/AMD/Styx/AcpiTables/Dsdt.c b/Silicon/AMD/Styx/AcpiTables/Dsdt.c new file mode 100644 index 0000000000..360a446f76 --- /dev/null +++ b/Silicon/AMD/Styx/AcpiTables/Dsdt.c @@ -0,0 +1,192 @@ +/** @file
+
+ C language wrapper to build DSDT generated data.
+
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+#include <Dsdt.hex>
+#include <Dsdt.offset.h>
+
+
+UINTN
+ShiftLeftByteToUlong (
+ IN UINT8 Byte,
+ IN UINTN Shift
+ )
+{
+ UINTN Data;
+
+ Data = (UINTN)Byte;
+ Data <<= Shift;
+ return Data;
+}
+
+UINTN
+AmlGetPkgLength (
+ IN UINT8 *Buffer,
+ OUT UINTN *PkgLength
+ )
+{
+ UINTN Bytes, Length;
+
+ Bytes = (UINTN)((Buffer[0] >> 6) & 0x3) + 1;
+ switch (Bytes) {
+ case 1:
+ Length = (UINTN)Buffer[0];
+ break;
+
+ case 2:
+ Length = ShiftLeftByteToUlong(Buffer[1], 4) +
+ (UINTN)(Buffer[0] & 0x0F);
+ break;
+
+ case 3:
+ Length = ShiftLeftByteToUlong(Buffer[2], 12) +
+ ShiftLeftByteToUlong(Buffer[1], 4) +
+ (UINTN)(Buffer[0] & 0x0F);
+ break;
+
+ default: /* 4 bytes */
+ Length = ShiftLeftByteToUlong(Buffer[3], 20) +
+ ShiftLeftByteToUlong(Buffer[2], 12) +
+ ShiftLeftByteToUlong(Buffer[1], 4) +
+ (UINTN)(Buffer[0] & 0x0F);
+ break;
+ }
+
+ *PkgLength = Length;
+ return Bytes;
+}
+
+UINT8 *
+AmlSearchStringPackage (
+ IN UINT8 *Buffer,
+ IN UINTN Length,
+ IN CHAR8 *String
+ )
+{
+ UINTN StrLength;
+
+ StrLength = AsciiStrLen (String) + 1;
+ if (Length > StrLength ) {
+ Length -= StrLength;
+ while (AsciiStrCmp((CHAR8 *)Buffer, String) != 0 && Length) {
+ --Length;
+ ++Buffer;
+ }
+ if (Length) {
+ return &Buffer[StrLength];
+ }
+ }
+ return NULL;
+}
+
+VOID
+OverrideMacAddr (
+ IN UINT8 *DSD_Data,
+ IN UINT64 MacAddr
+ )
+{
+ UINT8 *MacAddrPkg;
+ UINTN Bytes, Length, Index = 0;
+
+ // AML encoding: PackageOp
+ if (DSD_Data[0] == 0x12) {
+ // AML encoding: PkgLength
+ Bytes = AmlGetPkgLength (&DSD_Data[1], &Length);
+
+ // Search for "mac-address" property
+ MacAddrPkg = AmlSearchStringPackage (&DSD_Data[Bytes + 1],
+ Length - Bytes,
+ "mac-address");
+ if (MacAddrPkg &&
+ MacAddrPkg[0] == 0x12 && // PackageOp
+ MacAddrPkg[1] == 0x0E && // PkgLength
+ MacAddrPkg[2] == 0x06) { // NumElements (element must have a BytePrefix)
+
+ MacAddrPkg += 3;
+ do {
+ MacAddrPkg[0] = 0x0A; // BytePrefix
+ MacAddrPkg[1] = (UINT8)(MacAddr & 0xFF);
+ MacAddrPkg += 2;
+ MacAddr >>= 8;
+ } while (++Index < 6);
+ }
+ }
+}
+
+VOID
+OverrideStatus (
+ IN UINT8 *DSD_Data,
+ IN BOOLEAN Enable
+ )
+{
+ if (Enable) {
+ // AML encoding: ReturnOp + BytePrefix
+ if (DSD_Data[1] == 0xA4 && DSD_Data[2] == 0x0A) {
+ DSD_Data[3] = 0x0F;
+ }
+ } else {
+ // AML encoding: ReturnOp
+ if (DSD_Data[1] == 0xA4) {
+ // AML encoding: BytePrefix?
+ if (DSD_Data[2] == 0x0A) {
+ DSD_Data[3] = 0x00;
+ } else {
+ DSD_Data[2] = 0x00;
+ }
+ }
+ }
+}
+
+EFI_ACPI_DESCRIPTION_HEADER *
+DsdtHeader (
+ VOID
+ )
+{
+ AML_OFFSET_TABLE_ENTRY *Table;
+ BOOLEAN EnableOnB1;
+ UINT32 CpuId = PcdGet32 (PcdSocCpuId);
+
+ // Enable features on Styx-B1 or later
+ EnableOnB1 = (CpuId & 0xFF0) && (CpuId & 0x00F);
+
+ Table = &DSDT_SEATTLE__OffsetTable[0];
+ while (Table->Pathname) {
+ if (AsciiStrCmp(Table->Pathname, "_SB_.ETH0._DSD") == 0) {
+ OverrideMacAddr ((UINT8 *)&AmlCode[Table->Offset], PcdGet64 (PcdEthMacA));
+ }
+ else if (AsciiStrCmp(Table->Pathname, "_SB_.ETH1._DSD") == 0) {
+ OverrideMacAddr ((UINT8 *)&AmlCode[Table->Offset], PcdGet64 (PcdEthMacB));
+ }
+ else if (AsciiStrCmp(Table->Pathname, "_SB_.AHC1._STA") == 0) {
+ OverrideStatus ((UINT8 *)&AmlCode[Table->Offset],
+ EnableOnB1 && FixedPcdGet8(PcdSata1PortCount) > 0);
+ }
+ else if (AsciiStrCmp(Table->Pathname, "_SB_.GIO2._STA") == 0) {
+ OverrideStatus ((UINT8 *)&AmlCode[Table->Offset], EnableOnB1);
+ }
+ else if (AsciiStrCmp(Table->Pathname, "_SB_.GIO3._STA") == 0) {
+ OverrideStatus ((UINT8 *)&AmlCode[Table->Offset], EnableOnB1);
+ }
+
+ ++Table;
+ }
+
+ return (EFI_ACPI_DESCRIPTION_HEADER *) &AmlCode[0];
+}
diff --git a/Silicon/AMD/Styx/AcpiTables/Fadt.c b/Silicon/AMD/Styx/AcpiTables/Fadt.c new file mode 100644 index 0000000000..bcbff37988 --- /dev/null +++ b/Silicon/AMD/Styx/AcpiTables/Fadt.c @@ -0,0 +1,104 @@ +/** @file
+
+ Fixed ACPI Description Table (FADT)
+
+ Copyright (c) 2012 - 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+
+ Derived from:
+ ArmPlatformPkg/ArmJunoPkg/AcpiTables/Fadt.aslc
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+
+#define FADT_FLAGS ( EFI_ACPI_5_1_HW_REDUCED_ACPI | \
+ EFI_ACPI_5_1_LOW_POWER_S0_IDLE_CAPABLE | \
+ EFI_ACPI_5_1_HEADLESS )
+
+#pragma pack(push, 1)
+
+STATIC EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE AcpiFadt = {
+ AMD_ACPI_HEADER (EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE,
+ EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION),
+ 0, // UINT32 FirmwareCtrl
+ 0, // UINT32 Dsdt
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
+ EFI_ACPI_5_1_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmProfile
+ 0, // UINT16 SciInt
+ 0, // UINT32 SmiCmd
+ 0, // UINT8 AcpiEnable
+ 0, // UINT8 AcpiDisable
+ 0, // UINT8 S4BiosReq
+ 0, // UINT8 PstateCnt
+ 0, // UINT32 Pm1aEvtBlk
+ 0, // UINT32 Pm1bEvtBlk
+ 0, // UINT32 Pm1aCntBlk
+ 0, // UINT32 Pm1bCntBlk
+ 0, // UINT32 Pm2CntBlk
+ 0, // UINT32 PmTmrBlk
+ 0, // UINT32 Gpe0Blk
+ 0, // UINT32 Gpe1Blk
+ 0, // UINT8 Pm1EvtLen
+ 0, // UINT8 Pm1CntLen
+ 0, // UINT8 Pm2CntLen
+ 0, // UINT8 PmTmrLen
+ 0, // UINT8 Gpe0BlkLen
+ 0, // UINT8 Gpe1BlkLen
+ 0, // UINT8 Gpe1Base
+ 0, // UINT8 CstCnt
+ 0, // UINT16 PLvl2Lat
+ 0, // UINT16 PLvl3Lat
+ 0, // UINT16 FlushSize
+ 0, // UINT16 FlushStride
+ 0, // UINT8 DutyOffset
+ 0, // UINT8 DutyWidth
+ 0, // UINT8 DayAlrm
+ 0, // UINT8 MonAlrm
+ 0, // UINT8 Century
+ 0, // UINT16 IaPcBootArch
+ 0, // UINT8 Reserved1
+ FADT_FLAGS, // UINT32 Flags
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE ResetReg
+ 0, // UINT8 ResetValue
+ 0, // UINT16 ArmBootArch
+ 1, // UINT8 MinorVersion
+ 0, // UINT64 XFirmwareCtrl
+ 0, // UINT64 XDsdt
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XGpe0Blk
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XGpe1Blk
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE SleepControlReg
+ NULL_GAS // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE SleepStatusReg
+};
+
+#pragma pack(pop)
+
+EFI_ACPI_DESCRIPTION_HEADER *
+FadtTable (
+ VOID
+ )
+{
+ if (FixedPcdGetBool (PcdPsciOsSupport) && FixedPcdGetBool (PcdTrustedFWSupport)) {
+ AcpiFadt.ArmBootArch = EFI_ACPI_5_1_ARM_PSCI_COMPLIANT;
+ }
+ return (EFI_ACPI_DESCRIPTION_HEADER *) &AcpiFadt;
+}
+
diff --git a/Silicon/AMD/Styx/AcpiTables/Gtdt.c b/Silicon/AMD/Styx/AcpiTables/Gtdt.c new file mode 100644 index 0000000000..139c9ae0ba --- /dev/null +++ b/Silicon/AMD/Styx/AcpiTables/Gtdt.c @@ -0,0 +1,189 @@ +/** @file
+
+ Generic Timer Description Table (GTDT)
+
+ Copyright (c) 2012 - 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+
+ Derived from:
+ ArmPlatformPkg/ArmJunoPkg/AcpiTables/Gtdt.aslc
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+
+#pragma pack(push, 1)
+
+#define CNT_CONTROL_BASE_ADDRESS FixedPcdGet64(PcdCntControlBase)
+#define CNT_READ_BASE_ADDRESS FixedPcdGet64(PcdCntReadBase)
+#define CNT_CTL_BASE_ADDRESS FixedPcdGet64(PcdCntCTLBase)
+#define CNT_BASE0_ADDRESS FixedPcdGet64(PcdCntBase0)
+#define CNT_EL0_BASE0_ADDRESS FixedPcdGet64(PcdCntEL0Base0)
+#define SBSA_WATCHDOG_REFRESH_BASE FixedPcdGet64(PcdSbsaWatchDogRefreshBase)
+#define SBSA_WATCHDOG_CONTROL_BASE FixedPcdGet64(PcdSbsaWatchDogControlBase)
+#define SBSA_WAKEUP_GSIV FixedPcdGet64(PcdSbsaWakeUpGSIV)
+#define SBSA_WATCHDOG_GSIV FixedPcdGet64(PcdSbsaWatchDogGSIV)
+
+
+/*
+ * Section 8.2.3 of Cortex-A15 r2p1 TRM
+ */
+#define CP15_TIMER_SEC_INTR 29
+#define CP15_TIMER_NS_INTR 30
+#define CP15_TIMER_VIRT_INTR 27
+#define CP15_TIMER_NSHYP_INTR 26
+
+/* SBSA Timers */
+ #define PLATFORM_TIMER_COUNT 2
+ #define PLATFORM_TIMER_OFFSET sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE)
+
+/*
+// GTDT Table timer flags.
+
+Bit 0: Timer interrupt Mode
+ This bit indicates the mode of the timer interrupt
+ 1: Interrupt is Edge triggered
+ 0: Interrupt is Level triggered
+Timer Interrupt polarity
+ This bit indicates the polarity of the timer interrupt
+ 1: Interrupt is Active low
+ 0: Interrupt is Active high
+Reserved 2 30 Reserved, must be zero.
+
+From A15 TRM:
+ 9.2 Generic Timer functional description
+ ...
+ Each timer provides an active-LOW interrupt output that is an external pin to the SoC and is
+ sent to the GIC as a Private Peripheral Interrupt (PPI). See Interrupt sources on page 8-4 for
+ the ID and PPI allocation of the Timer interrupts.
+ PPI6 Virtual Maintenance Interrupt.
+ PPI5 Hypervisor timer event.
+ PPI4 Virtual timer event.
+ PPI3 nIRQ.
+ PPI2 Non-secure physical timer event.
+ PPI1 Secure physical timer event.
+ PPI0-5 Active-LOW level-sensitive.
+ PPI6 Active-HIGH level-sensitive.*/
+
+#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTDT_TIMER_LEVEL_TRIGGERED 0
+#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTDT_TIMER_ACTIVE_HIGH 0
+#define GTDT_TIMER_SECURE EFI_ACPI_5_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY
+#define GTDT_TIMER_NON_SECURE 0
+#define GTDT_GTIMER_FLAGS (GTDT_TIMER_NON_SECURE | GTDT_TIMER_ACTIVE_HIGH | GTDT_TIMER_LEVEL_TRIGGERED)
+
+#define GTX_TIMER_EDGE_TRIGGERED EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTX_TIMER_LEVEL_TRIGGERED 0
+#define GTX_TIMER_ACTIVE_LOW EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTX_TIMER_ACTIVE_HIGH 0
+#define GTX_TIMER_FLAGS (GTX_TIMER_ACTIVE_HIGH | GTX_TIMER_LEVEL_TRIGGERED)
+
+#define GTX_TIMER_SECURE EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER
+#define GTX_TIMER_NON_SECURE 0
+#define GTX_TIMER_SAVE_CONTEXT EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY
+#define GTX_TIMER_LOSE_CONTEXT 0
+#define GTX_COMMON_FLAGS (GTX_TIMER_SAVE_CONTEXT | GTX_TIMER_NON_SECURE)
+
+#define SBSA_WATCHDOG_EDGE_TRIGGERED EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE
+#define SBSA_WATCHDOG_LEVEL_TRIGGERED 0
+#define SBSA_WATCHDOG_ACTIVE_LOW EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY
+#define SBSA_WATCHDOG_ACTIVE_HIGH 0
+#define SBSA_WATCHDOG_SECURE EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER
+#define SBSA_WATCHDOG_NON_SECURE 0
+#define SBSA_WATCHDOG_FLAGS (SBSA_WATCHDOG_NON_SECURE | SBSA_WATCHDOG_ACTIVE_HIGH | SBSA_WATCHDOG_LEVEL_TRIGGERED)
+
+
+#define AMD_SBSA_GTX { \
+ EFI_ACPI_5_1_GTDT_GT_BLOCK, /* UINT8 Type */ \
+ sizeof (EFI_ACPI_5_1_GTDT_GT_BLOCK_STRUCTURE) + \
+ sizeof (EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_STRUCTURE), /* UINT16 Length */ \
+ EFI_ACPI_RESERVED_BYTE, /* UINT8 Reserved */ \
+ CNT_CTL_BASE_ADDRESS, /* UINT64 CntCtlBase */ \
+ 1, /* UINT32 GTBlockTimerCount */ \
+ sizeof (EFI_ACPI_5_1_GTDT_GT_BLOCK_STRUCTURE) /* UINT32 GTBlockTimerOffset */ \
+ }
+
+#define AMD_SBSA_GTX_TIMER { \
+ 0, /* UINT8 GTFrameNumber */ \
+ {0, 0, 0}, /* UINT8 Reserved[3] */ \
+ CNT_BASE0_ADDRESS, /* UINT64 CntBaseX */ \
+ CNT_EL0_BASE0_ADDRESS, /* UINT64 CntEL0BaseX */ \
+ SBSA_WAKEUP_GSIV, /* UINT32 GTxPhysicalTimerGSIV */ \
+ GTX_TIMER_FLAGS, /* UINT32 GTxPhysicalTimerFlags */ \
+ 0, /* UINT32 GTxVirtualTimerGSIV */ \
+ GTX_TIMER_FLAGS, /* UINT32 GTxVirtualTimerFlags */ \
+ GTX_COMMON_FLAGS /* UINT32 GTxCommonFlags */ \
+ }
+
+#define AMD_SBSA_WATCHDOG { \
+ EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG, /* UINT8 Type */ \
+ sizeof (EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE), /* UINT16 Length */ \
+ EFI_ACPI_RESERVED_BYTE, /* UINT8 Reserved */ \
+ SBSA_WATCHDOG_REFRESH_BASE, /* UINT64 RefreshFramePhysicalAddress */ \
+ SBSA_WATCHDOG_CONTROL_BASE, /* UINT64 WatchdogControlFramePhysicalAddress */ \
+ SBSA_WATCHDOG_GSIV, /* UINT32 WatchdogTimerGSIV */ \
+ SBSA_WATCHDOG_FLAGS /* UINT32 WatchdogTimerFlags */ \
+ }
+
+typedef struct {
+ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
+ EFI_ACPI_5_1_GTDT_GT_BLOCK_STRUCTURE GTxBlock;
+ EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_STRUCTURE GTxTimer;
+ EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE WatchDog;
+} AMD_ACPI_5_1_ARM_GTDT_STRUCTURE;
+
+STATIC AMD_ACPI_5_1_ARM_GTDT_STRUCTURE AcpiGtdt = {
+ {
+ AMD_ACPI_HEADER(EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+ AMD_ACPI_5_1_ARM_GTDT_STRUCTURE,
+ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION),
+ CNT_CONTROL_BASE_ADDRESS, // UINT64 PhysicalAddress
+ 0, // UINT32 Reserved
+ CP15_TIMER_SEC_INTR, // UINT32 SecureEL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 SecureEL1TimerFlags
+ CP15_TIMER_NS_INTR, // UINT32 NonSecureEL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecureEL1TimerFlags
+ CP15_TIMER_VIRT_INTR, // UINT32 VirtualTimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
+ CP15_TIMER_NSHYP_INTR, // UINT32 NonSecureEL2TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecureEL2TimerFlags
+ CNT_READ_BASE_ADDRESS, // UINT64 CntReadBaseAddress
+ PLATFORM_TIMER_COUNT, // UINT32 PlatformTimerCount
+ PLATFORM_TIMER_OFFSET // UINT32 PlatformTimerOffset
+ },
+ AMD_SBSA_GTX,
+ AMD_SBSA_GTX_TIMER,
+ AMD_SBSA_WATCHDOG,
+};
+
+#pragma pack(pop)
+
+
+EFI_ACPI_DESCRIPTION_HEADER *
+GtdtHeader (
+ VOID
+ )
+{
+ UINT32 CpuId = PcdGet32 (PcdSocCpuId);
+
+ // Check BaseModel and Stepping: Styx-B0 or prior?
+ if (((CpuId & 0xFF0) == 0) || ((CpuId & 0x00F) == 0)) {
+ AcpiGtdt.Gtdt.Header.Length = sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE);
+ AcpiGtdt.Gtdt.PlatformTimerCount = 0;
+ AcpiGtdt.Gtdt.PlatformTimerOffset = 0;
+ }
+
+ return (EFI_ACPI_DESCRIPTION_HEADER *) &AcpiGtdt.Gtdt.Header;
+}
diff --git a/Silicon/AMD/Styx/AcpiTables/Iort.c b/Silicon/AMD/Styx/AcpiTables/Iort.c new file mode 100644 index 0000000000..80872773ba --- /dev/null +++ b/Silicon/AMD/Styx/AcpiTables/Iort.c @@ -0,0 +1,375 @@ +/** @file
+
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+#include <IndustryStandard/IoRemappingTable.h>
+
+#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name)
+
+#define STYX_PCIE_SMMU_BASE 0xE0A00000
+#define STYX_PCIE_SMMU_SIZE 0x10000
+#define STYX_PCIE_SMMU_INTERRUPT 0x16d
+
+#define STYX_ETH0_SMMU_BASE 0xE0600000
+#define STYX_ETH0_SMMU_SIZE 0x10000
+#define STYX_ETH0_SMMU_INTERRUPT 0x170
+
+#define STYX_ETH1_SMMU_BASE 0xE0800000
+#define STYX_ETH1_SMMU_SIZE 0x10000
+#define STYX_ETH1_SMMU_INTERRUPT 0x16f
+
+#define STYX_SATA0_SMMU_BASE 0xE0200000
+#define STYX_SATA0_SMMU_SIZE 0x10000
+#define STYX_SATA0_SMMU_INTERRUPT 0x16c
+
+#define STYX_SATA1_SMMU_BASE 0xE0C00000
+#define STYX_SATA1_SMMU_SIZE 0x10000
+#define STYX_SATA1_SMMU_INTERRUPT 0x16b
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE Node;
+ EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT Context[1];
+} STYX_SMMU_NODE;
+
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_RC_NODE Node;
+ EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping[1];
+} STYX_RC_NODE;
+
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE Node;
+ CONST CHAR8 Name[11];
+ EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping[32];
+} STYX_NC_NODE;
+
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort;
+ STYX_SMMU_NODE PciSmmuNode;
+ STYX_RC_NODE PciRcNode;
+
+#if DO_XGBE
+ STYX_SMMU_NODE Eth0SmmuNode;
+ STYX_NC_NODE Eth0NamedNode;
+ STYX_SMMU_NODE Eth1SmmuNode;
+ STYX_NC_NODE Eth1NamedNode;
+#endif
+
+ STYX_SMMU_NODE Sata0SmmuNode;
+ STYX_NC_NODE Sata0NamedNode;
+ STYX_SMMU_NODE Sata1SmmuNode;
+ STYX_NC_NODE Sata1NamedNode;
+} STYX_IO_REMAPPING_STRUCTURE;
+
+#define __STYX_SMMU_NODE(Base, Size, Irq) \
+ { \
+ { \
+ EFI_ACPI_IORT_TYPE_SMMUv1v2, \
+ sizeof(STYX_SMMU_NODE), \
+ 0x0, \
+ 0x0, \
+ 0x0, \
+ 0x0, \
+ }, \
+ Base, \
+ Size, \
+ EFI_ACPI_IORT_SMMUv1v2_MODEL_v1, \
+ EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK, \
+ FIELD_OFFSET(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE, \
+ SMMU_NSgIrpt), \
+ 0x1, \
+ sizeof(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE), \
+ 0x0, \
+ 0x0, \
+ Irq, \
+ EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, \
+ 0x0, \
+ 0x0, \
+ }, { \
+ { \
+ Irq, \
+ EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, \
+ }, \
+ }
+
+#define __STYX_ID_MAPPING(In, Num, Out, Ref, Flags) \
+ { \
+ In, \
+ Num, \
+ Out, \
+ FIELD_OFFSET(STYX_IO_REMAPPING_STRUCTURE, Ref), \
+ Flags \
+ }
+
+#define __STYX_ID_MAPPING_SINGLE(Out, Ref) \
+ { \
+ 0x0, \
+ 0x0, \
+ Out, \
+ FIELD_OFFSET(STYX_IO_REMAPPING_STRUCTURE, Ref), \
+ EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE \
+ }
+
+#define __STYX_NAMED_COMPONENT_NODE(Name) \
+ { \
+ { \
+ EFI_ACPI_IORT_TYPE_NAMED_COMP, \
+ sizeof(STYX_NC_NODE), \
+ 0x0, \
+ 0x0, \
+ 0x20, \
+ FIELD_OFFSET(STYX_NC_NODE, RcIdMapping), \
+ }, \
+ 0x0, \
+ EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, \
+ 0x0, \
+ 0x0, \
+ EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM | \
+ EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, \
+ 40, \
+ }, \
+ Name
+
+STATIC STYX_IO_REMAPPING_STRUCTURE AcpiIort = {
+ {
+ AMD_ACPI_HEADER(EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE,
+ STYX_IO_REMAPPING_STRUCTURE,
+ EFI_ACPI_IO_REMAPPING_TABLE_REVISION),
+#if DO_XGBE
+ 10, // NumNodes
+#else
+ 6, // NumNodes
+#endif
+ sizeof(EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset
+ 0 // Reserved
+ }, {
+ // PciSmmuNode
+ __STYX_SMMU_NODE(STYX_PCIE_SMMU_BASE,
+ STYX_PCIE_SMMU_SIZE,
+ STYX_PCIE_SMMU_INTERRUPT)
+ }, {
+ // PciRcNode
+ {
+ {
+ EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type
+ sizeof(STYX_RC_NODE), // Length
+ 0x0, // Revision
+ 0x0, // Reserved
+ 0x1, // NumIdMappings
+ FIELD_OFFSET(STYX_RC_NODE, RcIdMapping), // IdReference
+ },
+ EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, // CacheCoherent
+ 0x0, // AllocationHints
+ 0x0, // Reserved
+ EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM |
+ EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, // MemoryAccessFlags
+ EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, // AtsAttribute
+ 0x0, // PciSegmentNumber
+ }, {
+ __STYX_ID_MAPPING(0x0, 0xffff, 0x0, PciSmmuNode, 0x0),
+ }
+#if DO_XGBE
+ }, {
+ // Eth0SmmuNode
+ __STYX_SMMU_NODE(STYX_ETH0_SMMU_BASE,
+ STYX_ETH0_SMMU_SIZE,
+ STYX_ETH0_SMMU_INTERRUPT)
+ }, {
+ // Eth0NamedNode
+ __STYX_NAMED_COMPONENT_NODE("\\_SB_.ETH0"),
+ {
+ __STYX_ID_MAPPING_SINGLE(0x00, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x01, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x02, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x03, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x04, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x05, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x06, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x07, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x08, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x09, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0A, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0B, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0C, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0D, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0E, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0F, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x10, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x11, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x12, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x13, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x14, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x15, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x16, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x17, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x18, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x19, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1A, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1B, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1C, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1D, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1E, Eth0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1F, Eth0SmmuNode),
+ }
+ }, {
+ // Eth1SmmuNode
+ __STYX_SMMU_NODE(STYX_ETH1_SMMU_BASE,
+ STYX_ETH1_SMMU_SIZE,
+ STYX_ETH1_SMMU_INTERRUPT)
+ }, {
+ // Eth1NamedNode
+ __STYX_NAMED_COMPONENT_NODE("\\_SB_.ETH1"),
+ {
+ __STYX_ID_MAPPING_SINGLE(0x00, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x01, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x02, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x03, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x04, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x05, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x06, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x07, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x08, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x09, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0A, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0B, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0C, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0D, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0E, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0F, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x10, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x11, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x12, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x13, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x14, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x15, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x16, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x17, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x18, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x19, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1A, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1B, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1C, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1D, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1E, Eth1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1F, Eth1SmmuNode),
+ }
+#endif
+ }, {
+ // Sata0SmmuNode
+ __STYX_SMMU_NODE(STYX_SATA0_SMMU_BASE,
+ STYX_SATA0_SMMU_SIZE,
+ STYX_SATA0_SMMU_INTERRUPT)
+ }, {
+ // Sata0NamedNode
+ __STYX_NAMED_COMPONENT_NODE("\\_SB_.AHC0"),
+ {
+ __STYX_ID_MAPPING_SINGLE(0x00, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x01, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x02, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x03, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x04, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x05, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x06, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x07, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x08, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x09, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0A, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0B, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0C, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0D, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0E, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0F, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x10, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x11, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x12, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x13, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x14, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x15, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x16, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x17, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x18, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x19, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1A, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1B, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1C, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1D, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1E, Sata0SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1F, Sata0SmmuNode),
+ }
+ }, {
+ // Sata1SmmuNode
+ __STYX_SMMU_NODE(STYX_SATA1_SMMU_BASE,
+ STYX_SATA1_SMMU_SIZE,
+ STYX_SATA1_SMMU_INTERRUPT)
+ }, {
+ // Sata1NamedNode
+ __STYX_NAMED_COMPONENT_NODE("\\_SB_.AHC1"),
+ {
+ __STYX_ID_MAPPING_SINGLE(0x00, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x01, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x02, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x03, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x04, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x05, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x06, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x07, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x08, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x09, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0A, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0B, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0C, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0D, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0E, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x0F, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x10, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x11, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x12, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x13, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x14, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x15, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x16, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x17, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x18, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x19, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1A, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1B, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1C, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1D, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1E, Sata1SmmuNode),
+ __STYX_ID_MAPPING_SINGLE(0x1F, Sata1SmmuNode),
+ }
+ }
+};
+
+#pragma pack()
+
+#define STYX_SOC_VERSION_MASK 0xFFF
+#define STYX_SOC_VERSION_A0 0x000
+#define STYX_SOC_VERSION_B0 0x010
+#define STYX_SOC_VERSION_B1 0x011
+
+EFI_ACPI_DESCRIPTION_HEADER *
+IortHeader (
+ VOID
+ )
+{
+ if ((PcdGet32 (PcdSocCpuId) & STYX_SOC_VERSION_MASK) < STYX_SOC_VERSION_B1) {
+ //
+ // Silicon revisions prior to B1 have only one SATA port,
+ // so omit the nodes of the second port in this case.
+ //
+ AcpiIort.Iort.NumNodes -= 2;
+ }
+ return (EFI_ACPI_DESCRIPTION_HEADER *)&AcpiIort.Iort.Header;
+}
diff --git a/Silicon/AMD/Styx/AcpiTables/Madt.c b/Silicon/AMD/Styx/AcpiTables/Madt.c new file mode 100644 index 0000000000..96182e790f --- /dev/null +++ b/Silicon/AMD/Styx/AcpiTables/Madt.c @@ -0,0 +1,336 @@ +/** @file
+
+ Multiple APIC Description Table (MADT)
+
+ Copyright (c) 2012 - 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+
+ Derived from:
+ ArmPlatformPkg/ArmJunoPkg/AcpiTables/Madt.aslc
+
+**/
+
+#include <Uefi.h>
+#include <Library/ArmLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Guid/ArmMpCoreInfo.h>
+
+#include <AmdStyxAcpiLib.h>
+#include <Protocol/AmdMpCoreInfo.h>
+
+AMD_MP_CORE_INFO_PROTOCOL *mAmdMpCoreInfoProtocol = NULL;
+
+
+// ARM PL390 General Interrupt Controller
+#define GIC_BASE (FixedPcdGet64 (PcdGicInterruptInterfaceBase))
+#define GICD_BASE (FixedPcdGet64 (PcdGicDistributorBase))
+#define GICV_BASE (FixedPcdGet64 (PcdGicVirtualInterruptInterfaceBase))
+#define GICH_BASE (FixedPcdGet64 (PcdGicHypervisorInterruptInterfaceBase))
+#define VGIC_MAINT_INT (FixedPcdGet32 (PcdGicVirtualMaintenanceInterrupt))
+#define GICVR_BASE (FixedPcdGet64 (PcdGicVirtualRegisterInterfaceBase))
+#define GIC_MSI_FRAME (FixedPcdGet64 (PcdGicMSIFrameBase))
+#define GIC_VERSION (FixedPcdGet8 (PcdGicVersion))
+
+#define GICD_ID ( 0 )
+#define GICD_VECTOR ( 0 )
+
+#define GICM_ID ( 0 )
+#define GICM_SPI_COUNT ( 0x100 )
+#define GICM_SPI_BASE ( 0x40 )
+#define GSIV_SPI_OFFSET ( 32 )
+
+#if STYX_A0
+ #define MSI_TYPER_FLAG ( 1 ) // Ignore TYPER register and use Count/Base fields
+#else
+ #define MSI_TYPER_FLAG ( 0 ) // Use TYPER register and ignore Count/Base fields
+#endif
+
+#define PARKING_PROTOCOL_VERSION (FixedPcdGet32 (PcdParkingProtocolVersion))
+#define PARKED_OFFSET ( 4096 )
+
+#define CORES_PER_CLUSTER (FixedPcdGet32 (PcdSocCoresPerCluster))
+#define PARKED_ADDRESS(Base, ClusterId, CoreId) \
+ ((Base) + (CORES_PER_CLUSTER * ClusterId + CoreId) * PARKED_OFFSET)
+
+
+/* Macro to populate EFI_ACPI_5_1_GIC_STRUCTURE */
+#define AMD_GIC(CpuNum, ClusterId, CoreId, PerfInt) { \
+ EFI_ACPI_5_1_GIC, /* UINT8 Type */ \
+ sizeof (EFI_ACPI_5_1_GIC_STRUCTURE), /* UINT8 Length */ \
+ EFI_ACPI_RESERVED_WORD, /* UINT16 Reserved */ \
+ CpuNum, /* UINT32 CPUInterfaceNumber */ \
+ (ClusterId << 8) | CoreId, /* UINT32 AcpiProcessorUid */ \
+ EFI_ACPI_5_1_GIC_ENABLED, /* UINT32 Flags */ \
+ PARKING_PROTOCOL_VERSION, /* UINT32 ParkingProtocolVersion */ \
+ PerfInt, /* UINT32 PerformanceInterruptGsiv */ \
+ 0, /* UINT64 ParkedAddress */ \
+ GIC_BASE, /* UINT64 PhysicalBaseAddress */ \
+ GICV_BASE, /* UINT64 GICV */ \
+ GICH_BASE, /* UINT64 GICH */ \
+ VGIC_MAINT_INT, /* UINT32 VGICMaintenanceInterrupt */ \
+ GICVR_BASE, /* UINT64 GICRBaseAddress */ \
+ (ClusterId << 8) | CoreId /* UINT64 MPIDR */ \
+ }
+
+/* Macro to initialise EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE */
+#define AMD_GICD(Id, Vec) { \
+ EFI_ACPI_5_1_GICD, /* UINT8 Type */ \
+ sizeof (EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE), /* UINT8 Length */ \
+ EFI_ACPI_RESERVED_WORD, /* UINT16 Reserved1 */ \
+ Id, /* UINT32 GicId */ \
+ GICD_BASE, /* UINT64 PhysicalBaseAddress */ \
+ Vec, /* UINT32 SystemVectorBase */ \
+ EFI_ACPI_RESERVED_DWORD /* UINT32 Reserved2 */ \
+ }
+
+/* Macro to initialise EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE */
+#define AMD_GICM(Id, SpiCount, SpiBase) { \
+ EFI_ACPI_5_1_GIC_MSI_FRAME, /* UINT8 Type */ \
+ sizeof(EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE), /* UINT8 Length */ \
+ EFI_ACPI_RESERVED_WORD, /* UINT16 Reserved1 */ \
+ Id, /* UINT32 GicMsiFrameId */ \
+ GIC_MSI_FRAME, /* UINT64 PhysicalBaseAddress */ \
+ MSI_TYPER_FLAG, /* UINT32 Flags */ \
+ SpiCount, /* UINT16 SPICount */ \
+ SpiBase /* UINT16 SPIBase */ \
+ }
+
+
+//
+// NOTE: NUM_CORES is a pre-processor macro passed in with -D option
+//
+#pragma pack(push, 1)
+typedef struct {
+ EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_5_1_GIC_STRUCTURE GicC[NUM_CORES];
+ EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE GicD;
+ EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE GicM;
+} EFI_ACPI_5_1_ARM_MADT_STRUCTURE;
+#pragma pack(pop)
+
+
+STATIC EFI_ACPI_5_1_ARM_MADT_STRUCTURE AcpiMadt = {
+ {
+ AMD_ACPI_HEADER (EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_5_1_ARM_MADT_STRUCTURE,
+ EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION),
+ GIC_BASE, // UINT32 LocalApicAddress
+ 0 // UINT32 Flags
+ },
+ {
+ /*
+ * GIC Interface for Cluster 0 CPU 0
+ */
+ AMD_GIC(0, 0, 0, 39), // EFI_ACPI_5_1_GIC_STRUCTURE
+#if (NUM_CORES > 1)
+ /*
+ * GIC Interface for Cluster 0 CPU 1
+ */
+ AMD_GIC(1, 0, 1, 40), // EFI_ACPI_5_1_GIC_STRUCTURE
+#endif
+#if (NUM_CORES > 2)
+ /*
+ * GIC Interface for Cluster 1 CPU 0
+ */
+ AMD_GIC(2, 1, 0, 41), // EFI_ACPI_5_1_GIC_STRUCTURE
+#endif
+#if (NUM_CORES > 3)
+ /*
+ * GIC Interface for Cluster 1 CPU 1
+ */
+ AMD_GIC(3, 1, 1, 42), // EFI_ACPI_5_1_GIC_STRUCTURE
+#endif
+#if (NUM_CORES > 4)
+ /*
+ * GIC Interface for Cluster 2 CPU 0
+ */
+ AMD_GIC(4, 2, 0, 43), // EFI_ACPI_5_1_GIC_STRUCTURE
+#endif
+#if (NUM_CORES > 5)
+ /*
+ * GIC Interface for Cluster 2 CPU 1
+ */
+ AMD_GIC(5, 2, 1, 44), // EFI_ACPI_5_1_GIC_STRUCTURE
+#endif
+#if (NUM_CORES > 6)
+ /*
+ * GIC Interface for Cluster 3 CPU 0
+ */
+ AMD_GIC(6, 3, 0, 45), // EFI_ACPI_5_1_GIC_STRUCTURE
+#endif
+#if (NUM_CORES > 7)
+ /*
+ * GIC Interface for Cluster 3 CPU 1
+ */
+ AMD_GIC(7, 3, 1, 46), // EFI_ACPI_5_1_GIC_STRUCTURE
+#endif
+ },
+ /*
+ * GIC Distributor
+ */
+ AMD_GICD(GICD_ID, GICD_VECTOR), // EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE
+ /*
+ * GIC MSI Frame
+ */
+ AMD_GICM(GICM_ID, GICM_SPI_COUNT, GICM_SPI_BASE),
+};
+
+
+STATIC
+EFI_STATUS
+BuildGicC (
+ EFI_ACPI_5_1_GIC_STRUCTURE *GicC,
+ UINT32 CpuNum,
+ UINT32 ClusterId,
+ UINT32 CoreId,
+ EFI_PHYSICAL_ADDRESS MpParkingBase
+ )
+{
+ UINT32 MpId, PmuSpi;
+ EFI_STATUS Status;
+
+ MpId = (UINT32) GET_MPID (ClusterId, CoreId);
+ Status = mAmdMpCoreInfoProtocol->GetPmuSpiFromMpId (MpId, &PmuSpi);
+ if (EFI_ERROR (Status))
+ return Status;
+
+ GicC->Type = EFI_ACPI_5_1_GIC;
+ GicC->Length = sizeof (EFI_ACPI_5_1_GIC_STRUCTURE);
+ GicC->Reserved = EFI_ACPI_RESERVED_WORD;
+ GicC->CPUInterfaceNumber = CpuNum;
+ GicC->AcpiProcessorUid = MpId;
+ GicC->Flags = EFI_ACPI_5_1_GIC_ENABLED;
+ GicC->ParkingProtocolVersion = PARKING_PROTOCOL_VERSION;
+ GicC->ParkedAddress = PARKED_ADDRESS(MpParkingBase, ClusterId, CoreId);
+ GicC->PhysicalBaseAddress = GIC_BASE;
+ GicC->GICV = GICV_BASE;
+ GicC->GICH = GICH_BASE;
+ GicC->VGICMaintenanceInterrupt = VGIC_MAINT_INT;
+ GicC->GICRBaseAddress = GICVR_BASE;
+ GicC->PerformanceInterruptGsiv = PmuSpi + GSIV_SPI_OFFSET;
+ GicC->MPIDR = MpId;
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+VOID
+BuildGicD (
+ EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE *GicD,
+ UINT32 GicId,
+ UINT32 SystemVectorBase
+ )
+{
+ GicD->Type = EFI_ACPI_5_1_GICD;
+ GicD->Length = sizeof (EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE);
+ GicD->Reserved1 = EFI_ACPI_RESERVED_WORD;
+ GicD->GicId = GicId;
+ GicD->PhysicalBaseAddress = GICD_BASE;
+ GicD->SystemVectorBase = SystemVectorBase;
+#if 0
+ GicD->Reserved2 = EFI_ACPI_RESERVED_DWORD;
+#else
+ GicD->GicVersion = EFI_ACPI_RESERVED_BYTE;
+ GicD->Reserved2[0] = EFI_ACPI_RESERVED_BYTE;
+ GicD->Reserved2[1] = EFI_ACPI_RESERVED_BYTE;
+ GicD->Reserved2[2] = EFI_ACPI_RESERVED_BYTE;
+#endif
+}
+
+
+STATIC
+VOID
+BuildGicM (
+ EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE *GicM,
+ UINT32 MsiFrameId,
+ UINT16 SpiCount,
+ UINT16 SpiBase
+ )
+{
+ GicM->Type = EFI_ACPI_5_1_GIC_MSI_FRAME;
+ GicM->Length = sizeof(EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE);
+ GicM->Reserved1 = EFI_ACPI_RESERVED_WORD;
+ GicM->GicMsiFrameId = MsiFrameId;
+ GicM->PhysicalBaseAddress = GIC_MSI_FRAME;
+ GicM->Flags = MSI_TYPER_FLAG;
+ GicM->SPICount = SpiCount;
+ GicM->SPIBase = SpiBase;
+}
+
+
+EFI_ACPI_DESCRIPTION_HEADER *
+MadtHeader (
+ VOID
+ )
+{
+ EFI_ACPI_5_1_GIC_STRUCTURE *GicC;
+ EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE *GicD;
+ EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE *GicM;
+ ARM_CORE_INFO *ArmCoreInfoTable;
+ UINTN CoreCount, CpuNum;
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS MpParkingBase;
+ UINTN MpParkingSize;
+
+ Status = gBS->LocateProtocol (
+ &gAmdMpCoreInfoProtocolGuid,
+ NULL,
+ (VOID **)&mAmdMpCoreInfoProtocol
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ // Get pointer to ARM core info table
+ ArmCoreInfoTable = mAmdMpCoreInfoProtocol->GetArmCoreInfoTable (&CoreCount);
+ ASSERT (ArmCoreInfoTable != NULL);
+
+ // Make sure SoC's core count does not exceed what we want to build
+ ASSERT (CoreCount <= NUM_CORES);
+ ASSERT (CoreCount <= PcdGet32(PcdSocCoreCount));
+
+ MpParkingSize = 0;
+ MpParkingBase = mAmdMpCoreInfoProtocol->GetMpParkingBase(&MpParkingSize);
+ if (MpParkingBase && MpParkingSize < (CoreCount * SIZE_4KB)) {
+ DEBUG ((EFI_D_ERROR, "MADT: Parking Protocol not supported.\n"));
+ MpParkingBase = 0;
+ }
+
+ GicC = (EFI_ACPI_5_1_GIC_STRUCTURE *)&AcpiMadt.GicC[0];
+ AcpiMadt.Header.Header.Length = sizeof (EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER);
+
+ for (CpuNum = 0; CpuNum < CoreCount; ++CpuNum, ++GicC) {
+ DEBUG ((EFI_D_ERROR, "MADT: Core[%d]: ClusterId = %d CoreId = %d\n",
+ CpuNum, ArmCoreInfoTable[CpuNum].ClusterId, ArmCoreInfoTable[CpuNum].CoreId));
+
+ Status = BuildGicC (GicC, CpuNum,
+ ArmCoreInfoTable[CpuNum].ClusterId,
+ ArmCoreInfoTable[CpuNum].CoreId,
+ MpParkingBase
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ AcpiMadt.Header.Header.Length += sizeof (EFI_ACPI_5_1_GIC_STRUCTURE);
+ }
+
+ GicD = (EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE *)(UINT8 *)((UINTN)&AcpiMadt + (UINTN)AcpiMadt.Header.Header.Length);
+ BuildGicD (GicD, GICD_ID, GICD_VECTOR);
+ AcpiMadt.Header.Header.Length += sizeof (EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE);
+
+ GicM = (EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE *)(UINT8 *)((UINTN)&AcpiMadt + (UINTN)AcpiMadt.Header.Header.Length);
+ BuildGicM (GicM, GICM_ID, GICM_SPI_COUNT, GICM_SPI_BASE);
+ AcpiMadt.Header.Header.Length += sizeof (EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE);
+
+ return &AcpiMadt.Header.Header;
+}
+
diff --git a/Silicon/AMD/Styx/AcpiTables/Mcfg.c b/Silicon/AMD/Styx/AcpiTables/Mcfg.c new file mode 100644 index 0000000000..4fc18e8efc --- /dev/null +++ b/Silicon/AMD/Styx/AcpiTables/Mcfg.c @@ -0,0 +1,51 @@ +/** @file
+
+ ACPI Memory mapped configuration space base address Description Table (MCFG).
+ Implementation based on PCI Firmware Specification Revision 3.0 final draft,
+ downloadable at http://www.pcisig.com/home
+
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+
+ This program and the accompanying materials are licensed and
+ made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the
+ license may be found at http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
+
+#if STYX_A0
+#define END_PCI_BUS_NUMBER 15
+#else
+#define END_PCI_BUS_NUMBER 255
+#endif
+
+#pragma pack(push, 1)
+
+typedef struct {
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header;
+ EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Structure;
+} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE;
+
+EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE AcpiMcfg = {
+ { AMD_ACPI_HEADER (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE,
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION),
+ EFI_ACPI_RESERVED_QWORD },
+ { 0xF0000000ULL, 0, 0, END_PCI_BUS_NUMBER, EFI_ACPI_RESERVED_DWORD }
+};
+
+#pragma pack(pop)
+
+EFI_ACPI_DESCRIPTION_HEADER *
+McfgHeader (
+ VOID
+ )
+{
+ return &AcpiMcfg.Header.Header;
+}
diff --git a/Silicon/AMD/Styx/AcpiTables/Spcr.c b/Silicon/AMD/Styx/AcpiTables/Spcr.c new file mode 100644 index 0000000000..719c276cfb --- /dev/null +++ b/Silicon/AMD/Styx/AcpiTables/Spcr.c @@ -0,0 +1,124 @@ +/** @file
+
+ Serial Port Console Redirection Table
+ © 2000 - 2014 Microsoft Corporation. All rights reserved.
+ http://go.microsoft.com/fwlink/?linkid=403368
+
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+
+#pragma pack(push, 1)
+
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_PL011 3
+
+STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE AcpiSpcr = {
+ //
+ // Header
+ //
+ AMD_ACPI_HEADER (EFI_ACPI_5_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
+ 2), /* New MS definition for PL011 support */
+ //
+ // InterfaceType
+ //
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_PL011,
+ //
+ // Reserved[3]
+ //
+ {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE},
+ //
+ // BaseAddress
+ //
+ AMD_GASN(FixedPcdGet64(PcdSerialRegisterBase)),
+ //
+ // InterruptType
+ //
+ 0,
+ //
+ // Irq
+ //
+ 0,
+ //
+ // GlobalSystemInterrupt
+ //
+ 0x148,
+ //
+ // BaudRate
+ //
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,
+ //
+ // Parity
+ //
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,
+ //
+ // StopBits
+ //
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,
+ //
+ // FlowControl
+ //
+ 0,
+ //
+ // TerminalType
+ //
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI,
+ //
+ // Language
+ //
+ EFI_ACPI_RESERVED_BYTE,
+ //
+ // PciDeviceId
+ //
+ 0xFFFF,
+ //
+ // PciVendorId
+ //
+ 0xFFFF,
+ //
+ // PciBusNumber
+ //
+ 0x00,
+ //
+ // PciDeviceNumber
+ //
+ 0x00,
+ //
+ // PciFunctionNumber
+ //
+ 0x00,
+ //
+ // PciFlags
+ //
+ 0,
+ //
+ // PciSegment
+ //
+ 0,
+ //
+ // Reserved2
+ //
+ EFI_ACPI_RESERVED_DWORD
+};
+
+#pragma pack(pop)
+
+EFI_ACPI_DESCRIPTION_HEADER *
+SpcrHeader (
+ VOID
+ )
+{
+ return &AcpiSpcr.Header;
+}
+
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