3 files changed, 211 insertions, 0 deletions
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Library/CpuPlatformLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Library/CpuPlatformLib.h
new file mode 100644
index 0000000000..02c813dc33
--- /dev/null
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Library/CpuPlatformLib.h
@@ -0,0 +1,89 @@
+/** @file
+  Header file for CpuPlatform Lib.
+
+  Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CPU_PLATFORM_LIB_H_
+#define _CPU_PLATFORM_LIB_H_
+
+#include <CpuRegs.h>
+#include <CpuDataStruct.h>
+
+/**
+  Check CPU Type of the platform
+
+  @retval  CPU_FAMILY              CPU type
+
+**/
+CPU_FAMILY
+EFIAPI
+GetCpuFamily (
+  VOID
+  );
+
+/**
+  Return Cpu stepping type
+
+  @retval  CPU_STEPPING                   Cpu stepping type
+
+**/
+CPU_STEPPING
+EFIAPI
+GetCpuStepping (
+  VOID
+  );
+
+/**
+  Returns the processor microcode revision of the processor installed in the system.
+
+  @retval  Processor Microcode Revision
+
+**/
+UINT32
+GetCpuUcodeRevision (
+  VOID
+  );
+
+/**
+  Check if this microcode is correct one for processor
+
+  @param[in] Cpuid                 Processor CPUID
+  @param[in] MicrocodeEntryPoint   Entry point of microcode
+  @param[in] Revision              Revision of microcode
+
+  @retval    CorrectMicrocode      If this microcode is correct
+
+**/
+BOOLEAN
+CheckMicrocode (
+  IN UINT32               Cpuid,
+  IN CPU_MICROCODE_HEADER *MicrocodeEntryPoint,
+  IN UINT32               *Revision
+  );
+
+/**
+  This function will set and lock PRMRR which is required to be locked before enabling normal mode
+  for memory.
+
+  @param[in]  PrmrrBase      Base address of PRMRR range.  Must be naturally algined
+  @param[in]  PrmrrSize      Size of the PRMRR range in Bytes
+
+**/
+VOID
+SetUncorePrmrr (
+  IN UINT32 PrmrrBase,
+  IN UINT32 PrmrrSize
+  );
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Library/CpuPolicyLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Library/CpuPolicyLib.h
new file mode 100644
index 0000000000..9ce0325829
--- /dev/null
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Library/CpuPolicyLib.h
@@ -0,0 +1,67 @@
+/** @file
+  Prototype of the CpuPolicy library.
+
+  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CPU_POLICY_LIB_H_
+#define _CPU_POLICY_LIB_H_
+
+#include <Ppi/CpuPolicy.h>
+#include <Library/ConfigBlockLib.h>
+#include <ConfigBlock.h>
+
+/**
+  Print whole CPU_POLICY_PPI and serial out.
+
+  @param[in]  SiCpuPolicyPpi             The RC Policy PPI instance
+
+**/
+VOID
+CpuPrintPolicyPpi (
+  IN  SI_CPU_POLICY_PPI                 *SiCpuPolicyPpi
+  );
+
+/**
+  CreateCpuConfigBlocks creates the Config Blocks for CPU Policy.
+
+  @param[in, out] SiCpuPolicyPpi                The pointer to get CPU Policy PPI instance
+
+  @retval         EFI_SUCCESS                   The policy default is initialized.
+  @retval         EFI_OUT_OF_RESOURCES          Insufficient resources to create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+CreateCpuConfigBlocks (
+  IN OUT  SI_CPU_POLICY_PPI          **SiCpuPolicyPpi
+  );
+
+/**
+  CpuInstallPolicyPpi installs SiCpuPolicyPpi.
+  While installed, RC assumes the Policy is ready and finalized. So please update and override
+  any setting before calling this function.
+
+  @param[in] SiCpuPolicyPpi                The pointer to PEI Cpu Policy PPI instance
+
+  @retval    EFI_SUCCESS                   The policy is installed.
+  @retval    EFI_OUT_OF_RESOURCES          Insufficient resources to create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+CpuInstallPolicyPpi (
+  IN  SI_CPU_POLICY_PPI                 *SiCpuPolicyPpi
+  );
+
+#endif // _PEI_CPU_POLICY_LIB_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Library/CpuRngLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Library/CpuRngLib.h
new file mode 100644
index 0000000000..c4efb1f0da
--- /dev/null
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Library/CpuRngLib.h
@@ -0,0 +1,55 @@
+/** @file
+  Header file for CpuRng Lib.
+
+  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CPU_RNG_LIB_H_
+#define _CPU_RNG_LIB_H_
+
+/**
+  Gets a random number from the CPU's 16 bits random number.
+
+  @param[out]  UINT16       Random value
+
+**/
+UINT16
+EFIAPI
+GetRandomNumber16 (
+  VOID
+  );
+
+/**
+  Gets a random number from the CPU's 32 bits random number.
+
+  @param[out]  UINT32      Random value
+
+**/
+UINT32
+EFIAPI
+GetRandomNumber32 (
+  VOID
+  );
+
+/**
+  Gets a random number from the CPU's 64 bits random number and only in 64 bits environment.
+
+  @param[out]  UINT64      Random value
+
+**/
+UINT64
+EFIAPI
+GetRandomNumber64 (
+  VOID
+  );
+#endif
+