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path: root/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/MrcEfiDefinitions.h
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Diffstat (limited to 'Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/MrcEfiDefinitions.h')
-rw-r--r--Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/MrcEfiDefinitions.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/MrcEfiDefinitions.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/MrcEfiDefinitions.h
index b19d6a05c6..5d36a6d3a5 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/MrcEfiDefinitions.h
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/MrcEfiDefinitions.h
@@ -64,10 +64,12 @@ typedef struct {
UINT8 RmtMode;
UINT8 RmtCheckRun;
UINT16 RmtMarginCheckScaleHighThreshold;
+ UINT8 Reserved1;
UINT32 MsgLevelMask;
UINT8 SpdAddress[DRAM_POLICY_NUMBER_SPD_ADDRESSES];
UINT8 ChSwizzle[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS];
DRP_DRAM_POLICY ChDrp[DRAM_POLICY_NUMBER_CHANNELS];
+ UINT8 Reserved2;
UINT8 DebugMsgLevel;
UINT8 reserved[13];
} DRAM_POLICY_PPI;
@@ -79,7 +81,6 @@ typedef struct {
typedef enum {
Bxt = 0x00,
Bxt1,
- BxtX,
BxtP,
BxtSeriesMax = 0xFF
} BXT_SERIES;