diff options
Diffstat (limited to 'Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock')
21 files changed, 1466 insertions, 0 deletions
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/DciConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/DciConfig.h new file mode 100644 index 0000000000..25217d846e --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/DciConfig.h @@ -0,0 +1,52 @@ +/** @file
+ DCI policy.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _DCI_CONFIG_H_
+#define _DCI_CONFIG_H_
+
+#define DCI_CONFIG_REVISION 1
+
+extern EFI_GUID gDciConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This structure contains the policies which are related to Direct Connection Interface (DCI).
+
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ <b>(Test)</b> DCI enable (HDCIEN bit)
+ when Enabled, allow DCI to be enabled. When Disabled, the host control is not enabling DCI feature.
+ BIOS provides policy to enable or disable DCI, and user would be able to use BIOS option to change this policy.
+ The user changing the setting from disable to enable, is taken as a consent from the user to enable this DCI feature.
+ <b>0:Disabled</b>; 1:Enabled
+ **/
+ UINT32 DciEn : 1;
+ /**
+ <b>(Test)</b> When set to Auto detect mode, it detects CCA being connected during BIOS post time.
+ This policy only applies when DciEn is disabled.
+ NOTE: this policy should not be visible to end customer.
+ 0: Disable AUTO mode, <b>1: Enable AUTO mode</b>
+ **/
+ UINT32 DciAutoDetect : 1;
+ UINT32 RsvdBits : 30; ///< Reserved bits
+} SC_DCI_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _DCI_CONFIG_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/FlashProtectionConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/FlashProtectionConfig.h new file mode 100644 index 0000000000..904f7d6ced --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/FlashProtectionConfig.h @@ -0,0 +1,59 @@ +/** @file
+ Flash Protection policy.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _FLASH_PROTECTION_CONFIG_H_
+#define _FLASH_PROTECTION_CONFIG_H_
+
+#define FLASH_PROTECTION_CONFIG_REVISION 1
+
+extern EFI_GUID gFlashProtectionConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ The SC provides a method for blocking writes and reads to specific ranges
+ in the SPI flash when the Protected Ranges are enabled.
+ PROTECTED_RANGE is used to specify if flash protection are enabled,
+ the write protection enable bit and the read protection enable bit,
+ and to specify the upper limit and lower base for each register
+ Platform code is responsible to get the range base by ScGetSpiRegionAddresses routine,
+ and set the limit and base accordingly.
+
+**/
+typedef struct {
+ UINT32 WriteProtectionEnable : 1; ///< Write or erase is blocked by hardware. <b>0: Disable</b>; 1: Enable.
+ UINT32 ReadProtectionEnable : 1; ///< Read is blocked by hardware. <b>0: Disable</b>; 1: Enable.
+ UINT32 RsvdBits : 30; ///< Reserved
+ /**
+ The address of the upper limit of protection
+ This is a left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison
+ **/
+ UINT16 ProtectedRangeLimit;
+ /**
+ The address of the upper limit of protection
+ This is a left shifted address by 12 bits with address bits 11:0 are assumed to be 0
+ **/
+ UINT16 ProtectedRangeBase;
+} PROTECTED_RANGE;
+
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ PROTECTED_RANGE ProtectRange[SC_FLASH_PROTECTED_RANGES];
+} SC_FLASH_PROTECTION_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _FLASH_PROTECTION_CONFIG_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/GmmConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/GmmConfig.h new file mode 100644 index 0000000000..0f9ce312b1 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/GmmConfig.h @@ -0,0 +1,52 @@ +/** @file
+ GMM(Gaussian Mixture Model) scoring accelerator policy.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _GMM_CONFIG_H_
+#define _GMM_CONFIG_H_
+
+#define GMM_CONFIG_REVISION 1
+
+extern EFI_GUID gGmmConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This structure contains the policies which are related to GMM.
+
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 Enable : 1; ///< <b>1: Enable</b>, 0: Disable
+ UINT32 ClkGatingPgcbClkTrunk : 1; ///< GMM Clock Gating - PGCB Clock Trunk: 0: Disable, 1: Enable;
+ UINT32 ClkGatingSb : 1; ///< GMM Clock Gating - Sideband: 0: Disable, 1: Enable;
+ UINT32 ClkGatingSbClkTrunk : 1; ///< GMM Clock Gating - Sideband Clock Trunk: 0: Disable, 1: Enable;
+ UINT32 ClkGatingSbClkPartition : 1; ///< GMM Clock Gating - Sideband Clock Partition: 0: Disable, 1: Enable;
+ UINT32 ClkGatingCore : 1; ///< GMM Clock Gating - Core: 0: Disable, 1: Enable;
+ UINT32 ClkGatingDma : 1; ///< GMM Clock Gating - DMA: 0: Disable, 1: Enable;
+ UINT32 ClkGatingRegAccess : 1; ///< GMM Clock Gating - Register Access: 0: Disable, 1: Enable;
+ UINT32 ClkGatingHost : 1; ///< GMM Clock Gating - Host: 0: Disable, 1: Enable;
+ UINT32 ClkGatingPartition : 1; ///< GMM Clock Gating - Partition: 0: Disable, 1: Enable;
+ UINT32 ClkGatingTrunk : 1; ///< GMM Clock Gating - Trunk: 0: Disable, 1: Enable;
+ UINT32 SvPwrGatingHwAutoEnable : 1; ///< GMM Power Gating - HW Autonomous Enabled: 0: Disable, 1: Enable;
+ UINT32 SvPwrGatingD3HotEnable : 1; ///< GMM Power Gating - D3 Hot Enabled: 0: Disable, 1: Enable;
+ UINT32 SvPwrGatingI3Enable : 1; ///< GMM Power Gating - I3 Enabled: 0: Disable, 1: Enable;
+ UINT32 SvPwrGatingPmcReqEnable : 1; ///< GMM Power Gating - PMC Request Enabled: 0: Disable, 1: Enable;
+ UINT32 RsvdBits : 17; ///< Reserved bits
+} SC_GMM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _GMM_CONFIG_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/HdAudioConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/HdAudioConfig.h new file mode 100644 index 0000000000..9d7281e8aa --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/HdAudioConfig.h @@ -0,0 +1,114 @@ +/** @file
+ HD-Audio policy.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _HDAUDIO_CONFIG_H_
+#define _HDAUDIO_CONFIG_H_
+
+#define HDAUDIO_CONFIG_REVISION 3
+
+extern EFI_GUID gHdAudioConfigGuid;
+
+#pragma pack (push,1)
+
+typedef struct {
+ UINT32 VendorDeviceId; ///< Codec Vendor/Device ID
+ UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
+ UINT8 SdiNo; ///< SDI number, 0xFF matches any SDI.
+ UINT16 DataDwords; ///< Number of data DWORDs following the header.
+} HDA_VERB_TABLE_HEADER;
+
+typedef struct {
+ HDA_VERB_TABLE_HEADER VerbTableHeader;
+ UINT32 VerbTableData[];
+} HDAUDIO_VERB_TABLE;
+
+//
+// The SC_HDAUDIO_CONFIG block describes the expected configuration of the Intel HD Audio feature.
+//
+enum SC_HDAUDIO_IO_BUFFER_OWNERSHIP {
+ ScHdaIoBufOwnerHdaLink = 0, ///< HD-Audio link owns all the I/O buffers.
+ ScHdaIoBufOwnerHdaLinkI2sPort = 1, ///< HD-Audio link owns 4 and I2S port owns 4 of the I/O buffers.
+ ScHdaIoBufOwnerI2sPort = 3 ///< I2S0 and I2S1 ports own all the I/O buffers.
+};
+
+enum SC_HDAUDIO_IO_BUFFER_VOLTAGE {
+ ScHdaIoBuf33V = 0,
+ ScHdaIoBuf18V = 1
+};
+
+enum SC_HDAUDIO_DMIC_TYPE {
+ ScHdaDmicDisabled = 0,
+ ScHdaDmic2chArray = 1,
+ ScHdaDmic4chArray = 2
+};
+
+enum SC_HDAUDIO_VC_TYPE {
+ ScHdaVc0 = 0,
+ ScHdaVc1 = 1,
+ ScHdaVc2 = 2
+};
+
+typedef enum {
+ ScHdaLinkFreq6MHz = 0,
+ ScHdaLinkFreq12MHz = 1,
+ ScHdaLinkFreq24MHz = 2,
+ ScHdaLinkFreq48MHz = 3,
+ ScHdaLinkFreq96MHz = 4,
+ ScHdaLinkFreqInvalid
+} SC_HDAUDIO_LINK_FREQUENCY;
+
+typedef enum {
+ ScHdaIDispMode2T = 0,
+ ScHdaIDispMode1T = 1
+} SC_HDAUDIO_IDISP_TMODE;
+
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 Enable : 2;
+ UINT32 DspEnable : 1; ///< DSP enablement: 0: Disable; <b>1: Enable</b>
+ UINT32 Pme : 1; ///< Azalia wake-on-ring, <b>0: Disable</b>; 1: Enable
+ UINT32 IoBufferOwnership : 2; ///< I/O Buffer Ownership Select: <b>0: HD-A Link</b>; 1: Shared, HD-A Link and I2S Port; 3: I2S Ports
+ UINT32 IoBufferVoltage : 1; ///< I/O Buffer Voltage Mode Select: <b>0: 3.3V</b>; 1: 1.8V
+ UINT32 VcType : 1; ///< Virtual Channel Type Select: <b>0: VC0</b>, 1: VC1
+ UINT32 HdAudioLinkFrequency : 4; ///< HDA-Link frequency (SC_HDAUDIO_LINK_FREQUENCY enum): <b>2: 24MHz</b>, 1: 12MHz, 0: 6MHz
+ UINT32 IDispLinkFrequency : 4; ///< iDisp-Link frequency (SC_HDAUDIO_LINK_FREQUENCY enum): <b>4: 96MHz</b>, 3: 48MHz
+ UINT32 IDispLinkTmode : 1; ///< iDisp-Link T-Mode (SC_HDAUDIO_IDISP_TMODE enum): <b>0: 2T</b>, 1: 1T
+ UINT32 RsvdBits0 : 15; ///< Reserved bits
+ UINT32 DspEndpointDmic : 2; ///< DMIC Select (SC_HDAUDIO_DMIC_TYPE enum): 0: Disable; 1: 2ch array; <b>2: 4ch array</b>
+ UINT32 DspEndpointBluetooth : 1; ///< Bluetooth enablement: <b>0: Disable</b>; 1: Enable
+ UINT32 DspEndpointI2sSkp : 1; ///< I2S SHK enablement: <b>0: Disable</b>; 1: Enable
+ UINT32 DspEndpointI2sHp : 1; ///< I2S HP enablement: <b>0: Disable</b>; 1: Enable
+ UINT32 AudioCtlPwrGate : 1; ///< Deprecated
+ UINT32 AudioDspPwrGate : 1; ///< Deprecated
+ UINT32 Mmt : 1; ///< CSME Memory Transfers : 0: VC0, 1: VC2
+ UINT32 Hmt : 1; ///< Host Memory Transfers : 0: VC0, 1: VC2
+ UINT32 BiosCfgLockDown : 1; ///< BIOS Configuration Lock Down : 0: Disable, 1: Enable
+ UINT32 PwrGate : 1; ///< Power Gating : 0: Disable, 1: Enable
+ UINT32 ClkGate : 1; ///< Clock Gating : 0: Disable, 1: Enable
+ UINT32 RsvdBits1 : 20; ///< Reserved bits
+ UINT32 DspFeatureMask;
+ UINT32 DspPpModuleMask;
+ UINT16 ResetWaitTimer; ///< < <b>(Test)</b> The delay timer after Azalia reset, the value is number of microseconds. Default is <b>300</b>.
+ UINT8 Rsvd0[2]; ///< Reserved bytes, align to multiple 4
+ UINT32 RsvdBits3 : 2;
+ UINT32 RsvdBits2 : 30; ///< Reserved bits
+ UINT8 VerbTableEntryNum;
+ UINT32 VerbTablePtr;
+} SC_HDAUDIO_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _HDAUDIO_CONFIG_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/HpetConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/HpetConfig.h new file mode 100644 index 0000000000..d5dbf8fda1 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/HpetConfig.h @@ -0,0 +1,51 @@ +/** @file
+ HPET policy.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _HPET_CONFIG_H_
+#define _HPET_CONFIG_H_
+
+#define HPET_CONFIG_REVISION 1
+
+extern EFI_GUID gHpetConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ The SC_HPET_CONFIG block passes the bus/device/function value for HPET.
+ The address resource range of HPET must be reserved in E820 and ACPI as
+ system resource.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ Determines if enable HPET timer. 0: Disable; <b>1: Enable</b>.
+ The HPET timer address decode is always enabled.
+ This policy is used to configure the HPET timer count, and also the _STA of HPET device in ACPI.
+ While enabled, the HPET timer is started, else the HPET timer is halted.
+ **/
+ UINT32 Enable : 1; ///< Determines if enable HPET function
+ UINT32 BdfValid : 1; ///< Whether the BDF value is valid. <b>0: Disable</b>; 1: Enable.
+ UINT32 RsvdBits0 : 6; ///< Reserved bits
+ UINT32 BusNumber : 8; ///< Bus Number HPETn used as Requestor / Completer ID. Default is <b>0xFA</b>.
+ UINT32 DeviceNumber : 5; ///< Device Number HPETn used as Requestor / Completer ID. Default is <b>0x1F</b>.
+ UINT32 FunctionNumber : 3; ///< Function Number HPETn used as Requestor / Completer ID. Default is <b>0x00</b>.
+ UINT32 RsvdBits1 : 8; ///< Reserved bits
+ UINT32 Base; ///< The HPET base address. Default is <b>0xFED00000</b>.
+} SC_HPET_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _HPET_CONFIG_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/IoApicConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/IoApicConfig.h new file mode 100644 index 0000000000..8213f54255 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/IoApicConfig.h @@ -0,0 +1,46 @@ +/** @file
+ Io Apic policy.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _IOAPIC_CONFIG_H_
+#define _IOAPIC_CONFIG_H_
+
+#define IOAPIC_CONFIG_REVISION 1
+
+extern EFI_GUID gIoApicConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This structure contains the policies which are related to IO Apic.
+
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 BdfValid : 1; ///< Set to 1 if BDF value is valid, SC code will not program these fields if this bit is not TRUE. <b>0: Disable</b>; 1: Enable.
+ UINT32 RsvdBits0 : 7; ///< Reserved bits
+ UINT32 BusNumber : 8; ///< Bus/Device/Function used as Requestor / Completer ID. Default is <b>0xFA</b>.
+ UINT32 DeviceNumber : 5; ///< Bus/Device/Function used as Requestor / Completer ID. Default is <b>0x0F</b>.
+ UINT32 FunctionNumber : 3; ///< Bus/Device/Function used as Requestor / Completer ID. Default is <b>0x00</b>.
+ UINT32 IoApicEntry24_119 : 1; ///< 0: Disable; <b>1: Enable</b> IOAPIC Entry 24-119
+ UINT32 RsvdBits1 : 7; ///< Reserved bits
+ UINT8 IoApicId; ///< This member determines IOAPIC ID.
+ UINT8 ApicRangeSelect; ///< Define address bits 19:12 for the IOxAPIC range. Default is <b>0</b>
+ UINT8 Rsvd0[2]; ///< Reserved bytes
+} SC_IOAPIC_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _IOAPIC_CONFIG_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/IshConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/IshConfig.h new file mode 100644 index 0000000000..fc2bc43f54 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/IshConfig.h @@ -0,0 +1,37 @@ +/** @file
+ ISH policy.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _ISH_CONFIG_H_
+#define _ISH_CONFIG_H_
+
+#define ISH_CONFIG_REVISION 1
+
+extern EFI_GUID gIshConfigGuid;
+
+#pragma pack (push,1)
+
+//
+// The SC_ISH_CONFIG block describes Integrated Sensor Hub device.
+//
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 Enable : 1; ///< ISH Controler 0: Disable; <b>1: Enable</b>.
+ UINT32 RsvdBits0: 31; ///< Reserved Bits
+} SC_ISH_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _ISH_CONFIG_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/LockDownConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/LockDownConfig.h new file mode 100644 index 0000000000..cacf48bb62 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/LockDownConfig.h @@ -0,0 +1,41 @@ +/** @file
+ Lock down policy.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _LOCK_DOWN_CONFIG_H_
+#define _LOCK_DOWN_CONFIG_H_
+
+#define LOCK_DOWN_CONFIG_REVISION 2
+
+extern EFI_GUID gLockDownConfigGuid;
+
+#pragma pack (push,1)
+
+typedef struct {
+
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 GlobalSmi : 1;
+ UINT32 BiosInterface : 1;
+ UINT32 RtcLock : 1;
+ UINT32 BiosLock : 1;
+ UINT32 SpiEiss : 1;
+ UINT32 BiosLockSwSmiNumber: 8;
+ UINT32 TcoLock : 1;
+ UINT32 RsvdBits0 : 18; ///< Reserved bits
+} SC_LOCK_DOWN_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _LOCK_DOWN_CONFIG_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/LpcConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/LpcConfig.h new file mode 100644 index 0000000000..1034b99b39 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/LpcConfig.h @@ -0,0 +1,43 @@ +/** @file
+ Lpc policy.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _LPC_CONFIG_H_
+#define _LPC_CONFIG_H_
+
+#define LPC_PREMEM_CONFIG_REVISION 1
+
+extern EFI_GUID gLpcPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This structure contains the policies which are related to LPC.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ Enhance the port 8xh decoding.
+ Original LPC only decodes one byte of port 80h, with this enhancement LPC can decode word or dword of port 80h-83h.
+ @note: this will occupy one LPC generic IO range register. While this is enabled, read from port 80h always return 0x00.
+ 0: Disable, <b>1: Enable</b>
+ **/
+ UINT32 EnhancePort8xhDecoding : 1;
+ UINT32 RsvdBits : 31; ///< Reserved bits
+} SC_LPC_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _LPC_CONFIG_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/LpssConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/LpssConfig.h new file mode 100644 index 0000000000..09adde126e --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/LpssConfig.h @@ -0,0 +1,81 @@ +/** @file
+ LPSS policy.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _LPSS_CONFIG_H_
+#define _LPSS_CONFIG_H_
+
+#define LPSS_CONFIG_REVISION 2
+
+extern EFI_GUID gLpssConfigGuid;
+
+#pragma pack (push,1)
+
+#define LPSS_I2C_DEVICE_NUM 8
+#define LPSS_HSUART_DEVICE_NUM 4
+#define LPSS_SPI_DEVICE_NUM 3
+
+/**
+ The SC_LPSS_CONFIG block describes Low Power Sub System (LPSS) settings for SC.
+ @note: the order defined below is per the PCI BDF sequence, and MUST not change.
+ Items defined will be accessed by its index in ScInit module
+
+**/
+typedef struct {
+ /**
+ Revision 1: Init version
+ Revision 2: Deprecated ExiEnable
+ **/
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ Determine if I2C_n is enabled.
+ 0: Disabled; <b>1: PCI Mode</b>; 2: ACPI Mode;
+ **/
+ SC_DEV_MODE I2c0Enable;
+ SC_DEV_MODE I2c1Enable;
+ SC_DEV_MODE I2c2Enable;
+ SC_DEV_MODE I2c3Enable;
+ SC_DEV_MODE I2c4Enable;
+ SC_DEV_MODE I2c5Enable;
+ SC_DEV_MODE I2c6Enable;
+ SC_DEV_MODE I2c7Enable;
+ /**
+ Determine if UART_n is enabled.
+ 0: Disabled; <b>1: PCI Mode</b>; 2: ACPI Mode;
+ **/
+ SC_DEV_MODE Hsuart0Enable;
+ SC_DEV_MODE Hsuart1Enable;
+ SC_DEV_MODE Hsuart2Enable;
+ SC_DEV_MODE Hsuart3Enable;
+ /**
+ Determine if SPI_n is enabled.
+ 0: Disabled; <b>1: PCI Mode</b>; 2: ACPI Mode;
+ **/
+ SC_DEV_MODE Spi0Enable;
+ SC_DEV_MODE Spi1Enable;
+ SC_DEV_MODE Spi2Enable;
+ UINT32 Uart2KernelDebugBaseAddress;
+ UINT8 I2cClkGateCfg[LPSS_I2C_DEVICE_NUM];
+ UINT8 HsuartClkGateCfg[LPSS_HSUART_DEVICE_NUM];
+ UINT8 SpiClkGateCfg[LPSS_SPI_DEVICE_NUM];
+ UINT32 S0ixEnable : 1; ///< <b>0: Disabled</b>; 1: Enabled
+ UINT32 OsDbgEnable : 1; ///< <b>0: Disabled</b>; 1: Enabled
+ UINT32 ExiEnable : 1; ///< @deprecated, please use DciEn from SC_DCI_CONFIG
+ UINT32 RsvdBits : 29;
+} SC_LPSS_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _LPSS_CONFIG_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/P2sbConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/P2sbConfig.h new file mode 100644 index 0000000000..600357d6ff --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/P2sbConfig.h @@ -0,0 +1,42 @@ +/** @file
+ P2SB policy.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _P2SB_CONFIG_H_
+#define _P2SB_CONFIG_H_
+
+#define P2SB_CONFIG_REVISION 1
+
+extern EFI_GUID gP2sbConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This structure contains the policies which are related to P2SB Interface.
+
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ <b>(Test)</b> P2SB
+ <b>0:Hide</b>; 1:UnHide
+ **/
+ UINT32 P2sbUnhide : 1;
+ UINT32 RsvdBytes :31; ///< Reserved bytes
+} SC_P2SB_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _P2SB_CONFIG_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/PcieRpConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/PcieRpConfig.h new file mode 100644 index 0000000000..a41fe76d7e --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/PcieRpConfig.h @@ -0,0 +1,238 @@ +/** @file
+ PCIe root port policy.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SC_PCIE_CONFIG_H_
+#define _SC_PCIE_CONFIG_H_
+
+#define PCIE_RP_PREMEM_CONFIG_REVISION 2
+#define PCIE_RP_CONFIG_REVISION 4
+
+extern EFI_GUID gPcieRpPreMemConfigGuid;
+extern EFI_GUID gPcieRpConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ The SC_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each SC PCIe root port.
+
+**/
+typedef struct {
+ UINT32 Perst; ///< PCIe reset# pin GPIO pad offset.
+ UINT32 Clock; ///< PCIe clock# ping GPIO pad offset.
+} SC_PCIE_ROOT_PORT_PREMEM_CONFIG;
+
+/**
+ The SC_PCIE_PREMEM_CONFIG block describes the expected configuration of the SC PCI Express controllers
+
+**/
+typedef struct {
+ /**
+ Revision 1: Init version
+
+ Revision 2: Add StartTimerTickerOfPerstAssert.
+
+ Revision 3: Add Clock in Root Port.
+ **/
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ These members describe the configuration of each PCH PCIe root port.
+ **/
+ SC_PCIE_ROOT_PORT_PREMEM_CONFIG RootPort[SC_MAX_PCIE_ROOT_PORTS];
+ /**
+ The Start Timer Ticker of PFET be asserted.
+ This policy item is primary for responsiveness improvement.
+ BIOS can utilize this policy item to reduce the delay time in ScConfigurePciePowerSequence()
+ **/
+ UINTN StartTimerTickerOfPfetAssert;
+} SC_PCIE_PREMEM_CONFIG;
+
+//
+// SW SMI values which are used by SC Policy
+//
+#define SW_SMI_PCIE_ASPM_OVERRIDE 0xAA
+
+enum SC_PCIE_SPEED {
+ ScPcieAuto,
+ ScPcieGen1,
+ ScPcieGen2,
+ ScPcieGen3
+};
+
+typedef enum {
+ ScPcieAspmDisabled,
+ ScPcieAspmL0s,
+ ScPcieAspmL1,
+ ScPcieAspmL0sL1,
+ ScPcieAspmAutoConfig,
+ ScPcieAspmMax
+} SC_PCIE_ASPM_CONTROL;
+
+typedef enum {
+ ScPcieL1SubstatesDisabled,
+ ScPcieL1SubstatesL1_1,
+ ScPcieL1SubstatesL1_2,
+ ScPcieL1SubstatesL1_1_2,
+ ScPcieL1SubstatesMax
+} SC_PCIE_L1SUBSTATES_CONTROL;
+
+enum SC_PCIE_COMPLETION_TIMEOUT {
+ ScPcieCompletionTO_Default,
+ ScPcieCompletionTO_50_100us,
+ ScPcieCompletionTO_1_10ms,
+ ScPcieCompletionTO_16_55ms,
+ ScPcieCompletionTO_65_210ms,
+ ScPcieCompletionTO_260_900ms,
+ ScPcieCompletionTO_1_3P5s,
+ ScPcieCompletionTO_4_13s,
+ ScPcieCompletionTO_17_64s,
+ ScPcieCompletionTO_Disabled
+};
+
+/**
+ The SC_PCIE_CONFIG block describes the expected configuration of the PCI Express controllers
+
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 Enable : 2; ///< Root Port enabling, 0: Disable; 1: Enable; 2: Auto.
+ UINT32 Hide : 1; ///< Whether or not to hide the configuration space of this port.
+ UINT32 SlotImplemented : 1; ///< Indicates whether the root port is connected to a slot.
+ UINT32 HotPlug : 1; ///< Indicate whether the root port is hot plug available.
+ UINT32 PmSci : 1; ///< Indicate whether the root port power manager SCI is enabled.
+ UINT32 ExtSync : 1; ///< Indicate whether the extended synch is enabled.
+ UINT32 TransmitterHalfSwing : 1; ///< Indicate whether the Transmitter Half Swing is enabled.
+ UINT32 AcsEnabled : 1; ///< Indicate whether the ACS is enabled
+
+ UINT32 RsvdBits0 : 5; ///< Reserved bits.
+ UINT32 ClkReqSupported : 1; ///< Indicate whether dedicated CLKREQ# is supported by the port.
+ /**
+ The ClkReq Signal mapped to this root port. Default is zero. Valid if ClkReqSupported is TRUE.
+ This Number should not exceed the Maximum Available ClkReq Signals.
+ **/
+ UINT32 ClkReqNumber : 4;
+ /**
+ Probe CLKREQ# signal before enabling CLKREQ# based power management.
+ Conforming device shall hold CLKREQ# low until CPM is enabled. This feature attempts
+ to verify CLKREQ# signal is connected by testing pad state before enabling CPM.
+ In particular this helps to avoid issues with open-ended PCIe slots.
+ This is only applicable to non hot-plug ports.
+ <b>0: Disable</b>; 1: Enable.
+ **/
+ UINT32 ClkReqDetect : 1;
+ //
+ // Error handlings
+ //
+ UINT32 AdvancedErrorReporting : 1; ///< Indicate whether the Advanced Error Reporting is enabled
+ UINT32 UnsupportedRequestReport : 1; ///< Indicate whether the Unsupported Request Report is enabled.
+ UINT32 FatalErrorReport : 1; ///< Indicate whether the Fatal Error Report is enabled.
+ UINT32 NoFatalErrorReport : 1; ///< Indicate whether the No Fatal Error Report is enabled.
+ UINT32 CorrectableErrorReport : 1; ///< Indicate whether the Correctable Error Report is enabled.
+ UINT32 PmeInterrupt : 1; ///< Indicate whether the PME Interrupt is enabled.
+ UINT32 SystemErrorOnFatalError : 1; ///< Indicate whether the System Error on Fatal Error is enabled.
+ UINT32 SystemErrorOnNonFatalError : 1; ///< Indicate whether the System Error on Non Fatal Error is enabled.
+ UINT32 SystemErrorOnCorrectableError : 1; ///< Indicate whether the System Error on Correctable Error is enabled.
+ UINT32 Rsvdbits1 : 3; ///< Reserved fields for future expansion w/o protocol change
+ /**
+ Determines each PCIE Port speed capability.
+ 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: SC_PCIE_SPEED)
+ **/
+ UINT8 PcieSpeed;
+ UINT8 PhysicalSlotNumber; ///< Indicates the slot number for the root port.
+ UINT8 CompletionTimeout; ///< The completion timeout configuration of the root port (see: SC_PCIE_COMPLETION_TIMEOUT)
+ UINT8 Reserved0; ///< Reserved byte
+ UINT32 PtmEnable : 1; ///< PTM enabling, <b>0: Disable</b>; 1: Enable.
+ /**
+ Selectable De-emphasis enabling.
+ When the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis for an Upstream component.
+ 1b: -3.5 dB, 0b:-6 dB
+ 0: Disable; <b>1: Enable</b>.
+ **/
+ UINT32 SelectableDeemphasis : 1;
+ UINT32 Rsvdbits2 : 30; ///< Reserved Bits
+ UINT32 Reserved1[1]; ///< Reserved bytes
+ //
+ // Power Management
+ //
+ UINT8 Aspm; ///< The ASPM configuration of the root port (see: SC_PCIE_ASPM_CONTROL)
+ UINT8 L1Substates; ///< The L1 Substates configuration of the root port (see: SC_PCIE_L1SUBSTATES_CONTROL)
+ UINT8 LtrEnable; ///< Latency Tolerance Reporting Mechanism.
+ UINT8 LtrConfigLock; ///< <b>0: Disable</b>; 1: Enable.
+ UINT16 LtrMaxSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Snoop Latency.
+ UINT16 LtrMaxNoSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Non-Snoop Latency.
+ UINT8 SnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Mode.
+ UINT8 SnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Multiplier.
+ UINT16 SnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Value.
+ UINT8 NonSnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
+ UINT8 NonSnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
+ UINT16 NonSnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Value.
+ UINT32 SlotPowerLimitScale : 2; ///< <b>(Test)</b> Specifies scale used for slot power limit value. Leave as 0 to set to default.
+ UINT32 SlotPowerLimitValue : 12; ///< <b>(Test)</b> Specifies upper limit on power supplie by slot. Leave as 0 to set to default.
+ UINT32 Rsvdbits3 : 18; ///< Reserved Bits
+ UINT32 Reserved2[16]; ///< Reserved bytes
+ UINT8 PcieRootRsvd0;
+} SC_PCIE_ROOT_PORT_CONFIG;
+
+/**
+ The SC_PCIE_CONFIG block describes the expected configuration of the SC PCI Express controllers
+
+**/
+typedef struct {
+ /**
+ Revision 1: Init version
+ Revision 2: Add ComplianceTestMode.
+ Revision 3: Add SelectableDeemphasis
+ **/
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ These members describe the configuration of each SC PCIe root port.
+ **/
+ SC_PCIE_ROOT_PORT_CONFIG RootPort[SC_MAX_PCIE_ROOT_PORTS];
+ /**
+ This member describes whether PCIE root port Port 8xh Decode is enabled
+ **/
+ UINT32 EnablePort8xhDecode : 1;
+ /**
+ The Index of PCIe Port that is selected for Port8xh Decode (0 Based)
+ **/
+ UINT32 ScPciePort8xhDecodePortIndex : 5;
+ /**
+ This member describes whether the PCI Express Clock Gating for each root port
+ is enabled by platform modules. It is enabled by default.
+ **/
+ UINT32 DisableRootPortClockGating : 1;
+ /**
+ This member describes whether Peer Memroy Writes are enabled on the platform
+ **/
+ UINT32 EnablePeerMemoryWrite : 1;
+ /**
+ This member describes the SwSmi value for override PCIe ASPM table. Default is <b>0xAA</b>
+ **/
+ UINT32 AspmSwSmiNumber : 8;
+ /**
+ Compliance Mode shall be enabled when using Compliance Load Board.
+ <b>0: Disable</b>, 1: Enable
+ **/
+ UINT32 ComplianceTestMode : 1;
+ UINT32 Rsvdbits : 15;
+
+ UINT32 PcieRsvdBits0 : 2;
+ UINT32 SvRsvdbits : 30;
+ UINT32 Reserved[3]; ///< Reserved bytes
+} SC_PCIE_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _SC_PCIE_CONFIG_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/PmConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/PmConfig.h new file mode 100644 index 0000000000..6a9fe614bf --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/PmConfig.h @@ -0,0 +1,55 @@ +/** @file
+ Power Management policy.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PM_CONFIG_H_
+#define _PM_CONFIG_H_
+
+#define PM_CONFIG_REVISION 2
+
+extern EFI_GUID gPmConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This structure allows to customize wake up capability from wake events.
+
+**/
+typedef struct {
+ UINT32 PmeB0S5Dis : 1;
+ UINT32 Rsvdbits : 31;
+} SC_WAKE_CONFIG;
+
+/**
+ The SC_PM_CONFIG block describes expected miscellaneous power management settings.
+ The PowerResetStatusClear field would clear the Power/Reset status bits, please
+ set the bits if you want PCH Init driver to clear it, if you want to check the
+ status later then clear the bits.
+
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ SC_WAKE_CONFIG WakeConfig; ///< Specify Wake Policy
+ UINT32 PciClockRun : 1;
+ UINT32 Timer8254ClkGateEn : 1;
+ UINT32 PwrBtnOverridePeriod : 3;
+ UINT32 DisableNativePowerButton : 1;
+ UINT32 PowerButterDebounceMode : 1;
+ UINT32 Rsvdbits :25;
+} SC_PM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _PM_CONFIG_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/SataConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/SataConfig.h new file mode 100644 index 0000000000..5e0a234b2a --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/SataConfig.h @@ -0,0 +1,79 @@ +/** @file
+ SATA policy.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SATA_CONFIG_H_
+#define _SATA_CONFIG_H_
+
+#define SATA_CONFIG_REVISION 1
+
+extern EFI_GUID gSataConfigGuid;
+
+#pragma pack (push,1)
+
+typedef enum {
+ ScSataModeAhci,
+ ScSataModeRaid,
+ ScSataModeMax
+} SC_SATA_MODE;
+
+typedef enum {
+ ScSataSpeedDefault,
+ ScSataSpeedGen1,
+ ScSataSpeedGen2,
+ ScSataSpeedGen3
+} SC_SATA_SPEED;
+
+typedef struct {
+ UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>
+ UINT32 HotPlug : 1; ///< <b>0: Disable</b>; 1: Enable
+ UINT32 InterlockSw : 1; ///< <b>0: Disable</b>; 1: Enable
+ UINT32 External : 1; ///< <b>0: Disable</b>; 1: Enable
+ UINT32 SpinUp : 1; ///< <b>0: Disable</b>; 1: Enable the COMRESET initialization Sequence to the device
+ UINT32 SolidStateDrive : 1; ///< <b>0: HDD</b>; 1: SSD
+ UINT32 DevSlp : 1; ///< <b>0: Disable</b>; 1: Enable DEVSLP on the port
+ UINT32 EnableDitoConfig : 1; ///< <b>0: Disable</b>; 1: Enable DEVSLP Idle Timeout settings (DmVal, DitoVal)
+ UINT32 DmVal : 4; ///< DITO multiplier. Default is <b>15</b>.
+ UINT32 DitoVal : 10; ///< DEVSLP Idle Timeout (DITO), Default is <b>625</b>.
+ UINT32 Rsvdbits0 : 10; ///< Reserved fields for future expansion w/o protocol change
+} SC_SATA_PORT_CONFIG;
+
+//
+// The SC_SATA_CONFIG block describes the expected configuration of the SATA controllers.
+//
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ //
+ // This member describes whether or not the SATA controllers should be enabled.
+ //
+ UINT32 Enable : 1;
+ UINT32 TestMode : 1; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Allow entrance to the SATA test modes
+ UINT32 SalpSupport : 1; ///< 0: Disable; <b>1: Enable</b> Aggressive Link Power Management
+ UINT32 PwrOptEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA Power Optimizer on SC side.
+ UINT32 eSATASpeedLimit : 1;
+ UINT32 Rsvdbits : 27; ///< Reserved bits
+ SC_SATA_MODE SataMode;
+ SC_SATA_SPEED SpeedLimit;
+ //
+ // This member configures the features, property, and capability for each SATA port.
+ //
+ SC_SATA_PORT_CONFIG PortSettings[SC_MAX_SATA_PORTS];
+ UINT32 Reserved; ///< Reserved bytes
+ UINT32 Reserved1[3]; ///< Reserved fields for future expansion
+} SC_SATA_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _SATA_CONFIG_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/ScGeneralConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/ScGeneralConfig.h new file mode 100644 index 0000000000..4c919f6a64 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/ScGeneralConfig.h @@ -0,0 +1,41 @@ +/** @file
+ SC General policy.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SC_GENERAL_CONFIG_H_
+#define _SC_GENERAL_CONFIG_H_
+
+#define SC_GENERAL_CONFIG_REVISION 1
+
+extern EFI_GUID gScGeneralConfigGuid;
+
+#pragma pack (push,1)
+
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT16 SubSystemVendorId; ///< Default Subsystem Vendor ID of the SC devices. Default is <b>0x8086</b>
+ UINT16 SubSystemId; ///< Default Subsystem ID of the SC devices. Default is <b>0x7270</b>
+ UINT16 AcpiBase; ///< Power management I/O base address. Default is <b>0x400</b>.
+ UINT32 PmcBase; ///< PMC Base Address. Default is <b>0xD1001000</b>.
+ UINT32 P2sbBase; ///< P2SB base Address. Default is <b>0xD0000000</b>.
+ UINT32 Crid : 1;
+ UINT32 S0ixSupport : 1;
+ UINT32 ResetSelect : 4;
+ UINT32 RsvdBits0 : 26; ///< Reserved bits
+} SC_GENERAL_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _SC_GENERAL_CONFIG_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/ScInterruptAssign.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/ScInterruptAssign.h new file mode 100644 index 0000000000..895ea00b18 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/ScInterruptAssign.h @@ -0,0 +1,72 @@ +/** @file
+ IoApic policy.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _INTERRUPT_CONFIG_H_
+#define _INTERRUPT_CONFIG_H_
+
+#define INTERRUPT_CONFIG_REVISION 1
+
+extern EFI_GUID gInterruptConfigGuid;
+
+#pragma pack (push,1)
+
+//
+// --------------------- Interrupts Config ------------------------------
+//
+typedef struct {
+ UINT8 Port;
+ UINT16 PciCfgOffset;
+ UINT8 PciIrqNumber;
+ UINT8 IrqPin;
+} PRIVATE_PCICFGCTRL;
+
+typedef enum {
+ ScNoInt, ///< No Interrupt Pin
+ ScIntA,
+ ScIntB,
+ ScIntC,
+ ScIntD
+} SC_INT_PIN;
+
+//
+// The SC_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for SC device.
+//
+typedef struct {
+ UINT8 Device; ///< Device number
+ UINT8 Function; ///< Device function
+ UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SC_INT_PIN)
+ UINT8 Irq; ///< IRQ to be set for device.
+} SC_DEVICE_INTERRUPT_CONFIG;
+
+#define SC_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all SC devices
+#define SC_MAX_PXRC_CONFIG 8 ///< Number of PXRC registers in ITSS
+#define SC_MAX_DIRECT_IRQ_CONFIG 25 ///< Number of direct Irq Table
+
+//
+// The SC_INTERRUPT_CONFIG block describes interrupt settings for SC.
+//
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT8 NumOfDevIntConfig; ///< Number of entries in DevIntConfig table
+ UINT8 NumOfDirectIrqTable;
+ PRIVATE_PCICFGCTRL DirectIrqTable[SC_MAX_DIRECT_IRQ_CONFIG];
+ SC_DEVICE_INTERRUPT_CONFIG DevIntConfig[SC_MAX_DEVICE_INTERRUPT_CONFIG]; ///< Array which stores SC devices interrupts settings
+ UINT8 PxRcRouting[SC_MAX_PXRC_CONFIG];
+} SC_INTERRUPT_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _INTERRUPT_CONFIG_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/ScsConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/ScsConfig.h new file mode 100644 index 0000000000..2a8c72c110 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/ScsConfig.h @@ -0,0 +1,122 @@ +/** @file
+ Scs policy.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SCS_CONFIG_H_
+#define _SCS_CONFIG_H_
+
+#define SCS_CONFIG_REVISION 3
+
+extern EFI_GUID gScsConfigGuid;
+
+#pragma pack (push,1)
+
+//
+// Device Operating Mode
+//
+typedef enum {
+ ScDisabled = 0,
+ ScPciMode = 1,
+ ScAcpiMode = 2,
+ ScDevModeMax
+} SC_DEV_MODE;
+
+//
+// SCC eMMC Host Speed
+//
+enum SCC_EMMC_MODE {
+ SccEmmcHs400 = 0,
+ SccEmmcHs200 = 1,
+ SccEmmcDdr50 = 2,
+};
+
+/**
+ The SDIO_REG_CONFIG block is the structure defined in SC_SCS_CONFIG for SC.
+ @note: the order defined below is for SDIO DLL registers settings, and MUST not change.
+ Items defined will be accessed by its index in ConfigureSdioDll module
+
+**/
+typedef struct {
+ UINT32 TxCmdCntl;
+ UINT32 TxDataCntl1;
+ UINT32 TxDataCntl2;
+ UINT32 RxCmdDataCntl1;
+ UINT32 RxCmdDataCntl2;
+} SDIO_REG_CONFIG;
+
+/**
+ The SDCARD_REG_CONFIG block is the structure defined in SC_SCS_CONFIG for SC.
+ @note: the order defined below is for SDCARD DLL registers settings, and MUST not change.
+ Items defined will be accessed by its index in ConfigureSdioDll module
+
+**/
+typedef struct {
+ UINT32 TxCmdCntl;
+ UINT32 TxDataCntl1;
+ UINT32 TxDataCntl2;
+ UINT32 RxCmdDataCntl1;
+ UINT32 RxStrobeCntl;
+ UINT32 RxCmdDataCntl2;
+} SDCARD_REG_CONFIG;
+
+/**
+ The EMMC_REG_CONFIG block is the structure defined in SC_SCS_CONFIG for SC.
+ @note: the order defined below is for EMMC DLL registers settings, and MUST not change.
+ Items defined will be accessed by its index in ConfigureSdioDll module
+**/
+typedef struct {
+ UINT32 TxCmdCntl;
+ UINT32 TxDataCntl1;
+ UINT32 TxDataCntl2;
+ UINT32 RxCmdDataCntl1;
+ UINT32 RxStrobeCntl;
+ UINT32 RxCmdDataCntl2;
+ UINT32 MasterSwCntl;
+} EMMC_REG_CONFIG;
+
+//
+// SCC eMMC Trace Length
+//
+#define SCC_EMMC_LONG_TRACE_LEN 0
+#define SCC_EMMC_SHORT_TRACE_LEN 1
+
+/**
+ The SC_SCS_CONFIG block describes Storage and Communication Subsystem (SCS) settings for SC.
+ @note: the order defined below is per the PCI BDF sequence, and MUST not change.
+ Items defined will be accessed by its index in ScInit module
+**/
+typedef struct {
+/**
+ Revision 1: Init version
+ Revision 2: Add SccEmmcTraceLength
+ Revision 3: Add SDIO_REG_CONFIG and SDCARD_REG_CONFIG and EMMC_REG_CONFIG structures.
+**/
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header //ChangeLog, Revision 1: Init version, Revision 2: Add SccEmmcTraceLength
+ SC_DEV_MODE SdcardEnable; ///< Determine if SD Card is enabled - 0: Disabled, <b>1: Enabled</b>. Default is <b>ScPciMode</b>
+ SC_DEV_MODE EmmcEnable; ///< Determine if eMMC is enabled - 0: Disabled, <b>1: Enabled</b>. Default is <b>ScPciMode</b>
+ SC_DEV_MODE UfsEnable; ///< Determine if UFS is enabled - <b>0: Disabled</b>, 1: Enabled.
+ SC_DEV_MODE SdioEnable; ///< Determine if SDIO is enabled - 0: Disabled, <b>1: Enabled</b>. Default is <b>ScPciMode</b>
+ UINT32 EmmcHostMaxSpeed : 2; ///< Determine eMMC Mode. Default is <b>0: HS400</b>, 1: HS200, 2:DDR50
+ UINT32 GppLock : 1; ///< Determine if GPP is locked <b>0: Disabled</b>; 1: Enabled
+ UINT32 SccEmmcTraceLength : 2; ///< Determine EMMC Trace length - 0: Longer Trace, Validated on Rvp <b>1: Shorter trace, Validated on FFD</b>. Default is <b>SCC_EMMC_LONG_TRACE_LEN</b>
+ UINT32 RsvdBits : 27; ///< Reserved bits
+ SDIO_REG_CONFIG SdioRegDllConfig; ///< SDIO DLL Configure structure
+ SDCARD_REG_CONFIG SdcardRegDllConfig; ///< SDCARD DLL Configure structure
+ EMMC_REG_CONFIG EmmcRegDllConfig; ///< eMMC DLL Configure structure
+} SC_SCS_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _SCS_CONFIG_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/SerialIrqConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/SerialIrqConfig.h new file mode 100644 index 0000000000..59c57e6aaf --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/SerialIrqConfig.h @@ -0,0 +1,50 @@ +/** @file
+ Serial IRQ policy.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SERIAL_IRQ_CONFIG_H_
+#define _SERIAL_IRQ_CONFIG_H_
+
+#define SERIAL_IRQ_CONFIG_REVISION 1
+
+extern EFI_GUID gSerialIrqConfigGuid;
+
+#pragma pack (push,1)
+
+typedef enum {
+ ScQuietMode,
+ ScContinuousMode
+} SC_SIRQ_MODE;
+
+typedef enum {
+ ScSfpw4Clk,
+ ScSfpw6Clk,
+ ScSfpw8Clk
+} SC_START_FRAME_PULSE;
+
+//
+// The SC_LPC_SIRQ_CONFIG block describes the expected configuration for Serial IRQ.
+//
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 SirqEnable : 1; ///< Determines if enable Serial IRQ. 0: Disable; <b>1: Enable</b>.
+ UINT32 SirqMode : 2; ///< Serial IRQ Mode Select. Refer to SC_SIRQ_MODE for each value. <b>0: quiet mode</b> 1: continuous mode.
+ UINT32 StartFramePulse : 3; ///< Start Frame Pulse Width. Refer to SC_START_FRAME_PULSE for each value. Default is <b>ScSfpw4Clk</b>.
+ UINT32 RsvdBits0 : 26; ///< Reserved bits
+} SC_LPC_SIRQ_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _SERIAL_IRQ_CONFIG_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/SmbusConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/SmbusConfig.h new file mode 100644 index 0000000000..4cc1788fd8 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/SmbusConfig.h @@ -0,0 +1,44 @@ +/** @file
+ Smbus policy.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SMBUS_CONFIG_H_
+#define _SMBUS_CONFIG_H_
+
+#define SMBUS_CONFIG_REVISION 1
+
+extern EFI_GUID gSmbusConfigGuid;
+
+#pragma pack (push,1)
+
+#define SC_MAX_SMBUS_RESERVED_ADDRESS 128
+
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 Enable : 1;
+ UINT32 ArpEnable : 1; ///< Enable SMBus ARP support, <b>0: Disable</b>; 1: Enable.
+ UINT32 DynamicPowerGating : 1; ///< <b>(Test)</b> <b>Disable</b> or Enable Smbus dynamic power gating.
+ UINT32 RsvdBits0 : 29; ///< Reserved bits
+ UINT16 SmbusIoBase; ///< SMBUS Base Address (IO space). Default is <b>0xEFA0</b>.
+ UINT8 Rsvd0; ///< Reserved bytes
+ UINT8 NumRsvdSmbusAddresses; ///< The number of elements in the RsvdSmbusAddressTable.
+ UINT8 RsvdSmbusAddressTable[SC_MAX_SMBUS_RESERVED_ADDRESS];
+ UINT32 SpdRsvd : 2;
+ UINT32 SvRsvdbits : 30;
+} SC_SMBUS_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _SMBUS_CONFIG_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/UsbConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/UsbConfig.h new file mode 100644 index 0000000000..a29f8cc205 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/UsbConfig.h @@ -0,0 +1,107 @@ +/** @file
+ USB policy.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _USB_CONFIG_H_
+#define _USB_CONFIG_H_
+
+#define USB_CONFIG_REVISION 2
+
+extern EFI_GUID gUsbConfigGuid;
+
+#pragma pack (push,1)
+
+typedef enum {
+ ScUsbOverCurrentPin0 = 0,
+ ScUsbOverCurrentPin1,
+ ScUsbOverCurrentPinSkip,
+ ScUsbOverCurrentPinMax
+} SC_USB_OVERCURRENT_PIN;
+
+#define XHCI_MODE_OFF 0
+#define XHCI_MODE_ON 1
+
+typedef struct {
+ UINT8 Mode : 2; /// 0: Disable; 1: Enable, 2: Auto, 3: Smart Auto
+ UINT8 Rsvdbits : 4;
+} SC_USB30_CONTROLLER_SETTINGS;
+
+typedef struct {
+ UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>.
+ UINT32 RsvdBits0 : 31; ///< Reserved bits
+ UINT8 OverCurrentPin;
+ UINT8 Rsvd0[3]; ///< Reserved bytes, align to multiple 4.
+ UINT32 Rsvd1[1]; ///< Reserved bytes
+} SC_USB20_PORT_CONFIG;
+
+typedef struct {
+ UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>.
+ UINT32 RsvdBits0 : 31; ///< Reserved bits
+ UINT8 OverCurrentPin;
+ UINT8 Rsvd0[3]; ///< Reserved bytes, align to multiple 4
+ UINT32 Rsvd1[2]; ///< Reserved bytes
+} SC_USB30_PORT_CONFIG;
+
+typedef struct {
+ UINT32 Enable : 2;
+ UINT32 RsvdBits : 30; ///< Reserved bits
+} SC_XDCI_CONFIG;
+
+typedef struct {
+ UINT32 Enable : 1;
+ UINT32 RsvdBits : 31;
+} SC_XHCI_HSIC_PORT;
+
+/**
+ These members describe some settings which are related to the SSIC ports.
+
+**/
+typedef struct {
+ SC_XHCI_HSIC_PORT HsicPort[XHCI_MAX_HSIC_PORTS];
+} SC_HSIC_CONFIG;
+
+typedef enum {
+ XhciSsicRateA = 1,
+ XhciSsicRateB
+} SC_XHCI_SSIC_PORT_RATE;
+
+typedef struct {
+ UINT32 Enable : 1;
+ UINT32 Rate : 2;
+ UINT32 RsvdBits : 29;
+} SC_XHCI_SSIC_PORT;
+
+typedef struct {
+ SC_XHCI_SSIC_PORT SsicPort[XHCI_MAX_SSIC_PORTS];
+ UINT32 DlanePwrGating : 1;
+ UINT32 RsvdBits : 31;
+} SC_SSIC_CONFIG;
+
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 DisableComplianceMode : 1;
+ UINT32 UsbPerPortCtl : 1; ///< @deprecated since revision 2
+ UINT32 RsvdBits : 30;
+ SC_USB30_CONTROLLER_SETTINGS Usb30Settings;
+ SC_USB20_PORT_CONFIG PortUsb20[SC_MAX_USB2_PORTS];
+ SC_USB30_PORT_CONFIG PortUsb30[SC_MAX_USB3_PORTS];
+ SC_XDCI_CONFIG XdciConfig;
+ SC_HSIC_CONFIG HsicConfig;
+ SC_SSIC_CONFIG SsicConfig;
+} SC_USB_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _USB_CONFIG_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/VtdConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/VtdConfig.h new file mode 100644 index 0000000000..e6fb1a24ec --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/VtdConfig.h @@ -0,0 +1,40 @@ +/** @file
+ VT-d policy.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _VTD_CONFIG_H_
+#define _VTD_CONFIG_H_
+
+#define VTD_CONFIG_REVISION 1
+
+extern EFI_GUID gVtdConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This structure contains the policies which are related to VT-d.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 VtdEnable : 1; ///< 1: Enable, <b>0: Disable</b> VT-d
+ UINT8 x2ApicEnabled : 1;
+ UINT32 RsvdBits : 30; ///< Reserved bits
+ UINT64 RmrrUsbBaseAddr;
+ UINT64 RmrrUsbLimit;
+} SC_VTD_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _VTD_CONFIG_H_
+
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