diff options
Diffstat (limited to 'Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library')
12 files changed, 1999 insertions, 0 deletions
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/DxeRuntimePciLibPciExpress.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/DxeRuntimePciLibPciExpress.h new file mode 100644 index 0000000000..2d3dc46574 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/DxeRuntimePciLibPciExpress.h @@ -0,0 +1,54 @@ +/** @file
+ Header file for the Dxe Runtime PCI library.
+
+ Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _DXE_RUNTIME_PCI_LIB_PCIEXPRESS_H_
+#define _DXE_RUNTIME_PCI_LIB_PCIEXPRESS_H_
+
+
+/**
+ Constructor for Pci library. Register VirtualAddressNotifyEvent() notify function
+ It will ASSERT() if that operation fails
+
+ @param[in] None
+
+ @retval EFI_SUCCESS The function completed successfully
+
+**/
+EFI_STATUS
+EFIAPI
+PciLibConstructor (
+ VOID
+ );
+
+/**
+ Register memory space
+ If StartAddress > 0x0FFFFFFF, then ASSERT().
+ If SmPciLibAddressMapIndex) > PCI_LIB_ADDRESS_MAP_MAX_ITEM, then ASSERT().
+
+ @param[in] Address Starting address of the memory space
+ @param[in] Length Length of the memory space
+
+ @retval EFI_SUCCESS The function completed successfully
+
+**/
+EFI_STATUS
+EFIAPI
+PciLibRegisterMemory (
+ IN UINTN Address,
+ IN UINTN Length
+ );
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/DxeVtdLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/DxeVtdLib.h new file mode 100644 index 0000000000..bf88f5b220 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/DxeVtdLib.h @@ -0,0 +1,78 @@ +/** @file
+ Prototype of Intel VT-d (Virtualization Technology for Directed I/O).
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _VT_D_DXE_H_
+#define _VT_D_DXE_H_
+
+//
+// Include files
+//
+#include <PiPei.h>
+#include <DmaRemappingTable.h>
+#include <ScAccess.h>
+#include <Uefi.h>
+#include <Protocol/AcpiSupport.h>
+#include <Protocol/AcpiTable.h>
+#include <Protocol/FirmwareVolume2.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/PeiDxeSmmMmPciLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Guid/EventGroup.h>
+#include <CpuRegs.h>
+#include <SaRegs.h>
+#include <ScRegs/RegsPcu.h>
+#include <PlatformBaseAddresses.h>
+
+#define VTD_ECAP_REG 0x10
+#define IR BIT3
+#define VTD_RMRR_USB_LENGTH 0x20000
+
+#define EFI_MSR_XAPIC_BASE 0x1B
+#define R_SA_MCHBAR 0x48
+//
+// VT-d Engine base address.
+//
+#define R_SA_MCHBAR_VTD1_OFFSET 0x6C88 ///< DMA Remapping HW UNIT1 for IGD
+#define R_SA_MCHBAR_VTD2_OFFSET 0x6C80 ///< DMA Remapping HW UNIT2 for all other - PEG, USB, SATA etc
+
+/**
+ Locate the VT-d ACPI tables data file and update it based on current configuration and capabilities.
+
+ @retval EFI_SUCCESS VT-d initialization complete
+ @retval EFI_UNSUPPORTED VT-d is disabled by policy or not supported
+
+**/
+EFI_STATUS
+VtdInit (
+ VOID
+ );
+
+/**
+ ReadyToBoot callback routine to update DMAR.
+
+**/
+VOID
+UpdateDmarOnReadyToBoot (
+ BOOLEAN VtEnable
+ );
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/HsioLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/HsioLib.h new file mode 100644 index 0000000000..d68143efef --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/HsioLib.h @@ -0,0 +1,87 @@ +/** @file
+ Header file for ScHsioLib.
+
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SC_HSIO_LIB_H_
+#define _SC_HSIO_LIB_H_
+
+/**
+ The function returns the Port Id and lane owner for the specified lane.
+
+ @param[in] LaneNum Lane number that needs to be checked
+ @param[out] PortId Common Lane End Point ID
+ @param[out] LaneOwner Lane Owner
+
+ @retval EFI_SUCCESS Read success
+ @retval EFI_INVALID_PARAMETER Invalid lane number
+
+**/
+EFI_STATUS
+EFIAPI
+ScGetLaneInfo (
+ IN UINT32 LaneNum,
+ OUT UINT8 *PortId,
+ OUT UINT8 *LaneOwner
+ );
+
+/**
+ Determine the lane number of a specified port.
+
+ @param[in] PcieLaneIndex PCIE Root Port Lane Index
+ @param[out] LaneNum Lane Number
+
+ @retval EFI_SUCCESS Lane number valid.
+ @retval EFI_UNSUPPORTED Incorrect input device port
+
+**/
+EFI_STATUS
+ScGetPcieLaneNum (
+ IN UINT32 PcieLaneIndex,
+ OUT UINT8 *LaneNum
+ );
+
+/**
+ Determine the lane number of a specified port.
+
+ @param[in] SataLaneIndex Sata Lane Index
+ @param[out] LaneNum Lane Number
+
+ @retval EFI_SUCCESS Lane number valid.
+ @retval EFI_UNSUPPORTED Incorrect input device port
+
+**/
+EFI_STATUS
+ScGetSataLaneNum (
+ IN UINT32 SataLaneIndex,
+ OUT UINT8 *LaneNum
+ );
+
+/**
+ Determine the lane number of a specified port.
+
+ @param[in] Usb3LaneIndex USB3 Lane Index
+ @param[out] LaneNum Lane Number
+
+ @retval EFI_SUCCESS Lane number valid.
+ @retval EFI_UNSUPPORTED Incorrect input device port
+
+**/
+EFI_STATUS
+ScGetUsb3LaneNum (
+ IN UINT32 Usb3LaneIndex,
+ OUT UINT8 *LaneNum
+ );
+
+#endif // _SC_HSIO_LIB_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/I2CLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/I2CLib.h new file mode 100644 index 0000000000..b593620106 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/I2CLib.h @@ -0,0 +1,227 @@ +/** @file
+ Register Definitions for I2C Library.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _I2C_LIB_H_
+#define _I2C_LIB_H_
+
+#include <Uefi.h>
+#include <Library/IoLib.h>
+
+//
+// FIFO write workaround value.
+//
+#define FIFO_WRITE_DELAY 2
+
+//
+// MMIO Register Definitions
+//
+#define R_IC_CON (0x00) ///< I2C Control
+#define B_IC_RESTART_EN BIT5
+#define B_IC_SLAVE_DISABLE BIT6
+#define V_SPEED_STANDARD 0x02
+#define V_SPEED_FAST 0x04
+#define V_SPEED_HIGH 0x06
+#define B_MASTER_MODE BIT0
+
+#define R_IC_TAR (0x04) ///< I2C Target Address
+#define IC_TAR_10BITADDR_MASTER BIT12
+
+#define R_IC_SAR (0x08) ///< I2C Slave Address
+#define R_IC_HS_MADDR (0x0C) ///< I2C HS MasterMode Code Address
+#define R_IC_DATA_CMD (0x10) ///< I2C Rx/Tx Data Buffer and Command
+
+#define B_READ_CMD BIT8 ///< 1 = read, 0 = write
+#define B_CMD_STOP BIT9 ///< 1 = STOP
+#define B_CMD_RESTART BIT10 ///< 1 = IC_RESTART_EN
+
+#define V_WRITE_CMD_MASK (0xFF)
+
+#define R_IC_SS_SCL_HCNT (0x14) ///< Standard Speed I2C Clock SCL High Count
+#define R_IC_SS_SCL_LCNT (0x18) ///< Standard Speed I2C Clock SCL Low Count
+#define R_IC_FS_SCL_HCNT (0x1C) ///< Full Speed I2C Clock SCL High Count
+#define R_IC_FS_SCL_LCNT (0x20) ///< Full Speed I2C Clock SCL Low Count
+#define R_IC_HS_SCL_HCNT (0x24) ///< High Speed I2C Clock SCL High Count
+#define R_IC_HS_SCL_LCNT (0x28) ///< High Speed I2C Clock SCL Low Count
+#define R_IC_INTR_STAT (0x2C) ///< I2C Inetrrupt Status
+#define R_IC_INTR_MASK (0x30) ///< I2C Interrupt Mask
+#define I2C_INTR_GEN_CALL BIT11 ///< General call received
+#define I2C_INTR_START_DET BIT10
+#define I2C_INTR_STOP_DET BIT9
+#define I2C_INTR_ACTIVITY BIT8
+#define I2C_INTR_TX_ABRT BIT6 ///< Set on NACK
+#define I2C_INTR_TX_EMPTY BIT4
+#define I2C_INTR_TX_OVER BIT3
+#define I2C_INTR_RX_FULL BIT2 ///< Data bytes in RX FIFO over threshold
+#define I2C_INTR_RX_OVER BIT1
+#define I2C_INTR_RX_UNDER BIT0
+#define R_IC_RAW_INTR_STAT (0x34) ///< I2C Raw Interrupt Status
+#define R_IC_RX_TL (0x38) ///< I2C Receive FIFO Threshold
+#define R_IC_TX_TL (0x3C) ///< I2C Transmit FIFO Threshold
+#define R_IC_CLR_INTR (0x40) ///< Clear Combined and Individual Interrupts
+#define R_IC_CLR_RX_UNDER (0x44) ///< Clear RX_UNDER Interrupt
+#define R_IC_CLR_RX_OVER (0x48) ///< Clear RX_OVERinterrupt
+#define R_IC_CLR_TX_OVER (0x4C) ///< Clear TX_OVER interrupt
+#define R_IC_CLR_RD_REQ (0x50) ///< Clear RD_REQ interrupt
+#define R_IC_CLR_TX_ABRT (0x54) ///< Clear TX_ABRT interrupt
+#define R_IC_CLR_RX_DONE (0x58) ///< Clear RX_DONE interrupt
+#define R_IC_CLR_ACTIVITY (0x5C) ///< Clear ACTIVITY interrupt
+#define R_IC_CLR_STOP_DET (0x60) ///< Clear STOP_DET interrupt
+#define R_IC_CLR_START_DET (0x64) ///< Clear START_DET interrupt
+#define R_IC_CLR_GEN_CALL (0x68) ///< Clear GEN_CALL interrupt
+#define R_IC_ENABLE (0x6C) ///< I2C Enable
+#define R_IC_STATUS (0x70) ///< I2C Status
+
+#define R_IC_SDA_HOLD (0x7C) ///< I2C IC_DEFAULT_SDA_HOLD//16bits
+
+#define STAT_MST_ACTIVITY BIT5 ///< Master FSM Activity Status.
+#define STAT_RFF BIT4 ///< RX FIFO is completely full
+#define STAT_RFNE BIT3 ///< RX FIFO is not empty
+#define STAT_TFE BIT2 ///< TX FIFO is completely empty
+#define STAT_TFNF BIT1 ///< TX FIFO is not full
+
+#define R_IC_TXFLR (0x74) ///< Transmit FIFO Level Register
+#define R_IC_RXFLR (0x78) ///< Receive FIFO Level Register
+#define R_IC_TX_ABRT_SOURCE (0x80) ///< I2C Transmit Abort Status Register
+#define R_IC_SLV_DATA_NACK_ONLY (0x84) ///< Generate SLV_DATA_NACK Register
+#define R_IC_DMA_CR (0x88) ///< DMA Control Register
+#define R_IC_DMA_TDLR (0x8C) ///< DMA Transmit Data Level
+#define R_IC_DMA_RDLR (0x90) ///< DMA Receive Data Level
+#define R_IC_SDA_SETUP (0x94) ///< I2C SDA Setup Register
+#define R_IC_ACK_GENERAL_CALL (0x98) ///< I2C ACK General Call Register
+#define R_IC_ENABLE_STATUS (0x9C) ///< I2C Enable Status Register
+#define R_IC_COMP_PARAM (0xF4) ///< Component Parameter Register
+#define R_IC_COMP_VERSION (0xF8) ///< Component Version ID
+#define R_IC_COMP_TYPE (0xFC) ///< Component Type
+
+#define R_IC_CLK_GATE (0xC0) ///< Clock Gate
+
+#define IC_TAR_10BITADDR_MASTER BIT12
+#define FIFO_SIZE 32
+
+
+/**
+ Program LPSS I2C PCI controller's BAR0 and enable memory decode.
+
+ @param[in] BusNo I2C Bus number to which the I2C device has been connected
+
+ @retval EFI_SUCCESS I2C controller's BAR0 is programmed and memory decode enabled.
+ @retval EFI_NOT_READY I2C controller's is not exist or its function has been disabled.
+
+**/
+EFI_STATUS
+ProgramPciLpssI2C (
+ IN UINT8 BusNo
+ );
+
+/**
+ Read bytes from I2C Device
+ This is actual I2C hardware operation function.
+
+ @param[in] BusNo I2C Bus number to which the I2C device has been connected
+ @param[in] SlaveAddress Slave address of the I2C device
+ @param[in] ReadBytes Number of bytes to be read
+ @param[out] ReadBuffer Address to which the value read has to be stored
+ @param[in] Start It controls whether a RESTART is issued before the byte is sent or received.
+ @param[in] End It controls whether a STOP is issued after the byte is sent or received.
+
+ @retval EFI_SUCCESS The byte value read successfully
+ @retval EFI_DEVICE_ERROR Operation failed
+ @retval EFI_TIMEOUT Hardware retry timeout
+ @retval Others Failed to read a byte via I2C
+
+**/
+EFI_STATUS
+ByteReadI2C_Basic (
+ IN UINT8 BusNo,
+ IN UINT8 SlaveAddress,
+ IN UINTN ReadBytes,
+ OUT UINT8 *ReadBuffer,
+ IN UINT8 Start,
+ IN UINT8 End
+ );
+
+/**
+ Write bytes to I2C Device
+ This is actual I2C hardware operation function.
+
+ @param[in] BusNo I2C Bus number to which the I2C device has been connected
+ @param[in] SlaveAddress Slave address of the I2C device
+ @param[in] WriteBytes Number of bytes to be written
+ @param[in] WriteBuffer Address to which the byte value has to be written
+ @param[in] Start It controls whether a RESTART is issued before the byte is sent or received.
+ @param[in] End It controls whether a STOP is issued after the byte is sent or received.
+
+ @retval EFI_SUCCESS The byte value written successfully
+ @retval EFI_DEVICE_ERROR Operation failed
+ @retval EFI_TIMEOUT Hardware retry timeout
+ @retval Others Failed to write a byte via I2C
+
+**/
+EFI_STATUS
+ByteWriteI2C_Basic (
+ IN UINT8 BusNo,
+ IN UINT8 SlaveAddress,
+ IN UINTN WriteBytes,
+ IN UINT8 *WriteBuffer,
+ IN UINT8 Start,
+ IN UINT8 End
+ );
+
+/**
+ Read bytes from I2C Device
+
+ @param[in] BusNo I2C Bus number to which the I2C device has been connected
+ @param[in] SlaveAddress Slave address of the I2C device
+ @param[in] Offset Register offset from which the data has to be read
+ @param[in] ReadBytes Number of bytes to be read
+ @param[out] ReadBuffer Address to which the value read has to be stored
+
+ @retval EFI_SUCCESS Read bytes from I2C device successfully
+ @retval Others Return status depends on ByteReadI2C_Basic
+
+**/
+EFI_STATUS
+ByteReadI2C (
+ IN UINT8 BusNo,
+ IN UINT8 SlaveAddress,
+ IN UINT8 Offset,
+ IN UINTN ReadBytes,
+ OUT UINT8 *ReadBuffer
+ );
+
+/**
+ Write bytes to I2C Device
+
+ @param[in] BusNo I2C Bus number to which the I2C device has been connected
+ @param[in] SlaveAddress Slave address of the I2C device
+ @param[in] Offset Register offset from which the data has to be read
+ @param[in] WriteBytes Number of bytes to be written
+ @param[in] WriteBuffer Address to which the byte value has to be written
+
+ @retval EFI_SUCCESS Write bytes to I2C device successfully
+ @retval Others Return status depends on ByteWriteI2C_Basic
+
+**/
+EFI_STATUS
+ByteWriteI2C (
+ IN UINT8 BusNo,
+ IN UINT8 SlaveAddress,
+ IN UINT8 Offset,
+ IN UINTN WriteBytes,
+ IN UINT8 *WriteBuffer
+ );
+
+#endif // _I2C_LIB_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/PeiMmcMainLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/PeiMmcMainLib.h new file mode 100644 index 0000000000..7a4172daa5 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/PeiMmcMainLib.h @@ -0,0 +1,36 @@ +/** @file
+ Mmc Main PEI Library header.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PEI_MMC_MAIN_LIB_H_
+#define _PEI_MMC_MAIN_LIB_H_
+
+/**
+ Entry point for EFI drivers.
+
+ @param[in] PeiServices EFI_PEI_SERVICES
+
+ @retval EFI_SUCCESS Success
+ @retval EFI_DEVICE_ERROR Fail
+
+**/
+EFI_STATUS
+EFIAPI
+MmcMainEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/PeiScPolicyLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/PeiScPolicyLib.h new file mode 100644 index 0000000000..84ed7b1dfd --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/PeiScPolicyLib.h @@ -0,0 +1,125 @@ +/** @file
+ Prototype of the PeiScPolicy library.
+
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PEI_SC_POLICY_LIBRARY_H_
+#define _PEI_SC_POLICY_LIBRARY_H_
+
+#include <Ppi/ScPolicy.h>
+#include <Ppi/ScPolicyPreMem.h>
+
+/**
+ Print whole SC_PREMEM_POLICY_PPI and serial out.
+
+ @param[in] ScPreMemPolicyPpi The RC Policy PPI instance
+
+**/
+VOID
+EFIAPI
+ScPreMemPrintPolicyPpi (
+ IN SC_PREMEM_POLICY_PPI *ScPreMemPolicyPpi
+ );
+
+/**
+ Print whole SC_POLICY_PPI and serial out.
+
+ @param[in] ScPolicy The SC Policy Ppi instance
+
+**/
+VOID
+EFIAPI
+ScPrintPolicyPpi (
+ IN SC_POLICY_PPI *ScPolicy
+ );
+
+/**
+ CreatePreMemConfigBlocks generates the config blocks of SC Policy.
+ It allocates and zero out buffer, and fills in the Intel default settings.
+
+ @param[out] ScPreMemPolicyPpi The pointer to get SC PREMEM Policy PPI instance
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+ScCreatePreMemConfigBlocks (
+ OUT SC_PREMEM_POLICY_PPI **ScPreMemPolicyPpi
+ );
+
+/**
+ ScInstallPreMemPolicyPpi installs ScPolicyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @param[in] ScPreMemPolicyPpi The pointer to SC PREMEM Policy PPI instance
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+ScInstallPreMemPolicyPpi (
+ IN SC_PREMEM_POLICY_PPI *ScPreMemPolicyPpi
+ );
+
+/**
+ Get SC config block table total size.
+
+ @retval Size of SC config block table
+
+**/
+UINT32
+EFIAPI
+ScGetConfigBlockTotalSize (
+ VOID
+ );
+
+/**
+ ScCreateConfigBlocks generates the config blocks of SC Policy.
+ It allocates and zero out buffer, and fills in the Intel default settings.
+
+ @param[out] ScPolicyPpi The pointer to get SC Policy PPI instance
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+ScCreateConfigBlocks (
+ OUT SC_POLICY_PPI **ScPolicyPpi
+ );
+
+/**
+ ScInstallPolicyPpi installs ScPolicyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @param[in] ScPolicyPpi The pointer to SC Policy PPI instance
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+ScInstallPolicyPpi (
+ IN SC_POLICY_PPI *ScPolicyPpi
+ );
+
+#endif // _PEI_SC_POLICY_LIBRARY_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/PeiVtdLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/PeiVtdLib.h new file mode 100644 index 0000000000..614a6c0d1a --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/PeiVtdLib.h @@ -0,0 +1,47 @@ +/** @file
+ Prototype of Intel VT-d (Virtualization Technology for Directed I/O).
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _VT_D_PEI_H_
+#define _VT_D_PEI_H_
+
+#include <PlatformBaseAddresses.h>
+
+#define VTD_ECAP_REG 0x10
+#define IR BIT3
+#define R_SA_MCHBAR 0x48
+
+//
+// VT-d Engine base address.
+//
+#define R_SA_MCHBAR_VTD1_OFFSET 0x6C88 ///< DMA Remapping HW UNIT1 for IGD
+#define R_SA_MCHBAR_VTD2_OFFSET 0x6C80 ///< DMA Remapping HW UNIT2 for all other - PEG, USB, SATA etc
+
+#define SA_VTD_ENGINE_NUMBER 2
+
+/**
+ Configure VT-d Base and capabilities.
+
+ @param[in] ScPolicyPpi The SC Policy PPI instance
+
+ @retval EFI_SUCCESS VT-d initialization complete
+ @retval EFI_UNSUPPORTED VT-d is disabled by policy or not supported
+
+**/
+EFI_STATUS
+VtdInit (
+ IN SC_POLICY_PPI *ScPolicyPpi
+ );
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScInfoLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScInfoLib.h new file mode 100644 index 0000000000..2a2d4ac8dc --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScInfoLib.h @@ -0,0 +1,52 @@ +/** @file
+ Header file for PchInfoLib.
+
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_INFO_LIB_H_
+#define _PCH_INFO_LIB_H_
+
+#include <ScAccess.h>
+
+typedef enum {
+ PchH = 1,
+ PchLp,
+ PchUnknownSeries
+} PCH_SERIES;
+
+/**
+ Return Pch Series.
+
+ @retval PCH_SERIES Pch Series
+
+**/
+PCH_SERIES
+EFIAPI
+GetPchSeries (
+ VOID
+ );
+
+/**
+ Get Pch Maximum Pcie Root Port Number.
+
+ @retval PcieMaxRootPort Pch Maximum Pcie Root Port Number
+
+**/
+UINT8
+EFIAPI
+GetPchMaxPciePortNum (
+ VOID
+ );
+
+#endif // _PCH_INFO_LIB_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScPcrLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScPcrLib.h new file mode 100644 index 0000000000..a192e27276 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScPcrLib.h @@ -0,0 +1,208 @@ +/** @file
+ Header file for PchPcrLib.
+
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_PCR_LIB_H_
+#define _PCH_PCR_LIB_H_
+
+#include <ScAccess.h>
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+ @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+
+**/
+EFI_STATUS
+PchPcrRead32 (
+ IN SC_SBI_PID Pid,
+ IN UINT16 Offset,
+ OUT UINT32 *OutData
+ );
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+ @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+
+**/
+EFI_STATUS
+PchPcrRead16 (
+ IN SC_SBI_PID Pid,
+ IN UINT16 Offset,
+ OUT UINT16 *OutData
+ );
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+ @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+
+**/
+EFI_STATUS
+PchPcrRead8 (
+ IN SC_SBI_PID Pid,
+ IN UINT16 Offset,
+ OUT UINT8 *OutData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] InData Input Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+
+**/
+EFI_STATUS
+PchPcrWrite32 (
+ IN SC_SBI_PID Pid,
+ IN UINT16 Offset,
+ IN UINT32 InData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] InData Input Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+
+**/
+EFI_STATUS
+PchPcrWrite16 (
+ IN SC_SBI_PID Pid,
+ IN UINT16 Offset,
+ IN UINT16 InData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] InData Input Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+
+**/
+EFI_STATUS
+PchPcrWrite8 (
+ IN SC_SBI_PID Pid,
+ IN UINT16 Offset,
+ IN UINT8 InData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+
+**/
+EFI_STATUS
+PchPcrAndThenOr32 (
+ IN SC_SBI_PID Pid,
+ IN UINT16 Offset,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+
+**/
+EFI_STATUS
+PchPcrAndThenOr16 (
+ IN SC_SBI_PID Pid,
+ IN UINT16 Offset,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+
+**/
+EFI_STATUS
+PchPcrAndThenOr8 (
+ IN SC_SBI_PID Pid,
+ IN UINT16 Offset,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+#endif // _PCH_PCR_LIB_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScPlatformLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScPlatformLib.h new file mode 100644 index 0000000000..896cb05ca5 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScPlatformLib.h @@ -0,0 +1,805 @@ +/** @file
+ Header file for ScPlatform Lib.
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SC_PLATFORM_LIB_H_
+#define _SC_PLATFORM_LIB_H_
+
+#include <ScAccess.h>
+#include <Uefi/UefiBaseType.h>
+
+typedef struct {
+ UINT8 DevNum;
+ UINT8 Pid;
+ UINT8 RpNumBase;
+} PCIE_CONTROLLER_INFO;
+
+/**
+ Get Sc Maximum Pcie Root Port Number.
+
+ @retval UINT8 Sc Maximum Pcie Root Port Number
+
+**/
+UINT8
+EFIAPI
+GetScMaxPciePortNum (
+ VOID
+ );
+
+/**
+ Delay for at least the request number of microseconds.
+ This function would be called by runtime driver, please do not use any MMIO marco here.
+
+ @param[in] Microseconds Number of microseconds to delay.
+
+**/
+VOID
+EFIAPI
+ScPmTimerStall (
+ IN UINTN Microseconds
+ );
+
+/**
+ Check whether SPI is in descriptor mode.
+
+ @param[in] SpiBase The SC SPI Base Address
+
+ @retval TRUE SPI is in descriptor mode
+ @retval FALSE SPI is not in descriptor mode
+
+**/
+BOOLEAN
+EFIAPI
+ScIsSpiDescriptorMode (
+ IN UINTN SpiBase
+ );
+
+/**
+ Determine if SC is supported.
+
+ @retval TRUE SC is supported
+ @retval FALSE SC is not supported
+
+**/
+BOOLEAN
+IsScSupported (
+ VOID
+ );
+
+/**
+ This function can be called to poll for certain value within a time given.
+
+ @param[in] MmioAddress The Mmio Address.
+ @param[in] BitMask Bits to be masked.
+ @param[in] BitValue Value to be polled.
+ @param[in] DelayTime Delay time in terms of 100 micro seconds.
+
+ @retval EFI_SUCCESS Successfully polled the value.
+ @retval EFI_TIMEOUT Timeout while polling the value.
+
+**/
+EFI_STATUS
+EFIAPI
+ScMmioPoll32 (
+ IN UINTN MmioAddress,
+ IN UINT32 BitMask,
+ IN UINT32 BitValue,
+ IN UINT16 DelayTime
+ );
+
+/**
+ Get SC Pcie Root Port Device and Function Number by Root Port physical Number.
+
+ @param[in] RpNumber Root port physical number. (0-based)
+ @param[out] RpDev Return corresponding root port device number.
+ @param[out] RpFun Return corresponding root port function number.
+
+ @retval EFI_SUCCESS Root port device and function is retrieved
+ @retval EFI_INVALID_PARAMETER RpNumber is invalid
+
+**/
+EFI_STATUS
+EFIAPI
+GetScPcieRpDevFun (
+ IN UINTN RpNumber,
+ OUT UINTN *RpDev,
+ OUT UINTN *RpFun
+ );
+
+/**
+ Get Root Port physical Number by SC Pcie Root Port Device and Function Number.
+
+ @param[in] RpDev Root port device number.
+ @param[in] RpFun Root port function number.
+ @param[out] RpNumber Return corresponding Root port physical number.
+
+ @retval EFI_SUCCESS Physical root port is retrieved
+ @retval EFI_INVALID_PARAMETER RpDev and/or RpFun are invalid
+ @retval EFI_UNSUPPORTED Root port device and function is not assigned to any physical root port
+
+**/
+EFI_STATUS
+EFIAPI
+GetScPcieRpNumber (
+ IN UINTN RpDev,
+ IN UINTN RpFun,
+ OUT UINTN *RpNumber
+ );
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+ @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+
+**/
+EFI_STATUS
+PchPcrRead32 (
+ IN SC_SBI_PID Pid,
+ IN UINT16 Offset,
+ OUT UINT32 *OutData
+ );
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+ @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+
+**/
+EFI_STATUS
+PchPcrRead16 (
+ IN SC_SBI_PID Pid,
+ IN UINT16 Offset,
+ OUT UINT16 *OutData
+ );
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+ @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+
+**/
+EFI_STATUS
+PchPcrRead8 (
+ IN SC_SBI_PID Pid,
+ IN UINT16 Offset,
+ OUT UINT8 *OutData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] InData Input Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+
+**/
+EFI_STATUS
+PchPcrWrite32 (
+ IN SC_SBI_PID Pid,
+ IN UINT16 Offset,
+ IN UINT32 InData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] InData Input Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+
+**/
+EFI_STATUS
+PchPcrWrite16 (
+ IN SC_SBI_PID Pid,
+ IN UINT16 Offset,
+ IN UINT16 InData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] InData Input Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+
+**/
+EFI_STATUS
+PchPcrWrite8 (
+ IN SC_SBI_PID Pid,
+ IN UINT16 Offset,
+ IN UINT8 InData
+ );
+
+/**
+ Reads an 4-byte Pcr register, performs a bitwise AND followed by a bitwise
+ inclusive OR, and writes the result back to the 4-byte Pcr register.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+
+**/
+EFI_STATUS
+PchPcrAndThenOr32 (
+ IN SC_SBI_PID Pid,
+ IN UINT16 Offset,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads an 2-byte Pcr register, performs a bitwise AND followed by a bitwise
+ inclusive OR, and writes the result back to the 2-byte Pcr register.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+
+**/
+EFI_STATUS
+PchPcrAndThenOr16 (
+ IN SC_SBI_PID Pid,
+ IN UINT16 Offset,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads an 1-byte Pcr register, performs a bitwise AND followed by a bitwise
+ inclusive OR, and writes the result back to the 1-byte Pcr register.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+
+**/
+EFI_STATUS
+PchPcrAndThenOr8 (
+ IN SC_SBI_PID Pid,
+ IN UINT16 Offset,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ Hide P2SB device.
+
+ @param[in] P2sbBase Pci base address of P2SB controller.
+
+ @retval EFI_SUCCESS Always return success.
+
+**/
+EFI_STATUS
+PchHideP2sb (
+ IN UINTN P2sbBase
+ );
+
+/**
+ Reveal P2SB device.
+ Also return the original P2SB status which is for Hidding P2SB or not after.
+ If OrgStatus is not NULL, then TRUE means P2SB is unhidden,
+ and FALSE means P2SB is hidden originally.
+
+ @param[in] P2sbBase Pci base address of P2SB controller.
+ @param[out] OrgStatus Original P2SB hidding/unhidden status
+
+ @retval EFI_SUCCESS Always return success.
+
+**/
+EFI_STATUS
+PchRevealP2sb (
+ IN UINTN P2sbBase,
+ OUT BOOLEAN *OrgStatus
+ );
+
+//
+// implemented in PchSbiAccess.c
+//
+
+/**
+ PCH SBI Register structure
+
+**/
+typedef struct {
+ UINT32 SbiAddr;
+ UINT32 SbiExtAddr;
+ UINT32 SbiData;
+ UINT16 SbiStat;
+ UINT16 SbiRid;
+} PCH_SBI_REGISTER_STRUCT;
+
+/**
+ PCH SBI opcode definitions
+
+**/
+typedef enum {
+ MemoryRead = 0x0,
+ MemoryWrite = 0x1,
+ PciConfigRead = 0x4,
+ PciConfigWrite = 0x5,
+ PrivateControlRead = 0x6,
+ PrivateControlWrite = 0x7,
+ GpioLockUnlock = 0x13
+} PCH_SBI_OPCODE;
+
+/**
+ PCH SBI response status definitions
+
+**/
+typedef enum {
+ SBI_SUCCESSFUL = 0,
+ SBI_UNSUCCESSFUL = 1,
+ SBI_POWERDOWN = 2,
+ SBI_MIXED = 3,
+ SBI_INVALID_RESPONSE
+} PCH_SBI_RESPONSE;
+
+/**
+ Execute PCH SBI message
+ Take care of that there is no lock protection when using SBI programming in both POST time and SMI.
+ It will clash with POST time SBI programming when SMI happen.
+ Programmer MUST do the save and restore opration while using the PchSbiExecution inside SMI
+ to prevent from racing condition.
+ This function will reveal P2SB and hide P2SB if it's originally hidden. If more than one SBI access
+ needed, it's better to unhide the P2SB before calling and hide it back after done.
+
+ When the return value is "EFI_SUCCESS", the "Response" do not need to be checked as it would have been
+ SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would provide additional information
+ when needed.
+
+ @param[in] Pid Port ID of the SBI message
+ @param[in] Offset Offset of the SBI message
+ @param[in] Opcode Opcode
+ @param[in] Posted Posted message
+ @param[in, out] Data32 Read/Write data
+ @param[out] Response Response
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_DEVICE_ERROR Transaction fail
+ @retval EFI_INVALID_PARAMETER Invalid parameter
+
+**/
+EFI_STATUS
+EFIAPI
+PchSbiExecution (
+ IN SC_SBI_PID Pid,
+ IN UINT64 Offset,
+ IN PCH_SBI_OPCODE Opcode,
+ IN BOOLEAN Posted,
+ IN OUT UINT32 *Data32,
+ OUT UINT8 *Response
+ );
+
+/**
+ Full function for executing PCH SBI message
+ Take care of that there is no lock protection when using SBI programming in both POST time and SMI.
+ It will clash with POST time SBI programming when SMI happen.
+ Programmer MUST do the save and restore opration while using the PchSbiExecution inside SMI
+ to prevent from racing condition.
+ This function will reveal P2SB and hide P2SB if it's originally hidden. If more than one SBI access
+ needed, it's better to unhide the P2SB before calling and hide it back after done.
+
+ When the return value is "EFI_SUCCESS", the "Response" do not need to be checked as it would have been
+ SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would provide additional information
+ when needed.
+
+ @param[in] Pid Port ID of the SBI message
+ @param[in] Offset Offset of the SBI message
+ @param[in] Opcode Opcode
+ @param[in] Posted Posted message
+ @param[in] Fbe First byte enable
+ @param[in] Bar Bar
+ @param[in] Fid Function ID
+ @param[in, out] Data32 Read/Write data
+ @param[out] Response Response
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_DEVICE_ERROR Transaction fail
+ @retval EFI_INVALID_PARAMETER Invalid parameter
+
+**/
+EFI_STATUS
+EFIAPI
+PchSbiExecutionEx (
+ IN SC_SBI_PID Pid,
+ IN UINT64 Offset,
+ IN PCH_SBI_OPCODE Opcode,
+ IN BOOLEAN Posted,
+ IN UINT16 Fbe,
+ IN UINT16 Bar,
+ IN UINT16 Fid,
+ IN OUT UINT32 *Data32,
+ OUT UINT8 *Response
+ );
+
+/**
+ This function saves all PCH SBI registers.
+ The save and restore operations must be done while using the PchSbiExecution inside SMM.
+ It prevents the racing condition of PchSbiExecution re-entry between POST and SMI.
+ Before using this function, make sure the P2SB is not hidden.
+
+ @param[in, out] PchSbiRegister Structure for saving the registers
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_DEVICE_ERROR Device is hidden.
+
+**/
+EFI_STATUS
+EFIAPI
+PchSbiRegisterSave (
+ IN OUT PCH_SBI_REGISTER_STRUCT *PchSbiRegister
+ );
+
+/**
+ This function restores all PCH SBI registers
+ The save and restore operations must be done while using the PchSbiExecution inside SMM.
+ It prevents the racing condition of PchSbiExecution re-entry between POST and SMI.
+ Before using this function, make sure the P2SB is not hidden.
+
+ @param[in] PchSbiRegister Structure for restoring the registers
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_DEVICE_ERROR Device is hidden.
+
+**/
+EFI_STATUS
+EFIAPI
+PchSbiRegisterRestore (
+ IN PCH_SBI_REGISTER_STRUCT *PchSbiRegister
+ );
+
+//
+// implemented in PchCycleDecoding.c
+//
+//
+// structure of LPC general IO range register
+// It contains base address, address mask, and enable status.
+//
+typedef struct {
+ UINT32 BaseAddr :16;
+ UINT32 Length :15;
+ UINT32 Enable : 1;
+} PCH_LPC_GEN_IO_RANGE;
+
+#define PCH_LPC_GEN_IO_RANGE_MAX 4
+
+//
+// structure of LPC general IO range register list
+// It lists all LPC general IO ran registers supported by PCH.
+//
+typedef struct {
+ PCH_LPC_GEN_IO_RANGE Range[PCH_LPC_GEN_IO_RANGE_MAX];
+} PCH_LPC_GEN_IO_RANGE_LIST;
+
+/**
+ Set PCH LPC generic IO range.
+ For generic IO range, the base address must align to 4 and less than 0xFFFF, and the length must be power of 2
+ and less than or equal to 256. Moreover, the address must be length aligned.
+ This function basically checks the address and length, which should not overlap with all other generic ranges.
+ If no more generic range register available, it returns out of resource error.
+ This cycle decoding is allowed to set when DMIC.SRL is 0.
+ Steps of programming generic IO range:
+ 1. Program LPC/eSPI PCI Offset 84h ~ 93h of Mask, Address, and Enable.
+ 2. Program LPC/eSPI Generic IO Range #, PCR[DMI] + 2730h ~ 273Fh to the same value programmed in LPC/eSPI PCI Offset 84h~93h.
+
+ @param[in] Address Address for generic IO range base address.
+ @param[in] Length Length of generic IO range.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid base address or length passed.
+ @retval EFI_OUT_OF_RESOURCES No more generic range available.
+
+**/
+EFI_STATUS
+EFIAPI
+PchLpcGenIoRangeSet (
+ IN UINT16 Address,
+ IN UINTN Length
+ );
+
+/**
+ Get PCH LPC generic IO range list.
+ This function returns a list of base address, length, and enable for all LPC generic IO range regsiters.
+
+ @param[in] LpcGenIoRangeList Return all LPC generic IO range register status.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid base address passed.
+
+**/
+EFI_STATUS
+EFIAPI
+PchLpcGenIoRangeGet (
+ IN PCH_LPC_GEN_IO_RANGE_LIST *LpcGenIoRangeList
+ );
+
+/**
+ Set PCH LPC memory range decoding.
+ This cycle decoding is allowed to set when DMIC.SRL is 0.
+ Programming steps:
+ 1. Program LPC/eSPI PCI 98h [0] to [0] to disable memory decoding first before changing base address.
+ 2. Program LPC/eSPI PCI 98h [31:16, 0] to [Address, 1].
+ 3. Program LPC/eSPI Memory Range, PCR[DMI] + 2740h to the same value programmed in LPC/eSPI PCI Offset 98h.
+
+ @param[in] Address Address for memory base address.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid base address or length passed.
+ @retval EFI_OUT_OF_RESOURCES No more generic range available.
+
+**/
+EFI_STATUS
+EFIAPI
+PchLpcMemRangeSet (
+ IN UINT32 Address
+ );
+
+/**
+ Get PCH LPC memory range decoding address.
+
+ @param[in] Address Address of LPC memory decoding base address.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid base address passed.
+
+**/
+EFI_STATUS
+EFIAPI
+PchLpcMemRangeGet (
+ IN UINT32 *Address
+ );
+
+/**
+ Set PCH BIOS range deocding.
+ This will check General Control and Status bit 10 (GCS.BBS) to identify SPI or LPC/eSPI and program BDE register accordingly.
+ Please check EDS for detail of BiosDecodeEnable bit definition.
+ bit 15: F8-FF Enable
+ bit 14: F0-F8 Enable
+ bit 13: E8-EF Enable
+ bit 12: E0-E8 Enable
+ bit 11: D8-DF Enable
+ bit 10: D0-D7 Enable
+ bit 9: C8-CF Enable
+ bit 8: C0-C7 Enable
+ bit 7: Legacy F Segment Enable
+ bit 6: Legacy E Segment Enable
+ bit 5: Reserved
+ bit 4: Reserved
+ bit 3: 70-7F Enable
+ bit 2: 60-6F Enable
+ bit 1: 50-5F Enable
+ bit 0: 40-4F Enable
+ This cycle decoding is allowed to set when DMIC.SRL is 0.
+ Programming steps:
+ 1. if GCS.BBS is 0 (SPI), program SPI PCI offset D8h to BiosDecodeEnable.
+ if GCS.BBS is 1 (LPC/eSPi), program LPC/eSPI PCI offset D8h to BiosDecodeEnable.
+ 2. program LPC/eSPI/SPI BIOS Decode Enable, PCR[DMI] + 2744h to the same value programmed in LPC/eSPI or SPI PCI Offset D8h.
+
+ @param[in] BiosDecodeEnable Bios decode enable setting.
+
+ @retval EFI_SUCCESS Successfully completed.
+
+**/
+EFI_STATUS
+EFIAPI
+PchBiosDecodeEnableSet (
+ IN UINT16 BiosDecodeEnable
+ );
+
+/**
+ Set PCH LPC IO decode ranges.
+ Program LPC I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same value programmed in LPC offset 80h.
+ Please check EDS for detail of Lpc IO decode ranges bit definition.
+ Bit 12: FDD range
+ Bit 9:8: LPT range
+ Bit 6:4: ComB range
+ Bit 2:0: ComA range
+
+ @param[in] LpcIoDecodeRanges Lpc IO decode ranges bit settings.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+
+**/
+EFI_STATUS
+EFIAPI
+PchLpcIoDecodeRangesSet (
+ IN UINT16 LpcIoDecodeRanges
+ );
+
+/**
+ Set PCH LPC IO enable decoding.
+ Setup LPC I/O Enables, PCR[DMI] + 2774h[15:0] to the same value program in LPC offset 82h.
+ Note: Bit[15:10] of the source decode register is Read-Only. The IO range indicated by the Enables field
+ in LPC 82h[13:10] is always forwarded by DMI to subtractive agent for handling.
+ Please check EDS for detail of Lpc IO decode ranges bit definition.
+
+ @param[in] LpcIoEnableDecoding Lpc IO enable decoding bit settings.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+
+**/
+EFI_STATUS
+EFIAPI
+PchLpcIoEnableDecodingSet (
+ IN UINT16 LpcIoEnableDecoding
+ );
+
+/**
+ Enable VTd support in PSF.
+
+ @retval EFI_SUCCESS Successfully completed.
+
+**/
+EFI_STATUS
+PchPsfEnableVtd (
+ VOID
+ );
+
+/**
+ Get Sc Maximum Usb2 Port Number of XHCI Controller.
+
+ @retval UINT8 Sc Maximum Usb2 Port Number of XHCI Controller
+
+**/
+UINT8
+EFIAPI
+GetScXhciMaxUsb2PortNum (
+ VOID
+ );
+
+/**
+ Get Sc Maximum Usb3 Port Number of XHCI Controller.
+
+ @retval UINT8 Sc Maximum Usb3 Port Number of XHCI Controller
+
+**/
+UINT8
+EFIAPI
+GetScXhciMaxUsb3PortNum (
+ VOID
+ );
+
+/**
+ Get SPI linear Base address of descriptor region section.
+
+ @param[in] RegNum FLREG number of region section defined in the descriptor
+
+ @retval UINT32 Base address of the FLREG
+
+**/
+UINT32
+GetSpiFlashRegionBase (
+ IN UINTN RegNum
+ );
+
+/**
+ return SPI linear Base address of descriptor region section.
+
+ @param[in] RegNum FLREG number of region section defined in the descriptor
+
+ @retval UINTN Base address of the FLREG
+
+**/
+UINT32
+GetSpiFlashRegionLimit (
+ UINTN RegNum
+ );
+
+typedef enum {
+ PcieP1,
+ PcieP2,
+ PcieP3,
+ PcieP4,
+ PcieP5,
+ PcieP6,
+ SataP0,
+ SataP1,
+ UsbP0,
+ UsbP1,
+ UsbP2,
+ UsbP3,
+ UsbP4,
+ UsbP5,
+ UsbP6,
+ UsbP7
+} SC_DEVICE_PORT;
+
+
+/**
+ Set TCO base address for legacy Smbus.
+
+ @param[in] Address Address for TCO base address.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid base address passed.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+
+**/
+EFI_STATUS
+EFIAPI
+SetTcoBase (
+ IN UINT16 Address
+ );
+
+/**
+ Get TCO base address.
+
+ @param[in] Address Address of TCO base address.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid pointer passed.
+
+**/
+EFI_STATUS
+EFIAPI
+GetTcoBase (
+ IN UINT16 *Address
+ );
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScSerialIoLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScSerialIoLib.h new file mode 100644 index 0000000000..df6f4f5ba7 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScSerialIoLib.h @@ -0,0 +1,174 @@ +/** @file
+ Header file for PCH Serial IO Lib implementation.
+
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_SERIAL_IO_LIB_H_
+#define _PCH_SERIAL_IO_LIB_H_
+
+typedef enum {
+ PchSerialIoIndexUart0,
+ PchSerialIoIndexUart1,
+ PchSerialIoIndexUart2,
+ PchSerialIoIndexUart3,
+ PchSerialIoIndexMax
+} PCH_SERIAL_IO_CONTROLLER;
+
+typedef enum {
+ PchSerialIoDisabled,
+ PchSerialIoAcpi,
+ PchSerialIoPci,
+ PchSerialIoAcpiHidden,
+ PchSerialIoLegacyUart
+} PCH_SERIAL_IO_MODE;
+
+enum PCH_LP_SERIAL_IO_VOLTAGE_SEL {
+ PchSerialIoIs33V = 0,
+ PchSerialIoIs18V
+};
+enum PCH_LP_SERIAL_IO_CS_POLARITY {
+ PchSerialIoCsActiveLow = 0,
+ PchSerialIoCsActiveHigh = 1
+};
+enum PCH_LP_SERIAL_IO_HW_FLOW_CTRL {
+ PchSerialIoHwFlowCtrlDisabled = 0,
+ PchSerialIoHwFlowControlEnabled = 1
+};
+
+#define SERIALIO_HID_LENGTH 8 // including null terminator
+#define SERIALIO_UID_LENGTH 1
+#define SERIALIO_CID_LENGTH 1
+#define SERIALIO_TOTAL_ID_LENGTH SERIALIO_HID_LENGTH+SERIALIO_UID_LENGTH+SERIALIO_CID_LENGTH
+
+/**
+ Returns index of the last i2c controller.
+
+ @retval Value Index of I2C controller
+
+**/
+PCH_SERIAL_IO_CONTROLLER
+GetMaxI2cNumber (
+ VOID
+ );
+
+/**
+ Configures Serial IO Controller.
+
+ @param[in] Controller 0=I2C0, ..., 11=UART2
+ @param[in] DeviceMode Different type of serial io mode defined in PCH_SERIAL_IO_MODE
+ @param[in] SerialIoSafeRegister D0i3 Max Power On Latency and Device PG config
+
+**/
+VOID
+ConfigureSerialIoController (
+ IN PCH_SERIAL_IO_CONTROLLER Controller,
+ IN PCH_SERIAL_IO_MODE DeviceMode
+#ifdef PCH_PO_FLAG
+ , IN UINT32 SerialIoSafeRegister
+#endif
+ );
+
+#if 0
+/**
+ Initializes GPIO pins used by SerialIo I2C devices.
+
+ @param[in] Controller 0=I2C0, ..., 11=UART2
+ @param[in] DeviceMode Different type of serial io mode defined in PCH_SERIAL_IO_MODE
+ @param[in] I2cVoltage Select I2C voltage, 1.8V or 3.3V
+
+**/
+VOID
+SerialIoI2cGpioInit (
+ IN PCH_SERIAL_IO_CONTROLLER Controller,
+ IN PCH_SERIAL_IO_MODE DeviceMode,
+ IN UINT32 I2cVoltage
+ );
+
+/**
+ Initializes GPIO pins used by SerialIo SPI devices.
+
+ @param[in] Controller 0=I2C0, ..., 11=UART2
+ @param[in] DeviceMode Different type of serial io mode defined in PCH_SERIAL_IO_MODE
+ @param[in] SpiCsPolarity SPI CS polarity
+
+**/
+VOID
+SerialIoSpiGpioInit (
+ IN PCH_SERIAL_IO_CONTROLLER Controller,
+ IN PCH_SERIAL_IO_MODE DeviceMode,
+ IN UINT32 SpiCsPolarity
+ );
+
+/**
+ Initializes GPIO pins used by SerialIo devices.
+
+ @param[in] Controller 0=I2C0, ..., 11=UART2
+ @param[in] DeviceMode Different type of serial io mode defined in PCH_SERIAL_IO_MODE
+ @param[in] HardwareFlowControl Hardware flow control method
+
+**/
+VOID
+SerialIoUartGpioInit (
+ IN PCH_SERIAL_IO_CONTROLLER Controller,
+ IN PCH_SERIAL_IO_MODE DeviceMode,
+ IN BOOLEAN HardwareFlowControl
+ );
+#endif
+
+/**
+ Finds PCI Device Number of SerialIo devices.
+ SerialIo devices' BDF is configurable.
+
+ @param[in] SerialIoDevice 0=I2C0, ..., 11=UART2
+
+ @retval UINT8 SerialIo device number
+
+**/
+UINT8
+GetSerialIoDeviceNumber (
+ IN PCH_SERIAL_IO_CONTROLLER SerialIoNumber
+ );
+
+/**
+ Finds PCI Function Number of SerialIo devices.
+ SerialIo devices' BDF is configurable.
+
+ @param[in] SerialIoDevice 0=I2C0, ..., 11=UART2
+
+ @retval UINT8 SerialIo funciton number
+
+**/
+UINT8
+GetSerialIoFunctionNumber (
+ IN PCH_SERIAL_IO_CONTROLLER SerialIoNumber
+ );
+
+/**
+ Finds BAR values of SerialIo devices.
+ SerialIo devices can be configured to not appear on PCI so traditional method of reading BAR might not work.
+ If the SerialIo device is in PCI mode, a request for BAR1 will return its PCI CFG space instead.
+
+ @param[in] SerialIoDevice 0=I2C0, ..., 11=UART2
+ @param[in] BarNumber 0=BAR0, 1=BAR1
+
+ @retval UINTN SerialIo Bar value
+
+**/
+UINTN
+FindSerialIoBar (
+ IN PCH_SERIAL_IO_CONTROLLER SerialIoDevice,
+ IN UINT8 BarNumber
+ );
+
+#endif // _PEI_DXE_SMM_PCH_SERIAL_IO_LIB_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScSerialIoUartLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScSerialIoUartLib.h new file mode 100644 index 0000000000..68c04695ac --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScSerialIoUartLib.h @@ -0,0 +1,106 @@ +/** @file
+ Header file for PCH Serial IO UART Lib implementation.
+
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_SERIAL_IO_UART_LIB_H_
+#define _PCH_SERIAL_IO_UART_LIB_H_
+
+/**
+ Initialize selected SerialIo UART.
+ This init function MUST be used prior any SerialIo UART functions to init serial io controller if platform is going use serialio UART as debug output.
+
+ @param[in] UartNumber Selects Serial IO UART device (0-2)
+ @param[in] FifoEnable When TRUE, enables 64-byte FIFOs.
+ @param[in] BaudRate Baud rate.
+ @param[in] LineControl Data length, parity, stop bits.
+ @param[in] HardwareFlowControl Automated hardware flow control. If TRUE, hardware automatically checks CTS when sending data, and sets RTS when receiving data.
+
+ @retval BOOLEAN Initilization succeeded.
+
+**/
+BOOLEAN
+EFIAPI
+PchSerialIoUartInit (
+ IN UINT8 UartNumber,
+ IN BOOLEAN FifoEnable,
+ IN UINT32 BaudRate,
+ IN UINT8 LineControl,
+ IN BOOLEAN HardwareFlowControl
+ );
+
+/**
+ Write data to serial device.
+
+ If the buffer is NULL, then return 0;
+ if NumberOfBytes is zero, then return 0.
+
+ @param[in] UartNumber Selects Serial IO UART device (0-2)
+ @param[in] Buffer Point of data buffer which need to be writed.
+ @param[in] NumberOfBytes Number of output bytes which are cached in Buffer.
+
+ @retval UINTN Actual number of bytes writed to serial device.
+
+**/
+UINTN
+EFIAPI
+PchSerialIoUartOut (
+ IN UINT8 UartNumber,
+ IN UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+ );
+
+/**
+ Read data from serial device and save the datas in buffer.
+
+ If the buffer is NULL, then return 0;
+ if NumberOfBytes is zero, then return 0.
+
+ @param[in] UartNumber Selects Serial IO UART device (0-2)
+ @param[out] Buffer Point of data buffer which need to be writed.
+ @param[in] NumberOfBytes Number of output bytes which are cached in Buffer.
+ @param[in] WaitUntilBufferFull When TRUE, function waits until whole buffer is filled. When FALSE,
+ function returns as soon as no new characters are available.
+
+ @retval UINTN Actual number of bytes raed to serial device.
+
+**/
+UINTN
+EFIAPI
+PchSerialIoUartIn (
+ IN UINT8 UartNumber,
+ OUT UINT8 *Buffer,
+ IN UINTN NumberOfBytes,
+ IN BOOLEAN WaitUntilBufferFull
+ );
+
+/**
+ Polls a serial device to see if there is any data waiting to be read.
+
+ If there is data waiting to be read from the serial device, then TRUE is returned.
+ If there is no data waiting to be read from the serial device, then FALSE is returned.
+
+ @param[in] UartNumber Selects Serial IO UART device (0-2)
+
+ @retval TRUE Data is waiting to be read from the serial device.
+ @retval FALSE There is no data waiting to be read from the serial device.
+
+**/
+BOOLEAN
+EFIAPI
+PchSerialIoUartPoll (
+ IN UINT8 UartNumber
+ );
+
+#endif // _PEI_DXE_SMM_PCH_SERIAL_IO_UART_LIB_H_
+
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