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path: root/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/BaseScSpiCommonLib/SpiCommon.c
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Diffstat (limited to 'Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/BaseScSpiCommonLib/SpiCommon.c')
-rw-r--r--Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/BaseScSpiCommonLib/SpiCommon.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/BaseScSpiCommonLib/SpiCommon.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/BaseScSpiCommonLib/SpiCommon.c
index 97a13fa0d7..722f297309 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/BaseScSpiCommonLib/SpiCommon.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/BaseScSpiCommonLib/SpiCommon.c
@@ -601,6 +601,7 @@ SendSpiCmd (
UINT8 BiosCtlSave;
UINT32 SmiEnSave;
UINT16 ABase;
+ UINT32 HsfstsCtl;
Status = EFI_SUCCESS;
SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
@@ -653,6 +654,15 @@ SendSpiCmd (
goto SendSpiCmdEnd;
}
+
+ if (FlashCycleType == FlashCycleWriteStatus) {
+ HsfstsCtl = MmioRead32 (ScSpiBar0 + R_SPI_HSFS);
+ if ((HsfstsCtl & B_SPI_HSFS_WRSDIS) != 0) {
+ Status = EFI_ACCESS_DENIED;
+ goto SendSpiCmdEnd;
+ }
+ }
+
HardwareSpiAddr = Address;
if ((FlashCycleType == FlashCycleRead) ||
(FlashCycleType == FlashCycleWrite) ||