diff options
Diffstat (limited to 'Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt')
| -rw-r--r-- | Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl | 280 | ||||
| -rw-r--r-- | Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl | 28 | ||||
| -rw-r--r-- | Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 1272 | ||||
| -rw-r--r-- | Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl | 56 | ||||
| -rw-r--r-- | Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl | 445 | ||||
| -rw-r--r-- | Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 974 | ||||
| -rw-r--r-- | Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 244 | ||||
| -rw-r--r-- | Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl | 127 | ||||
| -rw-r--r-- | Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl | 31 | ||||
| -rw-r--r-- | Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl | 104 |
10 files changed, 3561 insertions, 0 deletions
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl new file mode 100644 index 0000000000..5ecbf5046d --- /dev/null +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl @@ -0,0 +1,280 @@ +/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+Scope(_SB)
+{
+ //
+ // A57x16 Processor declaration
+ //
+ Device(CPU0) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0)
+ }
+ Device(CPU1) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 1)
+ }
+ Device(CPU2) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 2)
+ }
+ Device(CPU3) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 3)
+ }
+ Device(CPU4) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 4)
+ }
+ Device(CPU5) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 5)
+ }
+ Device(CPU6) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 6)
+ }
+ Device(CPU7) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 7)
+ }
+ Device(CPU8) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 8)
+ }
+ Device(CPU9) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 9)
+ }
+ Device(CP10) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 10)
+ }
+ Device(CP11) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 11)
+ }
+ Device(CP12) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 12)
+ }
+ Device(CP13) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 13)
+ }
+ Device(CP14) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 14)
+ }
+ Device(CP15) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 15)
+ }
+ Device(CP16) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 16)
+ }
+ Device(CP17) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 17)
+ }
+ Device(CP18) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 18)
+ }
+ Device(CP19) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 19)
+ }
+ Device(CP20) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 20)
+ }
+ Device(CP21) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 21)
+ }
+ Device(CP22) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 22)
+ }
+ Device(CP23) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 23)
+ }
+ Device(CP24) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 24)
+ }
+ Device(CP25) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 25)
+ }
+ Device(CP26) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 26)
+ }
+ Device(CP27) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 27)
+ }
+ Device(CP28) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 28)
+ }
+ Device(CP29) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 29)
+ }
+ Device(CP30) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 30)
+ }
+ Device(CP31) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 31)
+ }
+ Device(CP32) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 32)
+ }
+ Device(CP33) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 33)
+ }
+ Device(CP34) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 34)
+ }
+ Device(CP35) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 35)
+ }
+ Device(CP36) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 36)
+ }
+ Device(CP37) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 37)
+ }
+ Device(CP38) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 38)
+ }
+ Device(CP39) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 39)
+ }
+ Device(CP40) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 40)
+ }
+ Device(CP41) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 41)
+ }
+ Device(CP42) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 42)
+ }
+ Device(CP43) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 43)
+ }
+ Device(CP44) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 44)
+ }
+ Device(CP45) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 45)
+ }
+ Device(CP46) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 46)
+ }
+ Device(CP47) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 47)
+ }
+ Device(CP48) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 48)
+ }
+ Device(CP49) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 49)
+ }
+ Device(CP50) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 50)
+ }
+ Device(CP51) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 51)
+ }
+ Device(CP52) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 52)
+ }
+ Device(CP53) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 53)
+ }
+ Device(CP54) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 54)
+ }
+ Device(CP55) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 55)
+ }
+ Device(CP56) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 56)
+ }
+ Device(CP57) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 57)
+ }
+ Device(CP58) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 58)
+ }
+ Device(CP59) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 59)
+ }
+ Device(CP60) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 60)
+ }
+ Device(CP61) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 61)
+ }
+ Device(CP62) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 62)
+ }
+ Device(CP63) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 63)
+ }
+}
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl new file mode 100644 index 0000000000..f0169ce75f --- /dev/null +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl @@ -0,0 +1,28 @@ +/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(_SB)
+{
+ Device(COM0) {
+ Name(_HID, "ARMH0011")
+ Name(_CID, "PL011")
+ Name(_UID, Zero)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x602B0000, 0x1000)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI0") { 807 }
+ })
+ }
+}
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl new file mode 100644 index 0000000000..11c28baf8c --- /dev/null +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl @@ -0,0 +1,1272 @@ +/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(_SB)
+{
+ Device (MDIO)
+ {
+ OperationRegion(CLKR, SystemMemory, 0x60000550, 8)
+ Field(CLKR, DWordAcc, NoLock, Preserve) {
+ CLKE, 1, // clock enable
+ , 31,
+ CLKD, 1, // clode disable
+ , 31,
+ }
+ OperationRegion(RSTR, SystemMemory, 0x60000c40, 8)
+ Field(RSTR, DWordAcc, NoLock, Preserve) {
+ RSTE, 1, // reset
+ , 31,
+ RSTD, 1, // de-reset
+ , 31,
+ }
+
+ Name(_HID, "HISI0141")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed (ReadWrite, 0x603c0000 , 0x10000)
+ })
+
+ Method(_RST, 0, Serialized) {
+ Store (0x1, RSTE)
+ Sleep (10)
+ Store (0x1, CLKD)
+ Sleep (10)
+ Store (0x1, RSTD)
+ Sleep (10)
+ Store (0x1, CLKE)
+ Sleep (10)
+ }
+ }
+
+ Device (DSF0)
+ {
+ OperationRegion(H3SR, SystemMemory, 0xC0000184, 4)
+ Field(H3SR, DWordAcc, NoLock, Preserve) {
+ H3ST, 1,
+ , 31, //RESERVED
+ }
+ OperationRegion(H4SR, SystemMemory, 0xC0000194, 4)
+ Field(H4SR, DWordAcc, NoLock, Preserve) {
+ H4ST, 1,
+ , 31, //RESERVED
+ }
+ // DSAF RESET
+ OperationRegion(DRER, SystemMemory, 0xC0000A00, 8)
+ Field(DRER, DWordAcc, NoLock, Preserve) {
+ DRTE, 1,
+ , 31, //RESERVED
+ DRTD, 1,
+ , 31, //RESERVED
+ }
+ // NT RESET
+ OperationRegion(NRER, SystemMemory, 0xC0000A08, 8)
+ Field(NRER, DWordAcc, NoLock, Preserve) {
+ NRTE, 1,
+ , 31, //RESERVED
+ NRTD, 1,
+ , 31, //RESERVED
+ }
+ // XGE RESET
+ OperationRegion(XRER, SystemMemory, 0xC0000A10, 8)
+ Field(XRER, DWordAcc, NoLock, Preserve) {
+ XRTE, 31,
+ , 1, //RESERVED
+ XRTD, 31,
+ , 1, //RESERVED
+ }
+
+ // GE RESET
+ OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16)
+ Field(GRTR, DWordAcc, NoLock, Preserve) {
+ GR0E, 30,
+ , 2, //RESERVED
+ GR0D, 30,
+ , 2, //RESERVED
+ GR1E, 18,
+ , 14, //RESERVED
+ GR1D, 18,
+ , 14, //RESERVED
+ }
+ // PPE RESET
+ OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8)
+ Field(PRTR, DWordAcc, NoLock, Preserve) {
+ PRTE, 10,
+ , 22, //RESERVED
+ PRTD, 10,
+ , 22, //RESERVED
+ }
+
+ // RCB PPE COM RESET
+ OperationRegion(RRTR, SystemMemory, 0xC0000A88, 8)
+ Field(RRTR, DWordAcc, NoLock, Preserve) {
+ RRTE, 1,
+ , 31, //RESERVED
+ RRTD, 1,
+ , 31, //RESERVED
+ }
+
+ // DSAF Channel RESET
+ OperationRegion(DCRR, SystemMemory, 0xC0000AA8, 8)
+ Field(DCRR, DWordAcc, NoLock, Preserve) {
+ DCRE, 1,
+ , 31, //RESERVED
+ DCRD, 1,
+ , 31, //RESERVED
+ }
+
+ // RoCE RESET
+ OperationRegion(RKRR, SystemMemory, 0xC0000A50, 8)
+ Field(RKRR, DWordAcc, NoLock, Preserve) {
+ RKRE, 1,
+ , 31, //RESERVED
+ RKRD, 1,
+ , 31, //RESERVED
+ }
+
+ // RoCE Clock enable/disable
+ OperationRegion(RKCR, SystemMemory, 0xC0000328, 8)
+ Field(RKCR, DWordAcc, NoLock, Preserve) {
+ RCLE, 1,
+ , 31, //RESERVED
+ RCLD, 1,
+ , 31, //RESERVED
+ }
+
+ // Hilink access sel cfg reg
+ OperationRegion(HSER, SystemMemory, 0xC2240008, 0x4)
+ Field(HSER, DWordAcc, NoLock, Preserve) {
+ HSEL, 2, // hilink_access_sel & hilink_access_wr_pul
+ , 30, // RESERVED
+ }
+
+ // Serdes
+ OperationRegion(H4LR, SystemMemory, 0xC2208100, 0x1000)
+ Field(H4LR, DWordAcc, NoLock, Preserve) {
+ H4L0, 16, // port0
+ , 16, //RESERVED
+ Offset (0x400),
+ H4L1, 16, // port1
+ , 16, //RESERVED
+ Offset (0x800),
+ H4L2, 16, // port2
+ , 16, //RESERVED
+ Offset (0xc00),
+ H4L3, 16, // port3
+ , 16, //RESERVED
+ }
+ OperationRegion(H3LR, SystemMemory, 0xC2208900, 0x800)
+ Field(H3LR, DWordAcc, NoLock, Preserve) {
+ H3L2, 16, // port4
+ , 16, //RESERVED
+ Offset (0x400),
+ H3L3, 16, // port5
+ , 16, //RESERVED
+ }
+ OperationRegion(HSFP, SystemMemory, 0x78000010, 0x100)
+ Field(HSFP, ByteAcc, NoLock, Preserve) {
+ Offset (0x2),
+ HSF0, 1, // port0
+ , 7, //RESERVED
+ Offset (0x6),
+ HSF1, 1, // port1
+ , 7, //RESERVED
+ }
+ Name (_HID, "HISI00B2")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_CRS, ResourceTemplate (){
+ Memory32Fixed (ReadWrite, 0xc5000000 , 0x890000)
+ Memory32Fixed (ReadWrite, 0xc7000000 , 0x60000)
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI1")
+ {
+ 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,
+ 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,
+ }
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI1")
+ {
+ 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,
+ 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,
+ 992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,
+ 1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,
+ 1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,
+ 1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,
+ 1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,
+ 1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,
+ 1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,
+ 1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,
+ 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,
+ 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,
+ }
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI1")
+ {
+ 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,
+ 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,
+ 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,
+ 1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,
+ 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,
+ 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,
+ 1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,
+ 1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,
+ 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,
+ 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,
+ 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,
+ 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"mode", "6port-16rss"},
+ Package () {"buf-size", 4096},
+ Package () {"desc-num", 1024},
+ }
+ })
+
+ //reset XGE port
+ //Arg0 : XGE port index in dsaf
+ //Arg1 : 0 reset, 1 cancle reset
+ Method(XRST, 2, Serialized) {
+ ShiftLeft (0x2082082, Arg0, Local0)
+ Or (Local0, 0x1, Local0)
+
+ If (LEqual (Arg1, 0)) {
+ Store(Local0, XRTE)
+ } Else {
+ Store(Local0, XRTD)
+ }
+ }
+
+ //reset XGE core
+ //Arg0 : XGE port index in dsaf
+ //Arg1 : 0 reset, 1 cancle reset
+ Method(XCRT, 2, Serialized) {
+ ShiftLeft (0x2080, Arg0, Local0)
+
+ If (LEqual (Arg1, 0)) {
+ Store(Local0, XRTE)
+ } Else {
+ Store(Local0, XRTD)
+ }
+ }
+
+ //reset GE port
+ //Arg0 : GE port index in dsaf
+ //Arg1 : 0 reset, 1 cancle reset
+ Method(GRST, 2, Serialized) {
+ If (LLessEqual (Arg0, 5)) {
+ //Service port
+ ShiftLeft (0x2082082, Arg0, Local0)
+ ShiftLeft (0x1, Arg0, Local1)
+
+ If (LEqual (Arg1, 0)) {
+ Store(Local1, GR1E)
+ Store(Local0, GR0E)
+ } Else {
+ Store(Local0, GR0D)
+ Store(Local1, GR1D)
+ }
+ }
+ }
+
+ //reset PPE port
+ //Arg0 : PPE port index in dsaf
+ //Arg1 : 0 reset, 1 cancle reset
+ Method(PRST, 2, Serialized) {
+ ShiftLeft (0x1, Arg0, Local0)
+ If (LEqual (Arg1, 0)) {
+ Store(Local0, PRTE)
+ } Else {
+ Store(Local0, PRTD)
+ }
+ }
+
+ //reset DSAF channels
+ //Arg0 : mask
+ //Arg1 : 0 reset, 1 de-reset
+ Method(DCRT, 2, Serialized) {
+ If (LEqual (Arg1, 0)) {
+ Store(Arg0, DCRE)
+ } Else {
+ Store(Arg0, DCRD)
+ }
+ }
+
+ //reset RoCE
+ //Arg0 : 0 reset, 1 de-reset
+ Method(RRST, 1, Serialized) {
+ If (LEqual (Arg0, 0)) {
+ Store(0x1, RKRE)
+ } Else {
+ Store(0x1, RCLD)
+ Store(0x1, RKRD)
+ sleep(20)
+ Store(0x1, RCLE)
+ }
+ }
+
+ // Set Serdes Loopback
+ //Arg0 : port
+ //Arg1 : 0 disable, 1 enable
+ Method(SRLP, 2, Serialized) {
+ ShiftLeft (Arg1, 10, Local0)
+ Switch (ToInteger(Arg0))
+ {
+ case (0x0){
+ Store (0, HSEL)
+ Store (H4L0, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local0, H4L0)
+ }
+ case (0x1){
+ Store (0, HSEL)
+ Store (H4L1, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local0, H4L1)
+ }
+ case (0x2){
+ Store (0, HSEL)
+ Store (H4L2, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local0, H4L2)
+ }
+ case (0x3){
+ Store (0, HSEL)
+ Store (H4L3, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local0, H4L3)
+ }
+ case (0x4){
+ Store (3, HSEL)
+ Store (H3L2, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local0, H3L2)
+ }
+ case (0x5){
+ Store (3, HSEL)
+ Store (H3L3, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local0, H3L3)
+ }
+ }
+ }
+
+ //Reset
+ //Arg0 : reset type (1: dsaf; 2: ppe; 3:XGE core; 4:XGE; 5:ge; 6:dchan; 7:RoCE)
+ //Arg1 : port
+ //Arg2 : 0 disable, 1 enable
+ Method(DRST, 3, Serialized)
+ {
+ Switch (ToInteger(Arg0))
+ {
+ //DSAF reset
+ case (0x1)
+ {
+ Store (Arg2, Local0)
+ If (LEqual (Local0, 0))
+ {
+ Store (0x1, DRTE)
+ Store (0x1, NRTE)
+ Sleep (10)
+ Store (0x1, RRTE)
+ }
+ Else
+ {
+ Store (0x1, DRTD)
+ Store (0x1, NRTD)
+ Sleep (10)
+ Store (0x1, RRTD)
+ }
+ }
+ //Reset PPE port
+ case (0x2)
+ {
+ Store (Arg1, Local0)
+ Store (Arg2, Local1)
+ PRST (Local0, Local1)
+ }
+
+ //Reset XGE core
+ case (0x3)
+ {
+ Store (Arg1, Local0)
+ Store (Arg2, Local1)
+ XCRT (Local0, Local1)
+ }
+ //Reset XGE port
+ case (0x4)
+ {
+ Store (Arg1, Local0)
+ Store (Arg2, Local1)
+ XRST (Local0, Local1)
+ }
+
+ //Reset GE port
+ case (0x5)
+ {
+ Store (Arg1, Local0)
+ Store (Arg2, Local1)
+ GRST (Local0, Local1)
+ }
+
+ //Reset DSAF Channels
+ case (0x6)
+ {
+ Store (Arg1, Local0)
+ Store (Arg2, Local1)
+ DCRT (Local0, Local1)
+ }
+
+ //Reset RoCE
+ case (0x7)
+ {
+ // Discarding Arg1 as it is always 0
+ Store (Arg2, Local0)
+ RRST (Local0)
+ }
+ }
+ }
+
+ // _DSM Device Specific Method
+ //
+ // Arg0: UUID Unique function identifier
+ // Arg1: Integer Revision Level
+ // Arg2: Integer Function Index
+ // 0 : Return Supported Functions bit mask
+ // 1 : Reset Sequence
+ // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5: ge; 6:dchan; 7:RoCE)
+ // Arg3[1] : port index in dsaf
+ // Arg3[2] : 0 reset, 1 cancle reset
+ // 2 : Set Serdes Loopback
+ // Arg3[0] : port
+ // Arg3[1] : 0 disable, 1 enable
+ // 3 : LED op set
+ // Arg3[0] : op type
+ // Arg3[1] : port
+ // Arg3[2] : para
+ // 4 : Get port type (GE or XGE)
+ // Arg3[0] : port index in dsaf
+ // Return : 0 GE, 1 XGE
+ // 5 : Get sfp status
+ // Arg3[0] : port index in dsaf
+ // Return : 0 no sfp, 1 have sfp
+ // Arg3: Package Parameters
+ Method (_DSM, 4, Serialized)
+ {
+ If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A")))
+ {
+ If (LEqual (Arg1, 0x00))
+ {
+ Switch (ToInteger(Arg2))
+ {
+ case (0x0)
+ {
+ Return (Buffer () {0x3F})
+ }
+
+ //Reset Sequence
+ case (0x1)
+ {
+ Store (DeRefOf (Index (Arg3, 0)), Local0)
+ Store (DeRefOf (Index (Arg3, 1)), Local1)
+ Store (DeRefOf (Index (Arg3, 2)), Local2)
+ DRST (Local0, Local1, Local2)
+ }
+
+ //Set Serdes Loopback
+ case (0x2)
+ {
+ Store (DeRefOf (Index (Arg3, 0)), Local0)
+ Store (DeRefOf (Index (Arg3, 1)), Local1)
+ SRLP (Local0, Local1)
+ }
+
+ //LED op set
+ case (0x3)
+ {
+
+ }
+
+ // Get port type (GE or XGE)
+ case (0x4)
+ {
+ Store (0, Local1)
+ Store (DeRefOf (Index (Arg3, 0)), Local0)
+ If (LLessEqual (Local0, 3))
+ {
+ // mac0: Hilink4 Lane0
+ // mac1: Hilink4 Lane1
+ // mac2: Hilink4 Lane2
+ // mac3: Hilink4 Lane3
+ Store (H4ST, Local1)
+ }
+ ElseIf (LLessEqual (Local0, 5))
+ {
+ // mac4: Hilink3 Lane2
+ // mac5: Hilink3 Lane3
+ Store (H3ST, Local1)
+ }
+
+ Return (Local1)
+ }
+
+ //Get sfp status
+ case (0x5)
+ {
+ Store (1, Local1) //set no sfp default
+ Store (DeRefOf (Index (Arg3, 0)), Local0)
+ If (LEqual (Local0, 0))
+ {
+ // port 0:
+ Store (HSF0, Local1)
+ }
+ ElseIf (LEqual (Local0, 1))
+ {
+ // port 1
+ Store (HSF1, Local1)
+ }
+
+ XOr (Local1, 1, local1)
+ Return (Local1)
+ }
+ }
+ }
+ }
+ Return (Buffer() {0x00})
+ }
+ Device (PRT0)
+ {
+ Name (_ADR, 0x0)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"reg", 0},
+ Package () {"media-type", "fiber"},
+ }
+ })
+ }
+ Device (PRT1)
+ {
+ Name (_ADR, 0x1)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"reg", 1},
+ Package () {"media-type", "fiber"},
+ }
+ })
+ }
+
+ Device (PRT2)
+ {
+ Name (_ADR, 0x2)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"reg", 2},
+ Package () {"media-type", "fiber"},
+ }
+ })
+ }
+ Device (PRT3)
+ {
+ Name (_ADR, 0x3)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"reg", 3},
+ Package () {"media-type", "fiber"},
+ }
+ })
+ }
+
+ Device (PRT4)
+ {
+ Name (_ADR, 0x4)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"reg", 4},
+ Package () {"phy-mode", "sgmii"},
+ Package () {"phy-addr", 0},
+ Package () {"mdio-node", Package (){\_SB.MDIO}},
+ Package () {"media-type", "copper"},
+ }
+ })
+ }
+ Device (PRT5)
+ {
+ Name (_ADR, 0x5)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"reg", 5},
+ Package () {"phy-mode", "sgmii"},
+ Package () {"phy-addr", 1},
+ Package () {"mdio-node", Package (){\_SB.MDIO}},
+ Package () {"media-type", "copper"},
+ }
+ })
+ }
+ }
+ Device (ETH4) {
+ Name(_HID, "HISI00C2")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+ Package () {"ae-handle", Package (){\_SB.DSF0}},
+ Package () {"port-idx-in-ae", 4},
+ }
+ })
+ }
+ Device (ETH5) {
+ Name(_HID, "HISI00C2")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+ Package () {"ae-handle", Package (){\_SB.DSF0}},
+ Package () {"port-idx-in-ae", 5},
+ }
+ })
+ }
+ Device (ETH0) {
+ Name(_HID, "HISI00C2")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+ Package () {"ae-handle", Package (){\_SB.DSF0}},
+ Package () {"port-idx-in-ae", 0},
+ }
+ })
+ }
+ Device (ETH1) {
+ Name(_HID, "HISI00C2")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+ Package () {"ae-handle", Package (){\_SB.DSF0}},
+ Package () {"port-idx-in-ae", 1},
+ }
+ })
+ }
+
+ Device (ETH2) {
+ Name(_HID, "HISI00C2")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+ Package () {"ae-handle", Package (){\_SB.DSF0}},
+ Package () {"port-idx-in-ae", 2},
+ }
+ })
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0)
+ }
+ }
+ Device (ETH3) {
+ Name(_HID, "HISI00C2")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+ Package () {"ae-handle", Package (){\_SB.DSF0}},
+ Package () {"port-idx-in-ae", 3},
+ }
+ })
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0)
+ }
+ }
+
+ Device (ROCE) {
+ Name(_HID, "HISI00D1")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"eth-handle", Package () {\_SB.ETH0, \_SB.ETH1, 0, 0, \_SB.ETH4, \_SB.ETH5}},
+ Package () {"dsaf-handle", Package (){\_SB.DSF0}},
+ Package () {"node-guid", Package () { 0x00, 0x9A, 0xCD, 0x00, 0x00, 0x01, 0x02, 0x03 }}, // 8-bytes
+ Package () {"interrupt-names", Package() {"hns-roce-comp-0",
+ "hns-roce-comp-1",
+ "hns-roce-comp-2",
+ "hns-roce-comp-3",
+ "hns-roce-comp-4",
+ "hns-roce-comp-5",
+ "hns-roce-comp-6",
+ "hns-roce-comp-7",
+ "hns-roce-comp-8",
+ "hns-roce-comp-9",
+ "hns-roce-comp-10",
+ "hns-roce-comp-11",
+ "hns-roce-comp-12",
+ "hns-roce-comp-13",
+ "hns-roce-comp-14",
+ "hns-roce-comp-15",
+ "hns-roce-comp-16",
+ "hns-roce-comp-17",
+ "hns-roce-comp-18",
+ "hns-roce-comp-19",
+ "hns-roce-comp-20",
+ "hns-roce-comp-21",
+ "hns-roce-comp-22",
+ "hns-roce-comp-23",
+ "hns-roce-comp-24",
+ "hns-roce-comp-25",
+ "hns-roce-comp-26",
+ "hns-roce-comp-27",
+ "hns-roce-comp-28",
+ "hns-roce-comp-29",
+ "hns-roce-comp-30",
+ "hns-roce-comp-31",
+ "hns-roce-async",
+ "hns-roce-common"}},
+ }
+ })
+ Name (_CRS, ResourceTemplate (){
+ Memory32Fixed (ReadWrite, 0xc4000000 , 0x100000)
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI9")
+ {
+ 722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733,
+ 734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745,
+ 746, 747, 748, 749, 750, 751, 752, 753, 785, 754,
+ }
+ })
+ }
+
+ /* for p1 */
+ Device (DSF1)
+ {
+
+ OperationRegion(H3SR, SystemMemory, 0x400C0000184, 4)
+ Field(H3SR, DWordAcc, NoLock, Preserve) {
+ H3ST, 1,
+ , 31, //RESERVED
+ }
+ OperationRegion(H4SR, SystemMemory, 0x400C0000194, 4)
+ Field(H4SR, DWordAcc, NoLock, Preserve) {
+ H4ST, 1,
+ , 31, //RESERVED
+ }
+ // DSAF RESET
+ OperationRegion(DRER, SystemMemory, 0x400C0000A00, 8)
+ Field(DRER, DWordAcc, NoLock, Preserve) {
+ DRTE, 1,
+ , 31, //RESERVED
+ DRTD, 1,
+ , 31, //RESERVED
+ }
+ // NT RESET
+ OperationRegion(NRER, SystemMemory, 0x400C0000A08, 8)
+ Field(NRER, DWordAcc, NoLock, Preserve) {
+ NRTE, 1,
+ , 31, //RESERVED
+ NRTD, 1,
+ , 31, //RESERVED
+ }
+ // XGE RESET
+ OperationRegion(XRER, SystemMemory, 0x400C0000A10, 8)
+ Field(XRER, DWordAcc, NoLock, Preserve) {
+ XRTE, 31,
+ , 1, //RESERVED
+ XRTD, 31,
+ , 1, //RESERVED
+ }
+
+ // GE RESET
+ OperationRegion(GRTR, SystemMemory, 0x400C0000A18, 16)
+ Field(GRTR, DWordAcc, NoLock, Preserve) {
+ GR0E, 30,
+ , 2, //RESERVED
+ GR0D, 30,
+ , 2, //RESERVED
+ GR1E, 18,
+ , 14, //RESERVED
+ GR1D, 18,
+ , 14, //RESERVED
+ }
+ // PPE RESET
+ OperationRegion(PRTR, SystemMemory, 0x400C0000A48, 8)
+ Field(PRTR, DWordAcc, NoLock, Preserve) {
+ PRTE, 10,
+ , 22, //RESERVED
+ PRTD, 10,
+ , 22, //RESERVED
+ }
+
+ // RCB PPE COM RESET
+ OperationRegion(RRTR, SystemMemory, 0x400C0000A88, 8)
+ Field(RRTR, DWordAcc, NoLock, Preserve) {
+ RRTE, 1,
+ , 31, //RESERVED
+ RRTD, 1,
+ , 31, //RESERVED
+ }
+
+ // RCB_2X COM RESET
+ OperationRegion(RBTR, SystemMemory, 0x400C0000AC0, 8)
+ Field(RBTR, DWordAcc, NoLock, Preserve) {
+ RBTE, 1,
+ , 31, //RESERVED
+ RBTD, 1,
+ , 31, //RESERVED
+ }
+
+ // Hilink access sel cfg reg
+ OperationRegion(HSER, SystemMemory, 0x400C2240008, 0x4)
+ Field(HSER, DWordAcc, NoLock, Preserve) {
+ HSEL, 2, // hilink_access_sel & hilink_access_wr_pul
+ , 30, // RESERVED
+ }
+
+ // Serdes
+ OperationRegion(H4LR, SystemMemory, 0x400C2208100, 0x1000)
+ Field(H4LR, DWordAcc, NoLock, Preserve) {
+ H4L0, 16, // port0
+ , 16, //RESERVED
+ Offset (0x400),
+ H4L1, 16, // port1
+ , 16, //RESERVED
+ Offset (0x800),
+ H4L2, 16, // port2
+ , 16, //RESERVED
+ Offset (0xc00),
+ H4L3, 16, // port3
+ , 16, //RESERVED
+ }
+ OperationRegion(H3LR, SystemMemory, 0x400C2208900, 0x800)
+ Field(H3LR, DWordAcc, NoLock, Preserve) {
+ H3L2, 16, // port4
+ , 16, //RESERVED
+ Offset (0x400),
+ H3L3, 16, // port5
+ , 16, //RESERVED
+ }
+
+ Name (_HID, "HISI00B2")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_CRS, ResourceTemplate (){
+ QwordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x400c5000000, // Min Base Address
+ 0x400c588ffff, // Max Base Address
+ 0x0, // Translate
+ 0x890000 // Length
+ )
+ QwordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x400c7000000, // Min Base Address
+ 0x400c705ffff, // Max Base Address
+ 0x0, // Translate
+ 0x60000 // Length
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI8")
+ {
+ 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,
+ 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,
+ }
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI8")
+ {
+ 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,
+ 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,
+ 992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,
+ 1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,
+ 1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,
+ 1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,
+ 1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,
+ 1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,
+ 1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,
+ 1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,
+ 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,
+ 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,
+ }
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI8")
+ {
+ 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,
+ 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,
+ 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,
+ 1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,
+ 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,
+ 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,
+ 1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,
+ 1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,
+ 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,
+ 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,
+ 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,
+ 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"mode", "6port-16rss"},
+ Package () {"buf-size", 4096},
+ Package () {"desc-num", 1024},
+ }
+ })
+
+ //reset XGE port
+ //Arg0 : XGE port index in dsaf
+ //Arg1 : 0 reset, 1 cancle reset
+ Method(XRST, 2, Serialized) {
+ ShiftLeft (0x2082082, Arg0, Local0)
+ Or (Local0, 0x1, Local0)
+
+ If (LEqual (Arg1, 0)) {
+ Store(Local0, XRTE)
+ } Else {
+ Store(Local0, XRTD)
+ }
+ }
+
+ //reset XGE core
+ //Arg0 : XGE port index in dsaf
+ //Arg1 : 0 reset, 1 cancle reset
+ Method(XCRT, 2, Serialized) {
+ ShiftLeft (0x2080, Arg0, Local0)
+
+ If (LEqual (Arg1, 0)) {
+ Store(Local0, XRTE)
+ } Else {
+ Store(Local0, XRTD)
+ }
+ }
+
+ //reset GE port
+ //Arg0 : GE port index in dsaf
+ //Arg1 : 0 reset, 1 cancle reset
+ Method(GRST, 2, Serialized) {
+ If (LLessEqual (Arg0, 5)) {
+ //Service port
+ ShiftLeft (0x2082082, Arg0, Local0)
+ ShiftLeft (0x1, Arg0, Local1)
+
+ If (LEqual (Arg1, 0)) {
+ Store(Local1, GR1E)
+ Store(Local0, GR0E)
+ } Else {
+ Store(Local0, GR0D)
+ Store(Local1, GR1D)
+ }
+ }
+ }
+
+ //reset PPE port
+ //Arg0 : PPE port index in dsaf
+ //Arg1 : 0 reset, 1 cancle reset
+ Method(PRST, 2, Serialized) {
+ ShiftLeft (0x1, Arg0, Local0)
+ If (LEqual (Arg1, 0)) {
+ Store(Local0, PRTE)
+ } Else {
+ Store(Local0, PRTD)
+ }
+ }
+
+ // Set Serdes Loopback
+ //Arg0 : port
+ //Arg1 : 0 disable, 1 enable
+ Method(SRLP, 2, Serialized) {
+ ShiftLeft (Arg1, 10, Local0)
+ Switch (ToInteger(Arg0))
+ {
+ case (0x0){
+ Store (0, HSEL)
+ Store (H4L0, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local0, H4L0)
+ }
+ case (0x1){
+ Store (0, HSEL)
+ Store (H4L1, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local0, H4L1)
+ }
+ case (0x2){
+ Store (0, HSEL)
+ Store (H4L2, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local0, H4L2)
+ }
+ case (0x3){
+ Store (0, HSEL)
+ Store (H4L3, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local0, H4L3)
+ }
+ case (0x4){
+ Store (3, HSEL)
+ Store (H3L2, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local0, H3L2)
+ }
+ case (0x5){
+ Store (3, HSEL)
+ Store (H3L3, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local0, H3L3)
+ }
+ }
+ }
+
+ //Reset
+ //Arg0 : reset type (1: dsaf; 2: ppe; 3:XGE core; 4:XGE; 5:G3)
+ //Arg1 : port
+ //Arg2 : 0 disable, 1 enable
+ Method(DRST, 3, Serialized)
+ {
+ Switch (ToInteger(Arg0))
+ {
+ //DSAF reset
+ case (0x1)
+ {
+ Store (Arg2, Local0)
+ If (LEqual (Local0, 0))
+ {
+ Store (0x1, DRTE)
+ Store (0x1, NRTE)
+ Sleep (10)
+ Store (0x1, RRTE)
+ Store (0x1, RBTE)
+ }
+ Else
+ {
+ Store (0x1, DRTD)
+ Store (0x1, NRTD)
+ Sleep (10)
+ Store (0x1, RRTD)
+ Store (0x1, RBTD)
+ }
+ }
+ //Reset PPE port
+ case (0x2)
+ {
+ Store (Arg1, Local0)
+ Store (Arg2, Local1)
+ PRST (Local0, Local1)
+ }
+
+ //Reset XGE core
+ case (0x3)
+ {
+ Store (Arg1, Local0)
+ Store (Arg2, Local1)
+ XCRT (Local0, Local1)
+ }
+ //Reset XGE port
+ case (0x4)
+ {
+ Store (Arg1, Local0)
+ Store (Arg2, Local1)
+ XRST (Local0, Local1)
+ }
+
+ //Reset GE port
+ case (0x5)
+ {
+ Store (Arg1, Local0)
+ Store (Arg2, Local1)
+ GRST (Local0, Local1)
+ }
+ }
+ }
+
+ // _DSM Device Specific Method
+ //
+ // Arg0: UUID Unique function identifier
+ // Arg1: Integer Revision Level
+ // Arg2: Integer Function Index
+ // 0 : Return Supported Functions bit mask
+ // 1 : Reset Sequence
+ // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5: ge)
+ // Arg3[1] : port index in dsaf
+ // Arg3[2] : 0 reset, 1 cancle reset
+ // 2 : Set Serdes Loopback
+ // Arg3[0] : port
+ // Arg3[1] : 0 disable, 1 enable
+ // 3 : LED op set
+ // Arg3[0] : op type
+ // Arg3[1] : port
+ // Arg3[2] : para
+ // 4 : Get port type (GE or XGE)
+ // Arg3[0] : port index in dsaf
+ // Return : 0 GE, 1 XGE
+ // 5 : Get sfp status
+ // Arg3[0] : port index in dsaf
+ // Return : 0 no sfp, 1 have sfp
+ // Arg3: Package Parameters
+ Method (_DSM, 4, Serialized)
+ {
+ If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A")))
+ {
+ If (LEqual (Arg1, 0x00))
+ {
+ Switch (ToInteger(Arg2))
+ {
+ case (0x0)
+ {
+ Return (Buffer () {0x3F})
+ }
+
+ //Reset Sequence
+ case (0x1)
+ {
+ Store (DeRefOf (Index (Arg3, 0)), Local0)
+ Store (DeRefOf (Index (Arg3, 1)), Local1)
+ Store (DeRefOf (Index (Arg3, 2)), Local2)
+ DRST (Local0, Local1, Local2)
+ }
+
+ //Set Serdes Loopback
+ case (0x2)
+ {
+ Store (DeRefOf (Index (Arg3, 0)), Local0)
+ Store (DeRefOf (Index (Arg3, 1)), Local1)
+ SRLP (Local0, Local1)
+ }
+
+ //LED op set
+ case (0x3)
+ {
+
+ }
+
+ // Get port type (GE or XGE)
+ case (0x4)
+ {
+ Store (0, Local1)
+ Store (DeRefOf (Index (Arg3, 0)), Local0)
+ If (LLessEqual (Local0, 3))
+ {
+ // mac0: Hilink4 Lane0
+ // mac1: Hilink4 Lane1
+ // mac2: Hilink4 Lane2
+ // mac3: Hilink4 Lane3
+ Store (H4ST, Local1)
+ }
+ ElseIf (LLessEqual (Local0, 5))
+ {
+ // mac4: Hilink3 Lane2
+ // mac5: Hilink3 Lane3
+ Store (H3ST, Local1)
+ }
+
+ Return (Local1)
+ }
+
+ //Get sfp status
+ case (0x5)
+ {
+
+ }
+ }
+ }
+ }
+ Return (Buffer() {0x00})
+ }
+
+ Device (PRT6)
+ {
+ Name (_ADR, 0x6)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"reg", 0},
+ Package () {"media-type", "fiber"},
+ }
+ })
+ }
+ Device (PRT7)
+ {
+ Name (_ADR, 0x7)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"reg", 1},
+ Package () {"media-type", "fiber"},
+ }
+ })
+ }
+ }
+
+ Device (ETH6) {
+ Name(_HID, "HISI00C2")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+ Package () {"ae-handle", Package (){\_SB.DSF1}},
+ Package () {"port-idx-in-ae", 0},
+ }
+ })
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0)
+ }
+ }
+ Device (ETH7) {
+ Name(_HID, "HISI00C2")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+ Package () {"ae-handle", Package (){\_SB.DSF1}},
+ Package () {"port-idx-in-ae", 1},
+ }
+ })
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0)
+ }
+ }
+
+}
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl new file mode 100644 index 0000000000..eb906ef20b --- /dev/null +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl @@ -0,0 +1,56 @@ +/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+Scope(_SB)
+{
+ Device(I2C0) {
+ Name(_HID, "APMC0D0F")
+ Name(_CID, "APMC0D0F")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xd00e0000, 0x10000)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI6") { 705 }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"clock-frequency", 100000},
+ Package () {"i2c-sda-falling-time-ns", 913},
+ Package () {"i2c-scl-falling-time-ns", 303},
+ Package () {"i2c-sda-hold-time-ns", 0x9c2},
+ }
+ })
+ }
+
+ Device(I2C2) {
+ Name(_HID, "APMC0D0F")
+ Name(_CID, "APMC0D0F")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xd0100000, 0x10000)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI7") { 707 }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"clock-frequency", 100000},
+ Package () {"i2c-sda-falling-time-ns", 913},
+ Package () {"i2c-scl-falling-time-ns", 303},
+ Package () {"i2c-sda-hold-time-ns", 0x9c2},
+ }
+ })
+ }
+}
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl new file mode 100644 index 0000000000..cdf3e57613 --- /dev/null +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl @@ -0,0 +1,445 @@ +/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(_SB)
+{
+ // Mbi-gen peri b intc
+ Device(MBI0) {
+ Name(_HID, "HISI0152")
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x60080000, 0x10000)
+ })
+
+ Name(_PRS, ResourceTemplate() {
+ Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0, ,) { 807 }
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ Device(MBI1) {
+ Name(_HID, "HISI0152")
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
+ })
+
+ Name(_PRS, ResourceTemplate() {
+ Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
+ {
+ 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,
+ 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,
+ }
+ Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
+ {
+ 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,
+ 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,
+ 992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,
+ 1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,
+ 1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,
+ 1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,
+ 1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,
+ 1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,
+ 1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,
+ 1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,
+ 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,
+ 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,
+ }
+ Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
+ {
+ 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,
+ 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,
+ 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,
+ 1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,
+ 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,
+ 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,
+ 1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,
+ 1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,
+ 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,
+ 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,
+ 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,
+ 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,
+ }
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 409}
+ }
+ })
+ }
+
+ // Mbi-gen sas0
+ Device(MBI2) {
+ Name(_HID, "HISI0152")
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
+ })
+
+ Name(_PRS, ResourceTemplate() {
+ Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0, ,)
+ {
+ 64,65,66,67,68,
+ 69,70,71,72,73,
+ 74,75,76,77,78,
+ 79,80,81,82,83,
+ 84,85,86,87,88,
+ 89,90,91,92,93,
+ 94,95,96,97,98,
+ 99,100,101,102,103,
+ 104,105,106,107,108,
+ 109,110,111,112,113,
+ 114,115,116,117,118,
+ 119,120,121,122,123,
+ 124,125,126,127,128,
+ 129,130,131,132,133,
+ 134,135,136,137,138,
+ 139,140,141,142,143,
+ 144,145,146,147,148,
+ 149,150,151,152,153,
+ 154,155,156,157,158,
+ 159,
+ }
+
+ Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0,,)
+ {
+ 601,602,603,604,
+ 605,606,607,608,609,
+ 610,611,612,613,614,
+ 615,616,617,618,619,
+ 620,621,622,623,624,
+ 625,626,627,628,629,
+ 630,631,632,
+ }
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 128}
+ }
+ })
+ }
+
+ Device(MBI3) { // Mbi-gen sas1 intc
+ Name(_HID, "HISI0152")
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
+ })
+
+ Name(_PRS, ResourceTemplate() {
+ Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0, ,)
+ {
+ 64,65,66,67,68,
+ 69,70,71,72,73,
+ 74,75,76,77,78,
+ 79,80,81,82,83,
+ 84,85,86,87,88,
+ 89,90,91,92,93,
+ 94,95,96,97,98,
+ 99,100,101,102,103,
+ 104,105,106,107,108,
+ 109,110,111,112,113,
+ 114,115,116,117,118,
+ 119,120,121,122,123,
+ 124,125,126,127,128,
+ 129,130,131,132,133,
+ 134,135,136,137,138,
+ 139,140,141,142,143,
+ 144,145,146,147,148,
+ 149,150,151,152,153,
+ 154,155,156,157,158,
+ 159,
+ }
+
+ Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
+ {
+ 576,577,578,579,580,
+ 581,582,583,584,585,
+ 586,587,588,589,590,
+ 591,592,593,594,595,
+ 596,597,598,599,600,
+ 601,602,603,604,605,
+ 606,607,
+ }
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 128}
+ }
+ })
+ }
+ Device(MBI4) { // Mbi-gen sas2 intc
+ Name(_HID, "HISI0152")
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
+ })
+
+ Name(_PRS, ResourceTemplate() {
+ Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0, ,)
+ {
+ 192,193,194,195,196,
+ 197,198,199,200,201,
+ 202,203,204,205,206,
+ 207,208,209,210,211,
+ 212,213,214,215,216,
+ 217,218,219,220,221,
+ 222,223,224,225,226,
+ 227,228,229,230,231,
+ 232,233,234,235,236,
+ 237,238,239,240,241,
+ 242,243,244,245,246,
+ 247,248,249,250,251,
+ 252,253,254,255,256,
+ 257,258,259,260,261,
+ 262,263,264,265,266,
+ 267,268,269,270,271,
+ 272,273,274,275,276,
+ 277,278,279,280,281,
+ 282,283,284,285,286,
+ 287,
+ }
+
+ Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
+ {
+ 608,609,610,611,
+ 612,613,614,615,616,
+ 617,618,619,620,621,
+ 622,623,624,625,626,
+ 627,628,629,630,631,
+ 632,633,634,635,636,
+ 637,638,639,
+ }
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 128}
+ }
+ })
+ }
+
+ Device(MBI5) {
+ Name(_HID, "HISI0152")
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
+ })
+
+ Name(_PRS, ResourceTemplate() {
+ Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0,,) {640,641,}
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 2}
+ }
+ })
+ }
+
+ Device(MBI6) {
+ Name(_HID, "HISI0152")
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xd0080000, 0x10000)
+ })
+
+ Name(_PRS, ResourceTemplate() {
+ Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0,,) { 705 }
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ Device(MBI7) {
+ Name(_HID, "HISI0152")
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xd0080000, 0x10000)
+ })
+
+ Name(_PRS, ResourceTemplate() {
+ Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0,,) { 707 }
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ Device(MBI8) {
+ Name(_HID, "HISI0152")
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QwordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x400c0080000, // Min Base Address
+ 0x400c008ffff, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+ })
+
+ Name(_PRS, ResourceTemplate() {
+ Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
+ {
+ 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,
+ 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,
+ }
+ Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
+ {
+ 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,
+ 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,
+ 992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,
+ 1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,
+ 1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,
+ 1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,
+ 1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,
+ 1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,
+ 1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,
+ 1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,
+ 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,
+ 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,
+ }
+ Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
+ {
+ 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,
+ 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,
+ 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,
+ 1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,
+ 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,
+ 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,
+ 1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,
+ 1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,
+ 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,
+ 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,
+ 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,
+ 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,
+ }
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 409}
+ }
+ })
+ }
+/*
+ Device(MBI4) { // Mbi-gen dsa1 dbg0 intc
+ Name(_HID, "HISI0152")
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
+ })
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 9}
+ }
+ })
+ }
+
+ Device(MBI5) { // Mbi-gen dsa2 dbg1 intc
+ Name(_HID, "HISI0152")
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
+ })
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 9}
+ }
+ })
+ }
+
+ Device(MBI6) { // Mbi-gen dsa sas0 intc
+ Name(_HID, "HISI0152")
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
+ })
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 128}
+ }
+ })
+ }
+*/
+ Device(MBI9) { // Mbi-gen roce intc
+ Name(_HID, "HISI0152")
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
+ })
+ Name (_PRS, ResourceTemplate (){
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
+ {
+ 722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733,
+ 734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745,
+ 746, 747, 748, 749, 750, 751, 752, 753, 785, 754,
+ }
+ })
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 34}
+ }
+ })
+ }
+}
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl new file mode 100644 index 0000000000..79267e5db8 --- /dev/null +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl @@ -0,0 +1,974 @@ +/** @file
+*
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+//#include "ArmPlatform.h"
+Scope(_SB)
+{
+ /* 0xD000E014:Hi1616 chip version reg[19:8], 0x102-after EC, 0x101/0-before EC. */
+ OperationRegion (ECRA, SystemMemory, 0xD000E014, 0x4)
+ Field (ECRA, AnyAcc, NoLock, Preserve)
+ {
+ VECA, 32,
+ }
+
+ /* RBYV:Return by chip version
+ * the pcie device should be disable for chip's reason before EC,
+ * and the pcie device should be enable after EC for OS */
+ Method (RBYV)
+ {
+ Store(VECA, local0)
+ And (local0, 0xFFF00, local1)
+ If (LEqual (local1, 0x10200)) {
+ Return (0xf)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+/*
+ See ACPI 6.1 Spec, 6.2.11, PCI Firmware Spec 3.0, 4.5
+*/
+#define PCI_OSC_SUPPORT() \
+ Name(SUPP, Zero) /* PCI _OSC Support Field value */ \
+ Name(CTRL, Zero) /* PCI _OSC Control Field value */ \
+ Method(_OSC,4) { \
+ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { \
+ /* Create DWord-adressable fields from the Capabilities Buffer */ \
+ CreateDWordField(Arg3,0,CDW1) \
+ CreateDWordField(Arg3,4,CDW2) \
+ CreateDWordField(Arg3,8,CDW3) \
+ /* Save Capabilities DWord2 & 3 */ \
+ Store(CDW2,SUPP) \
+ Store(CDW3,CTRL) \
+ /* Only allow native hot plug control if OS supports: */ \
+ /* ASPM */ \
+ /* Clock PM */ \
+ /* MSI/MSI-X */ \
+ If(LNotEqual(And(SUPP, 0x16), 0x16)) { \
+ And(CTRL,0x1E,CTRL) \
+ }\
+ \
+ /* Do not allow native PME, AER */ \
+ /* Never allow SHPC (no SHPC controller in this system)*/ \
+ And(CTRL,0x10,CTRL) \
+ If(LNotEqual(Arg1,One)) { /* Unknown revision */ \
+ Or(CDW1,0x08,CDW1) \
+ } \
+ \
+ If(LNotEqual(CDW3,CTRL)) { /* Capabilities bits were masked */ \
+ Or(CDW1,0x10,CDW1) \
+ } \
+ \
+ /* Update DWORD3 in the buffer */ \
+ Store(CTRL,CDW3) \
+ Return(Arg3) \
+ } Else { \
+ Or(CDW1,4,CDW1) /* Unrecognized UUID */ \
+ Return(Arg3) \
+ } \
+ } // End _OSC
+
+ // 1P NA PCIe2
+ Device (PCI2)
+ {
+ Name (_HID, "PNP0A08") // PCI Express Root Bridge
+ Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+ Name(_SEG, 2) // Segment of this Root complex
+ Name(_BBN, 0x80) // Base Bus Number
+ Name(_CCA, 1)
+ Method (_CRS, 0, Serialized) { // Root complex resources
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 0x80, // AddressMinimum - Minimum Bus Number
+ 0x87, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 0x8 // RangeLength - Number of Busses
+ )
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0xa8800000, // Min Base Address
+ 0xaffeffff, // Max Base Address
+ 0x0, // Translate
+ 0x77f0000 // Length
+ )
+ QWordIO (
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x0, // Granularity
+ 0x0, // Min Base Address
+ 0xffff, // Max Base Address
+ 0xafff0000, // Translate
+ 0x10000 // Length
+ )
+ }) // Name(RBUF)
+ Return (RBUF)
+ } // Method(_CRS)
+ Device (RES2)
+ {
+ Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+ Name (_CRS, ResourceTemplate (){
+ Memory32Fixed (ReadWrite, 0xa00a0000 , 0x10000)
+ })
+ }
+ PCI_OSC_SUPPORT()
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0xf)
+ }
+
+ } // Device(PCI2)
+
+ Device (RES2)
+ {
+ Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+ Name (_CID, "PNP0C02") // Motherboard reserved resource
+ Name (_UID, 0x2) // Unique ID
+ Name (_CRS, ResourceTemplate (){
+ Memory32Fixed (ReadWrite, 0xa00a0000 , 0x10000) //host bridge register space
+ })
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0xf)
+ }
+ }
+
+ Device (R1NA) // reserve 1p NA ECAM resource
+ {
+ Name (_HID, "PNP0C02") // Motherboard reserved resource
+ Name (_CRS, ResourceTemplate (){
+ Memory32Fixed (ReadWrite, 0xa8000000 , 0x800000) //ECAM space for [bus 80-87]
+ })
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0xf)
+ }
+ }
+
+ // 1p NB PCIe0
+ Device (PCI4)
+ {
+ Name (_HID, "PNP0A08") // PCI Express Root Bridge
+ Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+ Name(_SEG, 4) // Segment of this Root complex
+ Name(_BBN, 0x88) // Base Bus Number
+ Name(_CCA, 1)
+ Method (_CRS, 0, Serialized) { // Root complex resources
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 0x88, // AddressMinimum - Minimum Bus Number
+ 0x8f, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 0x8 // RangeLength - Number of Busses
+ )
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0xa9000000, // Min Base Address
+ 0xabfeffff, // Max Base Address
+ 0x800000000, // Translate
+ 0x2ff0000 // Length
+ )
+ QWordIO (
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x0, // Granularity
+ 0x0, // Min Base Address
+ 0xffff, // Max Base Address
+ 0x8abff0000, // Translate
+ 0x10000 // Length
+ )
+ }) // Name(RBUF)
+ Return (RBUF)
+ } // Method(_CRS)
+ Device (RES4)
+ {
+ Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+ Name (_CRS, ResourceTemplate (){
+ QwordMemory (
+ ResourceConsumer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x8a0090000, // Min Base Address
+ 0x8a009ffff, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+ })
+ }
+ PCI_OSC_SUPPORT()
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (RBYV())
+ }
+
+ } // Device(PCI4)
+ Device (RES4)
+ {
+ Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+ Name (_CID, "PNP0C02") // Motherboard reserved resource
+ Name (_UID, 0x4) // Unique ID
+ Name (_CRS, ResourceTemplate (){
+ QwordMemory ( //host bridge register space
+ ResourceConsumer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x8a0090000, // Min Base Address
+ 0x8a009ffff, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+ })
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (RBYV())
+ }
+ }
+
+ // 1P NB PCI1
+ Device (PCI5)
+ {
+ Name (_HID, "PNP0A08") // PCI Express Root Bridge
+ Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+ Name(_SEG, 5) // Segment of this Root complex
+ Name(_BBN, 0x0) // Base Bus Number
+ Name(_CCA, 1)
+ Method (_CRS, 0, Serialized) { // Root complex resources
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 0x0, // AddressMinimum - Minimum Bus Number
+ 0x7, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 0x8 // RangeLength - Number of Busses
+ )
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0xb0800000, // Min Base Address
+ 0xb7feffff, // Max Base Address
+ 0x800000000, // Translate
+ 0x77f0000 // Length
+ )
+ QWordIO (
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x0, // Granularity
+ 0x0, // Min Base Address
+ 0xffff, // Max Base Address
+ 0x8b7ff0000, // Translate
+ 0x10000 // Length
+ )
+ }) // Name(RBUF)
+ Return (RBUF)
+ } // Method(_CRS)
+ Device (RES5)
+ {
+ Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+ Name (_CRS, ResourceTemplate (){
+ QwordMemory (
+ ResourceConsumer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x8a0200000, // Min Base Address
+ 0x8a020ffff, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+ })
+ }
+ PCI_OSC_SUPPORT()
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (RBYV())
+ }
+ } // Device(PCI5)
+ Device (RES5)
+ {
+ Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+ Name (_CID, "PNP0C02") // Motherboard reserved resource
+ Name (_UID, 0x5) // Unique ID
+ Name (_CRS, ResourceTemplate (){
+ QwordMemory ( //host bridge register space
+ ResourceConsumer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x8a0200000, // Min Base Address
+ 0x8a020ffff, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+ })
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (RBYV())
+ }
+ }
+
+ // 1P NB PCIe2
+ Device (PCI6)
+ {
+ Name (_HID, "PNP0A08") // PCI Express Root Bridge
+ Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+ Name(_SEG, 0x6) // Segment of this Root complex
+ Name(_BBN, 0xc0) // Base Bus Number
+ Name(_CCA, 1)
+ Method (_CRS, 0, Serialized) { // Root complex resources
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 0xc0, // AddressMinimum - Minimum Bus Number
+ 0xc7, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 0x8 // RangeLength - Number of Busses
+ )
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0xac900000, // Min Base Address
+ 0xaffeffff, // Max Base Address
+ 0x800000000, // Translate
+ 0x36f0000 // Length
+ )
+ QWordIO (
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x0, // Granularity
+ 0x0, // Min Base Address
+ 0xffff, // Max Base Address
+ 0x8afff0000, // Translate
+ 0x10000 // Length
+ )
+ }) // Name(RBUF)
+ Return (RBUF)
+ } // Method(_CRS)
+ Device (RES6)
+ {
+ Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+ Name (_CRS, ResourceTemplate (){
+ QwordMemory (
+ ResourceConsumer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x8a00a0000, // Min Base Address
+ 0x8a00affff, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+ })
+ }
+ PCI_OSC_SUPPORT()
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (RBYV())
+ }
+ } // Device(PCI6)
+ Device (RES6)
+ {
+ Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+ Name (_CID, "PNP0C02") // Motherboard reserved resource
+ Name (_UID, 0x6) // Unique ID
+ Name (_CRS, ResourceTemplate (){
+ QwordMemory ( //host bridge register space
+ ResourceConsumer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x8a00a0000, // Min Base Address
+ 0x8a00affff, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+ })
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (RBYV())
+ }
+ }
+ // 1P NB PCIe3
+ Device (PCI7)
+ {
+ Name (_HID, "PNP0A08") // PCI Express Root Bridge
+ Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+ Name(_SEG, 0x7) // Segment of this Root complex
+ Name(_BBN, 0x90) // Base Bus Number
+ Name(_CCA, 1)
+ Method (_CRS, 0, Serialized) { // Root complex resources
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 0x90, // AddressMinimum - Minimum Bus Number
+ 0x97, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 0x8 // RangeLength - Number of Busses
+ )
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0xb9800000, // Min Base Address
+ 0xbffeffff, // Max Base Address
+ 0x800000000, // Translate
+ 0x67f0000 // Length
+ )
+ QWordIO (
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x0, // Granularity
+ 0x0, // Min Base Address
+ 0xffff, // Max Base Address
+ 0x8bfff0000, // Translate
+ 0x10000 // Length
+ )
+ }) // Name(RBUF)
+ Return (RBUF)
+ } // Method(_CRS)
+ Device (RES7)
+ {
+ Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+ Name (_CRS, ResourceTemplate (){
+ QwordMemory (
+ ResourceConsumer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x8a00b0000, // Min Base Address
+ 0x8a00bffff, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+ })
+ }
+ PCI_OSC_SUPPORT()
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (RBYV())
+ }
+ } // Device(PCI7)
+ Device (RES7)
+ {
+ Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+ Name (_CID, "PNP0C02") // Motherboard reserved resource
+ Name (_UID, 0x7) // Unique ID
+ Name (_CRS, ResourceTemplate (){
+ QwordMemory ( //host bridge register space
+ ResourceConsumer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x8a00b0000, // Min Base Address
+ 0x8a00bffff, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+ })
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (RBYV())
+ }
+ }
+
+ Device (R1NB) // reserve 1p NB ECAM resource
+ {
+ Name (_HID, "PNP0C02") // Motherboard reserved resource
+ Name (_CRS, ResourceTemplate (){
+ QwordMemory ( //ECAM space for [bus 88-8f]
+ ResourceConsumer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x8a8800000, // Min Base Address
+ 0x8a8ffffff, // Max Base Address
+ 0x0, // Translate
+ 0x800000 // Length
+ )
+ QwordMemory ( //ECAM space for [bus 0-7]
+ ResourceConsumer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x8b0000000, // Min Base Address
+ 0x8b07fffff, // Max Base Address
+ 0x0, // Translate
+ 0x800000 // Length
+ )
+ QwordMemory ( //ECAM space for [bus c0-c7]
+ ResourceConsumer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x8ac000000, // Min Base Address
+ 0x8ac7fffff, // Max Base Address
+ 0x0, // Translate
+ 0x800000 // Length
+ )
+ QwordMemory ( //ECAM space for [bus 90-97]
+ ResourceConsumer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x8b9000000, // Min Base Address
+ 0x8b97fffff, // Max Base Address
+ 0x0, // Translate
+ 0x800000 // Length
+ )
+ })
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (RBYV())
+ }
+ }
+ // 2P NA PCIe2
+ Device (PCIa)
+ {
+ Name (_HID, "PNP0A08") // PCI Express Root Bridge
+ Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+ Name(_SEG, 0xa) // Segment of this Root complex
+ Name(_BBN, 0x10) // Base Bus Number
+ Name(_CCA, 1)
+ Method (_CRS, 0, Serialized) { // Root complex resources
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 0x10, // AddressMinimum - Minimum Bus Number
+ 0x1f, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 0x10 // RangeLength - Number of Busses
+ )
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x20000000, // Min Base Address
+ 0xefffffff, // Max Base Address
+ 0x65000000000, // Translate
+ 0xd0000000 // Length
+ )
+ QWordIO (
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x0, // Granularity
+ 0x0, // Min Base Address
+ 0xffff, // Max Base Address
+ 0x67fffff0000, // Translate
+ 0x10000 // Length
+ )
+ }) // Name(RBUF)
+ Return (RBUF)
+ } // Method(_CRS)
+ Device (RESa)
+ {
+ Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+ Name (_CRS, ResourceTemplate (){
+ QwordMemory (
+ ResourceConsumer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x600a00a0000, // Min Base Address
+ 0x600a00affff, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+ })
+ }
+ PCI_OSC_SUPPORT()
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0xf)
+ }
+ } // Device(PCIa)
+ Device (RESa)
+ {
+ Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+ Name (_CID, "PNP0C02") // Motherboard reserved resource
+ Name (_UID, 0xa) // Unique ID
+ Name (_CRS, ResourceTemplate (){
+ QwordMemory ( //host bridge register space
+ ResourceConsumer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x600a00a0000, // Min Base Address
+ 0x600a00affff, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+ })
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0xf)
+ }
+ }
+
+ Device (R2NA) //reserve for 2p NA ecam resource
+ {
+ Name (_HID, "PNP0C02") // Motherboard reserved resource
+ Name (_CRS, ResourceTemplate (){
+ QwordMemory ( //ECAM space for [bus 10-1f]
+ ResourceConsumer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x64001000000, // Min Base Address
+ 0x64001ffffff, // Max Base Address
+ 0x0, // Translate
+ 0x1000000 // Length
+ )
+ })
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0xf)
+ }
+ }
+ // 2P NB PCIe0
+ Device (PCIc)
+ {
+ Name (_HID, "PNP0A08") // PCI Express Root Bridge
+ Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+ Name(_SEG, 0xc) // Segment of this Root complex
+ Name(_BBN, 0x20) // Base Bus Number
+ Name(_CCA, 1)
+ Method (_CRS, 0, Serialized) { // Root complex resources
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 0x20, // AddressMinimum - Minimum Bus Number
+ 0x2f, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 0x10 // RangeLength - Number of Busses
+ )
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x30000000, // Min Base Address
+ 0xefffffff, // Max Base Address
+ 0x75000000000, // Translate
+ 0xc0000000 // Length
+ )
+ QWordIO (
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x0, // Granularity
+ 0x0, // Min Base Address
+ 0xffff, // Max Base Address
+ 0x77fffff0000, // Translate
+ 0x10000 // Length
+ )
+ }) // Name(RBUF)
+ Return (RBUF)
+ } // Method(_CRS)
+ Device (RESc)
+ {
+ Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+ Name (_CRS, ResourceTemplate (){
+ QwordMemory (
+ ResourceConsumer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x700a0090000, // Min Base Address
+ 0x700a009ffff, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+ })
+ }
+ PCI_OSC_SUPPORT()
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (RBYV())
+ }
+ } // Device(PCIc)
+
+ Device (RESc)
+ {
+ Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+ Name (_CID, "PNP0C02") // Motherboard reserved resource
+ Name (_UID, 0xc) // Unique ID
+ Name (_CRS, ResourceTemplate (){
+ QwordMemory ( //host bridge register space
+ ResourceConsumer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x700a0090000, // Min Base Address
+ 0x700a009ffff, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+ })
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (RBYV())
+ }
+ }
+ //2P NB PCIe1
+ Device (PCId)
+ {
+ Name (_HID, "PNP0A08") // PCI Express Root Bridge
+ Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+ Name(_SEG, 0xd) // Segment of this Root complex
+ Name(_BBN, 0x30) // Base Bus Number
+ Name(_CCA, 1)
+ Method (_CRS, 0, Serialized) { // Root complex resources
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 0x30, // AddressMinimum - Minimum Bus Number
+ 0x3f, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 0x10 // RangeLength - Number of Busses
+ )
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x40000000, // Min Base Address
+ 0xefffffff, // Max Base Address
+ 0x79000000000, // Translate
+ 0xB0000000 // Length
+ )
+ QWordIO (
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x0, // Granularity
+ 0x0, // Min Base Address
+ 0xffff, // Max Base Address
+ 0x7bfffff0000, // Translate
+ 0x10000 // Length
+ )
+ }) // Name(RBUF)
+ Return (RBUF)
+ } // Method(_CRS)
+ Device (RESd)
+ {
+ Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+ Name (_CRS, ResourceTemplate (){
+ QwordMemory (
+ ResourceConsumer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x700a0200000, // Min Base Address
+ 0x700a020ffff, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+ })
+ }
+ PCI_OSC_SUPPORT()
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (RBYV())
+ }
+ } // Device(PCId)
+ Device (RESd)
+ {
+ Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+ Name (_CID, "PNP0C02") // Motherboard reserved resource
+ Name (_UID, 0xd) // Unique ID
+ Name (_CRS, ResourceTemplate (){ //host bridge register space
+ QwordMemory (
+ ResourceConsumer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x700a0200000, // Min Base Address
+ 0x700a020ffff, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+ })
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (RBYV())
+ }
+ }
+
+ Device (R2NB) //reserve for 2p NB ecam resource
+ {
+ Name (_HID, "PNP0C02") // Motherboard reserved resource
+ Name (_CRS, ResourceTemplate (){
+ QwordMemory ( //ECAM space for [bus 20-2f]
+ ResourceConsumer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x74002000000, // Min Base Address
+ 0x74002ffffff, // Max Base Address
+ 0x0, // Translate
+ 0x1000000 // Length
+ )
+ QwordMemory ( //ECAM space for [bus 30-3f]
+ ResourceConsumer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x78003000000, // Min Base Address
+ 0x78003ffffff, // Max Base Address
+ 0x0, // Translate
+ 0x1000000 // Length
+ )
+ })
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (RBYV())
+ }
+ }
+}
+
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl new file mode 100644 index 0000000000..93beb952c9 --- /dev/null +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl @@ -0,0 +1,244 @@ +/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(_SB)
+{
+ Device(SAS0) {
+ Name(_HID, "HISI0162")
+ Name(_CCA, 1)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xC3000000, 0x10000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI2")
+ {
+ 64,65,66,67,68,
+ 69,70,71,72,73,
+ 74,75,76,77,78,
+ 79,80,81,82,83,
+ 84,85,86,87,88,
+ 89,90,91,92,93,
+ 94,95,96,97,98,
+ 99,100,101,102,103,
+ 104,105,106,107,108,
+ 109,110,111,112,113,
+ 114,115,116,117,118,
+ 119,120,121,122,123,
+ 124,125,126,127,128,
+ 129,130,131,132,133,
+ 134,135,136,137,138,
+ 139,140,141,142,143,
+ 144,145,146,147,148,
+ 149,150,151,152,153,
+ 154,155,156,157,158,
+ 159,
+ }
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI2")
+ {
+ 601,602,603,604,
+ 605,606,607,608,609,
+ 610,611,612,613,614,
+ 615,616,617,618,619,
+ 620,621,622,623,624,
+ 625,626,627,628,629,
+ 630,631,632,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 0x00}},
+ Package () {"queue-count", 16},
+ Package () {"phy-count", 8},
+ }
+ })
+
+ OperationRegion (CTL, SystemMemory, 0xC0000000, 0x10000)
+ Field (CTL, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x338),
+ CLK, 32,
+ CLKD, 32,
+ Offset (0xa60),
+ RST, 32,
+ DRST, 32,
+ Offset (0x5a30),
+ STS, 32,
+ }
+
+ Method (_RST, 0x0, Serialized)
+ {
+ Store(0x7ffff, RST)
+ Store(0x7ffff, CLKD)
+ Sleep(1)
+ Store(0x7ffff, DRST)
+ Store(0x7ffff, CLK)
+ Sleep(1)
+ }
+ }
+
+ Device(SAS1) {
+ Name(_HID, "HISI0162")
+ Name(_CCA, 1)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xA2000000, 0x10000)
+
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI3")
+ {
+ 64,65,66,67,68,
+ 69,70,71,72,73,
+ 74,75,76,77,78,
+ 79,80,81,82,83,
+ 84,85,86,87,88,
+ 89,90,91,92,93,
+ 94,95,96,97,98,
+ 99,100,101,102,103,
+ 104,105,106,107,108,
+ 109,110,111,112,113,
+ 114,115,116,117,118,
+ 119,120,121,122,123,
+ 124,125,126,127,128,
+ 129,130,131,132,133,
+ 134,135,136,137,138,
+ 139,140,141,142,143,
+ 144,145,146,147,148,
+ 149,150,151,152,153,
+ 154,155,156,157,158,
+ 159,
+ }
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3")
+ {
+ 576,577,578,579,580,
+ 581,582,583,584,585,
+ 586,587,588,589,590,
+ 591,592,593,594,595,
+ 596,597,598,599,600,
+ 601,602,603,604,605,
+ 606,607,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}},
+ Package () {"queue-count", 16},
+ Package () {"phy-count", 8},
+ Package () {"hip06-sas-v2-quirk-amt", 1},
+ }
+ })
+
+ OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000)
+ Field (CTL, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x318),
+ CLK, 32,
+ CLKD, 32,
+ Offset (0xa18),
+ RST, 32,
+ DRST, 32,
+ Offset (0x5a0c),
+ STS, 32,
+ }
+
+ Method (_RST, 0x0, Serialized)
+ {
+ Store(0x7ffff, RST)
+ Store(0x7ffff, CLKD)
+ Sleep(1)
+ Store(0x7ffff, DRST)
+ Store(0x7ffff, CLK)
+ Sleep(1)
+ }
+ }
+
+ Device(SAS2) {
+ Name(_HID, "HISI0162")
+ Name(_CCA, 1)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xA3000000, 0x10000)
+
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI4")
+ {
+ 192,193,194,195,196,
+ 197,198,199,200,201,
+ 202,203,204,205,206,
+ 207,208,209,210,211,
+ 212,213,214,215,216,
+ 217,218,219,220,221,
+ 222,223,224,225,226,
+ 227,228,229,230,231,
+ 232,233,234,235,236,
+ 237,238,239,240,241,
+ 242,243,244,245,246,
+ 247,248,249,250,251,
+ 252,253,254,255,256,
+ 257,258,259,260,261,
+ 262,263,264,265,266,
+ 267,268,269,270,271,
+ 272,273,274,275,276,
+ 277,278,279,280,281,
+ 282,283,284,285,286,
+ 287,
+ }
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI4")
+ {
+ 608,609,610,611,
+ 612,613,614,615,616,
+ 617,618,619,620,621,
+ 622,623,624,625,626,
+ 627,628,629,630,631,
+ 632,633,634,635,636,
+ 637,638,639,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}},
+ Package () {"queue-count", 16},
+ Package () {"phy-count", 8},
+ }
+ })
+
+ OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000)
+ Field (CTL, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x3a8),
+ CLK, 32,
+ CLKD, 32,
+ Offset (0xae0),
+ RST, 32,
+ DRST, 32,
+ Offset (0x5a70),
+ STS, 32,
+ }
+
+ Method (_RST, 0x0, Serialized)
+ {
+ Store(0x7ffff, RST)
+ Store(0x7ffff, CLKD)
+ Sleep(1)
+ Store(0x7ffff, DRST)
+ Store(0x7ffff, CLK)
+ Sleep(1)
+ }
+ }
+
+}
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl new file mode 100644 index 0000000000..43e6f9210d --- /dev/null +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl @@ -0,0 +1,127 @@ +/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+//#include "ArmPlatform.h"
+Scope(_SB)
+{
+ Device (USB0)
+ {
+ Name (_HID, "PNP0D20") // _HID: Hardware ID
+ Name (_CID, "HISI0D2" /* EHCI USB Controller without debug */) // _CID: Compatible ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0xa7020000, // Address Base
+ 0x00010000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI5")
+ {
+ 641,
+ }
+ })
+ Return (RBUF) /* \_SB_.USB0._CRS.RBUF */
+ }
+
+ Device (RHUB)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ Device (PRT1)
+ {
+ Name (_ADR, One) // _ADR: Address
+ Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
+ {
+ 0xFF,
+ Zero,
+ Zero,
+ Zero
+ })
+ Name (_PLD, Package (0x01) // _PLD: Physical Location of Device
+ {
+ ToPLD (
+ PLD_Revision = 0x1,
+ PLD_IgnoreColor = 0x1,
+ PLD_Red = 0x0,
+ PLD_Green = 0x0,
+ PLD_Blue = 0x0,
+ PLD_Width = 0x0,
+ PLD_Height = 0x0,
+ PLD_UserVisible = 0x1,
+ PLD_Dock = 0x0,
+ PLD_Lid = 0x0,
+ PLD_Panel = "UNKNOWN",
+ PLD_VerticalPosition = "UPPER",
+ PLD_HorizontalPosition = "LEFT",
+ PLD_Shape = "UNKNOWN",
+ PLD_GroupOrientation = 0x0,
+ PLD_GroupToken = 0x0,
+ PLD_GroupPosition = 0x0,
+ PLD_Bay = 0x0,
+ PLD_Ejectable = 0x0,
+ PLD_EjectRequired = 0x0,
+ PLD_CabinetNumber = 0x0,
+ PLD_CardCageNumber = 0x0,
+ PLD_Reference = 0x0,
+ PLD_Rotation = 0x0,
+ PLD_Order = 0x0,
+ PLD_VerticalOffset = 0x0,
+ PLD_HorizontalOffset = 0x0)
+ })
+ }
+
+ Device (PRT2)
+ {
+ Name (_ADR, 0x02) // _ADR: Address
+ Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
+ {
+ Zero,
+ 0xFF,
+ Zero,
+ Zero
+ })
+ }
+
+ Device (PRT3)
+ {
+ Name (_ADR, 0x03) // _ADR: Address
+ Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
+ {
+ Zero,
+ 0xFF,
+ Zero,
+ Zero
+ })
+ }
+
+ Device (PRT4)
+ {
+ Name (_ADR, 0x04) // _ADR: Address
+ Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
+ {
+ Zero,
+ 0xFF,
+ Zero,
+ Zero
+ })
+ }
+ }
+ }
+}
+
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl new file mode 100644 index 0000000000..b4fc53873f --- /dev/null +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl @@ -0,0 +1,31 @@ +/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+#include "Hi1616Platform.h"
+
+DefinitionBlock("DsdtTable.aml", "DSDT", 2, "HISI ", "HIP07 ", EFI_ACPI_ARM_OEM_REVISION) {
+ include ("Lpc.asl")
+ include ("D05Mbig.asl")
+ include ("Com.asl")
+ include ("CPU.asl")
+ include ("D05I2c.asl")
+ include ("D05Usb.asl")
+ include ("D05Hns.asl")
+ include ("D05Sas.asl")
+ include ("D05Pci.asl")
+}
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl new file mode 100644 index 0000000000..d4b2372578 --- /dev/null +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl @@ -0,0 +1,104 @@ +/** @file
+*
+* Copyright (c) 2016 Hisilicon Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+//
+// LPC
+//
+
+Scope(_SB) {
+ Device (LPC0) {
+ Name (_HID, "HISI0191") // HiSi LPC
+ Name (_CRS, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0xa01b0000, 0x1000)
+ })
+ }
+
+ Device (LPC0.IPMI) {
+ Name (_HID, "IPI0001")
+ Method (_IFT) {
+ Return (0x03)
+ }
+ Name (LORS, ResourceTemplate() {
+ QWordIO (
+ ResourceConsumer,
+ MinNotFixed, // _MIF
+ MaxNotFixed, // _MAF
+ PosDecode,
+ EntireRange,
+ 0x0, // _GRA
+ 0xe4, // _MIN
+ 0x3fff, // _MAX
+ 0x0, // _TRA
+ 0x04, // _LEN
+ , ,
+ BTIO
+ )
+ })
+ CreateQWordField (LORS, BTIO._MIN, CMIN)
+ CreateQWordField (LORS, BTIO._MAX, CMAX)
+ CreateQWordField (LORS, BTIO._LEN, CLEN)
+
+ Method (_PRS, 0) {
+ Return (LORS)
+ }
+
+ Method (_CRS, 0) {
+ Return (LORS)
+ }
+ Method (_SRS, 1) {
+ CreateQWordField (Arg0, \_SB.LPC0.IPMI.BTIO._MIN, IMIN)
+ Store (IMIN, CMIN)
+ CreateQWordField (Arg0, \_SB.LPC0.IPMI.BTIO._MAX, IMAX)
+ Store (IMAX, CMAX)
+ }
+ }
+
+ Device (LPC0.CON0) {
+ Name (_HID, "HISI1031")
+ Name (_CID, "PNP0501")
+ Name (LORS, ResourceTemplate() {
+ QWordIO (
+ ResourceConsumer,
+ MinNotFixed, // _MIF
+ MaxNotFixed, // _MAF
+ PosDecode,
+ EntireRange,
+ 0x0, // _GRA
+ 0x2F8, // _MIN
+ 0x3fff, // _MAX
+ 0x0, // _TRA
+ 0x08, // _LEN
+ , ,
+ IO02
+ )
+ })
+ CreateQWordField (LORS, IO02._MIN, CMIN)
+ CreateQWordField (LORS, IO02._MAX, CMAX)
+ CreateQWordField (LORS, IO02._LEN, CLEN)
+
+ Method (_PRS, 0) {
+ Return (LORS)
+ }
+
+ Method (_CRS, 0) {
+ Return (LORS)
+ }
+ Method (_SRS, 1) {
+ CreateQWordField (Arg0, \_SB.LPC0.CON0.IO02._MIN, IMIN)
+ Store (IMIN, CMIN)
+ CreateQWordField (Arg0, \_SB.LPC0.CON0.IO02._MAX, IMAX)
+ Store (IMAX, CMAX)
+ }
+ }
+}
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