diff options
Diffstat (limited to 'Silicon/Hisilicon/Include')
21 files changed, 18751 insertions, 0 deletions
diff --git a/Silicon/Hisilicon/Include/Guid/MemoryMapData.h b/Silicon/Hisilicon/Include/Guid/MemoryMapData.h new file mode 100644 index 0000000000..5e418f970f --- /dev/null +++ b/Silicon/Hisilicon/Include/Guid/MemoryMapData.h @@ -0,0 +1,28 @@ +/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+
+#ifndef _MEMORY_MAP_GUID_H_
+#define _MEMORY_MAP_GUID_H_
+
+#define EFI_MEMORY_MAP_GUID \
+ { \
+ 0xf8870015,0x6994,0x4b98,0x95,0xa2,0xbd,0x56,0xda,0x91,0xc0,0x7f \
+ }
+
+extern EFI_GUID gHisiEfiMemoryMapGuid;
+
+#endif
diff --git a/Silicon/Hisilicon/Include/Guid/VersionInfoHobGuid.h b/Silicon/Hisilicon/Include/Guid/VersionInfoHobGuid.h new file mode 100644 index 0000000000..a61a244a92 --- /dev/null +++ b/Silicon/Hisilicon/Include/Guid/VersionInfoHobGuid.h @@ -0,0 +1,35 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _VERSION_INFO_HOB_GUID_H_
+#define _VERSION_INFO_HOB_GUID_H_
+
+// {0E13A14C-859C-4f22-82BD-180EE14212BF}
+#define VERSION_INFO_HOB_GUID \
+ {0xe13a14c, 0x859c, 0x4f22, {0x82, 0xbd, 0x18, 0xe, 0xe1, 0x42, 0x12, 0xbf}}
+
+extern GUID gVersionInfoHobGuid;
+
+#pragma pack(1)
+
+typedef struct {
+ EFI_TIME BuildTime;
+ CHAR16 String[1];
+} VERSION_INFO;
+
+#pragma pack()
+
+#endif
+
diff --git a/Silicon/Hisilicon/Include/Library/AcpiNextLib.h b/Silicon/Hisilicon/Include/Library/AcpiNextLib.h new file mode 100644 index 0000000000..60f9925c1a --- /dev/null +++ b/Silicon/Hisilicon/Include/Library/AcpiNextLib.h @@ -0,0 +1,83 @@ +/** @file
+*
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+
+#ifndef __ACPI_NEXT_LIB_H__
+#define __ACPI_NEXT_LIB_H__
+
+#define EFI_ACPI_6_1_GIC_ITS_INIT(GicITSHwId, GicITSBase) \
+ { \
+ EFI_ACPI_6_1_GIC_ITS, sizeof (EFI_ACPI_6_1_GIC_ITS_STRUCTURE), EFI_ACPI_RESERVED_WORD, \
+ GicITSHwId, GicITSBase, EFI_ACPI_RESERVED_DWORD\
+ }
+
+#define EFI_ACPI_5_1_GICR_STRUCTURE_INIT( \
+ GicRBase, GicRlength) \
+ { \
+ EFI_ACPI_5_1_GICR, sizeof (EFI_ACPI_5_1_GICR_STRUCTURE), EFI_ACPI_RESERVED_WORD, \
+ GicRBase, GicRlength \
+ }
+
+#define EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT( \
+ ProximityDomain, ACPIProcessorUID, Flags, ClockDomain) \
+ { \
+ 3, sizeof (EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE),ProximityDomain , \
+ ACPIProcessorUID, Flags, ClockDomain \
+ }
+
+#define EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT( \
+ ProximityDomain, AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, Flags) \
+ { \
+ 1, sizeof (EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE),ProximityDomain , EFI_ACPI_RESERVED_WORD, \
+ AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, EFI_ACPI_RESERVED_DWORD, Flags, \
+ EFI_ACPI_RESERVED_QWORD \
+ }
+
+#define EFI_ACPI_6_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, PmuIrq, \
+ GicBase, GicVBase, GicHBase, GsivId, GicRBase, ProcessorPowerEfficiencyClass) \
+ { \
+ EFI_ACPI_6_1_GIC, sizeof (EFI_ACPI_6_1_GIC_STRUCTURE), EFI_ACPI_RESERVED_WORD, \
+ GicId, AcpiCpuUid, Flags, 0, PmuIrq, 0, GicBase, GicVBase, GicHBase, \
+ GsivId, GicRBase, Mpidr, ProcessorPowerEfficiencyClass, {0, 0, 0} \
+ }
+
+#define EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT(GicDistHwId, GicDistBase, GicDistVector, GicVersion) \
+ { \
+ EFI_ACPI_6_1_GICD, sizeof (EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE), EFI_ACPI_RESERVED_WORD, \
+ GicDistHwId, GicDistBase, GicDistVector, GicVersion, \
+ {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE} \
+ }
+
+
+#pragma pack(1)
+//
+// Define the number of each table type.
+// This is where the table layout is modified.
+//
+#define EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT 64
+#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT 10
+
+
+typedef struct {
+ EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header;
+ EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE Memory[EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT];
+ EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE Gicc[EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT];
+} EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE;
+
+#pragma pack()
+#endif
+
diff --git a/Silicon/Hisilicon/Include/Library/CpldIoLib.h b/Silicon/Hisilicon/Include/Library/CpldIoLib.h new file mode 100644 index 0000000000..afc6b9164b --- /dev/null +++ b/Silicon/Hisilicon/Include/Library/CpldIoLib.h @@ -0,0 +1,22 @@ +/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _CPLD_IO_LIB_H_
+#define _CPLD_IO_LIB_H_
+
+VOID WriteCpldReg(UINTN ulRegAddr, UINT8 ulValue);
+UINT8 ReadCpldReg(UINTN ulRegAddr);
+
+#endif /* _CPLD_IO_LIB_H_ */
diff --git a/Silicon/Hisilicon/Include/Library/FdtUpdateLib.h b/Silicon/Hisilicon/Include/Library/FdtUpdateLib.h new file mode 100644 index 0000000000..94fc3d31f1 --- /dev/null +++ b/Silicon/Hisilicon/Include/Library/FdtUpdateLib.h @@ -0,0 +1,45 @@ +/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+
+#ifndef _FDTUPDATELIB_H_
+#define _FDTUPDATELIB_H_
+
+#define ADD_FILE_LENGTH 0x400
+
+typedef struct
+{
+ UINT32 BaseHigh;
+ UINT32 BaseLow;
+ UINT32 LengthHigh;
+ UINT32 LengthLow;
+}PHY_MEM_REGION;
+
+typedef struct
+{
+ UINT8 data0;
+ UINT8 data1;
+ UINT8 data2;
+ UINT8 data3;
+ UINT8 data4;
+ UINT8 data5;
+}MAC_ADDRESS;
+
+extern EFI_STATUS EFIFdtUpdate(UINTN FdtFileAddr);
+
+#endif
+
+
diff --git a/Silicon/Hisilicon/Include/Library/HwMemInitLib.h b/Silicon/Hisilicon/Include/Library/HwMemInitLib.h new file mode 100644 index 0000000000..2663cad836 --- /dev/null +++ b/Silicon/Hisilicon/Include/Library/HwMemInitLib.h @@ -0,0 +1,930 @@ +/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _HW_MEM_INIT_LIB_H_
+#define _HW_MEM_INIT_LIB_H_
+
+#include <PlatformArch.h>
+
+#define I2C_CHANNEL 2
+#define MAX_I2C_DEV 6
+
+#define SPD_MODULE_PART 18
+#define SPD_MODULE_PART_DDR4 20
+
+#define NVRAM_ADDR 0x00D00000
+
+typedef enum {
+ DDR_FREQ_AUTO = 0,
+ DDR_FREQ_800,
+ DDR_FREQ_1000,
+ DDR_FREQ_1066,
+ DDR_FREQ_1200,
+ DDR_FREQ_1333,
+ DDR_FREQ_1400,
+ DDR_FREQ_1600,
+ DDR_FREQ_1800,
+ DDR_FREQ_1866,
+ DDR_FREQ_2000,
+ DDR_FREQ_2133,
+ DDR_FREQ_2200,
+ DDR_FREQ_2400,
+ DDR_FREQ_2600,
+ DDR_FREQ_2666,
+ DDR_FREQ_2800,
+ DDR_FREQ_2933,
+ DDR_FREQ_3000,
+ DDR_FREQ_3200,
+ DDR_FREQ_MAX
+} DDR_FREQUENCY_INDEX;
+
+typedef struct _DDR_FREQ_TCK
+{
+ UINT32 ddrFreq;
+ UINT32 ddrCk;
+}DDR_FREQ_TCK;
+
+typedef struct _GBL_CFG{
+
+
+}GBL_CFG;
+
+typedef struct _GBL_VAR{
+
+
+}GBL_VAR;
+
+typedef struct _GBL_NVDATA{
+
+
+}GBL_NVDATA;
+
+typedef struct _GOBAL {
+ const GBL_CFG Config; // constant input data
+ GBL_VAR Variable; // variable, volatile data
+ GBL_NVDATA NvData; // variable, non-volatile data for S3, warm boot path
+ UINT32 PreBootFailed;
+}GOBAL, *PGOBAL;
+
+struct DDR_RANK {
+ BOOLEAN Status;
+ UINT16 RttNom;
+ UINT16 RttPark;
+ UINT16 RttWr;
+ UINT16 MR0;
+ UINT16 MR1;
+ UINT16 MR2;
+ UINT16 MR3;
+ UINT16 MR4;
+ UINT16 MR5;
+ UINT16 MR6[9];
+};
+
+struct baseMargin {
+ INT16 n;
+ INT16 p;
+};
+
+struct rankMargin {
+ struct baseMargin rank[MAX_CHANNEL][MAX_RANK_CH];
+};
+
+typedef struct _DDR_DIMM{
+ BOOLEAN Status;
+ UINT8 mapout;
+ UINT8 DramType; //Byte 2
+ UINT8 ModuleType; //Byte 3
+ UINT8 ExtendModuleType;
+ UINT8 SDRAMCapacity; //Byte 4
+ UINT8 BankNum;
+ UINT8 BGNum; //Byte 4 For DDR4
+ UINT8 RowBits; //Byte 5
+ UINT8 ColBits; //Byte 5
+ UINT8 SpdVdd; //Byte 6
+ UINT8 DramWidth; //Byte 7
+ UINT8 RankNum; //Byte 7
+ UINT8 PrimaryBusWidth; //Byte 8
+ UINT8 ExtensionBusWidth; //Byte 8
+ UINT32 Mtb;
+ UINT32 Ftb;
+ UINT32 minTck;
+ UINT8 MtbDividend;
+ UINT8 MtbDivsor;
+ UINT8 nCL;
+ UINT32 nRCD;
+ UINT32 nRP;
+ UINT8 SPDftb;
+ UINT8 SpdMinTCK;
+ UINT8 SpdMinTCKFtb;
+ UINT8 SpdMaxTCK;
+ UINT8 SpdMinTCL;
+ UINT8 SpdMinTCLFtb;
+ UINT8 SpdMinTWR;
+ UINT8 SpdMinTRCD;
+ UINT8 SpdMinTRCDFtb;
+ UINT8 SpdMinTRRD;
+ UINT8 SpdMinTRRDL;
+ UINT16 SpdMinTRAS;
+ UINT16 SpdMinTRC;
+ UINT16 SpdMinTRCFtb;
+ UINT16 SpdMinTRFC;
+ UINT8 SpdMinTWTR;
+ UINT8 SpdMinTRTP;
+ UINT8 SpdMinTAA;
+ UINT8 SpdMinTAAFtb;
+ UINT8 SpdMinTFAW;
+ UINT8 SpdMinTRP;
+ UINT8 SpdMinTRPFtb;
+ UINT8 SpdMinTCCDL;
+ UINT8 SpdMinTCCDLFtb;
+ UINT8 SpdAddrMap;
+ UINT8 SpdModuleAttr;
+
+ UINT8 SpdModPart[SPD_MODULE_PART]; // Module Part Number
+ UINT8 SpdModPartDDR4[SPD_MODULE_PART_DDR4]; // Module Part Number DDR4
+ UINT16 SpdMMfgId; // Module Mfg Id from SPD
+ UINT16 SpdRMId; // Register Manufacturer Id
+ UINT16 SpdMMDate; // Module Manufacturing Date
+ UINT32 SpdSerialNum;
+ UINT16 DimmSize;
+ UINT16 DimmSpeed;
+ UINT32 RankSize;
+ UINT8 SpdMirror; //Denote the dram address mapping is standard mode or mirrored mode
+ struct DDR_RANK Rank[MAX_RANK_DIMM];
+}DDR_DIMM;
+
+typedef struct {
+ UINT32 ddrcTiming0;
+ UINT32 ddrcTiming1;
+ UINT32 ddrcTiming2;
+ UINT32 ddrcTiming3;
+ UINT32 ddrcTiming4;
+ UINT32 ddrcTiming5;
+ UINT32 ddrcTiming6;
+ UINT32 ddrcTiming7;
+ UINT32 ddrcTiming8;
+}DDRC_TIMING;
+
+typedef struct _MARGIN_RESULT{
+ UINT32 OptimalDramVref[12];
+ UINT32 optimalPhyVref[18];
+}MARGIN_RESULT;
+
+typedef struct _DDR_Channel{
+ BOOLEAN Status;
+ UINT8 CurrentDimmNum;
+ UINT8 CurrentRankNum;
+ UINT16 RankPresent;
+ UINT8 DramType;
+ UINT8 DramWidth;
+ UINT8 ModuleType;
+ UINT32 MemSize;
+ UINT32 tck;
+ UINT32 ratio;
+ UINT32 CLSupport;
+ UINT32 minTck;
+ UINT32 taref;
+ UINT32 nAA;
+ UINT32 nAOND;
+ UINT32 nCKE;
+ UINT32 nCL;
+ UINT32 nCCDL;
+ UINT32 nCKSRX;
+ UINT32 nCKSRE;
+ UINT32 nCCDNSW;
+ UINT32 nCCDNSR;
+ UINT32 nFAW;
+ UINT32 nMRD;
+ UINT32 nMOD;
+ UINT32 nRCD;
+ UINT32 nRRD;
+ UINT32 nRRDL;
+ UINT32 nRAS;
+ UINT32 nRC;
+ UINT32 nRFC;
+ UINT32 nRFCAB;
+ UINT32 nRTP;
+ UINT32 nRTW;
+ UINT32 nRP;
+ UINT32 nSRE;
+ UINT32 nWL;
+ UINT32 nWR;
+ UINT32 nWTR;
+ UINT32 nWTRL;
+ UINT32 nXARD;
+ UINT32 nZQPRD;
+ UINT32 nZQINIT;
+ UINT32 nZQCS;
+ UINT8 cwl; //tWL?
+ UINT8 pl; //parity latency
+ UINT8 wr_pre_2t_en;
+ UINT8 rd_pre_2t_en;
+ UINT8 cmd_2t_en;
+ UINT8 parity_en;
+ UINT8 wr_dbi_en;
+ UINT8 wr_dm_en;
+ UINT8 ddr4_crc_en;
+ UINT16 emrs0;
+ UINT16 emrs1;
+ UINT16 emrs1Wr;
+ UINT16 emrs2;
+ UINT16 emrs3;
+ UINT16 emrs4;
+ UINT16 emrs5;
+ UINT16 emrs5Wr;
+ UINT16 emrs6;
+ UINT16 emrs7;
+ UINT8 phy_rddata_set;
+ UINT8 phyif_tim_rdcs;
+ UINT8 phyif_tim_rden;
+ UINT8 phyif_tim_wden;
+ UINT8 phyif_tim_wdda;
+ UINT8 phyif_tim_wdcs;
+ UINT8 per_cs_training_en;
+ UINT32 phyRdDataEnIeDly;
+ UINT32 phyPadCalConfig;
+ UINT32 phyDqsFallRiseDelay;
+ UINT32 ddrcCfgDfiLat0;
+ UINT32 ddrcCfgDfiLat1;
+ UINT32 parityLatency;
+ UINT32 dimm_parity_en;
+ DDRC_TIMING ddrcTiming;
+ DDR_DIMM Dimm[MAX_DIMM];
+ MARGIN_RESULT sMargin;
+}DDR_CHANNEL;
+
+typedef struct _NVRAM_RANK{
+ UINT16 MR0;
+ UINT16 MR1;
+ UINT16 MR2;
+ UINT16 MR3;
+ UINT16 MR4;
+ UINT16 MR5;
+ UINT16 MR6[9];
+}NVRAM_RANK;
+
+typedef struct _NVRAM_DIMM{
+ NVRAM_RANK Rank[MAX_RANK_DIMM];
+}NVRAM_DIMM;
+
+
+typedef struct _NVRAM_CHANNEL{
+ NVRAM_DIMM Dimm[MAX_DIMM];
+ UINT32 DDRC_CFG_ECC;
+ UINT32 DDRC_CFG_WORKMODE;
+ UINT32 DDRC_CFG_WORKMODE1;
+ UINT32 DDRC_CFG_WORKMODE2;
+ UINT32 DDRC_CFG_DDRMODE;
+ UINT32 DDRC_CFG_DIMM;
+ UINT32 DDRC_CFG_RNKVOL_0;
+ UINT32 DDRC_CFG_RNKVOL_1;
+ UINT32 DDRC_CFG_RNKVOL_2;
+ UINT32 DDRC_CFG_RNKVOL_3;
+ UINT32 DDRC_CFG_RNKVOL_4;
+ UINT32 DDRC_CFG_RNKVOL_5;
+ UINT32 DDRC_CFG_RNKVOL_6;
+ UINT32 DDRC_CFG_RNKVOL_7;
+ UINT32 DDRC_CFG_RNKVOL_8;
+ UINT32 DDRC_CFG_RNKVOL_9;
+ UINT32 DDRC_CFG_RNKVOL_10;
+ UINT32 DDRC_CFG_RNKVOL_11;
+ UINT32 DDRC_CFG_ODT_0;
+ UINT32 DDRC_CFG_ODT_1;
+ UINT32 DDRC_CFG_ODT_2;
+ UINT32 DDRC_CFG_ODT_3;
+ UINT32 DDRC_CFG_ODT_4;
+ UINT32 DDRC_CFG_ODT_5;
+ UINT32 DDRC_CFG_ODT_6;
+ UINT32 DDRC_CFG_ODT_7;
+ UINT32 DDRC_CFG_ODT_8;
+ UINT32 DDRC_CFG_ODT_9;
+ UINT32 DDRC_CFG_ODT_10;
+ UINT32 DDRC_CFG_ODT_11;
+ UINT32 DDRC_CFG_TIMING0;
+ UINT32 DDRC_CFG_TIMING1;
+ UINT32 DDRC_CFG_TIMING2;
+ UINT32 DDRC_CFG_TIMING3;
+ UINT32 DDRC_CFG_TIMING4;
+ UINT32 DDRC_CFG_TIMING5;
+ UINT32 DDRC_CFG_TIMING6;
+ UINT32 DDRC_CFG_TIMING7;
+ UINT32 DDRC_CFG_DFI_LAT0;
+ UINT32 DDRC_CFG_DFI_LAT1;
+ UINT32 DDRC_CFG_DDRPHY;
+ UINT32 Config[24];
+ BOOLEAN Status;
+}NVRAM_CHANNEL;
+
+typedef struct _NVRAM{
+ UINT32 NvramCrc;
+ NVRAM_CHANNEL Channel[MAX_SOCKET][MAX_CHANNEL];
+ UINT32 DdrFreqIdx;
+
+}NVRAM;
+
+typedef struct _MEMORY{
+ UINT8 Config0;
+ UINT8 marginTest;
+ UINT8 Config1[5];
+ UINT8 ErrorBypass; //register of spd mirror mode
+ UINT32 Config2;
+}MEMORY;
+
+typedef struct _NUMAINFO{
+ UINT8 NodeId;
+ UINT64 Base;
+ UINT64 Length;
+ UINT32 ScclInterleaveEn;
+}NUMAINFO;
+
+
+typedef struct _GBL_DATA
+{
+ DDR_CHANNEL Channel[MAX_SOCKET][MAX_CHANNEL];
+ UINT8 DramType;
+ UINT8 CurrentDimmNum;
+ UINT8 CurrentRankNum;
+ UINT8 MaxSPCNum;
+ UINT32 Freq;
+ UINT32 SpdTckMtb;
+ UINT32 SpdTckFtb;
+ UINT32 SpdTck;
+ UINT32 Tck;
+ UINT32 DdrFreqIdx;
+ UINT32 DevParaFreqIdx; //Maximum frequency of DDR device
+ UINT32 MemSize;
+ UINT32 EccEn;
+
+ BOOLEAN SetupExist;
+ UINT8 warmReset;
+ UINT8 needColdReset;
+
+ UINT8 cl;
+ UINT8 cwl;
+ UINT8 pl;
+ UINT8 wr_pre_2t_en;
+ UINT8 rd_pre_2t_en;
+ UINT8 cmd_2t_en;
+ UINT8 ddr4_parity_en;
+ UINT8 wr_dbi_en;
+ UINT8 wr_dm_en;
+ UINT8 ddr4_crc_en;
+ UINT16 emrs0;
+ UINT16 emrs1;
+ UINT16 emrs2;
+ UINT16 emrs3;
+ UINT16 emrs4;
+ UINT16 emrs5;
+ UINT16 emrs6;
+ UINT16 emrs7;
+ UINT8 phy_rddata_set;
+ UINT8 phyif_tim_rdcs;
+ UINT8 phyif_tim_rden;
+ UINT8 phyif_tim_wden;
+ UINT8 phyif_tim_wdda;
+ UINT8 phyif_tim_wdcs;
+ UINT8 dimm_trtr;
+ UINT8 dimm_twtw;
+ UINT8 rnk_trtr;
+ UINT8 rnk_twtw;
+ UINT8 rnk_trtw;
+ UINT8 rnk_twtr;
+ UINT8 per_cs_training_en;
+ UINT8 scale;
+ UINT8 ddrFreq;
+ UINT8 debugNeed;
+ UINT8 ddr3OdtEnable;
+ double fprd;
+ BOOLEAN chipIsEc;
+ NVRAM nvram;
+ MEMORY mem;
+ NUMAINFO NumaInfo[MAX_SOCKET][MAX_NUM_PER_TYPE];
+
+}GBL_DATA, *pGBL_DATA;
+
+typedef union {
+ struct {
+ UINT16 freqIndex:4; //Frequency Index;
+ UINT16 slot0:4; //Channel slot0 for DIMM
+ UINT16 slot1:4; //Channel slot1 for DIMM
+ UINT16 slot2:4; //Channel slot2 for DIMM
+ }Bits;
+ UINT16 Data;
+}ODT_VALUE_INDEX;
+
+typedef union {
+ struct {
+ UINT8 RTTNom:3;
+ UINT8 reserved_3:1;
+ UINT8 RTTWr:2;
+ UINT8 reserved_6:2;
+ }Bits;
+ UINT8 Data;
+}ODT_RTT_VALUE_DDR3;
+
+typedef union {
+ struct {
+ UINT8 RTTNom:3;
+ UINT8 RTTPark:3;
+ UINT8 RTTWr:2;
+ }Bits;
+ UINT8 Data;
+}ODT_RTT_VALUE_DDR4;
+
+typedef union {
+ struct {
+ UINT16 tarDimm:2; // target DIMM
+ UINT16 tarRank:2; // target Rank
+ UINT16 slot0:4; // Channel slot0 for DIMM
+ UINT16 slot1:4; // Channel slot1 for DIMM
+ UINT16 slot2:4; // Channel slot2 for DIMM
+ }Bits;
+ UINT16 Data;
+}ODT_ACTIVE_INDEX;
+
+struct ODT_VALUE_STRUCT_DDR3 {
+ UINT16 config; // ODT_VALUE_INDEX
+ UINT8 dramOdt[MAX_DIMM][MAX_RANK_DIMM]; // ODT_VALUE_RTT_DDR3
+};
+
+struct ODT_VALUE_STRUCT_DDR4 {
+ UINT16 config;
+ UINT8 dramOdt[MAX_DIMM][MAX_RANK_DIMM];
+};
+
+struct ODT_ACTIVE_STRUCT {
+ UINT16 config; // ODT config index
+ UINT16 actBits[2]; // WR :Bits[3;0] = D0_R[3:0] Bits[7:4] = D1_R[3:0] Bits[11:8] = D2_R[3:0]
+};
+
+// JEDEC manufacturer IDs from JEP-106
+#define MFGID_AENEON 0x5705
+#define MFGID_QIMONDA 0x5105
+#define MFGID_NEC 0x1000
+#define MFGID_IDT 0xB300
+#define MFGID_TI 0x9700
+#define MFGID_HYNIX 0xAD00
+#define MFGID_MICRON 0x2C00
+#define MFGID_INFINEON 0xC100
+#define MFGID_SAMSUNG 0xCE00
+#define MFGID_TEK 0x3D00
+#define MFGID_KINGSTON 0x9801
+#define MFGID_ELPIDA 0xFE02
+#define MFGID_SMART 0x9401
+#define MFGID_AGILENT 0xC802
+#define MFGID_NANYA 0x0B03
+#define MFGID_INPHI 0xB304
+#define MFGID_MONTAGE 0x3206
+#define MFGID_RAMAXEL 0x4304
+
+//
+// DDR3 frequencies 800 - 2667
+// DDR4 frequencies 1333 - 3200
+//
+#define DDR_800 0 // tCK(ns)=2.5
+#define DDR_1000 1 // tCK(ns)=2.0
+#define DDR_1066 2 // tCK(ns)=1.875
+#define DDR_1200 3 // tCK(ns)=1.667
+#define DDR_1333 4 // tCK(ns)=1.5
+#define DDR_1400 5 // tCK(ns)=1.429
+#define DDR_1600 6 // tCK(ns)=1.25
+#define DDR_1800 7 // tCK(ns)=1.11
+#define DDR_1866 8 // tCK(ns)=1.07
+#define DDR_2000 9 // tCK(ns)=1.0
+#define DDR_2133 10 // tCK(ns)=0.9375
+#define DDR_2200 11 // tCK(ns)=0.909
+#define DDR_2400 12 // tCK(ns)=0.833
+#define DDR_2600 13 // tCK(ns)=0.769
+#define DDR_2666 14 // tCK(ns)=0.750
+#define DDR_2800 15 // tCK(ns)=0.714
+#define DDR_2933 16 // tCK(ns)=0.682
+#define DDR_3000 17 // tCK(ns)=0.667
+#define DDR_3200 18 // tCK(ns)=0.625
+#define DDR_MAX (DDR_3200)
+
+#define FREQUENCY_MTB_OFFSET 1000000
+#define FREQUENCY_FTB_OFFSET 1000
+
+//
+#define DDR_800_TCK_MIN 25000
+#define DDR_1000_TCK_MIN 20000
+#define DDR_1067_TCK_MIN 18750
+#define DDR_1200_TCK_MIN 16670
+#define DDR_1333_TCK_MIN 15000
+#define DDR_1400_TCK_MIN 14290
+#define DDR_1600_TCK_MIN 12500
+#define DDR_1800_TCK_MIN 11100
+#define DDR_1867_TCK_MIN 10710
+#define DDR_2000_TCK_MIN 10000
+#define DDR_2133_TCK_MIN 9380
+#define DDR_2200_TCK_MIN 9090
+#define DDR_2400_TCK_MIN 8330
+#define DDR_2600_TCK_MIN 7690
+#define DDR_2667_TCK_MIN 7500
+#define DDR_2800_TCK_MIN 7140
+#define DDR_2933_TCK_MIN 6820
+#define DDR_3000_TCK_MIN 6670
+#define DDR_3200_TCK_MIN 6250
+
+
+//
+// Serial Presence Detect bytes (JEDEC revision 1.0)
+//
+#define SPD_SIZE 0 // Bytes used, Device size, CRC coverage
+#define SPD_REVISION 1 // SPD Encoding Revision
+#define SPD_KEY_BYTE 2 // DRAM Device Type
+ #define SPD_TYPE_DDR3 0x0B // DDR3 SDRAM
+ #define SPD_TYPE_DDR4 0x0C // DDR4 SDRAM
+#define SPD_KEY_BYTE2 3 // Module Type and Thickness (RDIMM or UDIMM)
+ #define SPD_RDIMM 1 // Module type is RDIMM
+ #define SPD_UDIMM 2 // Module type is UDIMM
+ #define SPD_SODIMM 3 // Module type is SODIMM
+ #define SPD_MICRO_DIMM 4 // Module type is Micro-DIMM
+ #define SPD_LRDIMM_DDR4 4 // Module type is LRDIMM (DDR4)
+ #define SPD_MINI_RDIMM 5 // Module type is Mini-RDIMM
+ #define SPD_MINI_UDIMM 6 // Module type is Mini-UDIMM
+ #define SPD_MINI_CDIMM 7 // Module type is Mini-CDIMM
+ #define SPD_ECC_SO_UDIMM 9 // Module type is 72b-SO-UDIMM
+ #define SPD_ECC_SO_RDIMM 8 // Module type is 72b-SO-RDIMM
+ #define SPD_ECC_SO_CDIMM 10 // Module type is 72b-SO-CDIMM
+ #define SPD_LRDIMM 11 // Module type is LRDIMM
+ #define SPD_UDIMM_ECC 18 // Module type is UDIMM-ECC
+#define SPD_SDRAM_BANKS 4 // SDRAM Density and number of internal banks
+ #define SPD_1Gb 2 // Total SDRAM Capacity 1 Gigabits
+ #define SPD_2Gb 3 // Total SDRAM Capacity 2 Gigabits
+ #define SPD_4Gb 4 // Total SDRAM Capacity 4 Gigabits
+ #define SPD_8Gb 5 // Total SDRAM Capacity 8 Gigabits
+ #define SPD_16Gb 6 // Total SDRAM Capacity 16 Gigabits
+ #define SPD_32Gb 7 // Total SDRAM Capacity 32 Gigabits
+#define SPD_SDRAM_ADDR 5 // Number of Row and Column address bits
+ #define SPD_ROW_12 0 // 12 row bits
+ #define SPD_ROW_13 1 // 13 row bits
+ #define SPD_ROW_14 2 // 14 row bits
+ #define SPD_ROW_15 3 // 15 row bits
+ #define SPD_ROW_16 4 // 16 row bits
+ #define SPD_ROW_17 5 // 17 row bits
+ #define SPD_ROW_18 6 // 18 row bits
+ #define SPD_COL_9 0 // 9 colum bits
+ #define SPD_COL_10 1 // 10 colum bits
+ #define SPD_COL_11 2 // 11 colum bits
+ #define SPD_COL_12 3 // 12 colum bits
+#define SPD_VDD_SUPPORT 6 // Vdd DIMM supports
+ #define SPD_VDD_150 0 // Module Supports 1.50V
+ #define SPD_VDD_135 BIT1 // Module Supports 1.35V
+ #define SPD_VDD_125 BIT2 // Module Supports 1.25V
+#define SPD_MODULE_ORG_DDR3 7 // Number of Ranks and SDRAM device width
+#define SPD_MODULE_ORG_DDR4 12 // DDR4 Module Organization
+ #define DEVICE_WIDTH_X4 0 // SDRAM device width = 4 bits
+ #define DEVICE_WIDTH_X8 1 // SDRAM device width = 8 bits
+ #define DEVICE_WIDTH_X16 2 // SDRAM device width = 16 bits
+ #define SPD_NUM_RANKS_1 0
+ #define SPD_NUM_RANKS_2 1
+ #define SPD_NUM_RANKS_4 3
+ #define SPD_NUM_RANKS_8 4
+#define SPD_MEM_BUS_WID 8 // Width of SDRAM memory bus
+#define SPD_FTB 9 // Timebase for fine grain timing calculations
+#define SPD_MTB_DIVEND 10 // Medium Time Base Dividend
+#define SPD_MTB_DIVISOR 11 // Medium Time Base Divisor
+#define SPD_MIN_TCK 12 // Minimum cycle time (at max CL)
+ #define SPD_TCKMIN_800 20 // tCK(MTB)=20, tCK(ns)=2.5
+ #define SPD_TCKMIN_1067 15 // tCK(MTB)=15, tCK(ns)=1.875
+ #define SPD_TCKMIN_1333 12 // tCK(MTB)=12, tCK(ns)=1.5
+ #define SPD_TCKMIN_1600 10 // tCK(MTB)=10, tCK(ns)=1.25
+ #define SPD_TCKMIN_1867 9 // tCK(MTB)=9, tCK(ns)=1.07
+ #define SPD_TCKMIN_2133 8 // tCK(MTB)=8, tCK(ns)=0.9375
+ #define SPD_TCKMIN_2400 7 // tCK(MTB)=7, tCK(ns)=.833
+#define SPD_CAS_LT_SUP_LSB 14 // CAS Latencies Supported, Least Significant Byte
+#define SPD_CAS_LT_SUP_MSB 15 // CAS Latencies Supported, Most Significant Byte
+#define SPD_MIN_TAA 16 // Minimum CAS Latency Time (tAAmin)
+#define SPD_MIN_TWR 17 // Minimum Write Recovery Time
+#define SPD_MIN_TRCD 18 // Minimum RAS to CAS delay
+#define SPD_MIN_TRRD 19 // Minimum Row active to row active delay
+#define SPD_MIN_TRP 20 // Minimum Row Precharge time
+#define SPD_EXT_TRC_TRAS 21 // Upper nibbles for min tRAS and tRC
+#define SPD_MIN_TRAS 22 // Minimum Active to Precharge time
+#define SPD_MIN_TRC 23 // Minimum Active to Active/Refresh time
+#define SPD_MIN_TRFC_LSB 24 // Minimum Refresh Recovery time least-significant byte
+#define SPD_MIN_TRFC_MSB 25 // Minimum Refresh Recovery time most-significant byte
+#define SPD_MIN_TWTR 26 // Minimum Internal Write to Read command delay
+#define SPD_MIN_TRTP 27 // Minimum Internal Read to Precharge command delay
+#define SPD_UN_TFAW 28 // Upper Nibble for tFAW
+#define SPD_MIN_TFAW 29 // Minimum Four Activate Window Delay Time (tFAWmin)
+#define SPD_OD_SUP 30 // SDRAM Output Drivers Supported
+#define SPD_RFSH_OPT 31 // SDRAM Refresh Options
+ #define ETR BIT0 // Bit location for Extended Temp Range
+ #define ETRR BIT1 // Bit location for Extended Temp Refresh Rate
+ #define ASR BIT2 // Bit location for Automatic Self Refresh
+ #define ODTS BIT3 // Bit location for On-die Thermal Sensor
+#define SPD_DIMM_TS 32 // Module Temperature Sensor
+#define SPD_SDRAM_TYPE 33 // SDRAM device type
+#define SPD_FTB_TCK 34 // Fine Offset for SDRAM tCK
+#define SPD_FTB_TAA 35 // Fine Offset for SDRAM tAA
+#define SPD_FTB_TRCD 36 // Fine Offset for SDRAM tRCD
+#define SPD_FTB_TRP 37 // Fine Offset for SDRAM tRP
+#define SPD_FTB_TRC 38 // Fine Offset for SDRAM tRC
+#define SPD_OPT_FEAT 41 // SDRAM Optional Features
+ #define SPD_PTRR BIT7 // Indicates if the DIMM is pTRR compliant
+
+ // UDIMM specific bytes
+ // Applicable when Module Type (key byte 3) = 2, 3, 4, 6, or 8
+
+#define SPD_ADDR_MAP_FECTD 63 // Address Mapping from Edge Connector to DRAM
+
+ // RDIMM specific bytes
+ // Applicable when Module Type (key byte 3) = 1, 5, or 9
+
+#define SPD_RDIMM_ATTR 63 // RDIMM module attributes
+#define SPD_DIMM_HS 64 // Module Heat Spreader Solution
+#define SPD_REG_VEN_LSB 65 // Register Vendor ID LSB
+#define SPD_REG_VEN_MSB 66 // Register Vendor ID MSB
+#define SPD_REG_REV 67 // Register Revision
+#define SPD_CNTL_0 69 // Register Control Word 0 & 1
+#define SPD_CNTL_1 70 // Register Control Word 2 & 3
+#define SPD_CNTL_2 71 // Register Control Word 4 & 5
+#define SPD_CNTL_3 72 // Register Control Word 6 & 7 (reserved)
+#define SPD_CNTL_4 73 // Register Control Word 8 & 9 (reserved)
+#define SPD_CNTL_5 74 // Register Control Word 10 & 11 (reserved)
+#define SPD_CNTL_6 75 // Register Control Word 12 & 13 (reserved)
+#define SPD_CNTL_7 76 // Register Control Word 14 & 15 (reserved)
+
+ // LRDIMM specific bytes
+ // Applicable when Module Type (key byte 3) = 0xB
+ // Based on DDR3 SPD 1.0 Document Release 2.1 draft, dated May 27, 2011
+
+#define SPD_LRDIMM_ATTR 63 // LRDIMM module attributes
+#define SPD_LRBUF_REV 64 // LR Buffer Revision
+#define SPD_LRBUF_VEN_LSB 65 // LR Buffer Vendor ID LSB
+#define SPD_LRBUF_VEN_MSB 66 // LR Buffer Vendor ID MSB
+#define SPD_LR_F0_RC2_3 67 // LR Buffer Function 0, Control Word 2 & 3
+#define SPD_LR_F0_RC4_5 68 // LR Buffer Function 0, Control Word 4 & 5
+#define SPD_LR_F1_RC8_11 69 // LR Buffer Function 1, Control Word 8 & 11
+#define SPD_LR_F1_RC12_13 70 // LR Buffer Function 1, Control Word 12 & 13
+#define SPD_LR_F1_RC14_15 71 // LR Buffer Function 1, Control Word 14 & 15
+
+ // Speed bin 0 = 800 & 1066
+#define SPD_LR_SB0_MDQ_DS_ODT 72 // LR Buffer Function 3, Control Word 8 & 9
+#define SPD_LR_SB0_DR01_QODT_ACT 73 // LR Buffer Function 3 & 4, Control Word 10 & 11
+#define SPD_LR_SB0_DR23_QODT_ACT 74 // LR Buffer Function 5 & 6, Control Word 10 & 11
+#define SPD_LR_SB0_DR45_QODT_ACT 75 // LR Buffer Function 7 & 8, Control Word 10 & 11
+#define SPD_LR_SB0_DR67_QODT_ACT 76 // LR Buffer Function 9 & 10, Control Word 10 & 11
+#define SPD_LR_SB0_MR1_2_RTT 77 // LR Buffer SMBus offsets 0xC0 - 0xC7
+
+ // Speed bin 1 = 1333 & 1600
+#define SPD_LR_SB1_MDQ_DS_ODT 78 // LR Buffer Function 3, Control Word 8 & 9
+#define SPD_LR_SB1_DR01_QODT_ACT 79 // LR Buffer Function 3 & 4, Control Word 10 & 11
+#define SPD_LR_SB1_DR23_QODT_ACT 80 // LR Buffer Function 5 & 6, Control Word 10 & 11
+#define SPD_LR_SB1_DR45_QODT_ACT 81 // LR Buffer Function 7 & 8, Control Word 10 & 11
+#define SPD_LR_SB1_DR67_QODT_ACT 82 // LR Buffer Function 9 & 10, Control Word 10 & 11
+#define SPD_LR_SB1_MR1_2_RTT 83 // LR Buffer SMBus offsets 0xC0 - 0xC7
+
+ // Speed bin 2 = 1866 & 2133
+#define SPD_LR_SB2_MDQ_DS_ODT 84 // LR Buffer Function 3, Control Word 8 & 9
+#define SPD_LR_SB2_DR01_QODT_ACT 85 // LR Buffer Function 3 & 4, Control Word 10 & 11
+#define SPD_LR_SB2_DR23_QODT_ACT 86 // LR Buffer Function 5 & 6, Control Word 10 & 11
+#define SPD_LR_SB2_DR45_QODT_ACT 87 // LR Buffer Function 7 & 8, Control Word 10 & 11
+#define SPD_LR_SB2_DR67_QODT_ACT 88 // LR Buffer Function 9 & 10, Control Word 10 & 11
+#define SPD_LR_SB2_MR1_2_RTT 89 // LR Buffer SMBus offsets 0xC0 - 0xC7
+
+#define SPD_LR_150_MIN_MOD_DELAY 90 // LR DIMM minimum DQ Read propagation delay at 1.5V
+#define SPD_LR_150_MAX_MOD_DELAY 91 // LR DIMM maximum DQ Read propagation delay at 1.5V
+#define SPD_LR_135_MIN_MOD_DELAY 92 // LR DIMM minimum DQ Read propagation delay at 1.35V
+#define SPD_LR_135_MAX_MOD_DELAY 93 // LR DIMM maximum DQ Read propagation delay at 1.35V
+#define SPD_LR_12x_MIN_MOD_DELAY 94 // LR DIMM minimum DQ Read propagation delay at 1.2xV
+#define SPD_LR_12x_MAX_MOD_DELAY 95 // LR DIMM maximum DQ Read propagation delay at 1.2xV
+
+#define SPD_LR_PERS_BYTE_0 102 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_1 103 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_2 104 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_3 105 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_4 106 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_5 107 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_6 108 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_7 109 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_8 110 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_9 111 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_10 112 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_11 113 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_12 114 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_13 115 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_14 116 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTES_TOTAL 15 // LR DIMM Total number of Personality Bytes
+
+ // End module specific section
+
+#define SPD_MMID_LSB 117 // Module Manufacturer ID Code, Least Significant Byte
+#define SPD_MMID_MSB 118 // Module Manufacturer ID Code, Mostst Significant Byte
+#define SPD_MM_LOC 119 // Module Manufacturing Location
+#define SPD_MM_DATE 120 // Module Manufacturing Date 120-121
+#define SPD_MODULE_SN 122 // Module Serial Number 122-125
+#define SPD_CRC_LSB 126 // LSB of 16-bit CRC
+#define SPD_CRC_MSB 127 // MSB of 16-bit CRC
+
+#define SPD_MODULE_PN 128 // Module Part Number 128-145
+#define SPD_MODULE_RC 146 // Module Revision Code 146-147
+#define SPD_DRAM_MIDC_LSB 148 // DRAM Manufacturer ID Code, Least Significant Byte
+#define SPD_DRAM_MIDC_MSB 149 // DRAM Manufacturer ID Code, Most Significant Byte
+#ifdef MEM_NVDIMM_EN
+#define SPD_NVDIMM_ID_N 174 // If NVDIMM value will be 'N'
+#define SPD_NVDIMM_ID_V 175 // If NVDIMM value will be 'V'
+#endif //MEM_NVDIMM_EN
+#define SPD_BYTE_200 200 // Fixed value 0xBE
+
+ //
+ // DDR4 Specific Bytes
+ //
+#define SPD_SDRAM_TYPE_DDR4 6 // SDRAM Device Type (DDR4)
+#define SPD_OPT_FEAT_DDR4 7 // SDRAM Optional Features (DDR4)
+ #define SPD_MAC_MASK BIT0 | BIT1 | BIT2 // Mask for Maximum Active Count field
+ #define SPD_TRR_IMMUNE BIT3 // Indicates this DIMM does not require DRAM Maintenance
+#define SPD_RFSH_OPT_DDR4 8 // SDRAM Refresh Options (DDR4)
+#define SPD_VDD_DDR4 11 // Vdd DIMM supports (DDR4)
+ #define SPD_VDD_120 3 // Module operable and endurant 1.20V
+#define SPD_MODULE_ORG_DDR4 12 // Number of Ranks and SDRAM device width (DDR4)
+#define SPD_MEM_BUS_WID_DDR4 13 // Width of SDRAM memory bus
+#define SPD_DIMM_TS_DDR4 14 // Module Thermal Sensor
+#define SPD_TB_DDR4 17 // Timebase [3:2] MTB, [1:0] FTB
+#define SPD_MIN_TCK_DDR4 18 // Minimum cycle time
+ #define SPD_TCKMIN_DDR4_1600 10 // tCK(MTB)=10, tCK(ns)=1.25
+ #define SPD_TCKMIN_DDR4_1866 9 // tCK(MTB)=9, tCK(ns)=1.071
+ #define SPD_TCKMIN_DDR4_2133 8 // tCK(MTB)=8, tCK(ns)=.938
+ #define SPD_TCKMIN_DDR4_2400 7 // tCK(MTB)=7, tCK(ns)=.833
+#define SPD_MAX_TCK_DDR4 19 // Maximum cycle time
+#define SPD_CAS_LT_SUP_1_DDR4 20 // CAS Latencies Supported, first byte
+#define SPD_CAS_LT_SUP_2_DDR4 21 // CAS Latencies Supported, second byte
+#define SPD_CAS_LT_SUP_3_DDR4 22 // CAS Latencies Supported, third byte
+#define SPD_CAS_LT_SUP_4_DDR4 23 // CAS Latencies Supported, fourth byte
+#define SPD_MIN_TAA_DDR4 24 // Minimum CAS Latency Time (tAAmin)
+#define SPD_MIN_TRCD_DDR4 25 // Minimum RAS to CAS delay
+#define SPD_MIN_TRP_DDR4 26 // Minimum Row Precharge time
+#define SPD_EXT_TRC_TRAS_DDR4 27 // Upper nibbles for min tRAS and tRC
+#define SPD_MIN_TRAS_DDR4 28 // Minimum Active to Precharge time
+#define SPD_MIN_TRC_DDR4 29 // Minimum Active to Active/Refresh time
+#define SPD_MIN_TRFC1_LSB_DDR4 30 // Minimum Refresh Recovery time least-significant byte
+#define SPD_MIN_TRFC1_MSB_DDR4 31 // Minimum Refresh Recovery time most-significant byte
+#define SPD_MIN_TRFC2_LSB_DDR4 32 // Minimum Refresh Recovery time least-significant byte
+#define SPD_MIN_TRFC2_MSB_DDR4 33 // Minimum Refresh Recovery time most-significant byte
+#define SPD_MIN_TRFC3_LSB_DDR4 34 // Minimum Refresh Recovery time least-significant byte
+#define SPD_MIN_TRFC3_MSB_DDR4 35 // Minimum Refresh Recovery time most-significant byte
+#define SPD_TFAW_UPPER_DDR4 36 // Upper nibble for tFAW
+#define SPD_MIN_TFAW_DDR4 37 // Minimum For Active Window Delay Time (tFAW)
+#define SPD_MIN_TRRDS_DDR4 38 // Minimum Active to Active Delay Time tRRD_S Different Bank Group
+#define SPD_MIN_TRRDL_DDR4 39 // Minimum Active to Active Delay Time tRRD_L Same Bank Group
+#define SPD_MIN_TCCDL_DDR4 40 // Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group
+#define SPD_FTB_TCCDL_DDR4 117 // Fine offset for tCCD_L
+#define SPD_FTB_TRRDL_DDR4 118 // Fine offset for tRRD_L
+#define SPD_FTB_TRRDS_DDR4 119 // Fine offset for tRRD_S
+#define SPD_FTB_TRC_DDR4 120 // Fine offset for TRC
+#define SPD_FTB_TRP_DDR4 121 // Fine offset for TRP
+#define SPD_FTB_TRCD_DDR4 122 // Fine offset for TRCD
+#define SPD_FTB_TAA_DDR4 123 // Fine offset for TAA
+#define SPD_FTB_MAX_TCK_DDR4 124 // Fine offset for max TCK
+#define SPD_FTB_MIN_TCK_DDR4 125 // Fine offset for min TCK
+#define SPD_MIRROR_UNBUFFERED 131 // Unbuffered:Address Mapping from Edge Connector to DRAM
+#define SPD_MIRROR_REGISTERED 136 // Registered:Address Address Mapping from Register to DRAM
+
+#define SPD_MMID_LSB_DDR4 320 // Module Manufacturer ID Code, Least Significant Byte
+#define SPD_MMID_MSB_DDR4 321 // Module Manufacturer ID Code, Most Significant Byte
+#define SPD_MM_LOC_DDR4 322 // Module Manufacturing Location
+#define SPD_MM_DATE_DDR4 323 // Module Manufacturing Date 323-324
+#define SPD_MODULE_SN_DDR4 325 // Module Serial Number 325-328
+#define SPD_MODULE_PN_DDR4 329 // Module Part Number 329-348
+#define SPD_MODULE_RC_DDR4 349 // Module Revision Code
+#define SPD_DRAM_MIDC_LSB_DDR4 350 // DRAM Manufacturer ID Code, Least Significant Byte
+#define SPD_DRAM_MIDC_MSB_DDR4 351 // DRAM Manufacturer ID Code, Most Significant Byte
+#define SPD_DRAM_REV_DDR4 352 // DRAM Revision ID
+#define SPD_CRC_LSB_DDR4 382 // LSB of 16-bit CRC
+#define SPD_CRC_MSB_DDR4 383 // MSB of 16-bit CRC
+
+ // Begin DDR4 module specific section
+#define SPD_MODULE_NH_DDR4 128 // Module Nominal Height
+#define SPD_MODULE_MT_DDR4 129 // Module Maximum Thickness
+#define SPD_REF_RAW_CARD_DDR4 130 // Reference Raw Card Used
+
+ // UDIMM specific bytes
+ // Applicable when Module Type (key byte 3) = 2
+#define SPD_ADDR_MAP_FECTD_DDR4 131 // Address Mapping from Edge Connector to DRAM
+
+ // RDIMM specific bytes
+ // Applicable when Module Type (key byte 3) = 1
+#define SPD_RDIMM_ATTR_DDR4 131 // RDIMM module attributes
+#define SPD_DIMM_HS_DDR4 132 // Module Heat Spreader Solution
+#define SPD_REG_VEN_LSB_DDR4 133 // Register Vendor ID LSB
+#define SPD_REG_VEN_MSB_DDR4 134 // Register Vendor ID MSB
+#define SPD_REG_REV_DDR4 135 // Register Revision
+#define SPD_ADD_MAPPING_DDR4 136 // Address mapping from Reg to DRAM
+#define SPD_REG_OD_CTL_DDR4 137 // Register Output Drive Strength for Control
+#define SPD_REG_OD_CK_DDR4 138 // Register Output Drive Strength for Clock
+
+ // LRDIMM specific bytes
+ // Applicable when Module Type (key byte 3) = 0x4
+#define SPD_LRDIMM_ATTR_DDR4 131 // LRDIMM module attributes
+#define SPD_LRBUF_HS_DDR4 132 // LR Buffer Heat Spreader Solution
+#define SPD_LRBUF_VEN_LSB_DDR4 133 // LR Buffer Vendor ID LSB
+#define SPD_LRBUF_VEN_MSB_DDR4 134 // LR Buffer Vendor ID MSB
+#define SPD_LRBUF_REV_DDR4 135 // LR Buffer Register Revision
+#define SPD_LRBUF_DB_REV_DDR4 139 // LR Buffer Data Buffer Revision
+#define SPD_LRBUF_DRAM_VREFDQ_R0_DDR4 140 // LR Buffer DRAM VrefDQ for Package Rank 0
+#define SPD_LRBUF_DRAM_VREFDQ_R1_DDR4 141 // LR Buffer DRAM VrefDQ for Package Rank 1
+#define SPD_LRBUF_DRAM_VREFDQ_R2_DDR4 142 // LR Buffer DRAM VrefDQ for Package Rank 2
+#define SPD_LRBUF_DRAM_VREFDQ_R3_DDR4 143 // LR Buffer DRAM VrefDQ for Package Rank 3
+#define SPD_LRBUF_DB_VREFDQ_DDR4 144 // LR Data Buffer VrefDQ for DRAM Interface
+#define SPD_LRBUF_DB_DS_RTT_LE1866_DDR4 145 // LR Data Buffer MDQ Drive Strength and RTT for data rate <= 1866
+#define SPD_LRBUF_DB_DS_RTT_GT1866_LE2400_DDR4 146 // LR Data Buffer MDQ Drive Strength and RTT for data rate > 1866 and <= 2400
+#define SPD_LRBUF_DB_DS_RTT_GT2400_LE3200_DDR4 147 // LR Data Buffer MDQ Drive Strength and RTT for data rate > 2400 and <= 3200
+#define SPD_LRBUF_DRAM_DS_DDR4 148 // LR Buffer DRAM Drive Strength (for data rates <= 1866, 1866 < data rate <= 2400, and 2400 < data rate <= 3200)
+#define SPD_LRBUF_DRAM_ODT_WR_NOM_LE1866_DDR4 149 // LR Buffer DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 1866
+#define SPD_LRBUF_DRAM_ODT_WR_NOM_GT1866_LE2400_DDR4 150 // LR Buffer DRAM ODT (RTT_WR and RTT_NOM) for data rate > 1866 and <= 2400
+#define SPD_LRBUF_DRAM_ODT_WR_NOM_GT2400_LE3200_DDR4 151 // LR Buffer DRAM ODT (RTT_WR and RTT_NOM) for data rate > 2400 and <= 3200
+#define SPD_LRBUF_DRAM_ODT_PARK_LE1866_DDR4 152 // LR Buffer DRAM ODT (RTT_PARK) for data rate <= 1866
+#define SPD_LRBUF_DRAM_ODT_PARK_GT1866_LE2400_DDR4 153 // LR Buffer DRAM ODT (RTT_PARK) for data rate > 1866 and <= 2400
+#define SPD_LRBUF_DRAM_ODT_PARK_GT2400_LE3200_DDR4 154 // LR Buffer DRAM ODT (RTT_PARK) for data rate > 2400 and <= 3200
+
+ //
+ // End DDR4 Specific Bytes
+ //
+#define BANK0 0
+#define BANK1 BIT0
+#define BANK2 BIT1
+#define BANK3 BIT0 + BIT1
+#define BANK4 BIT2
+#define BANK5 BIT2 + BIT0
+#define BANK6 BIT2 + BIT1
+#define BANK7 BIT2 + BIT1 + BIT0
+
+#define RDIMM_RC00 0x00
+#define RDIMM_RC01 0x01
+#define RDIMM_RC02 0x02
+#define RDIMM_RC03 0x03
+#define RDIMM_RC04 0x04
+#define RDIMM_RC05 0x05
+#define RDIMM_RC08 0x08
+#define RDIMM_RC09 0x09
+#define RDIMM_RC0A 0x0A
+#define RDIMM_RC0B 0x0B
+#define RDIMM_RC0C 0x0C
+#define RDIMM_RC0D 0x0D
+#define RDIMM_RC0E 0x0E
+#define RDIMM_RC0F 0x0F
+#define RDIMM_RC1x 0x10
+#define RDIMM_RC2x 0x20
+#define RDIMM_RC3x 0x30
+#define RDIMM_RC4x 0x40
+#define RDIMM_RC5x 0x50
+#define RDIMM_RC6x 0x60
+#define RDIMM_RC7x 0x70
+#define RDIMM_RC8x 0x80
+#define RDIMM_RC9x 0x90
+#define RDIMM_RCAx 0xA0
+
+#define LRDIMM_BC00 0x00
+#define LRDIMM_BC01 0x01
+#define LRDIMM_BC02 0x02
+#define LRDIMM_BC03 0x03
+#define LRDIMM_BC04 0x04
+#define LRDIMM_BC05 0x05
+#define LRDIMM_BC06 0x06
+#define LRDIMM_BC07 0x07
+#define LRDIMM_BC08 0x08
+#define LRDIMM_BC09 0x09
+#define LRDIMM_BC0A 0x0A
+#define LRDIMM_BC0B 0x0B
+#define LRDIMM_BC0C 0x0C
+#define LRDIMM_BC0E 0x0E
+
+#define LRDIMM_BC0x 0x00
+#define LRDIMM_BC1x 0x10
+#define LRDIMM_BC2x 0x20
+#define LRDIMM_BC3x 0x30
+#define LRDIMM_BC4x 0x40
+#define LRDIMM_BC5x 0x50
+#define LRDIMM_BC6x 0x60
+#define LRDIMM_BC7x 0x70
+#define LRDIMM_BC8x 0x80
+#define LRDIMM_BC9x 0x90
+#define LRDIMM_BCAx 0xA0
+#define LRDIMM_BCBx 0xB0
+#define LRDIMM_BCCx 0xC0
+#define LRDIMM_BCDx 0xD0
+#define LRDIMM_BCEx 0xE0
+#define LRDIMM_BCFx 0xF0
+#define LRDIMM_F0 0x0
+#define LRDIMM_F1 0x1
+#define LRDIMM_F5 0x5
+#define LRDIMM_F6 0x6
+#define LRDIMM_F7 0x7
+#define LRDIMM_F8 0x8
+#define LRDIMM_F9 0x9
+
+#endif /* _HW_MEM_INIT_LIB_H_ */
diff --git a/Silicon/Hisilicon/Include/Library/I2CLib.h b/Silicon/Hisilicon/Include/Library/I2CLib.h new file mode 100644 index 0000000000..36e9f5f5f6 --- /dev/null +++ b/Silicon/Hisilicon/Include/Library/I2CLib.h @@ -0,0 +1,73 @@ +/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#ifndef _I2C_LIB_H_
+#define _I2C_LIB_H_
+
+//I2C0 or I2C1
+typedef enum {
+ DEVICE_TYPE_SPD = 0,
+ DEVICE_TYPE_E2PROM,
+ DEVICE_TYPE_CPLD_3BYTE_OPERANDS,
+ DEVICE_TYPE_CPLD_4BYTE_OPERANDS
+}I2C_DEVICE_TYPE;
+
+
+typedef enum {
+ Normal = 0,
+ Fast,
+ SPEED_MODE_MAX
+}SPEED_MODE;
+
+
+#define I2C_PORT_MAX 10
+
+
+
+typedef struct {
+ UINT32 Socket;
+ UINT32 Port;
+ I2C_DEVICE_TYPE DeviceType;
+ UINT32 SlaveDeviceAddress;
+}I2C_DEVICE;
+
+
+UINTN
+EFIAPI
+I2CInit(UINT32 Socket, UINT32 Port, SPEED_MODE SpeedMode);
+
+EFI_STATUS
+EFIAPI
+I2CWrite(I2C_DEVICE *I2cInfo, UINT16 InfoOffset, UINT32 ulLength, UINT8 *pBuf);
+
+EFI_STATUS
+EFIAPI
+I2CRead(I2C_DEVICE *I2cInfo, UINT16 InfoOffset,UINT32 ulRxLen,UINT8 *pBuf);
+
+EFI_STATUS
+EFIAPI
+I2CWriteMultiByte(I2C_DEVICE *I2cInfo, UINT32 InfoOffset, UINT32 ulLength, UINT8 *pBuf);
+
+EFI_STATUS
+EFIAPI
+I2CReadMultiByte(I2C_DEVICE *I2cInfo, UINT32 InfoOffset,UINT32 ulRxLen,UINT8 *pBuf);
+
+EFI_STATUS
+EFIAPI
+I2CSdaConfig(UINT32 Socket, UINT32 Port);
+
+
+#endif
diff --git a/Silicon/Hisilicon/Include/Library/IpmiCmdLib.h b/Silicon/Hisilicon/Include/Library/IpmiCmdLib.h new file mode 100644 index 0000000000..8868b76135 --- /dev/null +++ b/Silicon/Hisilicon/Include/Library/IpmiCmdLib.h @@ -0,0 +1,94 @@ +/** @file
+*
+* Copyright (c) 2017, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2017, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _IPMI_CMD_LIB_H_
+#define _IPMI_CMD_LIB_H_
+
+#define BOOT_OPTION_BOOT_FLAG_VALID 1
+#define BOOT_OPTION_BOOT_FLAG_INVALID 0
+
+typedef enum {
+ NoOverride = 0x0,
+ ForcePxe,
+ ForceDefaultHardDisk,
+ ForceDefaultHardDiskSafeMode,
+ ForceDefaultDiagnosticPartition,
+ ForceDefaultCD,
+ ForceSetupUtility,
+ ForceRemoteRemovableMedia,
+ ForceRemoteCD,
+ ForcePrimaryRemoteMedia,
+ ForceRemoteHardDisk = 0xB,
+ ForcePrimaryRemovableMedia = 0xF
+} BOOT_DEVICE_SELECTOR;
+
+//
+// Get System Boot Option data structure
+//
+typedef struct {
+ UINT8 ParameterVersion :4;
+ UINT8 Reserved1 :4;
+ UINT8 ParameterSelector :7;
+ UINT8 ParameterValid :1;
+ //
+ // Boot Flags Data 1
+ //
+ UINT8 Reserved2 :5;
+ UINT8 BiosBootType :1;
+ UINT8 Persistent :1;
+ UINT8 BootFlagsValid :1;
+ //
+ // Boot Flags Data 2
+ //
+ UINT8 LockResetBtn :1;
+ UINT8 ScreenBlank :1;
+ UINT8 BootDeviceSelector :4;
+ UINT8 LockKeyboard :1;
+ UINT8 ClearCmos :1;
+ //
+ // Boot Flags Data 3
+ //
+ UINT8 ConsoleRedirectionControl :2;
+ UINT8 LockSleepBtn :1;
+ UINT8 UserPasswordByPass :1;
+ UINT8 Reserved3 :1;
+ UINT8 FirmwareVerbosity :2;
+ UINT8 LockPowerBtn :1;
+ //
+ // Boot Flags Data 4
+ //
+ UINT8 MuxControlOverride :3;
+ UINT8 ShareModeOverride :1;
+ UINT8 Reserved4 :4;
+ //
+ // Boot Flags Data 5
+ //
+ UINT8 DeviceInstanceSelector :5;
+ UINT8 Reserved5 :3;
+} IPMI_GET_BOOT_OPTION;
+
+EFI_STATUS
+EFIAPI
+IpmiCmdSetSysBootOptions (
+ OUT IPMI_GET_BOOT_OPTION *BootOption
+ );
+
+EFI_STATUS
+EFIAPI
+IpmiCmdGetSysBootOptions (
+ IN IPMI_GET_BOOT_OPTION *BootOption
+ );
+
+#endif
diff --git a/Silicon/Hisilicon/Include/Library/LpcLib.h b/Silicon/Hisilicon/Include/Library/LpcLib.h new file mode 100755 index 0000000000..236a52ba45 --- /dev/null +++ b/Silicon/Hisilicon/Include/Library/LpcLib.h @@ -0,0 +1,113 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _LPC_LIB_H_
+#define _LPC_LIB_H_
+
+#include <Uefi.h>
+
+#define PCIE_SUBSYS_IO_MUX 0xA0170000
+#define PCIE_SUBSYS_IOMG033 (PCIE_SUBSYS_IO_MUX + 0x84)
+#define PCIE_SUBSYS_IOMG035 (PCIE_SUBSYS_IO_MUX + 0x8C)
+#define PCIE_SUBSYS_IOMG036 (PCIE_SUBSYS_IO_MUX + 0x90)
+#define PCIE_SUBSYS_IOMG045 (PCIE_SUBSYS_IO_MUX + 0xB4)
+#define PCIE_SUBSYS_IOMG046 (PCIE_SUBSYS_IO_MUX + 0xB8)
+#define PCIE_SUBSYS_IOMG047 (PCIE_SUBSYS_IO_MUX + 0xBC)
+#define PCIE_SUBSYS_IOMG048 (PCIE_SUBSYS_IO_MUX + 0xC0)
+#define PCIE_SUBSYS_IOMG049 (PCIE_SUBSYS_IO_MUX + 0xC4)
+#define PCIE_SUBSYS_IOMG050 (PCIE_SUBSYS_IO_MUX + 0xC8)
+
+#define IO_WRAP_CTRL_BASE 0xA0100000
+#define SC_LPC_CLK_EN_REG (IO_WRAP_CTRL_BASE + 0x03a0)
+#define SC_LPC_CLK_DIS_REG (IO_WRAP_CTRL_BASE + 0x03a4)
+#define SC_LPC_BUS_CLK_EN_REG (IO_WRAP_CTRL_BASE + 0x03a8)
+#define SC_LPC_BUS_CLK_DIS_REG (IO_WRAP_CTRL_BASE + 0x03ac)
+#define SC_LPC_RESET_REQ (IO_WRAP_CTRL_BASE + 0x0ad8)
+#define SC_LPC_RESET_DREQ (IO_WRAP_CTRL_BASE + 0x0adc)
+#define SC_LPC_BUS_RESET_REQ (IO_WRAP_CTRL_BASE + 0x0ae0)
+#define SC_LPC_BUS_RESET_DREQ (IO_WRAP_CTRL_BASE + 0x0ae4)
+#define SC_LPC_CTRL_REG (IO_WRAP_CTRL_BASE + 0x2028)
+
+
+#define LPC_BASE 0xA01B0000
+#define LPC_START_REG (LPC_BASE + 0x00)
+#define LPC_OP_STATUS_REG (LPC_BASE + 0x04)
+#define LPC_IRQ_ST_REG (LPC_BASE + 0x08)
+#define LPC_OP_LEN_REG (LPC_BASE + 0x10)
+#define LPC_CMD_REG (LPC_BASE + 0x14)
+#define LPC_FWH_ID_MSIZE_REG (LPC_BASE + 0x18)
+#define LPC_ADDR_REG (LPC_BASE + 0x20)
+#define LPC_WDATA_REG (LPC_BASE + 0x24)
+#define LPC_RDATA_REG (LPC_BASE + 0x28)
+#define LPC_LONG_CNT_REG (LPC_BASE + 0x30)
+#define LPC_TX_FIFO_ST_REG (LPC_BASE + 0x50)
+#define LPC_RX_FIFO_ST_REG (LPC_BASE + 0x54)
+#define LPC_TIME_OUT_REG (LPC_BASE + 0x58)
+#define LPC_SIRQ_CTRL0_REG (LPC_BASE + 0x80)
+#define LPC_SIRQ_CTRL1_REG (LPC_BASE + 0x84)
+#define LPC_SIRQ_INT_REG (LPC_BASE + 0x90)
+#define LPC_SIRQ_INT_MASK_REG (LPC_BASE + 0x94)
+#define LPC_SIRQ_STAT_REG (LPC_BASE + 0xA0)
+
+#define LPC_FIFO_LEN (16)
+
+typedef enum{
+ LPC_ADDR_MODE_INCREASE,
+ LPC_ADDR_MODE_SINGLE
+}LPC_ADDR_MODE;
+
+typedef enum{
+ LPC_TYPE_IO,
+ LPC_TYPE_MEM,
+ LPC_TYPE_FWH
+}LPC_TYPE;
+
+
+typedef union {
+ struct{
+ UINT32 lpc_wr:1;
+ UINT32 lpc_type:2;
+ UINT32 same_addr:1;
+ UINT32 resv:28;
+ }bits;
+ UINT32 u32;
+}LPC_CMD_STRUCT;
+
+typedef union {
+ struct{
+ UINT32 op_len:5;
+ UINT32 resv:27;
+ }bits;
+ UINT32 u32;
+}LPC_OP_LEN_STRUCT;
+
+
+VOID LpcInit(VOID);
+BOOLEAN LpcIdle(VOID);
+EFI_STATUS LpcByteWrite(
+ IN UINT32 Addr,
+ IN UINT8 Data);
+EFI_STATUS LpcByteRead(
+ IN UINT32 Addr,
+ IN OUT UINT8 *Data);
+
+EFI_STATUS LpcWrite(
+ IN UINT32 Addr,
+ IN UINT8 *Data,
+ IN UINT8 Len);
+
+#endif
+
+
diff --git a/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h b/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h new file mode 100644 index 0000000000..21498b7056 --- /dev/null +++ b/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h @@ -0,0 +1,37 @@ +/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _OEM_ADDRESS_MAP_LIB_H_
+#define _OEM_ADDRESS_MAP_LIB_H_
+
+typedef struct _DDRC_BASE_ID{
+ UINTN Base;
+ UINTN Id;
+}DDRC_BASE_ID;
+
+// Invalid address, will cause exception when accessed by bug code
+#define ADDRESS_MAP_INVALID ((UINTN)(-1))
+
+UINTN OemGetPoeSubBase (UINT32 NodeId);
+UINTN OemGetPeriSubBase (UINT32 NodeId);
+UINTN OemGetAlgSubBase (UINT32 NodeId);
+UINTN OemGetM3SubBase (UINT32 NodeId);
+
+VOID OemAddressMapInit(VOID);
+
+extern DDRC_BASE_ID DdrcBaseId[MAX_SOCKET][MAX_CHANNEL];
+
+#endif
+
diff --git a/Silicon/Hisilicon/Include/Library/OemMiscLib.h b/Silicon/Hisilicon/Include/Library/OemMiscLib.h new file mode 100644 index 0000000000..6f18c0fa72 --- /dev/null +++ b/Silicon/Hisilicon/Include/Library/OemMiscLib.h @@ -0,0 +1,51 @@ +/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#ifndef _OEM_MISC_LIB_H_
+#define _OEM_MISC_LIB_H_
+
+#include <Uefi.h>
+
+#include <PlatformArch.h>
+#include <Library/I2CLib.h>
+
+#define PCIEDEVICE_REPORT_MAX 4
+typedef struct _REPORT_PCIEDIDVID2BMC{
+ UINTN Bus;
+ UINTN Device;
+ UINTN Function;
+ UINTN Slot;
+}REPORT_PCIEDIDVID2BMC;
+extern REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX];
+
+BOOLEAN OemIsSocketPresent (UINTN Socket);
+VOID CoreSelectBoot(VOID);
+VOID OemPcieResetAndOffReset(void);
+extern I2C_DEVICE gDS3231RtcDevice;
+
+UINTN OemGetSocketNumber(VOID);
+UINTN OemGetDdrChannel (VOID);
+UINTN OemGetDimmSlot(UINTN Socket, UINTN Channel);
+
+BOOLEAN OemIsMpBoot();
+UINT32 OemIsWarmBoot();
+
+VOID OemBiosSwitch(UINT32 Master);
+BOOLEAN OemIsNeedDisableExpanderBuffer(VOID);
+
+extern EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM];
+EFI_HII_HANDLE EFIAPI OemGetPackages ();
+#endif
diff --git a/Silicon/Hisilicon/Include/Library/OemSetVirtualMapDesc.h b/Silicon/Hisilicon/Include/Library/OemSetVirtualMapDesc.h new file mode 100644 index 0000000000..da9a720bb9 --- /dev/null +++ b/Silicon/Hisilicon/Include/Library/OemSetVirtualMapDesc.h @@ -0,0 +1,26 @@ +/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _OEM_SET_VIRTUAL_MAP_DESC_H_
+#define _OEM_SET_VIRTUAL_MAP_DESC_H_
+
+
+UINTN OemSetVirtualMapDesc (
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable,
+ ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes
+ );
+
+#endif
+
diff --git a/Silicon/Hisilicon/Include/Library/PlatformPciLib.h b/Silicon/Hisilicon/Include/Library/PlatformPciLib.h new file mode 100644 index 0000000000..9d28fec375 --- /dev/null +++ b/Silicon/Hisilicon/Include/Library/PlatformPciLib.h @@ -0,0 +1,209 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _PLATFORM_PCI_LIB_H_
+#define _PLATFORM_PCI_LIB_H_
+
+#define PCIE_MAX_HOSTBRIDGE 2
+#define PCIE_MAX_ROOTBRIDGE 8
+//The extern pcie addresses will be initialized by oemmisclib
+extern UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE];
+extern UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE];
+extern UINT64 PCIE_PHY_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE];
+extern UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE];
+
+
+#define PCI_HB0RB0_PCI_BASE FixedPcdGet64(PciHb0Rb0Base)
+#define PCI_HB0RB1_PCI_BASE FixedPcdGet64(PciHb0Rb1Base)
+#define PCI_HB0RB2_PCI_BASE FixedPcdGet64(PciHb0Rb2Base)
+#define PCI_HB0RB3_PCI_BASE FixedPcdGet64(PciHb0Rb3Base)
+#define PCI_HB0RB4_PCI_BASE FixedPcdGet64(PciHb0Rb4Base)
+#define PCI_HB0RB5_PCI_BASE FixedPcdGet64(PciHb0Rb5Base)
+#define PCI_HB0RB6_PCI_BASE FixedPcdGet64(PciHb0Rb6Base)
+#define PCI_HB0RB7_PCI_BASE FixedPcdGet64(PciHb0Rb7Base)
+
+#define PCI_HB1RB0_PCI_BASE FixedPcdGet64(PciHb1Rb0Base)
+#define PCI_HB1RB1_PCI_BASE FixedPcdGet64(PciHb1Rb1Base)
+#define PCI_HB1RB2_PCI_BASE FixedPcdGet64(PciHb1Rb2Base)
+#define PCI_HB1RB3_PCI_BASE FixedPcdGet64(PciHb1Rb3Base)
+#define PCI_HB1RB4_PCI_BASE FixedPcdGet64(PciHb1Rb4Base)
+#define PCI_HB1RB5_PCI_BASE FixedPcdGet64(PciHb1Rb5Base)
+#define PCI_HB1RB6_PCI_BASE FixedPcdGet64(PciHb1Rb6Base)
+#define PCI_HB1RB7_PCI_BASE FixedPcdGet64(PciHb1Rb7Base)
+
+#define PCI_HB0RB0_ECAM_BASE FixedPcdGet64 (PcdHb0Rb0PciConfigurationSpaceBaseAddress)
+#define PCI_HB0RB0_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb0PciConfigurationSpaceSize)
+#define PCI_HB0RB1_ECAM_BASE FixedPcdGet64 (PcdHb0Rb1PciConfigurationSpaceBaseAddress)
+#define PCI_HB0RB1_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb1PciConfigurationSpaceSize)
+#define PCI_HB0RB2_ECAM_BASE FixedPcdGet64 (PcdHb0Rb2PciConfigurationSpaceBaseAddress)
+#define PCI_HB0RB2_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb2PciConfigurationSpaceSize)
+#define PCI_HB0RB3_ECAM_BASE FixedPcdGet64 (PcdHb0Rb3PciConfigurationSpaceBaseAddress)
+#define PCI_HB0RB3_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb3PciConfigurationSpaceSize)
+#define PCI_HB0RB4_ECAM_BASE FixedPcdGet64 (PcdHb0Rb4PciConfigurationSpaceBaseAddress)
+#define PCI_HB0RB4_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb4PciConfigurationSpaceSize)
+#define PCI_HB0RB5_ECAM_BASE FixedPcdGet64 (PcdHb0Rb5PciConfigurationSpaceBaseAddress)
+#define PCI_HB0RB5_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb5PciConfigurationSpaceSize)
+#define PCI_HB0RB6_ECAM_BASE FixedPcdGet64 (PcdHb0Rb6PciConfigurationSpaceBaseAddress)
+#define PCI_HB0RB6_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb6PciConfigurationSpaceSize)
+#define PCI_HB0RB7_ECAM_BASE FixedPcdGet64 (PcdHb0Rb7PciConfigurationSpaceBaseAddress)
+#define PCI_HB0RB7_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb7PciConfigurationSpaceSize)
+
+#define PCI_HB1RB0_ECAM_BASE FixedPcdGet64 (PcdHb1Rb0PciConfigurationSpaceBaseAddress)
+#define PCI_HB1RB0_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb0PciConfigurationSpaceSize)
+#define PCI_HB1RB1_ECAM_BASE FixedPcdGet64 (PcdHb1Rb1PciConfigurationSpaceBaseAddress)
+#define PCI_HB1RB1_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb1PciConfigurationSpaceSize)
+#define PCI_HB1RB2_ECAM_BASE FixedPcdGet64 (PcdHb1Rb2PciConfigurationSpaceBaseAddress)
+#define PCI_HB1RB2_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb2PciConfigurationSpaceSize)
+#define PCI_HB1RB3_ECAM_BASE FixedPcdGet64 (PcdHb1Rb3PciConfigurationSpaceBaseAddress)
+#define PCI_HB1RB3_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb3PciConfigurationSpaceSize)
+#define PCI_HB1RB4_ECAM_BASE FixedPcdGet64 (PcdHb1Rb4PciConfigurationSpaceBaseAddress)
+#define PCI_HB1RB4_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb4PciConfigurationSpaceSize)
+#define PCI_HB1RB5_ECAM_BASE FixedPcdGet64 (PcdHb1Rb5PciConfigurationSpaceBaseAddress)
+#define PCI_HB1RB5_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb5PciConfigurationSpaceSize)
+#define PCI_HB1RB6_ECAM_BASE FixedPcdGet64 (PcdHb1Rb6PciConfigurationSpaceBaseAddress)
+#define PCI_HB1RB6_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb6PciConfigurationSpaceSize)
+#define PCI_HB1RB7_ECAM_BASE FixedPcdGet64 (PcdHb1Rb7PciConfigurationSpaceBaseAddress)
+#define PCI_HB1RB7_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb7PciConfigurationSpaceSize)
+
+#define PCI_HB0RB0_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb0PciRegionBaseAddress))
+#define PCI_HB0RB0_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb0PciRegionSize))
+#define PCI_HB0RB1_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb1PciRegionBaseAddress))
+#define PCI_HB0RB1_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb1PciRegionSize))
+#define PCI_HB0RB2_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb2PciRegionBaseAddress))
+#define PCI_HB0RB2_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb2PciRegionSize))
+#define PCI_HB0RB3_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb3PciRegionBaseAddress))
+#define PCI_HB0RB3_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb3PciRegionSize))
+#define PCI_HB0RB4_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb4PciRegionBaseAddress))
+#define PCI_HB0RB4_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb4PciRegionSize))
+#define PCI_HB0RB5_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb5PciRegionBaseAddress))
+#define PCI_HB0RB5_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb5PciRegionSize))
+#define PCI_HB0RB6_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb6PciRegionBaseAddress))
+#define PCI_HB0RB6_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb6PciRegionSize))
+#define PCI_HB0RB7_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb7PciRegionBaseAddress))
+#define PCI_HB0RB7_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb7PciRegionSize))
+
+#define PCI_HB1RB0_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb0PciRegionBaseAddress))
+#define PCI_HB1RB0_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb0PciRegionSize))
+#define PCI_HB1RB1_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb1PciRegionBaseAddress))
+#define PCI_HB1RB1_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb1PciRegionSize))
+#define PCI_HB1RB2_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb2PciRegionBaseAddress))
+#define PCI_HB1RB2_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb2PciRegionSize))
+#define PCI_HB1RB3_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb3PciRegionBaseAddress))
+#define PCI_HB1RB3_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb3PciRegionSize))
+#define PCI_HB1RB4_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb4PciRegionBaseAddress))
+#define PCI_HB1RB4_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb4PciRegionSize))
+#define PCI_HB1RB5_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb5PciRegionBaseAddress))
+#define PCI_HB1RB5_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb5PciRegionSize))
+#define PCI_HB1RB6_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb6PciRegionBaseAddress))
+#define PCI_HB1RB6_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb6PciRegionSize))
+#define PCI_HB1RB7_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb7PciRegionBaseAddress))
+#define PCI_HB1RB7_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb7PciRegionSize))
+
+
+#define PCI_HB0RB0_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb0CpuMemRegionBase))
+#define PCI_HB0RB1_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb1CpuMemRegionBase))
+#define PCI_HB0RB2_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb2CpuMemRegionBase))
+#define PCI_HB0RB3_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb3CpuMemRegionBase))
+#define PCI_HB0RB4_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb4CpuMemRegionBase))
+#define PCI_HB0RB5_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb5CpuMemRegionBase))
+#define PCI_HB0RB6_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb6CpuMemRegionBase))
+#define PCI_HB0RB7_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb7CpuMemRegionBase))
+
+#define PCI_HB1RB0_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb0CpuMemRegionBase))
+#define PCI_HB1RB1_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb1CpuMemRegionBase))
+#define PCI_HB1RB2_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb2CpuMemRegionBase))
+#define PCI_HB1RB3_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb3CpuMemRegionBase))
+#define PCI_HB1RB4_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb4CpuMemRegionBase))
+#define PCI_HB1RB5_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb5CpuMemRegionBase))
+#define PCI_HB1RB6_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb6CpuMemRegionBase))
+#define PCI_HB1RB7_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb7CpuMemRegionBase))
+
+
+#define PCI_HB0RB0_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb0CpuIoRegionBase))
+#define PCI_HB0RB1_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb1CpuIoRegionBase))
+#define PCI_HB0RB2_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb2CpuIoRegionBase))
+#define PCI_HB0RB3_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb3CpuIoRegionBase))
+#define PCI_HB0RB4_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb4CpuIoRegionBase))
+#define PCI_HB0RB5_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb5CpuIoRegionBase))
+#define PCI_HB0RB6_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb6CpuIoRegionBase))
+#define PCI_HB0RB7_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb7CpuIoRegionBase))
+
+#define PCI_HB1RB0_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb0CpuIoRegionBase))
+#define PCI_HB1RB1_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb1CpuIoRegionBase))
+#define PCI_HB1RB2_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb2CpuIoRegionBase))
+#define PCI_HB1RB3_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb3CpuIoRegionBase))
+#define PCI_HB1RB4_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb4CpuIoRegionBase))
+#define PCI_HB1RB5_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb5CpuIoRegionBase))
+#define PCI_HB1RB6_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb6CpuIoRegionBase))
+#define PCI_HB1RB7_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb7CpuIoRegionBase))
+
+
+
+#define PCI_HB0RB0_IO_BASE (FixedPcdGet64 (PcdHb0Rb0IoBase))
+#define PCI_HB0RB1_IO_BASE (FixedPcdGet64 (PcdHb0Rb1IoBase))
+#define PCI_HB0RB2_IO_BASE (FixedPcdGet64 (PcdHb0Rb2IoBase))
+#define PCI_HB0RB3_IO_BASE (FixedPcdGet64 (PcdHb0Rb3IoBase))
+#define PCI_HB0RB4_IO_BASE (FixedPcdGet64 (PcdHb0Rb4IoBase))
+#define PCI_HB0RB5_IO_BASE (FixedPcdGet64 (PcdHb0Rb5IoBase))
+#define PCI_HB0RB6_IO_BASE (FixedPcdGet64 (PcdHb0Rb6IoBase))
+#define PCI_HB0RB7_IO_BASE (FixedPcdGet64 (PcdHb0Rb7IoBase))
+
+#define PCI_HB1RB0_IO_BASE (FixedPcdGet64 (PcdHb1Rb0IoBase))
+#define PCI_HB1RB1_IO_BASE (FixedPcdGet64 (PcdHb1Rb1IoBase))
+#define PCI_HB1RB2_IO_BASE (FixedPcdGet64 (PcdHb1Rb2IoBase))
+#define PCI_HB1RB3_IO_BASE (FixedPcdGet64 (PcdHb1Rb3IoBase))
+#define PCI_HB1RB4_IO_BASE (FixedPcdGet64 (PcdHb1Rb4IoBase))
+#define PCI_HB1RB5_IO_BASE (FixedPcdGet64 (PcdHb1Rb5IoBase))
+#define PCI_HB1RB6_IO_BASE (FixedPcdGet64 (PcdHb1Rb6IoBase))
+#define PCI_HB1RB7_IO_BASE (FixedPcdGet64 (PcdHb1Rb7IoBase))
+
+#define PCI_HB0RB0_IO_SIZE (FixedPcdGet64 (PcdHb0Rb0IoSize))
+#define PCI_HB0RB1_IO_SIZE (FixedPcdGet64 (PcdHb0Rb1IoSize))
+#define PCI_HB0RB2_IO_SIZE (FixedPcdGet64 (PcdHb0Rb2IoSize))
+#define PCI_HB0RB3_IO_SIZE (FixedPcdGet64 (PcdHb0Rb3IoSize))
+#define PCI_HB0RB4_IO_SIZE (FixedPcdGet64 (PcdHb0Rb4IoSize))
+#define PCI_HB0RB5_IO_SIZE (FixedPcdGet64 (PcdHb0Rb5IoSize))
+#define PCI_HB0RB6_IO_SIZE (FixedPcdGet64 (PcdHb0Rb6IoSize))
+#define PCI_HB0RB7_IO_SIZE (FixedPcdGet64 (PcdHb0Rb7IoSize))
+
+#define PCI_HB1RB0_IO_SIZE (FixedPcdGet64 (PcdHb1Rb0IoSize))
+#define PCI_HB1RB1_IO_SIZE (FixedPcdGet64 (PcdHb1Rb1IoSize))
+#define PCI_HB1RB2_IO_SIZE (FixedPcdGet64 (PcdHb1Rb2IoSize))
+#define PCI_HB1RB3_IO_SIZE (FixedPcdGet64 (PcdHb1Rb3IoSize))
+#define PCI_HB1RB4_IO_SIZE (FixedPcdGet64 (PcdHb1Rb4IoSize))
+#define PCI_HB1RB5_IO_SIZE (FixedPcdGet64 (PcdHb1Rb5IoSize))
+#define PCI_HB1RB6_IO_SIZE (FixedPcdGet64 (PcdHb1Rb6IoSize))
+#define PCI_HB1RB7_IO_SIZE (FixedPcdGet64 (PcdHb1Rb7IoSize))
+
+
+
+typedef struct {
+ UINT64 Ecam;
+ UINT64 BusBase;
+ UINT64 BusLimit;
+ UINT64 MemBase;
+ UINT64 MemLimit;
+ UINT64 IoBase;
+ UINT64 IoLimit;
+ UINT64 CpuMemRegionBase;
+ UINT64 CpuIoRegionBase;
+ UINT64 RbPciBar;
+ UINT64 PciRegionBase;
+ UINT64 PciRegionLimit;
+} PCI_ROOT_BRIDGE_RESOURCE_APPETURE;
+
+extern PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE];
+#endif
+
diff --git a/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h b/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h new file mode 100644 index 0000000000..ec2b9a36e7 --- /dev/null +++ b/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h @@ -0,0 +1,106 @@ +/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _PLATFORM_SYS_CTRL_LIB_H_
+#define _PLATFORM_SYS_CTRL_LIB_H_
+
+#define PACKAGE_16CORE 0
+#define PACKAGE_32CORE 1
+#define PACKAGE_RESERVED 2
+#define PACKAGE_TYPE_NUM 3
+
+UINT32 PlatformGetPackageType (VOID);
+
+VOID DisplayCpuInfo (VOID);
+UINT32 CheckChipIsEc(VOID);
+
+UINTN PlatformGetPll (UINT32 NodeId, UINTN Pll);
+
+#define DJTAG_READ_INVALID_VALUE 0xFFFFFFFF
+#define DJTAG_CHAIN_ID_AA 1
+#define DJTAG_CHAIN_ID_LLC 4
+
+
+#define SC_DJTAG_MSTR_EN_OFFSET 0x6800
+#define SC_DJTAG_MSTR_START_EN_OFFSET 0x6804
+#define SC_DJTAG_SEC_ACC_EN_OFFSET 0x6808
+#define SC_DJTAG_DEBUG_MODULE_SEL_OFFSET 0x680C
+#define SC_DJTAG_MSTR_WR_OFFSET 0x6810
+#define SC_DJTAG_CHAIN_UNIT_CFG_EN_OFFSET 0x6814
+#define SC_DJTAG_MSTR_ADDR_OFFSET 0x6818
+#define SC_DJTAG_MSTR_DATA_OFFSET 0x681C
+#define SC_DJTAG_TMOUT_OFFSET 0x6820
+#define SC_TDRE_OP_ADDR_OFFSET 0x6824
+#define SC_TDRE_WDATA_OFFSET 0x6828
+#define SC_TDRE_REPAIR_EN_OFFSET 0x682C
+#define SC_DJTAG_RD_DATA0_OFFSET 0xE800
+#define SC_TDRE_RDATA0_OFFSET 0xE830
+
+
+UINTN PlatformGetI2cBase(UINT32 Socket,UINT8 Port);
+
+VOID PlatformAddressMapCleanUp (VOID);
+VOID PlatformDisableDdrWindow (VOID);
+
+VOID PlatformEnableArchTimer (VOID);
+
+EFI_STATUS
+DawFindFreeWindow (UINTN Socket, UINTN *DawIndex);
+
+VOID DawSetWindow (UINTN Socket, UINTN WindowIndex, UINT32 Value);
+
+VOID DJTAG_TDRE_WRITE(UINT32 Offset, UINT32 Value, UINT32 ChainID, UINT32 NodeId, BOOLEAN Repair);
+
+UINT32 DJTAG_TDRE_READ(UINT32 Offset, UINT32 ChainID, UINT32 NodeId, BOOLEAN Repair);
+
+VOID RemoveRoceReset(VOID);
+
+UINTN PlatformGetDdrChannel (VOID);
+
+VOID ITSCONFIG (VOID);
+
+VOID MN_CONFIG (VOID);
+
+VOID SmmuConfigForOS (VOID);
+VOID SmmuConfigForBios (VOID);
+
+VOID StartupAp (VOID);
+
+VOID LlcCleanInvalidate (VOID);
+
+UINTN PlatformGetCpuFreq (UINT8 Socket);
+VOID ClearInterruptStatus(VOID);
+
+UINTN PlatformGetCoreCount (VOID);
+VOID DAWConfigEn(UINT32 socket);
+
+VOID DResetUsb ();
+UINT32 PlatformGetEhciBase ();
+UINT32 PlatformGetOhciBase ();
+VOID PlatformPllInit();
+// PLL initialization for super IO clusters.
+VOID SiclPllInit(UINT32 SclId);
+VOID PlatformDeviceDReset();
+VOID PlatformGicdInit();
+VOID PlatformLpcInit();
+// Synchronize architecture timer counter between different super computing
+// clusters.
+VOID PlatformArchTimerSynchronize(VOID);
+VOID PlatformEventBroadcastConfig(VOID);
+UINTN GetDjtagRegBase(UINT32 NodeId);
+VOID LlcCleanInvalidateAsm(VOID);
+VOID PlatformMdioInit(VOID);
+
+#endif
diff --git a/Silicon/Hisilicon/Include/PlatformArch.h b/Silicon/Hisilicon/Include/PlatformArch.h new file mode 100644 index 0000000000..45995c5893 --- /dev/null +++ b/Silicon/Hisilicon/Include/PlatformArch.h @@ -0,0 +1,35 @@ +/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+
+#ifndef _PLATFORM_ARCH_H_
+#define _PLATFORM_ARCH_H_
+
+#define MAX_SOCKET 2
+#define MAX_DIE 4
+#define MAX_DDRC 2
+#define MAX_NODE (MAX_SOCKET * MAX_DIE)
+#define MAX_CHANNEL 4
+#define MAX_DIMM 3
+#define MAX_RANK_CH 12
+#define MAX_RANK_DIMM 4
+// Max NUMA node number for each node type
+#define MAX_NUM_PER_TYPE 8
+
+#define S1_BASE 0x40000000000
+
+#endif
+
diff --git a/Silicon/Hisilicon/Include/Protocol/HisiBoardNicProtocol.h b/Silicon/Hisilicon/Include/Protocol/HisiBoardNicProtocol.h new file mode 100644 index 0000000000..8a9d13c9e7 --- /dev/null +++ b/Silicon/Hisilicon/Include/Protocol/HisiBoardNicProtocol.h @@ -0,0 +1,61 @@ +/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _HISI_BOARD_NIC_PROTOCOL_H_
+#define _HISI_BOARD_NIC_PROTOCOL_H_
+
+#define HISI_BOARD_NIC_PROTOCOL_GUID \
+ { 0xb5903955, 0x31e9, 0x4aaf, { 0xb2, 0x83, 0x7, 0x9f, 0x3c, 0xc4, 0x71, 0x66 } }
+
+#define HISI_BOARD_XGE_STATUS_PROTOCOL_GUID \
+ { 0xa6b8ed0e, 0xd8cc, 0x4853, { 0xaa, 0x39, 0x2c, 0x3e, 0xcd, 0x7c, 0xa5, 0x97 } }
+
+typedef
+EFI_STATUS
+(EFIAPI *HISI_BOARD_NIC_GET_MAC_ADDRESS) (
+ IN OUT EFI_MAC_ADDRESS *Mac,
+ IN UINTN Port
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *HISI_BOARD_NIC_SET_MAC_ADDRESS) (
+ IN EFI_MAC_ADDRESS *Mac,
+ IN UINTN Port
+ );
+
+typedef struct {
+ HISI_BOARD_NIC_GET_MAC_ADDRESS GetMac;
+ HISI_BOARD_NIC_SET_MAC_ADDRESS SetMac;
+} HISI_BOARD_NIC_PROTOCOL;
+
+typedef
+VOID
+(*HISI_BOARD_FEEDBACK_XGE_STATUS) (
+ BOOLEAN IsLinkup,
+ BOOLEAN IsActOK,
+ UINT32 port
+ );
+
+typedef struct {
+ HISI_BOARD_FEEDBACK_XGE_STATUS FeedbackXgeStatus;
+} HISI_BOARD_XGE_STATUS_PROTOCOL;
+
+
+extern EFI_GUID gHisiBoardNicProtocolGuid;
+extern EFI_GUID gHisiBoardXgeStatusProtocolGuid;
+
+
+#endif
diff --git a/Silicon/Hisilicon/Include/Protocol/HisiSpiFlashProtocol.h b/Silicon/Hisilicon/Include/Protocol/HisiSpiFlashProtocol.h new file mode 100644 index 0000000000..b7ed9ceb35 --- /dev/null +++ b/Silicon/Hisilicon/Include/Protocol/HisiSpiFlashProtocol.h @@ -0,0 +1,66 @@ +/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#ifndef _HISI_SPI_FLASH_PROTOCOL_H_
+#define _HISI_SPI_FLASH_PROTOCOL_H_
+
+typedef struct _HISI_SPI_FLASH_PROTOCOL HISI_SPI_FLASH_PROTOCOL;
+
+typedef
+EFI_STATUS
+(EFIAPI *HISI_SPI_FLASH_ERASE_INTERFACE) (
+ IN HISI_SPI_FLASH_PROTOCOL *This,
+ IN UINT32 Offset,
+ IN UINT32 ulLength
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *HISI_SPI_FLASH_WRITE_INTERFACE) (
+ IN HISI_SPI_FLASH_PROTOCOL *This,
+ IN UINT32 Offset,
+ IN UINT8 *Buffer,
+ IN UINT32 ulLength
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *HISI_SPI_FLASH_READ_INTERFACE) (
+ IN HISI_SPI_FLASH_PROTOCOL *This,
+ IN UINT32 Offset,
+ IN OUT UINT8 *Buffer,
+ IN UINT32 ulLength
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *HISI_SPI_FLASH_ERASE_WRITE_INTERFACE) (
+ IN HISI_SPI_FLASH_PROTOCOL *This,
+ IN UINT32 Offset,
+ IN UINT8 *Buffer,
+ IN UINT32 ulLength
+ );
+
+struct _HISI_SPI_FLASH_PROTOCOL {
+ HISI_SPI_FLASH_ERASE_INTERFACE Erase;
+ HISI_SPI_FLASH_WRITE_INTERFACE Write;
+ HISI_SPI_FLASH_READ_INTERFACE Read;
+ HISI_SPI_FLASH_ERASE_WRITE_INTERFACE EraseWrite;
+};
+
+extern EFI_GUID gHisiSpiFlashProtocolGuid;
+
+#endif
diff --git a/Silicon/Hisilicon/Include/Protocol/IpmiInterfaceProtocol.h b/Silicon/Hisilicon/Include/Protocol/IpmiInterfaceProtocol.h new file mode 100644 index 0000000000..c5f0f8551c --- /dev/null +++ b/Silicon/Hisilicon/Include/Protocol/IpmiInterfaceProtocol.h @@ -0,0 +1,99 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _IPMI_INTERFACE_PROTOCOL_H_
+#define _IPMI_INTERFACE_PROTOCOL_H_
+
+#define IPMI_INTERFACE_PROTOCOL_GUID \
+ {0xa37e200e, 0xda90, 0x473b, {0x8b, 0xb5, 0x1d, 0x7b, 0x11, 0xba, 0x32, 0x33}}
+
+typedef struct _IPMI_INTERFACE_PROTOCOL IPMI_INTERFACE_PROTOCOL;
+
+//
+// Structure to store IPMI Network Function, LUN and command
+//
+typedef struct {
+ UINT8 Lun : 2;
+ UINT8 NetFn : 6;
+ UINT8 Cmd;
+} IPMI_CMD_HEADER;
+
+//
+// System Interface Type
+//
+typedef enum {
+ IPMI_SYSTEM_INTERFACE_UNKNOWN,
+ IPMI_SYSTEM_INTERFACE_KCS,
+ IPMI_SYSTEM_INTERFACE_SMIC,
+ IPMI_SYSTEM_INTERFACE_BT,
+ IPMI_SYSTEM_INTERFACE_SSIF,
+ IPMI_SYSTEM_INTERFACE_MAX_TYPE
+} IPMI_SYSTEM_INTERFACE_TYPE;
+
+//
+// System Interface Address Type
+//
+typedef enum {
+ IPMI_MEMORY,
+ IPMI_IO,
+ IPMI_MAX_INTERFACE_ADDRESS_TYPE
+} IPMI_INTERFACE_ADDRESS_TYPE;
+
+typedef
+EFI_STATUS
+(EFIAPI *IPMI_INTERFACE_PROTOCOL_EXECUTE_IPMI_CMD) (
+ IN IPMI_INTERFACE_PROTOCOL *This,
+ IN IPMI_CMD_HEADER Request,
+ IN VOID *SendData OPTIONAL,
+ IN UINT8 SendLength,
+ OUT VOID *RecvData,
+ OUT UINT8 *RecvLength,
+ OUT UINT16 *StatusCodes OPTIONAL
+);
+typedef
+IPMI_SYSTEM_INTERFACE_TYPE
+(EFIAPI *IPMI_INTERFACE_PROTOCOL_GET_IPMI_INTERFACE_TYPE) (
+ IN IPMI_INTERFACE_PROTOCOL *This
+);
+typedef
+UINT16
+(EFIAPI *IPMI_INTERFACE_PROTOCOL_GET_IPMI_BASE_ADDRESS) (
+ IN IPMI_INTERFACE_PROTOCOL *This
+);
+typedef
+IPMI_INTERFACE_ADDRESS_TYPE
+(EFIAPI *IPMI_INTERFACE_PROTOCOL_GET_IPMI_BASE_ADDRESS_TYPE) (
+ IN IPMI_INTERFACE_PROTOCOL *This
+);
+typedef
+UINT8
+(EFIAPI *IPMI_INTERFACE_PROTOCOL_GET_IPMI_VERSION) (
+ IN IPMI_INTERFACE_PROTOCOL *This
+);
+
+//
+// Structure of IPMI_INTERFACE_PROTOCOL
+//
+struct _IPMI_INTERFACE_PROTOCOL{
+ IPMI_INTERFACE_PROTOCOL_EXECUTE_IPMI_CMD ExecuteIpmiCmd;
+ IPMI_INTERFACE_PROTOCOL_GET_IPMI_INTERFACE_TYPE GetIpmiInterfaceType;
+ IPMI_INTERFACE_PROTOCOL_GET_IPMI_BASE_ADDRESS GetIpmiBaseAddress;
+ IPMI_INTERFACE_PROTOCOL_GET_IPMI_BASE_ADDRESS_TYPE GetIpmiBaseAddressType;
+ IPMI_INTERFACE_PROTOCOL_GET_IPMI_VERSION GetIpmiVersion;
+} ;
+
+extern EFI_GUID gIpmiInterfaceProtocolGuid;
+
+#endif
diff --git a/Silicon/Hisilicon/Include/Protocol/NorFlashProtocol.h b/Silicon/Hisilicon/Include/Protocol/NorFlashProtocol.h new file mode 100644 index 0000000000..29e9de80c0 --- /dev/null +++ b/Silicon/Hisilicon/Include/Protocol/NorFlashProtocol.h @@ -0,0 +1,59 @@ +/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#ifndef _NOR_FLASH_PROTOCOL_H_
+#define _NOR_FLASH_PROTOCOL_H_
+
+#define UNI_NOR_FLASH_PROTOCOL_GUID \
+ {0x86F305EA, 0xDFAC, 0x4A6B, {0x92, 0x77, 0x47, 0x31, 0x2E, 0xCE, 0x42, 0xA}}
+
+typedef struct _UNI_NOR_FLASH_PROTOCOL UNI_NOR_FLASH_PROTOCOL;
+
+typedef
+EFI_STATUS
+(EFIAPI *UNI_FLASH_ERASE_INTERFACE) (
+ IN UNI_NOR_FLASH_PROTOCOL *This,
+ IN UINT32 Offset,
+ IN UINT32 Length
+ );
+typedef
+EFI_STATUS
+(EFIAPI *UNI_FLASH_WRITE_INTERFACE) (
+ IN UNI_NOR_FLASH_PROTOCOL *This,
+ IN UINT32 Offset,
+ IN UINT8 *Buffer,
+ UINT32 ulLength
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *UNI_FLASH_READ_INTERFACE) (
+ IN UNI_NOR_FLASH_PROTOCOL *This,
+ IN UINT32 Offset,
+ IN OUT UINT8 *Buffer,
+ IN UINT32 ulLen
+ );
+
+
+struct _UNI_NOR_FLASH_PROTOCOL {
+ UNI_FLASH_ERASE_INTERFACE Erase;
+ UNI_FLASH_WRITE_INTERFACE Write;
+ UNI_FLASH_READ_INTERFACE Read;
+};
+
+extern EFI_GUID gUniNorFlashProtocolGuid;
+
+#endif
diff --git a/Silicon/Hisilicon/Include/Protocol/PlatformSasProtocol.h b/Silicon/Hisilicon/Include/Protocol/PlatformSasProtocol.h new file mode 100644 index 0000000000..1e1892b011 --- /dev/null +++ b/Silicon/Hisilicon/Include/Protocol/PlatformSasProtocol.h @@ -0,0 +1,37 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _PLATFORM_SAS_PROTOCOL_H_
+#define _PLATFORM_SAS_PROTOCOL_H_
+
+#define PLATFORM_SAS_PROTOCOL_GUID \
+ { \
+ 0x40e9829f, 0x3a2c, 0x479a, 0x9a, 0x93, 0x45, 0x7d, 0x13, 0x50, 0x96, 0x5d \
+ }
+
+typedef struct _PLATFORM_SAS_PROTOCOL PLATFORM_SAS_PROTOCOL;
+
+typedef
+VOID
+(EFIAPI * SAS_INIT) (
+ IN PLATFORM_SAS_PROTOCOL *This
+);
+
+struct _PLATFORM_SAS_PROTOCOL {
+ IN UINT64 BaseAddr;
+ SAS_INIT Init;
+};
+
+#endif
diff --git a/Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h b/Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h new file mode 100644 index 0000000000..bf57652e53 --- /dev/null +++ b/Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h @@ -0,0 +1,16542 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __PCIE_REG_OFFSET__
+#define __PCIE_REG_OFFSET__
+
+
+
+
+#define PCIE_EEP_PCI_CFG_HDR0_REG (0x0)
+#define PCIE_EEP_PCI_CFG_HDR1_REG (0x4)
+#define PCIE_EEP_PCI_CFG_HDR2_REG (0x8)
+#define PCIE_EEP_PCI_CFG_HDR3_REG (0xC)
+#define PCIE_EEP_PCI_CFG_HDR4_REG (0x10)
+#define PCIE_EEP_PCI_CFG_HDR5_REG (0x14)
+#define PCIE_EEP_PCI_CFG_HDR6_REG (0x18)
+#define PCIE_EEP_PCI_CFG_HDR7_REG (0x1C)
+#define PCIE_EEP_PCI_CFG_HDR8_REG (0x20)
+#define PCIE_EEP_PCI_CFG_HDR9_REG (0x24)
+#define PCIE_EEP_PCI_CFG_HDR10_REG (0x28)
+#define PCIE_EEP_PCI_CFG_HDR11_REG (0x2C)
+#define PCIE_EEP_PCI_CFG_HDR12_REG (0x30)
+#define PCIE_EEP_PCI_CFG_HDR13_REG (0x34)
+#define PCIE_EEP_PCI_CFG_HDR14_REG (0x38)
+#define PCIE_EEP_PCI_CFG_HDR15_REG (0x3C)
+#define PCIE_EEP_PCI_PM_CAP0_REG (0x40)
+#define PCIE_EEP_PCI_PM_CAP1_REG (0x44)
+#define PCIE_EEP_PCI_MSI_CAP0_REG (0x50)
+#define PCIE_EEP_PCI_MSI_CAP1_REG (0x54)
+#define PCIE_EEP_PCI_MSI_CAP2_REG (0x58)
+#define PCIE_EEP_PCI_MSI_CAP3_REG (0x5C)
+#define PCIE_EEP_PCIE_CAP0_REG (0x70)
+#define PCIE_EEP_PCIE_CAP1_REG (0x74)
+#define PCIE_EEP_PCIE_CAP2_REG (0x78)
+#define PCIE_EEP_PCIE_CAP3_REG (0x7C)
+#define PCIE_EEP_PCIE_CAP4_REG (0x80)
+#define PCIE_EEP_PCIE_CAP5_REG (0x84)
+#define PCIE_EEP_PCIE_CAP6_REG (0x88)
+#define PCIE_EEP_PCIE_CAP7_REG (0x8C)
+#define PCIE_EEP_PCIE_CAP8_REG (0x90)
+#define PCIE_EEP_PCIE_CAP9_REG (0x94)
+#define PCIE_EEP_PCIE_CAP10_REG (0x98)
+#define PCIE_EEP_PCIE_CAP11_REG (0x9C)
+#define PCIE_EEP_PCIE_CAP12_REG (0xA0)
+#define PCIE_EEP_SLOT_CAP_REG (0xC0)
+#define PCIE_EEP_AER_CAP0_REG (0x100)
+#define PCIE_EEP_AER_CAP1_REG (0x104)
+#define PCIE_EEP_AER_CAP2_REG (0x108)
+#define PCIE_EEP_AER_CAP3_REG (0x10C)
+#define PCIE_EEP_AER_CAP4_REG (0x110)
+#define PCIE_EEP_AER_CAP5_REG (0x114)
+#define PCIE_EEP_AER_CAP6_REG (0x118)
+#define PCIE_EEP_AER_CAP7_REG (0x11C)
+#define PCIE_EEP_AER_CAP8_REG (0x120)
+#define PCIE_EEP_AER_CAP9_REG (0x124)
+#define PCIE_EEP_AER_CAP10_REG (0x128)
+#define PCIE_EEP_AER_CAP11_REG (0x12C)
+#define PCIE_EEP_AER_CAP12_REG (0x130)
+#define PCIE_EEP_AER_CAP13_REG (0x134)
+#define PCIE_EEP_VC_CAP0_REG (0x140)
+#define PCIE_EEP_VC_CAP1_REG (0x144)
+#define PCIE_EEP_VC_CAP2_REG (0x148)
+#define PCIE_EEP_VC_CAP3_REG (0x14C)
+#define PCIE_EEP_VC_CAP4_REG (0x150)
+#define PCIE_EEP_VC_CAP5_REG (0x154)
+#define PCIE_EEP_VC_CAP6_REG (0x158)
+#define PCIE_EEP_VC_CAP7_REG (0x15C)
+#define PCIE_EEP_VC_CAP8_REG (0x160)
+#define PCIE_EEP_VC_CAP9_REG (0x164)
+#define PCIE_EEP_PORT_LOGIC0_REG (0x700)
+#define PCIE_EEP_PORT_LOGIC1_REG (0x704)
+#define PCIE_EEP_PORT_LOGIC2_REG (0x708)
+#define PCIE_EEP_PORT_LOGIC3_REG (0x70C)
+#define PCIE_EEP_PORT_LOGIC4_REG (0x710)
+#define PCIE_EEP_PORT_LOGIC5_REG (0x714)
+#define PCIE_EEP_PORT_LOGIC6_REG (0x718)
+#define PCIE_EEP_PORT_LOGIC7_REG (0x71C)
+#define PCIE_EEP_PORT_LOGIC8_REG (0x720)
+#define PCIE_EEP_PORT_LOGIC9_REG (0x724)
+#define PCIE_EEP_PORT_LOGIC10_REG (0x728)
+#define PCIE_EEP_PORT_LOGIC11_REG (0x72C)
+#define PCIE_EEP_PORT_LOGIC12_REG (0x730)
+#define PCIE_EEP_PORT_LOGIC13_REG (0x734)
+#define PCIE_EEP_PORT_LOGIC14_REG (0x738)
+#define PCIE_EEP_PORT_LOGIC15_REG (0x73C)
+#define PCIE_EEP_PORT_LOGIC16_REG (0x748)
+#define PCIE_EEP_PORT_LOGIC17_REG (0x74C)
+#define PCIE_EEP_PORT_LOGIC18_REG (0x750)
+#define PCIE_EEP_PORT_LOGIC19_REG (0x7A8)
+#define PCIE_EEP_PORT_LOGIC20_REG (0x7AC)
+#define PCIE_EEP_PORT_LOGIC21_REG (0x7B0)
+#define PCIE_EEP_PORT_LOGIC22_REG (0x80C)
+#define PCIE_EEP_PORTLOGIC23_REG (0x810)
+#define PCIE_EEP_PORTLOGIC24_REG (0x814)
+#define PCIE_EEP_PORTLOGIC25_REG (0x818)
+#define PCIE_EEP_PORTLOGIC26_REG (0x81C)
+#define PCIE_EEP_PORTLOGIC27_REG (0x820)
+#define PCIE_EEP_PORTLOGIC28_REG (0x824)
+#define PCIE_EEP_PORTLOGIC29_REG (0x828)
+#define PCIE_EEP_PORTLOGIC30_REG (0x82C)
+#define PCIE_EEP_PORTLOGIC31_REG (0x830)
+#define PCIE_EEP_PORTLOGIC32_REG (0x834)
+#define PCIE_EEP_PORTLOGIC33_REG (0x838)
+#define PCIE_EEP_PORTLOGIC34_REG (0x83C)
+#define PCIE_EEP_PORTLOGIC35_REG (0x840)
+#define PCIE_EEP_PORTLOGIC36_REG (0x844)
+#define PCIE_EEP_PORTLOGIC37_REG (0x848)
+#define PCIE_EEP_PORTLOGIC38_REG (0x84C)
+#define PCIE_EEP_PORTLOGIC39_REG (0x850)
+#define PCIE_EEP_PORTLOGIC40_REG (0x854)
+#define PCIE_EEP_PORTLOGIC41_REG (0x858)
+#define PCIE_EEP_PORTLOGIC42_REG (0x85C)
+#define PCIE_EEP_PORTLOGIC43_REG (0x860)
+#define PCIE_EEP_PORTLOGIC44_REG (0x864)
+#define PCIE_EEP_PORTLOGIC45_REG (0x868)
+#define PCIE_EEP_PORTLOGIC46_REG (0x86C)
+#define PCIE_EEP_PORTLOGIC47_REG (0x870)
+#define PCIE_EEP_PORTLOGIC48_REG (0x874)
+#define PCIE_EEP_PORTLOGIC49_REG (0x878)
+#define PCIE_EEP_PORTLOGIC50_REG (0x87C)
+#define PCIE_EEP_PORTLOGIC51_REG (0x880)
+#define PCIE_EEP_PORTLOGIC52_REG (0x884)
+#define PCIE_EEP_PORTLOGIC53_REG (0x888)
+#define PCIE_EEP_GEN3_CONTRL_REG (0x890)
+#define PCIE_EEP_PIPE_LOOPBACK_REG (0x8B8)
+#define PCIE_EEP_PORTLOGIC54_REG (0x900)
+#define PCIE_EEP_PORTLOGIC55_REG (0x904)
+#define PCIE_EEP_PORTLOGIC56_REG (0x908)
+#define PCIE_EEP_PORTLOGIC57_REG (0x90C)
+#define PCIE_EEP_PORTLOGIC58_REG (0x910)
+#define PCIE_EEP_PORTLOGIC59_REG (0x914)
+#define PCIE_EEP_PORTLOGIC60_REG (0x918)
+#define PCIE_EEP_PORTLOGIC61_REG (0x91C)
+#define PCIE_EEP_PORTLOGIC62_REG (0x97C)
+#define PCIE_EEP_PORTLOGIC63_REG (0x980)
+#define PCIE_EEP_PORTLOGIC64_REG (0x99C)
+#define PCIE_EEP_PORTLOGIC65_REG (0x9A0)
+#define PCIE_EEP_PORTLOGIC66_REG (0x9BC)
+#define PCIE_EEP_PORTLOGIC67_REG (0x9C4)
+#define PCIE_EEP_PORTLOGIC68_REG (0x9C8)
+#define PCIE_EEP_PORTLOGIC69_REG (0x9CC)
+#define PCIE_EEP_PORTLOGIC70_REG (0x9D0)
+#define PCIE_EEP_PORTLOGIC71_REG (0x9D4)
+#define PCIE_EEP_PORTLOGIC72_REG (0x9D8)
+#define PCIE_EEP_PORTLOGIC73_REG (0x9DC)
+#define PCIE_EEP_PORTLOGIC74_REG (0x9E0)
+#define PCIE_EEP_PORTLOGIC75_REG (0xA00)
+#define PCIE_EEP_PORTLOGIC76_REG (0xA10)
+#define PCIE_EEP_PORTLOGIC77_REG (0xA18)
+#define PCIE_EEP_PORTLOGIC78_REG (0xA1C)
+#define PCIE_EEP_PORTLOGIC79_REG (0xA24)
+#define PCIE_EEP_PORTLOGIC80_REG (0xA28)
+#define PCIE_EEP_PORTLOGIC81_REG (0xA34)
+#define PCIE_EEP_PORTLOGIC82_REG (0xA3C)
+#define PCIE_EEP_PORTLOGIC83_REG (0xA40)
+#define PCIE_EEP_PORTLOGIC84_REG (0xA44)
+#define PCIE_EEP_PORTLOGIC85_REG (0xA48)
+#define PCIE_EEP_PORTLOGIC86_REG (0xA6C)
+#define PCIE_EEP_PORTLOGIC87_REG (0xA70)
+#define PCIE_EEP_PORTLOGIC88_REG (0xA78)
+#define PCIE_EEP_PORTLOGIC89_REG (0xA7C)
+#define PCIE_EEP_PORTLOGIC90_REG (0xA80)
+#define PCIE_EEP_PORTLOGIC91_REG (0xA84)
+#define PCIE_EEP_PORTLOGIC92_REG (0xA88)
+#define PCIE_EEP_PORTLOGIC93_REG (0xA8C)
+#define PCIE_EEP_PORTLOGIC94_REG (0xA90)
+
+//pcie iatu internal registers define
+#define IATU_OFFSET 0x700
+#define IATU_VIEW_POINT 0x200
+#define IATU_REGION_CTRL1 0x204
+#define IATU_REGION_CTRL2 0x208
+#define IATU_REGION_BASE_LOW 0x20C
+#define IATU_REGION_BASE_HIGH 0x210
+#define IATU_REGION_BASE_LIMIT 0x214
+#define IATU_REGION_TARGET_LOW 0x218
+#define IATU_REGION_TARGET_HIGH 0x21C
+#define IATU_SHIIF_MODE 0x90000000
+#define IATU_NORMAL_MODE 0x80000000
+#define IATU_CTRL1_TYPE_CONFIG0 0x4
+#define IATU_CTRL1_TYPE_CONFIG1 0x5
+#define IATU_CTRL1_TYPE_MEM 0
+#define IATU_CTRL1_TYPE_IO 2
+
+
+typedef union tagPipeLoopBack
+{
+ struct
+ {
+ UINT32 reserved : 31 ;
+ UINT32 pipe_loopback_enable : 1 ;
+ }Bits;
+ UINT32 UInt32;
+}PCIE_PIPE_LOOPBACK_U;
+
+typedef union tagEepPciCfgHdr0
+{
+
+ struct
+ {
+ UINT32 vendor_id : 16 ;
+ UINT32 device_id : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR0_U;
+
+
+
+typedef union tagEepPciCfgHdr1
+{
+
+ struct
+ {
+ UINT32 io_space_enable : 1 ;
+ UINT32 memory_space_enable : 1 ;
+ UINT32 bus_master_enable : 1 ;
+ UINT32 specialcycleenable : 1 ;
+ UINT32 memory_write_and_invalidate : 1 ;
+ UINT32 vga_palette_snoop_enable : 1 ;
+ UINT32 parity_error_response : 1 ;
+ UINT32 idsel_stepping_waitcycle_control : 1 ;
+ UINT32 serr_enable : 1 ;
+ UINT32 fastback_to_backenable : 1 ;
+ UINT32 interrupt_disable : 1 ;
+ UINT32 Reserved_2 : 5 ;
+ UINT32 Reserved_1 : 3 ;
+ UINT32 intx_status : 1 ;
+ UINT32 capabilitieslist : 1 ;
+ UINT32 pcibus66mhzcapable : 1 ;
+ UINT32 Reserved_0 : 1 ;
+ UINT32 fastback_to_back : 1 ;
+ UINT32 masterdataparityerror : 1 ;
+ UINT32 devsel_timing : 2 ;
+ UINT32 signaled_target_abort : 1 ;
+ UINT32 received_target_abort : 1 ;
+ UINT32 received_master_abort : 1 ;
+ UINT32 signaled_system_error : 1 ;
+ UINT32 detected_parity_error : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR1_U;
+
+typedef union tagEepPciCfgHdr2
+{
+
+ struct
+ {
+ UINT32 revision_identification : 8 ;
+ UINT32 Reserved_3 : 8 ;
+ UINT32 sub_class : 8 ;
+ UINT32 baseclass : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR2_U;
+
+
+
+typedef union tagEepPciCfgHdr3
+{
+
+ struct
+ {
+ UINT32 cache_line_size : 8 ;
+ UINT32 mstr_lat_tmr : 8 ;
+ UINT32 multi_function_device : 7 ;
+ UINT32 hdr_type : 1 ;
+ UINT32 bist : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR3_U;
+
+
+
+typedef union tagEepPciCfgHdr4
+{
+
+ struct
+ {
+ UINT32 sbar01_space_inicator : 1 ;
+ UINT32 sbar01_type : 2 ;
+ UINT32 sbar01_prefetchable : 1 ;
+ UINT32 sbar01_lower : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR4_U;
+
+
+
+typedef union tagEepPciCfgHdr6
+{
+
+ struct
+ {
+ UINT32 sbar23_space_inicator : 1 ;
+ UINT32 sbar23_type : 2 ;
+ UINT32 sbar23_prefetchable : 1 ;
+ UINT32 Reserved_4 : 8 ;
+ UINT32 sbar23_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR6_U;
+
+
+
+typedef union tagEepPciCfgHdr8
+{
+
+ struct
+ {
+ UINT32 sbar45_space_inicator : 1 ;
+ UINT32 sbar45_type : 2 ;
+ UINT32 sbar45_prefetchable : 1 ;
+ UINT32 Reserved_5 : 8 ;
+ UINT32 sbar45_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR8_U;
+
+
+
+typedef union tagEepPciCfgHdr11
+{
+
+ struct
+ {
+ UINT32 subsystem_vendor_id : 16 ;
+ UINT32 subsystemid : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR11_U;
+
+
+
+typedef union tagEepPciCfgHdr13
+{
+
+ struct
+ {
+ UINT32 capptr : 8 ;
+ UINT32 Reserved_6 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR13_U;
+
+
+
+typedef union tagEepPciCfgHdr15
+{
+
+ struct
+ {
+ UINT32 int_line : 8 ;
+ UINT32 int_pin : 8 ;
+ UINT32 Min_Grant : 8 ;
+ UINT32 Max_Latency : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR15_U;
+
+
+
+typedef union tagEepPciMsiCap0
+{
+
+ struct
+ {
+ UINT32 msi_cap_id : 8 ;
+ UINT32 next_capability_pointer : 8 ;
+ UINT32 msi_enabled : 1 ;
+ UINT32 multiple_message_capable : 3 ;
+ UINT32 multiple_message_enabled : 3 ;
+ UINT32 msi_64_en : 1 ;
+ UINT32 pvm_en : 1 ;
+ UINT32 message_control_register : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCI_MSI_CAP0_U;
+
+
+
+typedef union tagEepPciMsiCap1
+{
+
+ struct
+ {
+ UINT32 Reserved_11 : 2 ;
+ UINT32 msi_addr_low : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCI_MSI_CAP1_U;
+
+
+
+typedef union tagEepPciMsiCap3
+{
+
+ struct
+ {
+ UINT32 msi_data : 16 ;
+ UINT32 Reserved_12 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCI_MSI_CAP3_U;
+
+
+
+typedef union tagEepPcieCap0
+{
+
+ struct
+ {
+ UINT32 pcie_cap_id : 8 ;
+ UINT32 pcie_next_ptr : 8 ;
+ UINT32 pcie_capability_version : 4 ;
+ UINT32 device_port_type : 4 ;
+ UINT32 slot_implemented : 1 ;
+ UINT32 interrupt_message_number : 5 ;
+ UINT32 Reserved_13 : 2 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCIE_CAP0_U;
+
+
+
+typedef union tagEepPcieCap1
+{
+
+ struct
+ {
+ UINT32 max_payload_size_supported : 3 ;
+ UINT32 phantom_function_supported : 2 ;
+ UINT32 extended_tagEepfield_supported : 1 ;
+ UINT32 endpoint_l0sacceptable_latency : 3 ;
+ UINT32 endpoint_l1acceptable_latency : 3 ;
+ UINT32 undefined : 3 ;
+ UINT32 Reserved_16 : 3 ;
+ UINT32 captured_slot_power_limit_value : 8 ;
+ UINT32 captured_slot_power_limit_scale : 2 ;
+ UINT32 function_level_reset : 1 ;
+ UINT32 Reserved_15 : 3 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCIE_CAP1_U;
+
+
+
+typedef union tagEepPcieCap2
+{
+
+ struct
+ {
+ UINT32 correctable_error_reporting_enable : 1 ;
+ UINT32 non_fatal_error_reporting_enable : 1 ;
+ UINT32 fatal_error_reporting_enable : 1 ;
+ UINT32 urenable : 1 ;
+ UINT32 enable_relaxed_ordering : 1 ;
+ UINT32 max_payload_size : 3 ;
+ UINT32 extended_tagEepfieldenable : 1 ;
+ UINT32 phantom_function_enable : 1 ;
+ UINT32 auxpowerpmenable : 1 ;
+ UINT32 enablenosnoop : 1 ;
+ UINT32 max_read_request_size : 3 ;
+ UINT32 Reserved_18 : 1 ;
+ UINT32 correctableerrordetected : 1 ;
+ UINT32 non_fatalerrordetected : 1 ;
+ UINT32 fatalerrordetected : 1 ;
+ UINT32 unsupportedrequestdetected : 1 ;
+ UINT32 auxpowerdetected : 1 ;
+ UINT32 transactionpending : 1 ;
+ UINT32 Reserved_17 : 10 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCIE_CAP2_U;
+
+
+
+typedef union tagEepPcieCap3
+{
+
+ struct
+ {
+ UINT32 max_link_speed : 4 ;
+ UINT32 max_link_width : 6 ;
+ UINT32 active_state_power_management : 2 ;
+ UINT32 l0s_exitlatency : 3 ;
+ UINT32 l1_exit_latency : 3 ;
+ UINT32 clock_power_management : 1 ;
+ UINT32 surprise_down_error_report_cap : 1 ;
+ UINT32 data_link_layer_active_report_cap : 1 ;
+ UINT32 link_bandwidth_noti_cap : 1 ;
+ UINT32 aspm_option_compliance : 1 ;
+ UINT32 Reserved_19 : 1 ;
+ UINT32 port_number : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCIE_CAP3_U;
+
+
+
+
+typedef union tagEepPcieCap4
+{
+
+ struct
+ {
+ UINT32 active_state_power_management : 2 ;
+ UINT32 Reserved_22 : 1 ;
+ UINT32 rcb : 1 ;
+ UINT32 link_disable : 1 ;
+ UINT32 retrain_link : 1 ;
+ UINT32 common_clock_config : 1 ;
+ UINT32 extended_sync : 1 ;
+ UINT32 enable_clock_pwr_management : 1 ;
+ UINT32 hw_auto_width_disable : 1 ;
+ UINT32 link_bandwidth_management_int_en : 1 ;
+ UINT32 link_auto_bandwidth_int_en : 1 ;
+ UINT32 Reserved_21 : 4 ;
+ UINT32 current_link_speed : 4 ;
+ UINT32 negotiated_link_width : 6 ;
+ UINT32 Reserved_20 : 1 ;
+ UINT32 link_training : 1 ;
+ UINT32 slot_clock_configration : 1 ;
+ UINT32 data_link_layer_active : 1 ;
+ UINT32 link_bandwidth_management_status : 1 ;
+ UINT32 link_auto_bandwidth_status : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCIE_CAP4_U;
+
+
+
+
+typedef union tagEepPcieCap5
+{
+
+ struct
+ {
+ UINT32 attentioonbuttonpresent : 1 ;
+ UINT32 powercontrollerpresent : 1 ;
+ UINT32 mrlsensorpresent : 1 ;
+ UINT32 attentionindicatorpresent : 1 ;
+ UINT32 powerindicatorpresent : 1 ;
+ UINT32 hot_plugsurprise : 1 ;
+ UINT32 hot_plugcapable : 1 ;
+ UINT32 slotpowerlimitvalue : 8 ;
+ UINT32 slotpowerlimitscale : 2 ;
+ UINT32 electromechanicalinterlockpresen : 1 ;
+ UINT32 no_cmd_complete_support : 1 ;
+ UINT32 phy_slot_number : 13 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCIE_CAP5_U;
+
+
+
+
+typedef union tagEepPcieCap6
+{
+
+ struct
+ {
+ UINT32 attentionbuttonpressedenable : 1 ;
+ UINT32 powerfaultdetectedenable : 1 ;
+ UINT32 mrlsensorchangedenable : 1 ;
+ UINT32 presencedetectchangedenable : 1 ;
+ UINT32 commandcompletedinterruptenable : 1 ;
+ UINT32 hot_pluginterruptenable : 1 ;
+ UINT32 attentionindicatorcontrol : 2 ;
+ UINT32 powerindicatorcontrol : 2 ;
+ UINT32 powercontrollercontrol : 1 ;
+ UINT32 electromechanicalinterlockcontrol : 1 ;
+ UINT32 datalinklayerstatechangedenable : 1 ;
+ UINT32 Reserved_23 : 3 ;
+ UINT32 attentionbuttonpressed : 1 ;
+ UINT32 powerfaultdetected : 1 ;
+ UINT32 mrlsensorchanged : 1 ;
+ UINT32 presencedetectchanged : 1 ;
+ UINT32 commandcompleted : 1 ;
+ UINT32 mrlsensorstate : 1 ;
+ UINT32 presencedetectstate : 1 ;
+ UINT32 electromechanicalinterlockstatus : 1 ;
+ UINT32 datalinklayerstatechanged : 1 ;
+ UINT32 slot_ctrl_status : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCIE_CAP6_U;
+
+
+
+
+typedef union tagEepPcieCap7
+{
+
+ struct
+ {
+ UINT32 systemerroroncorrectableerrorenable : 1 ;
+ UINT32 systemerroronnon_fatalerrorenable : 1 ;
+ UINT32 systemerroronfatalerrorenable : 1 ;
+ UINT32 pmeinterruptenable : 1 ;
+ UINT32 crssoftwarevisibilityenable : 1 ;
+ UINT32 Reserved_24 : 11 ;
+ UINT32 crssoftwarevisibility : 1 ;
+ UINT32 root_cap : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCIE_CAP7_U;
+
+
+
+
+typedef union tagEepPcieCap8
+{
+
+ struct
+ {
+ UINT32 pmerequesterid : 16 ;
+ UINT32 pmestatus : 1 ;
+ UINT32 pmepending : 1 ;
+ UINT32 root_status : 14 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCIE_CAP8_U;
+
+
+
+
+typedef union tagEepPcieCap9
+{
+
+ struct
+ {
+ UINT32 completiontimeoutrangessupported : 4 ;
+ UINT32 completiontimeoutdisablesupported : 1 ;
+ UINT32 ariforwardingsupported : 1 ;
+ UINT32 atomicoproutingsupported : 1 ;
+ UINT32 _2_bitatomicopcompletersupported : 1 ;
+ UINT32 _4_bitatomicopcompletersupported : 1 ;
+ UINT32 _28_bitcascompletersupported : 1 ;
+ UINT32 noro_enabledpr_prpassing : 1 ;
+ UINT32 Reserved_25 : 1 ;
+ UINT32 tphcompletersupported : 2 ;
+ UINT32 dev_cap2 : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCIE_CAP9_U;
+
+
+
+
+typedef union tagEepPcieCap10
+{
+
+ struct
+ {
+ UINT32 completiontimeoutvalue : 4 ;
+ UINT32 completiontimeoutdisable : 1 ;
+ UINT32 ariforwardingsupported : 1 ;
+ UINT32 atomicoprequesterenable : 1 ;
+ UINT32 atomicopegressblocking : 1 ;
+ UINT32 idorequestenable : 1 ;
+ UINT32 idocompletionenable : 1 ;
+ UINT32 dev_ctrl2 : 22 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCIE_CAP10_U;
+
+
+
+
+typedef union tagEepPcieCap11
+{
+
+ struct
+ {
+ UINT32 Reserved_27 : 1 ;
+ UINT32 gen1_suport : 1 ;
+ UINT32 gen2_suport : 1 ;
+ UINT32 gen3_suport : 1 ;
+ UINT32 Reserved_26 : 4 ;
+ UINT32 crosslink_supported : 1 ;
+ UINT32 link_cap2 : 23 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCIE_CAP11_U;
+
+
+
+
+typedef union tagEepPcieCap12
+{
+
+ struct
+ {
+ UINT32 targetlinkspeed : 4 ;
+ UINT32 entercompliance : 1 ;
+ UINT32 hardwareautonomousspeeddisa : 1 ;
+ UINT32 selectablede_empha : 1 ;
+ UINT32 transmitmargin : 3 ;
+ UINT32 _entermodifiedcompliance : 1 ;
+ UINT32 compliancesos : 1 ;
+ UINT32 de_emphasislevel : 4 ;
+ UINT32 currentde_emphasislevel : 1 ;
+ UINT32 equalizationcomplete : 1 ;
+ UINT32 equalizationphase1successful : 1 ;
+ UINT32 equalizationphase2successful : 1 ;
+ UINT32 equalizationphase3successful : 1 ;
+ UINT32 linkequalizationrequest : 1 ;
+ UINT32 link_ctrl2_status2 : 10 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCIE_CAP12_U;
+
+
+
+
+typedef union tagEepSlotCap
+{
+
+ struct
+ {
+ UINT32 slotnumberingcapabilitiesid : 8 ;
+ UINT32 nextcapabilitypointer : 8 ;
+ UINT32 add_incardslotsprovided : 5 ;
+ UINT32 firstinchassis : 1 ;
+ UINT32 Reserved_28 : 2 ;
+ UINT32 slot_cap : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_SLOT_CAP_U;
+
+
+
+
+typedef union tagEepAerCap0
+{
+
+ struct
+ {
+ UINT32 pciexpressextendedcapabilityid : 16 ;
+ UINT32 capabilityversion : 4 ;
+ UINT32 aer_cap_hdr : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_AER_CAP0_U;
+
+
+
+
+typedef union tagEepAerCap1
+{
+
+ struct
+ {
+ UINT32 Reserved_34 : 1 ;
+ UINT32 Reserved_33 : 3 ;
+ UINT32 datalinkprotocolerrorsta : 1 ;
+ UINT32 surprisedownerrorstatus : 1 ;
+ UINT32 Reserved_32 : 6 ;
+ UINT32 poisonedtlpstatu : 1 ;
+ UINT32 flowcontrolprotocolerrorst : 1 ;
+ UINT32 completiontimeouts : 1 ;
+ UINT32 completerabortstatus : 1 ;
+ UINT32 receiveroverflowstatus : 1 ;
+ UINT32 malformedtlpstatus : 1 ;
+ UINT32 ecrcerrorstatus : 1 ;
+ UINT32 ecrcerrorstat : 1 ;
+ UINT32 unsupportedrequesterrorstatus : 1 ;
+ UINT32 Reserved_31 : 3 ;
+ UINT32 atomicopegressblockedstatus : 1 ;
+ UINT32 uncorr_err_status : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_AER_CAP1_U;
+
+
+
+
+typedef union tagEepAerCap2
+{
+
+ struct
+ {
+ UINT32 Reserved_38 : 1 ;
+ UINT32 Reserved_37 : 3 ;
+ UINT32 datalinkprotocolerrormask : 1 ;
+ UINT32 surprisedownerrormask : 1 ;
+ UINT32 Reserved_36 : 6 ;
+ UINT32 poisonedtlpmask : 1 ;
+ UINT32 flowcontrolprotocolerrormask : 1 ;
+ UINT32 completiontimeoutmask : 1 ;
+ UINT32 completerabortmask : 1 ;
+ UINT32 unexpectedcompletionmask : 1 ;
+ UINT32 receiveroverflowmask : 1 ;
+ UINT32 malformedtlpmask : 1 ;
+ UINT32 ecrcerrormask : 1 ;
+ UINT32 unsupportedrequesterrormask : 1 ;
+ UINT32 Reserved_35 : 3 ;
+ UINT32 atomicopegressblockedmask : 1 ;
+ UINT32 uncorr_err_mask : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_AER_CAP2_U;
+
+
+
+
+typedef union tagEepAerCap3
+{
+
+ struct
+ {
+ UINT32 Reserved_42 : 1 ;
+ UINT32 Reserved_41 : 3 ;
+ UINT32 datalinkprotocolerrorsever : 1 ;
+ UINT32 surprisedownerrorseverity : 1 ;
+ UINT32 Reserved_40 : 6 ;
+ UINT32 poisonedtlpseverity : 1 ;
+ UINT32 flowcontrolprotocolerrorseveri : 1 ;
+ UINT32 completiontimeoutseverity : 1 ;
+ UINT32 completerabortseverity : 1 ;
+ UINT32 unexpectedcompletionseverity : 1 ;
+ UINT32 receiveroverflowseverity : 1 ;
+ UINT32 malformedtlpseverity : 1 ;
+ UINT32 ecrcerrorseverity : 1 ;
+ UINT32 unsupportedrequesterrorseverity : 1 ;
+ UINT32 Reserved_39 : 3 ;
+ UINT32 atomicopegressblockedseverity : 1 ;
+ UINT32 uncorr_err_ser : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_AER_CAP3_U;
+
+
+
+
+typedef union tagEepAerCap4
+{
+
+ struct
+ {
+ UINT32 receivererrorstatus : 1 ;
+ UINT32 Reserved_44 : 5 ;
+ UINT32 badtlpstatus : 1 ;
+ UINT32 baddllpstatus : 1 ;
+ UINT32 replay_numrolloverstatus : 1 ;
+ UINT32 Reserved_43 : 3 ;
+ UINT32 replytimertimeoutstatus : 1 ;
+ UINT32 advisorynon_fatalerrorstatus : 1 ;
+ UINT32 corr_err_status : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_AER_CAP4_U;
+
+
+
+
+typedef union tagEepAerCap5
+{
+
+ struct
+ {
+ UINT32 receivererrormask : 1 ;
+ UINT32 Reserved_46 : 5 ;
+ UINT32 badtlpmask : 1 ;
+ UINT32 baddllpmask : 1 ;
+ UINT32 replay_numrollovermask : 1 ;
+ UINT32 Reserved_45 : 3 ;
+ UINT32 replytimertimeoutmask : 1 ;
+ UINT32 advisorynon_fatalerrormask : 1 ;
+ UINT32 corr_err_mask : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_AER_CAP5_U;
+
+
+
+
+typedef union tagEepAerCap6
+{
+
+ struct
+ {
+ UINT32 firsterrorpointer : 5 ;
+ UINT32 ecrcgenerationcapability : 1 ;
+ UINT32 ecrcgenerationenable : 1 ;
+ UINT32 ecrccheckcapable : 1 ;
+ UINT32 ecrccheckenable : 1 ;
+ UINT32 adv_cap_ctrl : 23 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_AER_CAP6_U;
+
+typedef union tagGen3Ctrol
+{
+ struct
+ {
+ UINT32 reserved : 16 ;
+ UINT32 equalization_disable : 1 ;
+ UINT32 reserved2 : 15 ;
+ }Bits;
+ UINT32 UInt32;
+}PCIE_GRN3_CONTRL;
+
+
+
+
+typedef union tagEepAerCap11
+{
+
+ struct
+ {
+ UINT32 correctableerrorreportingenable : 1 ;
+ UINT32 non_fatalerrorreportingenable : 1 ;
+ UINT32 fatalerrorreportingenable : 1 ;
+ UINT32 root_err_cmd : 29 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_AER_CAP11_U;
+
+
+
+
+typedef union tagEepAerCap12
+{
+
+ struct
+ {
+ UINT32 err_correceived : 1 ;
+ UINT32 multipleerr_correceived : 1 ;
+ UINT32 err_fatal_nonfatalreceived : 1 ;
+ UINT32 multipleerr_fatal_nonfatalreceived : 1 ;
+ UINT32 firstuncorrectablefatal : 1 ;
+ UINT32 non_fatalerrormessagesreceived : 1 ;
+ UINT32 fatalerrormessagesreceived : 1 ;
+ UINT32 Reserved_47 : 20 ;
+ UINT32 root_err_status : 5 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_AER_CAP12_U;
+
+
+
+
+typedef union tagEepAerCap13
+{
+
+ struct
+ {
+ UINT32 err_corsourceidentification : 16 ;
+ UINT32 err_src_id : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_AER_CAP13_U;
+
+
+
+
+typedef union tagEepVcCap0
+{
+
+ struct
+ {
+ UINT32 pciexpressextendedcapabilityid : 16 ;
+ UINT32 capabilityversion : 4 ;
+ UINT32 vc_cap_hdr : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_VC_CAP0_U;
+
+
+
+
+typedef union tagEepVcCap1
+{
+
+ struct
+ {
+ UINT32 extendedvccount : 3 ;
+ UINT32 Reserved_50 : 1 ;
+ UINT32 lowpriorityextendedvccount : 3 ;
+ UINT32 Reserved_49 : 1 ;
+ UINT32 referenceclock : 2 ;
+ UINT32 portarbitrationtableentrysize : 2 ;
+ UINT32 vc_cap1 : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_VC_CAP1_U;
+
+
+
+
+typedef union tagEepVcCap2
+{
+
+ struct
+ {
+ UINT32 vcarbitrationcapability : 8 ;
+ UINT32 Reserved_51 : 16 ;
+ UINT32 vc_cap2 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_VC_CAP2_U;
+
+
+
+
+typedef union tagEepVcCap3
+{
+
+ struct
+ {
+ UINT32 loadvcarbitrationtable : 1 ;
+ UINT32 vcarbitrationselect : 3 ;
+ UINT32 Reserved_53 : 12 ;
+ UINT32 arbitrationtablestatus : 1 ;
+ UINT32 Reserved_52 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_VC_CAP3_U;
+
+
+
+
+typedef union tagEepVcCap4
+{
+
+ struct
+ {
+ UINT32 portarbitrationcapability : 8 ;
+ UINT32 Reserved_56 : 6 ;
+ UINT32 Reserved_55 : 1 ;
+ UINT32 rejectsnooptransactions : 1 ;
+ UINT32 maximumtimeslots : 7 ;
+ UINT32 Reserved_54 : 1 ;
+ UINT32 vc_res_cap : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_VC_CAP4_U;
+
+
+
+
+typedef union tagEepVcCap5
+{
+
+ struct
+ {
+ UINT32 tc_vcmap : 8 ;
+ UINT32 Reserved_59 : 8 ;
+ UINT32 loadportarbitrationtable : 1 ;
+ UINT32 portarbitrationselec : 3 ;
+ UINT32 Reserved_58 : 4 ;
+ UINT32 vcid : 3 ;
+ UINT32 Reserved_57 : 4 ;
+ UINT32 vc_res_ctrl : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_VC_CAP5_U;
+
+
+
+
+typedef union tagEepVcCap6
+{
+
+ struct
+ {
+ UINT32 Reserved_60 : 16 ;
+ UINT32 portarbitrationtablestatus : 1 ;
+ UINT32 vcnegotiationpending : 1 ;
+ UINT32 vc_res_status : 14 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_VC_CAP6_U;
+
+
+
+
+typedef union tagEepVcCap7
+{
+
+ struct
+ {
+ UINT32 portarbitrationcapability : 8 ;
+ UINT32 Reserved_63 : 6 ;
+ UINT32 Reserved_62 : 1 ;
+ UINT32 rejectsnooptransactions : 1 ;
+ UINT32 maximumtimeslots : 7 ;
+ UINT32 Reserved_61 : 1 ;
+ UINT32 vc_res_cap0 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_VC_CAP7_U;
+
+
+
+
+typedef union tagEepVcCap8
+{
+
+ struct
+ {
+ UINT32 tc_vcmap : 8 ;
+ UINT32 Reserved_66 : 8 ;
+ UINT32 loadportarbitrationtable : 1 ;
+ UINT32 portarbitrationselect : 3 ;
+ UINT32 Reserved_65 : 4 ;
+ UINT32 vcid : 3 ;
+ UINT32 Reserved_64 : 4 ;
+ UINT32 vc_res_ctrl0 : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_VC_CAP8_U;
+
+
+
+
+typedef union tagEepVcCap9
+{
+
+ struct
+ {
+ UINT32 Reserved_67 : 16 ;
+ UINT32 arbitrationtablestatus : 1 ;
+ UINT32 vcnegotiationpending : 1 ;
+ UINT32 vc_res_status0 : 14 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_VC_CAP9_U;
+
+
+
+
+typedef union tagEepPortLogic0
+{
+
+ struct
+ {
+ UINT32 ack_lat_timer : 16 ;
+ UINT32 replay_timer : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC0_U;
+
+
+
+
+typedef union tagEepPortLogic2
+{
+
+ struct
+ {
+ UINT32 linknumber : 8 ;
+ UINT32 Reserved_70 : 7 ;
+ UINT32 forcelink : 1 ;
+ UINT32 linkstate : 6 ;
+ UINT32 Reserved_69 : 2 ;
+ UINT32 port_force_link : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC2_U;
+
+
+
+
+typedef union tagEepPortLogic3
+{
+
+ struct
+ {
+ UINT32 ackfrequency : 8 ;
+ UINT32 n_fts : 8 ;
+ UINT32 commonclockn_fts : 8 ;
+ UINT32 l0sentrancelatency : 3 ;
+ UINT32 l1entrancelatency : 3 ;
+ UINT32 enteraspml1withoutreceiveinl0s : 1 ;
+ UINT32 ack_aspm : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC3_U;
+
+
+
+
+typedef union tagEepPortLogic4
+{
+
+ struct
+ {
+ UINT32 vendorspecificdllprequest : 1 ;
+ UINT32 scrambledisable : 1 ;
+ UINT32 loopbackenable : 1 ;
+ UINT32 resetassert : 1 ;
+ UINT32 Reserved_73 : 1 ;
+ UINT32 dlllinkenable : 1 ;
+ UINT32 Reserved_72 : 1 ;
+ UINT32 fastlinkmode : 1 ;
+ UINT32 Reserved_71 : 8 ;
+ UINT32 linkmodeenable : 6 ;
+ UINT32 crosslinkenable : 1 ;
+ UINT32 crosslinkactive : 1 ;
+ UINT32 port_link_ctrl : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC4_U;
+
+
+
+
+typedef union tagEepPortLogic5
+{
+
+ struct
+ {
+ UINT32 insertlaneskewfortransmit : 24 ;
+ UINT32 flowcontroldisable : 1 ;
+ UINT32 ack_nakdisable : 1 ;
+ UINT32 Reserved_74 : 5 ;
+ UINT32 lane_skew : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC5_U;
+
+
+
+
+typedef union tagEepPortLogic6
+{
+
+ struct
+ {
+ UINT32 numberoftssymbols : 4 ;
+ UINT32 Reserved_76 : 4 ;
+ UINT32 numberofskpsymbols : 3 ;
+ UINT32 Reserved_75 : 3 ;
+ UINT32 timermodifierforreplaytimer : 5 ;
+ UINT32 timermodifierforack_naklatencytimer : 5 ;
+ UINT32 timermodifierforflowcontrolwatchdogtimer : 5 ;
+ UINT32 sym_num : 3 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC6_U;
+
+
+
+
+typedef union tagEepPortLogic7
+{
+
+ struct
+ {
+ UINT32 vc0posteddataqueuedepth : 11 ;
+ UINT32 Reserved_77 : 4 ;
+ UINT32 sym_timer : 1 ;
+ UINT32 maskfunctionmismatchfilteringfo : 1 ;
+ UINT32 maskpoisonedtlpfiltering : 1 ;
+ UINT32 maskbarmatchfiltering : 1 ;
+ UINT32 masktype1configurationrequestfiltering : 1 ;
+ UINT32 masklockedrequestfiltering : 1 ;
+ UINT32 masktagerrorrulesforreceivedcompletions : 1 ;
+ UINT32 maskrequesteridmismatcherrorforreceivedcompletions : 1 ;
+ UINT32 maskfunctionmismatcherrorforreceivedcompletions : 1 ;
+ UINT32 mask_traffic_classmis_match_error_forreceived_completions : 1 ;
+ UINT32 mask_attributesmismatcherrorforreceivedcompletions : 1 ;
+ UINT32 mask_length_mismatch_error_forreceive_dcompletions : 1 ;
+ UINT32 maske_crcerror_filtering : 1 ;
+ UINT32 maske_crcerror_filtering_forcompletions : 1 ;
+ UINT32 message_control : 1 ;
+ UINT32 maskfilteringofreceived : 1 ;
+ UINT32 flt_mask1 : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC7_U;
+
+
+
+
+typedef union tagEepPortLogic8
+{
+
+ struct
+ {
+ UINT32 cx_flt_mask_venmsg0_drop : 1 ;
+ UINT32 cx_flt_mask_venmsg1_drop : 1 ;
+ UINT32 cx_flt_mask_dabort_4ucpl : 1 ;
+ UINT32 cx_flt_mask_handle_flush : 1 ;
+ UINT32 flt_mask2 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC8_U;
+
+
+
+
+typedef union tagEepPortLogic9
+{
+
+ struct
+ {
+ UINT32 amba_multi_outbound_decomp_np : 1 ;
+ UINT32 amba_obnp_ctrl : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC9_U;
+
+
+
+
+typedef union tagEepPortLogic12
+{
+
+ struct
+ {
+ UINT32 transmitposteddatafccredits : 12 ;
+ UINT32 transmitpostedheaderfccredits : 8 ;
+ UINT32 tx_pfc_status : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC12_U;
+
+
+
+
+typedef union tagEepPortLogic13
+{
+
+ struct
+ {
+ UINT32 transmitnon_posteddatafccredits : 12 ;
+ UINT32 transmitnon_postedheaderfccredits : 8 ;
+ UINT32 tx_npfc_status : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC13_U;
+
+
+
+
+typedef union tagEepPortLogic14
+{
+
+ struct
+ {
+ UINT32 transmitcompletiondatafccredits : 12 ;
+ UINT32 transmitcompletionheaderfccredits : 8 ;
+ UINT32 tx_cplfc_status : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC14_U;
+
+
+
+
+typedef union tagEepPortLogic15
+{
+
+ struct
+ {
+ UINT32 rx_tlp_fc_credit_not_retured : 1 ;
+ UINT32 tx_retry_buf_not_empty : 1 ;
+ UINT32 rx_queue_not_empty : 1 ;
+ UINT32 Reserved_79 : 13 ;
+ UINT32 fc_latency_timer_override_value : 13 ;
+ UINT32 Reserved_78 : 2 ;
+ UINT32 fc_latency_timer_override_en : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC15_U;
+
+
+
+
+typedef union tagEepPortLogic16
+{
+
+ struct
+ {
+ UINT32 vc0posteddatacredits : 12 ;
+ UINT32 vc0postedheadercredits : 8 ;
+ UINT32 Reserved_81 : 1 ;
+ UINT32 vc0_postedtlpqueuemode : 1 ;
+ UINT32 vc0postedtlpqueuemode : 1 ;
+ UINT32 vc0postedtlpqueuemo : 1 ;
+ UINT32 Reserved_80 : 6 ;
+ UINT32 tlptypeorderingforvc0 : 1 ;
+ UINT32 rx_pque_ctrl : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC16_U;
+
+
+
+
+typedef union tagEepPortLogic17
+{
+
+ struct
+ {
+ UINT32 vc0non_posteddatacredits : 12 ;
+ UINT32 vc0non_postedheadercredits : 8 ;
+ UINT32 rx_npque_ctrl : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC17_U;
+
+
+
+
+typedef union tagEepPortLogic18
+{
+
+ struct
+ {
+ UINT32 vco_comp_data_credits : 12 ;
+ UINT32 vc0_cpl_header_credt : 8 ;
+ UINT32 Reserved_83 : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC18_U;
+
+
+
+
+typedef union tagEepPortLogic19
+{
+
+ struct
+ {
+ UINT32 vco_posted_data_que_path : 14 ;
+ UINT32 Reserved_84 : 2 ;
+ UINT32 vco_posted_head_queue_depth : 10 ;
+ UINT32 vc_pbuf_ctrl : 6 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC19_U;
+
+
+
+
+typedef union tagEepPortLogic20
+{
+
+ struct
+ {
+ UINT32 vco_np_data_que_depth : 14 ;
+ UINT32 Reserved_86 : 2 ;
+ UINT32 vco_np_header_que_depth : 10 ;
+ UINT32 vc_npbuf_ctrl : 6 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC20_U;
+
+
+
+
+typedef union tagEepPortLogic21
+{
+
+ struct
+ {
+ UINT32 vco_comp_data_queue_depth : 14 ;
+ UINT32 Reserved_88 : 2 ;
+ UINT32 vco_posted_head_queue_depth : 10 ;
+ UINT32 Reserved_87 : 6 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC21_U;
+
+
+
+
+typedef union tagEepPortLogic22
+{
+
+ struct
+ {
+ UINT32 n_fts : 8 ;
+ UINT32 pre_determ_num_of_lane : 9 ;
+ UINT32 det_sp_change : 1 ;
+ UINT32 config_phy_tx_sw : 1 ;
+ UINT32 config_tx_comp_rcv_bit : 1 ;
+ UINT32 set_emp_level : 1 ;
+ UINT32 Reserved_89 : 11 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC22_U;
+
+
+
+
+typedef union tagEepPortlogic25
+{
+
+ struct
+ {
+ UINT32 remote_rd_req_size : 3 ;
+ UINT32 Reserved_92 : 5 ;
+ UINT32 remote_max_brd_tag : 8 ;
+ UINT32 Reserved_91 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC25_U;
+
+
+
+
+typedef union tagEepPortlogic26
+{
+
+ struct
+ {
+ UINT32 resize_master_resp_compser : 1 ;
+ UINT32 axi_ctrl1 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC26_U;
+
+
+
+
+typedef union tagEepPortlogic54
+{
+
+ struct
+ {
+ UINT32 region_index : 4 ;
+ UINT32 Reserved_93 : 27 ;
+ UINT32 iatu_view : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC54_U;
+
+
+
+
+typedef union tagEepPortlogic55
+{
+
+ struct
+ {
+ UINT32 iatu1_type : 5 ;
+ UINT32 iatu1_tc : 3 ;
+ UINT32 iatu1_td : 1 ;
+ UINT32 iatu1_attr : 2 ;
+ UINT32 Reserved_97 : 5 ;
+ UINT32 iatu1_at : 2 ;
+ UINT32 Reserved_96 : 2 ;
+ UINT32 iatu1_id : 3 ;
+ UINT32 Reserved_95 : 9 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC55_U;
+
+
+
+
+typedef union tagEepPortlogic56
+{
+
+ struct
+ {
+ UINT32 iatu2_type : 8 ;
+ UINT32 iatu2_bar_num : 3 ;
+ UINT32 Reserved_101 : 3 ;
+ UINT32 iatu2_tc_match_en : 1 ;
+ UINT32 iatu2_td_match_en : 1 ;
+ UINT32 iatu2_attr_match_en : 1 ;
+ UINT32 Reserved_100 : 1 ;
+ UINT32 iatu2_at_match_en : 1 ;
+ UINT32 iatu2_func_num_match_en : 1 ;
+ UINT32 iatu2_virtual_func_num_match_en : 1 ;
+ UINT32 message_code_match_en : 1 ;
+ UINT32 Reserved_99 : 2 ;
+ UINT32 iatu2_response_code : 2 ;
+ UINT32 Reserved_98 : 1 ;
+ UINT32 iatu2_fuzzy_type_match_mode : 1 ;
+ UINT32 iatu2_cfg_shift_mode : 1 ;
+ UINT32 iatu2_ivert_mode : 1 ;
+ UINT32 iatu2_match_mode : 1 ;
+ UINT32 iatu2_region_en : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC56_U;
+
+
+
+
+typedef union tagEepPortlogic57
+{
+
+ struct
+ {
+ UINT32 iatu_start_low : 12 ;
+ UINT32 iatu_start_high : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC57_U;
+
+
+
+
+typedef union tagEepPortlogic59
+{
+
+ struct
+ {
+ UINT32 iatu_limit_low : 12 ;
+ UINT32 iatu_limit_high : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC59_U;
+
+
+
+
+typedef union tagEepPortlogic60
+{
+
+ struct
+ {
+ UINT32 xlated_addr_high : 12 ;
+ UINT32 xlated_addr_low : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC60_U;
+
+
+
+
+typedef union tagEepPortlogic62
+{
+
+ struct
+ {
+ UINT32 dma_wr_eng_en : 1 ;
+ UINT32 dma_wr_ena : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC62_U;
+
+
+
+
+typedef union tagEepPortlogic63
+{
+
+ struct
+ {
+ UINT32 wr_doorbell_num : 3 ;
+ UINT32 Reserved_103 : 28 ;
+ UINT32 dma_wr_dbell_stop : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC63_U;
+
+
+
+
+typedef union tagEepPortlogic64
+{
+
+ struct
+ {
+ UINT32 dma_read_eng_en : 1 ;
+ UINT32 Reserved_104 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC64_U;
+
+
+
+
+typedef union tagEepPortlogic65
+{
+
+ struct
+ {
+ UINT32 rd_doorbell_num : 3 ;
+ UINT32 Reserved_106 : 28 ;
+ UINT32 dma_rd_dbell_stop : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC65_U;
+
+
+
+
+typedef union tagEepPortlogic66
+{
+
+ struct
+ {
+ UINT32 done_int_status : 8 ;
+ UINT32 Reserved_108 : 8 ;
+ UINT32 abort_int_status : 8 ;
+ UINT32 Reserved_107 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC66_U;
+
+
+
+
+typedef union tagEepPortlogic67
+{
+
+ struct
+ {
+ UINT32 done_int_mask : 8 ;
+ UINT32 Reserved_111 : 8 ;
+ UINT32 abort_int_mask : 8 ;
+ UINT32 Reserved_110 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC67_U;
+
+
+
+
+typedef union tagEepPortlogic68
+{
+
+ struct
+ {
+ UINT32 done_int_clr : 8 ;
+ UINT32 Reserved_114 : 8 ;
+ UINT32 abort_int_clr : 8 ;
+ UINT32 Reserved_113 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC68_U;
+
+
+
+
+typedef union tagEepPortlogic69
+{
+
+ struct
+ {
+ UINT32 app_rd_err_det : 8 ;
+ UINT32 Reserved_116 : 8 ;
+ UINT32 ll_element_fetch_err_det : 8 ;
+ UINT32 Reserved_115 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC69_U;
+
+
+
+
+typedef union tagEepPortlogic74
+{
+
+ struct
+ {
+ UINT32 dma_wr_c0_imwr_data : 16 ;
+ UINT32 dma_wr_c1_imwr_data : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC74_U;
+
+
+
+
+typedef union tagEepPortlogic75
+{
+
+ struct
+ {
+ UINT32 wr_ch_ll_remote_abort_int_en : 8 ;
+ UINT32 Reserved_118 : 8 ;
+ UINT32 wr_ch_ll_local_abort_int_en : 8 ;
+ UINT32 Reserved_117 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC75_U;
+
+
+
+
+typedef union tagEepPortlogic76
+{
+
+ struct
+ {
+ UINT32 done_int_status : 8 ;
+ UINT32 Reserved_121 : 8 ;
+ UINT32 abort_int_status : 8 ;
+ UINT32 Reserved_120 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC76_U;
+
+
+
+
+typedef union tagEepPortlogic77
+{
+
+ struct
+ {
+ UINT32 done_int_mask : 8 ;
+ UINT32 Reserved_123 : 8 ;
+ UINT32 abort_int_mask : 8 ;
+ UINT32 dma_rd_int_mask : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC77_U;
+
+
+
+
+typedef union tagEepPortlogic78
+{
+
+ struct
+ {
+ UINT32 done_int_clr : 8 ;
+ UINT32 Reserved_125 : 8 ;
+ UINT32 abort_int_clr : 8 ;
+ UINT32 dma_rd_int_clr : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC78_U;
+
+
+
+
+typedef union tagEepPortlogic79
+{
+
+ struct
+ {
+ UINT32 app_wr_err_det : 8 ;
+ UINT32 Reserved_126 : 8 ;
+ UINT32 link_list_fetch_err_det : 8 ;
+ UINT32 dma_rd_err_low : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC79_U;
+
+
+
+
+typedef union tagEepPortlogic80
+{
+
+ struct
+ {
+ UINT32 unspt_request : 8 ;
+ UINT32 completer_abort : 8 ;
+ UINT32 cpl_time_out : 8 ;
+ UINT32 data_poison : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC80_U;
+
+
+
+
+typedef union tagEepPortlogic81
+{
+
+ struct
+ {
+ UINT32 remote_abort_int_en : 8 ;
+ UINT32 Reserved_128 : 8 ;
+ UINT32 local_abort_int_en : 8 ;
+ UINT32 dma_rd_ll_err_ena : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC81_U;
+
+
+
+
+typedef union tagEepPortlogic86
+{
+
+ struct
+ {
+ UINT32 channel_dir : 3 ;
+ UINT32 Reserved_131 : 28 ;
+ UINT32 dma_ch_con_idx : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC86_U;
+
+
+
+
+typedef union tagEepPortlogic87
+{
+
+ struct
+ {
+ UINT32 cycle_bit : 1 ;
+ UINT32 toggle_cycle_bit : 1 ;
+ UINT32 load_link_pointer : 1 ;
+ UINT32 local_int_en : 1 ;
+ UINT32 remote_int_en : 1 ;
+ UINT32 channel_status : 2 ;
+ UINT32 Reserved_135 : 1 ;
+ UINT32 consumer_cycle_state : 1 ;
+ UINT32 linked_list_en : 1 ;
+ UINT32 Reserved_134 : 2 ;
+ UINT32 func_num_dma : 5 ;
+ UINT32 Reserved_133 : 7 ;
+ UINT32 no_snoop : 1 ;
+ UINT32 ro : 1 ;
+ UINT32 td : 1 ;
+ UINT32 tc : 3 ;
+ UINT32 dma_ch_ctrl : 2 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC87_U;
+
+
+
+
+typedef union tagEepPortlogic93
+{
+
+ struct
+ {
+ UINT32 Reserved_137 : 2 ;
+ UINT32 dma_ll_ptr_low : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC93_U;
+
+
+
+#define PCIE_MEEP_SBAR23XLAT_LOWER_REG (0x0)
+#define PCIE_MEEP_SBAR23XLAT_UPPER_REG (0x4)
+#define PCIE_MEEP_SBAR45XLAT_LOWER_REG (0x8)
+#define PCIE_MEEP_SBAR45XLAT_UPPER_REG (0xC)
+#define PCIE_MEEP_SBAR23LMT_LOWER_REG (0x10)
+#define PCIE_MEEP_SBAR23LMT_UPPER_REG (0x14)
+#define PCIE_MEEP_SBAR45LMT_LOWER_REG (0x18)
+#define PCIE_MEEP_SBAR45LMT_UPPER_REG (0x1C)
+#define PCIE_MEEP_SDOORBELL_REG (0x20)
+#define PCIE_MEEP_SDOORBELL_MASK_REG (0x24)
+#define PCIE_MEEP_CBDF_SBDF_REG (0x28)
+#define PCIE_MEEP_NTB_CNTL_REG (0x2C)
+#define PCIE_MEEP_PCI_CFG_HDR0_REG (0x1000)
+#define PCIE_MEEP_PCI_CFG_HDR1_REG (0x1004)
+#define PCIE_MEEP_PCI_CFG_HDR2_REG (0x1008)
+#define PCIE_MEEP_PCI_CFG_HDR3_REG (0x100C)
+#define PCIE_MEEP_PCI_CFG_HDR4_REG (0x1010)
+#define PCIE_MEEP_PCI_CFG_HDR5_REG (0x1014)
+#define PCIE_MEEP_PCI_CFG_HDR6_REG (0x1018)
+#define PCIE_MEEP_PCI_CFG_HDR7_REG (0x101C)
+#define PCIE_MEEP_PCI_CFG_HDR8_REG (0x1020)
+#define PCIE_MEEP_PCI_CFG_HDR9_REG (0x1024)
+#define PCIE_MEEP_PCI_CFG_HDR10_REG (0x1028)
+#define PCIE_MEEP_PCI_CFG_HDR11_REG (0x102C)
+#define PCIE_MEEP_PCI_CFG_HDR12_REG (0x1030)
+#define PCIE_MEEP_PCI_CFG_HDR13_REG (0x1034)
+#define PCIE_MEEP_PCI_CFG_HDR14_REG (0x1038)
+#define PCIE_MEEP_PCI_CFG_HDR15_REG (0x103C)
+#define PCIE_MEEP_PCI_PM_CAP0_REG (0x1040)
+#define PCIE_MEEP_PCI_PM_CAP1_REG (0x1044)
+#define PCIE_MEEP_PCI_MSI_CAP0_REG (0x1050)
+#define PCIE_MEEP_PCI_MSI_CAP1_REG (0x1054)
+#define PCIE_MEEP_PCI_MSI_CAP2_REG (0x1058)
+#define PCIE_MEEP_PCI_MSI_CAP3_REG (0x105C)
+#define PCIE_MEEP_PCIE_CAP0_REG (0x1070)
+#define PCIE_MEEP_PCIE_CAP1_REG (0x1074)
+#define PCIE_MEEP_PCIE_CAP2_REG (0x1078)
+#define PCIE_MEEP_PCIE_CAP3_REG (0x107C)
+#define PCIE_MEEP_PCIE_CAP4_REG (0x1080)
+#define PCIE_MEEP_PCIE_CAP5_REG (0x1084)
+#define PCIE_MEEP_PCIE_CAP6_REG (0x1088)
+#define PCIE_MEEP_PCIE_CAP7_REG (0x108C)
+#define PCIE_MEEP_PCIE_CAP8_REG (0x1090)
+#define PCIE_MEEP_PCIE_CAP9_REG (0x1094)
+#define PCIE_MEEP_PCIE_CAP10_REG (0x1098)
+#define PCIE_MEEP_PCIE_CAP11_REG (0x109C)
+#define PCIE_MEEP_PCIE_CAP12_REG (0x10A0)
+#define PCIE_MEEP_SLOT_CAP_REG (0x10C0)
+#define PCIE_MEEP_AER_CAP0_REG (0x1100)
+#define PCIE_MEEP_AER_CAP1_REG (0x1104)
+#define PCIE_MEEP_AER_CAP2_REG (0x1108)
+#define PCIE_MEEP_AER_CAP3_REG (0x110C)
+#define PCIE_MEEP_AER_CAP4_REG (0x1110)
+#define PCIE_MEEP_AER_CAP5_REG (0x1114)
+#define PCIE_MEEP_AER_CAP6_REG (0x1118)
+#define PCIE_MEEP_AER_CAP7_REG (0x11C)
+#define PCIE_MEEP_AER_CAP8_REG (0x120)
+#define PCIE_MEEP_AER_CAP9_REG (0x124)
+#define PCIE_MEEP_AER_CAP10_REG (0x128)
+#define PCIE_MEEP_AER_CAP11_REG (0x112C)
+#define PCIE_MEEP_AER_CAP12_REG (0x1130)
+#define PCIE_MEEP_AER_CAP13_REG (0x1134)
+#define PCIE_MEEP_VC_CAP0_REG (0x1140)
+#define PCIE_MEEP_VC_CAP1_REG (0x1144)
+#define PCIE_MEEP_VC_CAP2_REG (0x1148)
+#define PCIE_MEEP_VC_CAP3_REG (0x114C)
+#define PCIE_MEEP_VC_CAP4_REG (0x1150)
+#define PCIE_MEEP_VC_CAP5_REG (0x1154)
+#define PCIE_MEEP_VC_CAP6_REG (0x1158)
+#define PCIE_MEEP_VC_CAP7_REG (0x115C)
+#define PCIE_MEEP_VC_CAP8_REG (0x1160)
+#define PCIE_MEEP_VC_CAP9_REG (0x1164)
+#define PCIE_MEEP_PORT_LOGIC0_REG (0x1700)
+#define PCIE_MEEP_PORT_LOGIC1_REG (0x1704)
+#define PCIE_MEEP_PORT_LOGIC2_REG (0x1708)
+#define PCIE_MEEP_PORT_LOGIC3_REG (0x170C)
+#define PCIE_MEEP_PORT_LOGIC4_REG (0x1710)
+#define PCIE_MEEP_PORT_LOGIC5_REG (0x1714)
+#define PCIE_MEEP_PORT_LOGIC6_REG (0x1718)
+#define PCIE_MEEP_PORT_LOGIC7_REG (0x171C)
+#define PCIE_MEEP_PORT_LOGIC8_REG (0x1720)
+#define PCIE_MEEP_PORT_LOGIC9_REG (0x1724)
+#define PCIE_MEEP_PORT_LOGIC10_REG (0x1728)
+#define PCIE_MEEP_PORT_LOGIC11_REG (0x172C)
+#define PCIE_MEEP_PORT_LOGIC12_REG (0x1730)
+#define PCIE_MEEP_PORT_LOGIC13_REG (0x1734)
+#define PCIE_MEEP_PORT_LOGIC14_REG (0x1738)
+#define PCIE_MEEP_PORT_LOGIC15_REG (0x173C)
+#define PCIE_MEEP_PORT_LOGIC16_REG (0x1748)
+#define PCIE_MEEP_PORT_LOGIC17_REG (0x174C)
+#define PCIE_MEEP_PORT_LOGIC18_REG (0x1750)
+#define PCIE_MEEP_PORT_LOGIC19_REG (0x17A8)
+#define PCIE_MEEP_PORT_LOGIC20_REG (0x17AC)
+#define PCIE_MEEP_PORT_LOGIC21_REG (0x17B0)
+#define PCIE_MEEP_PORT_LOGIC22_REG (0x180C)
+#define PCIE_MEEP_PORTLOGIC23_REG (0x1810)
+#define PCIE_MEEP_PORTLOGIC24_REG (0x1814)
+#define PCIE_MEEP_PORTLOGIC25_REG (0x1818)
+#define PCIE_MEEP_PORTLOGIC26_REG (0x181C)
+#define PCIE_MEEP_PORTLOGIC27_REG (0x1820)
+#define PCIE_MEEP_PORTLOGIC28_REG (0x1824)
+#define PCIE_MEEP_PORTLOGIC29_REG (0x1828)
+#define PCIE_MEEP_PORTLOGIC30_REG (0x182C)
+#define PCIE_MEEP_PORTLOGIC31_REG (0x1830)
+#define PCIE_MEEP_PORTLOGIC32_REG (0x1834)
+#define PCIE_MEEP_PORTLOGIC33_REG (0x1838)
+#define PCIE_MEEP_PORTLOGIC34_REG (0x183C)
+#define PCIE_MEEP_PORTLOGIC35_REG (0x1840)
+#define PCIE_MEEP_PORTLOGIC36_REG (0x1844)
+#define PCIE_MEEP_PORTLOGIC37_REG (0x1848)
+#define PCIE_MEEP_PORTLOGIC38_REG (0x184C)
+#define PCIE_MEEP_PORTLOGIC39_REG (0x1850)
+#define PCIE_MEEP_PORTLOGIC40_REG (0x1854)
+#define PCIE_MEEP_PORTLOGIC41_REG (0x1858)
+#define PCIE_MEEP_PORTLOGIC42_REG (0x185C)
+#define PCIE_MEEP_PORTLOGIC43_REG (0x1860)
+#define PCIE_MEEP_PORTLOGIC44_REG (0x1864)
+#define PCIE_MEEP_PORTLOGIC45_REG (0x1868)
+#define PCIE_MEEP_PORTLOGIC46_REG (0x186C)
+#define PCIE_MEEP_PORTLOGIC47_REG (0x1870)
+#define PCIE_MEEP_PORTLOGIC48_REG (0x1874)
+#define PCIE_MEEP_PORTLOGIC49_REG (0x1878)
+#define PCIE_MEEP_PORTLOGIC50_REG (0x187C)
+#define PCIE_MEEP_PORTLOGIC51_REG (0x1880)
+#define PCIE_MEEP_PORTLOGIC52_REG (0x1884)
+#define PCIE_MEEP_PORTLOGIC53_REG (0x1888)
+#define PCIE_MEEP_PORTLOGIC54_REG (0x1900)
+#define PCIE_MEEP_PORTLOGIC55_REG (0x1904)
+#define PCIE_MEEP_PORTLOGIC56_REG (0x908)
+#define PCIE_MEEP_PORTLOGIC57_REG (0x190C)
+#define PCIE_MEEP_PORTLOGIC58_REG (0x1910)
+#define PCIE_MEEP_PORTLOGIC59_REG (0x1914)
+#define PCIE_MEEP_PORTLOGIC60_REG (0x1918)
+#define PCIE_MEEP_PORTLOGIC61_REG (0x191C)
+#define PCIE_MEEP_PORTLOGIC62_REG (0x197C)
+#define PCIE_MEEP_PORTLOGIC63_REG (0x1980)
+#define PCIE_MEEP_PORTLOGIC64_REG (0x199C)
+#define PCIE_MEEP_PORTLOGIC65_REG (0x19A0)
+#define PCIE_MEEP_PORTLOGIC66_REG (0x19BC)
+#define PCIE_MEEP_PORTLOGIC67_REG (0x19C4)
+#define PCIE_MEEP_PORTLOGIC68_REG (0x19C8)
+#define PCIE_MEEP_PORTLOGIC69_REG (0x19CC)
+#define PCIE_MEEP_PORTLOGIC70_REG (0x19D0)
+#define PCIE_MEEP_PORTLOGIC71_REG (0x19D4)
+#define PCIE_MEEP_PORTLOGIC72_REG (0x19D8)
+#define PCIE_MEEP_PORTLOGIC73_REG (0x19DC)
+#define PCIE_MEEP_PORTLOGIC74_REG (0x19E0)
+#define PCIE_MEEP_PORTLOGIC75_REG (0x1A00)
+#define PCIE_MEEP_PORTLOGIC76_REG (0x1A10)
+#define PCIE_MEEP_PORTLOGIC77_REG (0x1A18)
+#define PCIE_MEEP_PORTLOGIC78_REG (0x1A1C)
+#define PCIE_MEEP_PORTLOGIC79_REG (0x1A24)
+#define PCIE_MEEP_PORTLOGIC80_REG (0x1A28)
+#define PCIE_MEEP_PORTLOGIC81_REG (0x1A34)
+#define PCIE_MEEP_PORTLOGIC82_REG (0x1A3C)
+#define PCIE_MEEP_PORTLOGIC83_REG (0x1A40)
+#define PCIE_MEEP_PORTLOGIC84_REG (0x1A44)
+#define PCIE_MEEP_PORTLOGIC85_REG (0xA48)
+#define PCIE_MEEP_PORTLOGIC86_REG (0xA6C)
+#define PCIE_MEEP_PORTLOGIC87_REG (0x1A70)
+#define PCIE_MEEP_PORTLOGIC88_REG (0x1A78)
+#define PCIE_MEEP_PORTLOGIC89_REG (0x1A7C)
+#define PCIE_MEEP_PORTLOGIC90_REG (0x1A80)
+#define PCIE_MEEP_PORTLOGIC91_REG (0x1A84)
+#define PCIE_MEEP_PORTLOGIC92_REG (0x1A88)
+#define PCIE_MEEP_PORTLOGIC93_REG (0x1A8C)
+#define PCIE_MEEP_PORTLOGIC94_REG (0x1A90)
+#define PCIE_MEEP_PBAR23XLAT_LOWER_REG (0x8000)
+#define PCIE_MEEP_PBAR23XLAT_UPPER_REG (0x8004)
+#define PCIE_MEEP_PBAR45XLAT_LOWER_REG (0x8008)
+#define PCIE_MEEP_PBAR45XLAT_UPPER_REG (0x800C)
+#define PCIE_MEEP_PBAR23LMT_LOWER_REG (0x8010)
+#define PCIE_MEEP_PBAR23LMT_UPPER_REG (0x8014)
+#define PCIE_MEEP_PBAR45LMT_LOWER_REG (0x8018)
+#define PCIE_MEEP_PBAR45LMT_UPPER_REG (0x801C)
+#define PCIE_MEEP_PDOORBELL_REG (0x8020)
+#define PCIE_MEEP_PDOORBELL_MASK_REG (0x8024)
+#define PCIE_MEEP_B2B_BAR01XLAT_LOWER_REG (0x8028)
+#define PCIE_MEEP_B2B_BAR01XLAT_UPPER_REG (0x802C)
+#define PCIE_MEEP_B2B_DOORBELL_REG (0x8030)
+#define PCIE_MEEP_SPAD0_REG (0x8038)
+#define PCIE_MEEP_SPAD1_REG (0x803C)
+#define PCIE_MEEP_SPAD2_REG (0x8040)
+#define PCIE_MEEP_SPAD3_REG (0x8044)
+#define PCIE_MEEP_SPAD4_REG (0x8048)
+#define PCIE_MEEP_SPAD5_REG (0x804C)
+#define PCIE_MEEP_SPAD6_REG (0x8050)
+#define PCIE_MEEP_SPAD7_REG (0x8054)
+#define PCIE_MEEP_SPAD8_REG (0x8058)
+#define PCIE_MEEP_SPAD9_REG (0x805C)
+#define PCIE_MEEP_SPAD10_REG (0x8060)
+#define PCIE_MEEP_SPAD11_REG (0x8064)
+#define PCIE_MEEP_SPAD12_REG (0x8068)
+#define PCIE_MEEP_SPAD13_REG (0x806C)
+#define PCIE_MEEP_SPAD14_REG (0x8070)
+#define PCIE_MEEP_SPAD15_REG (0x8074)
+#define PCIE_MEEP_SPAD16_REG (0x8078)
+#define PCIE_MEEP_SPAD17_REG (0x807C)
+#define PCIE_MEEP_SPAD18_REG (0x8080)
+#define PCIE_MEEP_SPAD19_REG (0x8084)
+#define PCIE_MEEP_SPAD20_REG (0x8088)
+#define PCIE_MEEP_SPAD21_REG (0x808C)
+#define PCIE_MEEP_SPAD22_REG (0x8090)
+#define PCIE_MEEP_SPAD23_REG (0x8094)
+#define PCIE_MEEP_SPAD24_REG (0x8098)
+#define PCIE_MEEP_SPAD25_REG (0x809C)
+#define PCIE_MEEP_SPAD26_REG (0x80A0)
+#define PCIE_MEEP_SPAD27_REG (0x80A4)
+#define PCIE_MEEP_SPAD28_REG (0x80A8)
+#define PCIE_MEEP_SPAD29_REG (0x80AC)
+#define PCIE_MEEP_SPAD30_REG (0x80B0)
+#define PCIE_MEEP_SPAD31_REG (0x80B4)
+#define PCIE_MEEP_PPD_REG (0x8138)
+#define PCIE_MEEP_DEVICE_VENDOR_ID_REG (0x9000)
+#define PCIE_MEEP_PCISTS_PCICMD_REG (0x9004)
+#define PCIE_MEEP_CCR_RID_REG (0x9008)
+#define PCIE_MEEP_PBAR01_BASE_LOWER_REG (0x9010)
+#define PCIE_MEEP_PBAR01_BASE_UPPER_REG (0x9014)
+#define PCIE_MEEP_PBAR23_BASE_LOWER_REG (0x9018)
+#define PCIE_MEEP_PBAR23_BASE_UPPER_REG (0x901C)
+#define PCIE_MEEP_PBAR45_BASE_LOWER_REG (0x9020)
+#define PCIE_MEEP_PBAR45_BASE_UPPER_REG (0x9024)
+#define PCIE_MEEP_CARDBUSCISPTR_REG (0x9028)
+#define PCIE_MEEP_SUBSYSTEMID_REG (0x902C)
+#define PCIE_MEEP_EXPANSIONROM_BASE_ADDR_REG (0x9030)
+#define PCIE_MEEP_CAPPTR_REG (0x9034)
+#define PCIE_MEEP_INTERRUPT_REG (0x903C)
+#define PCIE_MEEP_MSI_CAPABILITY_REGISTER_REG (0x9050)
+#define PCIE_MEEP_MSI_LOWER32_BITADDRESS_REG (0x9054)
+#define PCIE_MEEP_MSI_UPPER32_BIT_ADDRESS_REG (0x9058)
+#define PCIE_MEEP_MSI_DATA_REG (0x905C)
+#define PCIE_MEEP_MSI_MASK_REG (0x9060)
+#define PCIE_MEEP_MSI_PENDING_REG (0x9064)
+#define PCIE_MEEP_PCIE_CAPABILITY_REGISTER_REG (0x9070)
+#define PCIE_MEEP_DEVICE_CAPABILITIES_REGISTER_REG (0x9074)
+#define PCIE_MEEP_DEVICE_STATUS_REGISTER_REG (0x9078)
+#define PCIE_MEEP_LINK_CAPABILITY_REG (0x907C)
+#define PCIE_MEEP_LINK_CONTROL_STATUS_REG (0x9080)
+#define PCIE_MEEP_AER_CAP_HEADER_REG (0x9100)
+#define PCIE_MEEP_UC_ERROR_STATUS_REG (0x9104)
+#define PCIE_MEEP_UC_ERROR_MASK_REG (0x9108)
+#define PCIE_MEEP_UC_ERROR_SEVERITY_REG (0x910C)
+#define PCIE_MEEP_C_ERROR_STATUS_REG (0x9110)
+#define PCIE_MEEP_C_ERROR_MASK_REG (0x9114)
+#define PCIE_MEEP_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_REG (0x9118)
+#define PCIE_MEEP_HEADER_LOG_REGISTERS_1_REG (0x911C)
+#define PCIE_MEEP_HEADER_LOG_REGISTERS_2_REG (0x9120)
+#define PCIE_MEEP_HEADER_LOG_REGISTERS_3_REG (0x9124)
+#define PCIE_MEEP_HEADER_LOG_REGISTERS_4_REG (0x9128)
+#define PCIE_MEEP_TLP_PREFIX_LOGREGISTERS_1_REG (0x9130)
+#define PCIE_MEEP_TLP_PREFIX_LOGREGISTERS_2_REG (0x9134)
+#define PCIE_MEEP_TLP_PREFIX_LOGREGISTERS_3_REG (0x9138)
+#define PCIE_MEEP_TLP_PREFIX_LOGREGISTERS_4_REG (0x913C)
+#define PCIE_MEEP_NTB_IEP_CONFIG_SPACE_LOWER_REG (0x9700)
+#define PCIE_MEEP_NTB_IEP_CONFIG_SPACE_UPPER_REG (0x9704)
+#define PCIE_MEEP_NTB_IEP_BAR01_CTRL_REG (0x9708)
+#define PCIE_MEEP_NTB_IEP_BAR23_CTRL_REG (0x970C)
+#define PCIE_MEEP_NTB_IEP_BAR45_CTRL_REG (0x9710)
+#define PCIE_MEEP_MSI_CTRL_ADDRESS_LOWER_REG (0x9714)
+#define PCIE_MEEP_MSI_CTRL_ADDRESS_UPPER_REG (0x9718)
+#define PCIE_MEEP_MSI_CTRL_INT_EN_REG (0x971C)
+#define PCIE_MEEP_MSI_CTRL_INT0_MASK_REG (0x9720)
+#define PCIE_MEEP_MSI_CTRL_INT_STATUS_REG (0x9724)
+#define PCIE_MEEP_DBI_RO_WR_EN_REG (0x9728)
+#define PCIE_MEEP_AXI_ERR_RESPONSE_REG (0x972C)
+
+
+
+typedef union tagMeepSbar23xlatLower
+{
+
+ struct
+ {
+ UINT32 Reserved_0 : 12 ;
+ UINT32 sbar23xlat_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_SBAR23XLAT_LOWER_U;
+
+
+
+
+typedef union tagMeepSbar45xlatLower
+{
+
+ struct
+ {
+ UINT32 Reserved_1 : 12 ;
+ UINT32 sbar45xlat_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_SBAR45XLAT_LOWER_U;
+
+
+
+
+typedef union tagMeepSbar23lmtLower
+{
+
+ struct
+ {
+ UINT32 Reserved_2 : 12 ;
+ UINT32 sbar45limit_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_SBAR23LMT_LOWER_U;
+
+
+
+
+typedef union tagMeepSbar45lmtLower
+{
+
+ struct
+ {
+ UINT32 Reserved_3 : 12 ;
+ UINT32 sbar45limit_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_SBAR45LMT_LOWER_U;
+
+
+
+
+typedef union tagMeepSbar45lmtUpper
+{
+
+ struct
+ {
+ UINT32 Reserved_4 : 12 ;
+ UINT32 sbar45limit_upper : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_SBAR45LMT_UPPER_U;
+
+
+
+
+typedef union tagMeepCbdfSbdf
+{
+
+ struct
+ {
+ UINT32 sfunc : 3 ;
+ UINT32 sdev : 5 ;
+ UINT32 sbus : 8 ;
+ UINT32 cap_sfunc : 3 ;
+ UINT32 cap_sdev : 5 ;
+ UINT32 cap_sbus : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_CBDF_SBDF_U;
+
+
+
+
+typedef union tagMeepNtbCntl
+{
+
+ struct
+ {
+ UINT32 s_link_disable : 1 ;
+ UINT32 Reserved_6 : 1 ;
+ UINT32 eep_shadow_en : 1 ;
+ UINT32 Reserved_5 : 29 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_NTB_CNTL_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr0
+{
+
+ struct
+ {
+ UINT32 vendor_id : 16 ;
+ UINT32 device_id : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR0_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr1
+{
+
+ struct
+ {
+ UINT32 io_space_enable : 1 ;
+ UINT32 memory_space_enable : 1 ;
+ UINT32 bus_master_enable : 1 ;
+ UINT32 specialcycleenable : 1 ;
+ UINT32 memory_write_and_invalidate : 1 ;
+ UINT32 vga_palette_snoop_enable : 1 ;
+ UINT32 parity_error_response : 1 ;
+ UINT32 idsel_stepping_waitcycle_control : 1 ;
+ UINT32 serr_enable : 1 ;
+ UINT32 fastback_to_backenable : 1 ;
+ UINT32 interrupt_disable : 1 ;
+ UINT32 Reserved_10 : 5 ;
+ UINT32 Reserved_9 : 3 ;
+ UINT32 intx_status : 1 ;
+ UINT32 capabilitieslist : 1 ;
+ UINT32 pcibus66mhzcapable : 1 ;
+ UINT32 Reserved_8 : 1 ;
+ UINT32 fastback_to_back : 1 ;
+ UINT32 masterdataparityerror : 1 ;
+ UINT32 devsel_timing : 2 ;
+ UINT32 signaled_target_abort : 1 ;
+ UINT32 received_target_abort : 1 ;
+ UINT32 received_master_abort : 1 ;
+ UINT32 signaled_system_error : 1 ;
+ UINT32 detected_parity_error : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR1_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr2
+{
+
+ struct
+ {
+ UINT32 revision_identification : 8 ;
+ UINT32 Reserved_11 : 8 ;
+ UINT32 sub_class : 8 ;
+ UINT32 baseclass : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR2_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr3
+{
+
+ struct
+ {
+ UINT32 cache_line_size : 8 ;
+ UINT32 mstr_lat_tmr : 8 ;
+ UINT32 multi_function_device : 7 ;
+ UINT32 hdr_type : 1 ;
+ UINT32 bist : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR3_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr4
+{
+
+ struct
+ {
+ UINT32 sbar01_space_inicator : 1 ;
+ UINT32 sbar01_type : 2 ;
+ UINT32 sbar01_prefetchable : 1 ;
+ UINT32 sbar01_lower : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR4_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr6
+{
+
+ struct
+ {
+ UINT32 sbar23_space_inicator : 1 ;
+ UINT32 sbar23_type : 2 ;
+ UINT32 sbar23_prefetchable : 1 ;
+ UINT32 Reserved_12 : 8 ;
+ UINT32 sbar23_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR6_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr8
+{
+
+ struct
+ {
+ UINT32 sbar45_space_inicator : 1 ;
+ UINT32 sbar45_type : 2 ;
+ UINT32 sbar45_prefetchable : 1 ;
+ UINT32 Reserved_13 : 8 ;
+ UINT32 sbar45_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR8_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr11
+{
+
+ struct
+ {
+ UINT32 subsystem_vendor_id : 16 ;
+ UINT32 subsystemid : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR11_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr13
+{
+
+ struct
+ {
+ UINT32 cap_ptr : 8 ;
+ UINT32 Reserved_14 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR13_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr15
+{
+
+ struct
+ {
+ UINT32 int_line : 8 ;
+ UINT32 int_pin : 8 ;
+ UINT32 Min_Grant : 8 ;
+ UINT32 Max_Latency : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR15_U;
+
+
+
+
+typedef union tagMeepPciMsiCap0
+{
+
+ struct
+ {
+ UINT32 msi_cap_id : 8 ;
+ UINT32 next_capability_pointer : 8 ;
+ UINT32 msi_enabled : 1 ;
+ UINT32 multiple_message_capable : 3 ;
+ UINT32 multiple_message_enabled : 3 ;
+ UINT32 msi_64_en : 1 ;
+ UINT32 pvm : 1 ;
+ UINT32 Reserved_18 : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCI_MSI_CAP0_U;
+
+
+
+
+typedef union tagMeepPciMsiCap1
+{
+
+ struct
+ {
+ UINT32 Reserved_20 : 2 ;
+ UINT32 msi_addr_low : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCI_MSI_CAP1_U;
+
+
+
+
+typedef union tagMeepPciMsiCap3
+{
+
+ struct
+ {
+ UINT32 msi_data : 16 ;
+ UINT32 Reserved_21 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCI_MSI_CAP3_U;
+
+
+
+
+typedef union tagMeepPcieCap0
+{
+
+ struct
+ {
+ UINT32 pcie_cap_id : 8 ;
+ UINT32 pcie_next_ptr : 8 ;
+ UINT32 pcie_capability_version : 4 ;
+ UINT32 device_port_type : 4 ;
+ UINT32 slot_implemented : 1 ;
+ UINT32 interrupt_message_number : 5 ;
+ UINT32 Reserved_22 : 2 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCIE_CAP0_U;
+
+
+
+
+typedef union tagMeepPcieCap1
+{
+
+ struct
+ {
+ UINT32 max_payload_size_supported : 3 ;
+ UINT32 phantom_function_supported : 2 ;
+ UINT32 extended_tagfield_supported : 1 ;
+ UINT32 endpoint_l0sacceptable_latency : 3 ;
+ UINT32 endpoint_l1acceptable_latency : 3 ;
+ UINT32 undefined : 3 ;
+ UINT32 Reserved_24 : 3 ;
+ UINT32 captured_slot_power_limit_value : 8 ;
+ UINT32 captured_slot_power_limit_scale : 2 ;
+ UINT32 function_level_reset : 1 ;
+ UINT32 dev_cap : 3 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCIE_CAP1_U;
+
+
+
+
+typedef union tagMeepPcieCap2
+{
+
+ struct
+ {
+ UINT32 correctable_error_reporting_enable : 1 ;
+ UINT32 non_fatal_error_reporting_enable : 1 ;
+ UINT32 fatal_error_reporting_enable : 1 ;
+ UINT32 urenable : 1 ;
+ UINT32 enable_relaxed_ordering : 1 ;
+ UINT32 max_payload_size : 3 ;
+ UINT32 extended_tagfieldenable : 1 ;
+ UINT32 phantom_function_enable : 1 ;
+ UINT32 auxpowerpmenable : 1 ;
+ UINT32 enablenosnoop : 1 ;
+ UINT32 max_read_request_size : 3 ;
+ UINT32 Reserved_26 : 1 ;
+ UINT32 correctableerrordetected : 1 ;
+ UINT32 non_fatalerrordetected : 1 ;
+ UINT32 fatalerrordetected : 1 ;
+ UINT32 unsupportedrequestdetected : 1 ;
+ UINT32 auxpowerdetected : 1 ;
+ UINT32 transactionpending : 1 ;
+ UINT32 Reserved_25 : 10 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCIE_CAP2_U;
+
+
+
+
+typedef union tagMeepPcieCap3
+{
+
+ struct
+ {
+ UINT32 max_link_speed : 4 ;
+ UINT32 max_link_width : 6 ;
+ UINT32 active_state_power_management : 2 ;
+ UINT32 l0s_exitlatency : 3 ;
+ UINT32 l1_exit_latency : 3 ;
+ UINT32 clock_power_management : 1 ;
+ UINT32 surprise_down_error_report_cap : 1 ;
+ UINT32 data_link_layer_active_report_cap : 1 ;
+ UINT32 link_bandwidth_noti_cap : 1 ;
+ UINT32 aspm_option_compliance : 1 ;
+ UINT32 Reserved_27 : 1 ;
+ UINT32 port_number : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCIE_CAP3_U;
+
+
+
+
+typedef union tagMeepPcieCap4
+{
+
+ struct
+ {
+ UINT32 active_state_power_management : 2 ;
+ UINT32 Reserved_30 : 1 ;
+ UINT32 rcb : 1 ;
+ UINT32 link_disable : 1 ;
+ UINT32 retrain_link : 1 ;
+ UINT32 common_clock_config : 1 ;
+ UINT32 extended_sync : 1 ;
+ UINT32 enable_clock_pwr_management : 1 ;
+ UINT32 hw_auto_width_disable : 1 ;
+ UINT32 link_bandwidth_management_int_en : 1 ;
+ UINT32 link_auto_bandwidth_int_en : 1 ;
+ UINT32 Reserved_29 : 4 ;
+ UINT32 current_link_speed : 4 ;
+ UINT32 negotiated_link_width : 6 ;
+ UINT32 Reserved_28 : 1 ;
+ UINT32 link_training : 1 ;
+ UINT32 slot_clock_configration : 1 ;
+ UINT32 data_link_layer_active : 1 ;
+ UINT32 link_bandwidth_management_status : 1 ;
+ UINT32 link_auto_bandwidth_status : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCIE_CAP4_U;
+
+
+
+
+typedef union tagMeepPcieCap5
+{
+
+ struct
+ {
+ UINT32 attentionbuttonpresent : 1 ;
+ UINT32 powercontrollerpresent : 1 ;
+ UINT32 mrlsensorpresent : 1 ;
+ UINT32 attentionindicatorpresent : 1 ;
+ UINT32 powerindicatorpresent : 1 ;
+ UINT32 hot_plugsurprise : 1 ;
+ UINT32 hot_plugcapable : 1 ;
+ UINT32 slotpowerlimitvalue : 8 ;
+ UINT32 slotpowerlimitscale : 2 ;
+ UINT32 electromechanicalinterlockpresen : 1 ;
+ UINT32 no_cmd_complete_support : 1 ;
+ UINT32 phy_slot_number : 13 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCIE_CAP5_U;
+
+
+
+
+typedef union tagMeepPcieCap6
+{
+
+ struct
+ {
+ UINT32 attentionbuttonpressedenable : 1 ;
+ UINT32 powerfaultdetectedenable : 1 ;
+ UINT32 mrlsensorchangedenable : 1 ;
+ UINT32 presencedetectchangedenable : 1 ;
+ UINT32 commandcompletedinterruptenable : 1 ;
+ UINT32 hot_pluginterruptenable : 1 ;
+ UINT32 attentionindicatorcontrol : 2 ;
+ UINT32 powerindicatorcontrol : 2 ;
+ UINT32 powercontrollercontrol : 1 ;
+ UINT32 electromechanicalinterlockcontrol : 1 ;
+ UINT32 datalinklayerstatechangedenable : 1 ;
+ UINT32 Reserved_31 : 3 ;
+ UINT32 attentionbuttonpressed : 1 ;
+ UINT32 powerfaultdetected : 1 ;
+ UINT32 mrlsensorchanged : 1 ;
+ UINT32 presencedetectchanged : 1 ;
+ UINT32 commandcompleted : 1 ;
+ UINT32 mrlsensorstate : 1 ;
+ UINT32 presencedetectstate : 1 ;
+ UINT32 electromechanicalinterlockstatus : 1 ;
+ UINT32 datalinklayerstatechanged : 1 ;
+ UINT32 slot_ctrl_status : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCIE_CAP6_U;
+
+
+
+
+typedef union tagMeepPcieCap7
+{
+
+ struct
+ {
+ UINT32 systemerroroncorrectableerrorenable : 1 ;
+ UINT32 systemerroronnon_fatalerrorenable : 1 ;
+ UINT32 systemerroronfatalerrorenable : 1 ;
+ UINT32 pmeinterruptenable : 1 ;
+ UINT32 crssoftwarevisibilityenable : 1 ;
+ UINT32 Reserved_32 : 11 ;
+ UINT32 crssoftwarevisibility : 1 ;
+ UINT32 root_cap : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCIE_CAP7_U;
+
+
+
+
+typedef union tagMeepPcieCap8
+{
+
+ struct
+ {
+ UINT32 pmerequesterid : 16 ;
+ UINT32 pmestatus : 1 ;
+ UINT32 pmepending : 1 ;
+ UINT32 root_status : 14 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCIE_CAP8_U;
+
+
+
+
+typedef union tagMeepPcieCap9
+{
+
+ struct
+ {
+ UINT32 completiontimeoutrangessupported : 4 ;
+ UINT32 completiontimeoutdisablesupported : 1 ;
+ UINT32 ariforwardingsupported : 1 ;
+ UINT32 atomicoproutingsupported : 1 ;
+ UINT32 _2_bitatomicopcompletersupported : 1 ;
+ UINT32 _4_bitatomicopcompletersupported : 1 ;
+ UINT32 _28_bitcascompletersupported : 1 ;
+ UINT32 noro_enabledpr_prpassing : 1 ;
+ UINT32 Reserved_33 : 1 ;
+ UINT32 tphcompletersupported : 2 ;
+ UINT32 dev_cap2 : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCIE_CAP9_U;
+
+
+
+
+typedef union tagMeepPcieCap10
+{
+
+ struct
+ {
+ UINT32 completiontimeoutvalue : 4 ;
+ UINT32 completiontimeoutdisable : 1 ;
+ UINT32 ariforwardingsupported : 1 ;
+ UINT32 atomicoprequesterenable : 1 ;
+ UINT32 atomicopegressblocking : 1 ;
+ UINT32 idorequestenable : 1 ;
+ UINT32 idocompletionenable : 1 ;
+ UINT32 dev_ctrl2 : 22 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCIE_CAP10_U;
+
+
+
+
+typedef union tagMeepPcieCap11
+{
+
+ struct
+ {
+ UINT32 Reserved_35 : 1 ;
+ UINT32 gen1_suport : 1 ;
+ UINT32 gen2_suport : 1 ;
+ UINT32 gen3_suport : 1 ;
+ UINT32 Reserved_34 : 4 ;
+ UINT32 crosslink_supported : 1 ;
+ UINT32 link_cap2 : 23 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCIE_CAP11_U;
+
+
+
+
+typedef union tagMeepPcieCap12
+{
+
+ struct
+ {
+ UINT32 targetlinkspeed : 4 ;
+ UINT32 entercompliance : 1 ;
+ UINT32 hardwareautonomousspeeddisa : 1 ;
+ UINT32 selectablede_empha : 1 ;
+ UINT32 transmitmargin : 3 ;
+ UINT32 _entermodifiedcompliance : 1 ;
+ UINT32 compliancesos : 1 ;
+ UINT32 de_emphasislevel : 4 ;
+ UINT32 currentde_emphasislevel : 1 ;
+ UINT32 equalizationcomplete : 1 ;
+ UINT32 equalizationphase1successful : 1 ;
+ UINT32 equalizationphase2successful : 1 ;
+ UINT32 equalizationphase3successful : 1 ;
+ UINT32 linkequalizationrequest : 1 ;
+ UINT32 link_ctrl2_status2 : 10 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCIE_CAP12_U;
+
+
+
+
+typedef union tagMeepSlotCap
+{
+
+ struct
+ {
+ UINT32 slotnumberingcapabilitiesid : 8 ;
+ UINT32 nextcapabilitypointer : 8 ;
+ UINT32 add_incardslotsprovided : 5 ;
+ UINT32 firstinchassis : 1 ;
+ UINT32 Reserved_36 : 2 ;
+ UINT32 slot_cap : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_SLOT_CAP_U;
+
+
+
+
+typedef union tagMeepAerCap0
+{
+
+ struct
+ {
+ UINT32 pciexpressextendedcapabilityid : 16 ;
+ UINT32 capabilityversion : 4 ;
+ UINT32 aer_cap_hdr : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_AER_CAP0_U;
+
+
+
+
+typedef union tagMeepAerCap1
+{
+
+ struct
+ {
+ UINT32 Reserved_42 : 1 ;
+ UINT32 Reserved_41 : 3 ;
+ UINT32 datalinkprotocolerrorsta : 1 ;
+ UINT32 surprisedownerrorstatus : 1 ;
+ UINT32 Reserved_40 : 6 ;
+ UINT32 poisonedtlpstatu : 1 ;
+ UINT32 flowcontrolprotocolerrorst : 1 ;
+ UINT32 completiontimeouts : 1 ;
+ UINT32 completerabortstatus : 1 ;
+ UINT32 receiveroverflowstatus : 1 ;
+ UINT32 malformedtlpstatus : 1 ;
+ UINT32 ecrcerrorstatus : 1 ;
+ UINT32 ecrcerrorstat : 1 ;
+ UINT32 unsupportedrequesterrorstatus : 1 ;
+ UINT32 Reserved_39 : 3 ;
+ UINT32 atomicopegressblockedstatus : 1 ;
+ UINT32 uncorr_err_status : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_AER_CAP1_U;
+
+
+
+
+typedef union tagMeepAerCap2
+{
+
+ struct
+ {
+ UINT32 Reserved_46 : 1 ;
+ UINT32 Reserved_45 : 3 ;
+ UINT32 datalinkprotocolerrormask : 1 ;
+ UINT32 surprisedownerrormask : 1 ;
+ UINT32 Reserved_44 : 6 ;
+ UINT32 poisonedtlpmask : 1 ;
+ UINT32 flowcontrolprotocolerrormask : 1 ;
+ UINT32 completiontimeoutmask : 1 ;
+ UINT32 completerabortmask : 1 ;
+ UINT32 unexpectedcompletionmask : 1 ;
+ UINT32 receiveroverflowmask : 1 ;
+ UINT32 malformedtlpmask : 1 ;
+ UINT32 ecrcerrormask : 1 ;
+ UINT32 unsupportedrequesterrormask : 1 ;
+ UINT32 Reserved_43 : 3 ;
+ UINT32 atomicopegressblockedmask : 1 ;
+ UINT32 uncorr_err_mask : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_AER_CAP2_U;
+
+
+
+
+typedef union tagMeepAerCap3
+{
+
+ struct
+ {
+ UINT32 Reserved_50 : 1 ;
+ UINT32 Reserved_49 : 3 ;
+ UINT32 datalinkprotocolerrorsever : 1 ;
+ UINT32 surprisedownerrorseverity : 1 ;
+ UINT32 Reserved_48 : 6 ;
+ UINT32 poisonedtlpseverity : 1 ;
+ UINT32 flowcontrolprotocolerrorseveri : 1 ;
+ UINT32 completiontimeoutseverity : 1 ;
+ UINT32 completerabortseverity : 1 ;
+ UINT32 unexpectedcompletionseverity : 1 ;
+ UINT32 receiveroverflowseverity : 1 ;
+ UINT32 malformedtlpseverity : 1 ;
+ UINT32 ecrcerrorseverity : 1 ;
+ UINT32 unsupportedrequesterrorseverity : 1 ;
+ UINT32 Reserved_47 : 3 ;
+ UINT32 atomicopegressblockedseverity : 1 ;
+ UINT32 uncorr_err_ser : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_AER_CAP3_U;
+
+
+
+
+typedef union tagMeepAerCap4
+{
+
+ struct
+ {
+ UINT32 receivererrorstatus : 1 ;
+ UINT32 Reserved_52 : 5 ;
+ UINT32 badtlpstatus : 1 ;
+ UINT32 baddllpstatus : 1 ;
+ UINT32 replay_numrolloverstatus : 1 ;
+ UINT32 Reserved_51 : 3 ;
+ UINT32 replytimertimeoutstatus : 1 ;
+ UINT32 advisorynon_fatalerrorstatus : 1 ;
+ UINT32 corr_err_status : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_AER_CAP4_U;
+
+
+
+
+typedef union tagMeepAerCap5
+{
+
+ struct
+ {
+ UINT32 receivererrormask : 1 ;
+ UINT32 Reserved_54 : 5 ;
+ UINT32 badtlpmask : 1 ;
+ UINT32 baddllpmask : 1 ;
+ UINT32 replay_numrollovermask : 1 ;
+ UINT32 Reserved_53 : 3 ;
+ UINT32 replytimertimeoutmask : 1 ;
+ UINT32 advisorynon_fatalerrormask : 1 ;
+ UINT32 corr_err_mask : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_AER_CAP5_U;
+
+
+
+
+typedef union tagMeepAerCap6
+{
+
+ struct
+ {
+ UINT32 firsterrorpointer : 5 ;
+ UINT32 ecrcgenerationcapability : 1 ;
+ UINT32 ecrcgenerationenable : 1 ;
+ UINT32 ecrccheckcapable : 1 ;
+ UINT32 ecrccheckenable : 1 ;
+ UINT32 adv_cap_ctrl : 23 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_AER_CAP6_U;
+
+
+
+
+typedef union tagMeepAerCap11
+{
+
+ struct
+ {
+ UINT32 correctableerrorreportingenable : 1 ;
+ UINT32 non_fatalerrorreportingenable : 1 ;
+ UINT32 fatalerrorreportingenable : 1 ;
+ UINT32 root_err_cmd : 29 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_AER_CAP11_U;
+
+
+
+
+typedef union tagMeepAerCap12
+{
+
+ struct
+ {
+ UINT32 err_correceived : 1 ;
+ UINT32 multipleerr_correceived : 1 ;
+ UINT32 err_fatal_nonfatalreceived : 1 ;
+ UINT32 multipleerr_fatal_nonfatalreceived : 1 ;
+ UINT32 firstuncorrectablefatal : 1 ;
+ UINT32 non_fatalerrormessagesreceived : 1 ;
+ UINT32 fatalerrormessagesreceived : 1 ;
+ UINT32 Reserved_57 : 20 ;
+ UINT32 root_err_status : 5 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_AER_CAP12_U;
+
+
+
+
+typedef union tagMeepAerCap13
+{
+
+ struct
+ {
+ UINT32 err_corsourceidentification : 16 ;
+ UINT32 err_src_id : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_AER_CAP13_U;
+
+
+
+
+typedef union tagMeepVcCap0
+{
+
+ struct
+ {
+ UINT32 pciexpressextendedcapabilityid : 16 ;
+ UINT32 capabilityversion : 4 ;
+ UINT32 vc_cap_hdr : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_VC_CAP0_U;
+
+
+
+
+typedef union tagMeepVcCap1
+{
+
+ struct
+ {
+ UINT32 extendedvccount : 3 ;
+ UINT32 Reserved_60 : 1 ;
+ UINT32 lowpriorityextendedvccount : 3 ;
+ UINT32 Reserved_59 : 1 ;
+ UINT32 referenceclock : 2 ;
+ UINT32 portarbitrationtableentrysize : 2 ;
+ UINT32 vc_cap1 : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_VC_CAP1_U;
+
+
+
+
+typedef union tagMeepVcCap2
+{
+
+ struct
+ {
+ UINT32 vcarbitrationcapability : 8 ;
+ UINT32 Reserved_61 : 16 ;
+ UINT32 vc_cap2 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_VC_CAP2_U;
+
+
+
+
+typedef union tagMeepVcCap3
+{
+
+ struct
+ {
+ UINT32 loadvcarbitrationtable : 1 ;
+ UINT32 vcarbitrationselect : 3 ;
+ UINT32 Reserved_63 : 12 ;
+ UINT32 arbitrationtablestatus : 1 ;
+ UINT32 Reserved_62 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_VC_CAP3_U;
+
+
+
+
+typedef union tagMeepVcCap4
+{
+
+ struct
+ {
+ UINT32 portarbitrationcapability : 8 ;
+ UINT32 Reserved_66 : 6 ;
+ UINT32 Reserved_65 : 1 ;
+ UINT32 rejectsnooptransactions : 1 ;
+ UINT32 maximumtimeslots : 7 ;
+ UINT32 Reserved_64 : 1 ;
+ UINT32 vc_res_cap : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_VC_CAP4_U;
+
+
+
+
+typedef union tagMeepVcCap5
+{
+
+ struct
+ {
+ UINT32 tc_vcmap : 8 ;
+ UINT32 Reserved_69 : 8 ;
+ UINT32 loadportarbitrationtable : 1 ;
+ UINT32 portarbitrationselec : 3 ;
+ UINT32 Reserved_68 : 4 ;
+ UINT32 vcid : 3 ;
+ UINT32 Reserved_67 : 4 ;
+ UINT32 vc_res_ctrl : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_VC_CAP5_U;
+
+
+
+
+typedef union tagMeepVcCap6
+{
+
+ struct
+ {
+ UINT32 Reserved_70 : 16 ;
+ UINT32 portarbitrationtablestatus : 1 ;
+ UINT32 vcnegotiationpending : 1 ;
+ UINT32 vc_res_status : 14 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_VC_CAP6_U;
+
+
+
+
+typedef union tagMeepVcCap7
+{
+
+ struct
+ {
+ UINT32 portarbitrationcapability : 8 ;
+ UINT32 Reserved_73 : 6 ;
+ UINT32 Reserved_72 : 1 ;
+ UINT32 rejectsnooptransactions : 1 ;
+ UINT32 maximumtimeslots : 7 ;
+ UINT32 Reserved_71 : 1 ;
+ UINT32 vc_res_cap0 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_VC_CAP7_U;
+
+
+
+
+typedef union tagMeepVcCap8
+{
+
+ struct
+ {
+ UINT32 tc_vcmap : 8 ;
+ UINT32 Reserved_76 : 8 ;
+ UINT32 loadportarbitrationtable : 1 ;
+ UINT32 portarbitrationselect : 3 ;
+ UINT32 Reserved_75 : 4 ;
+ UINT32 vcid : 3 ;
+ UINT32 Reserved_74 : 4 ;
+ UINT32 vc_res_ctrl0 : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_VC_CAP8_U;
+
+
+
+
+typedef union tagMeepVcCap9
+{
+
+ struct
+ {
+ UINT32 Reserved_77 : 16 ;
+ UINT32 arbitrationtablestatus : 1 ;
+ UINT32 vcnegotiationpending : 1 ;
+ UINT32 vc_res_status0 : 14 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_VC_CAP9_U;
+
+
+
+
+typedef union tagMeepPortLogic0
+{
+
+ struct
+ {
+ UINT32 ack_lat_timer : 16 ;
+ UINT32 replay_timer : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC0_U;
+
+
+
+
+typedef union tagMeepPortLogic2
+{
+
+ struct
+ {
+ UINT32 linknumber : 8 ;
+ UINT32 Reserved_80 : 7 ;
+ UINT32 forcelink : 1 ;
+ UINT32 linkstate : 6 ;
+ UINT32 Reserved_79 : 2 ;
+ UINT32 port_force_link : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC2_U;
+
+
+
+
+typedef union tagMeepPortLogic3
+{
+
+ struct
+ {
+ UINT32 ackfrequency : 8 ;
+ UINT32 n_fts : 8 ;
+ UINT32 commonclockn_fts : 8 ;
+ UINT32 l0sentrancelatency : 3 ;
+ UINT32 l1entrancelatency : 3 ;
+ UINT32 enteraspml1withoutreceiveinl0s : 1 ;
+ UINT32 ack_aspm : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC3_U;
+
+
+
+
+typedef union tagMeepPortLogic4
+{
+
+ struct
+ {
+ UINT32 vendorspecificdllprequest : 1 ;
+ UINT32 scrambledisable : 1 ;
+ UINT32 loopbackenable : 1 ;
+ UINT32 resetassert : 1 ;
+ UINT32 Reserved_83 : 1 ;
+ UINT32 dlllinkenable : 1 ;
+ UINT32 Reserved_82 : 1 ;
+ UINT32 fastlinkmode : 1 ;
+ UINT32 Reserved_81 : 8 ;
+ UINT32 linkmodeenable : 6 ;
+ UINT32 crosslinkenable : 1 ;
+ UINT32 crosslinkactive : 1 ;
+ UINT32 port_link_ctrl : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC4_U;
+
+
+
+
+typedef union tagMeepPortLogic5
+{
+
+ struct
+ {
+ UINT32 insertlaneskewfortransmit : 24 ;
+ UINT32 flowcontroldisable : 1 ;
+ UINT32 ack_nakdisable : 1 ;
+ UINT32 Reserved_84 : 5 ;
+ UINT32 lane_skew : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC5_U;
+
+
+
+
+typedef union tagMeepPortLogic6
+{
+
+ struct
+ {
+ UINT32 numberoftssymbols : 4 ;
+ UINT32 Reserved_86 : 4 ;
+ UINT32 numberofskpsymbols : 3 ;
+ UINT32 Reserved_85 : 3 ;
+ UINT32 timermodifierforreplaytimer : 5 ;
+ UINT32 timermodifierforack_naklatencytimer : 5 ;
+ UINT32 timermodifierforflowcontrolwatchdogtimer : 5 ;
+ UINT32 sym_num : 3 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC6_U;
+
+
+
+
+typedef union tagMeepPortLogic7
+{
+
+ struct
+ {
+ UINT32 vc0posteddataqueuedepth : 11 ;
+ UINT32 Reserved_87 : 4 ;
+ UINT32 sym_timer : 1 ;
+ UINT32 maskfunctionmismatchfilteringfo : 1 ;
+ UINT32 maskpoisonedtlpfiltering : 1 ;
+ UINT32 maskbarmatchfiltering : 1 ;
+ UINT32 masktype1configurationrequestfiltering : 1 ;
+ UINT32 masklockedrequestfiltering : 1 ;
+ UINT32 masktagerrorrulesforreceivedcompletions : 1 ;
+ UINT32 maskrequesteridmismatcherrorforreceivedcompletions : 1 ;
+ UINT32 maskfunctionmismatcherrorforreceivedcompletions : 1 ;
+ UINT32 mask_traffic_classmis_match_error_forreceived_completions : 1 ;
+ UINT32 mask_attributesmismatcherrorforreceivedcompletions : 1 ;
+ UINT32 mask_length_mismatch_error_forreceive_dcompletions : 1 ;
+ UINT32 maske_crcerror_filtering : 1 ;
+ UINT32 maske_crcerror_filtering_forcompletions : 1 ;
+ UINT32 message_control : 1 ;
+ UINT32 maskfilteringofreceived : 1 ;
+ UINT32 flt_mask1 : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC7_U;
+
+
+
+
+typedef union tagMeepPortLogic8
+{
+
+ struct
+ {
+ UINT32 cx_flt_mask_venmsg0_drop : 1 ;
+ UINT32 cx_flt_mask_venmsg1_drop : 1 ;
+ UINT32 cx_flt_mask_dabort_4ucpl : 1 ;
+ UINT32 cx_flt_mask_handle_flush : 1 ;
+ UINT32 flt_mask2 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC8_U;
+
+
+
+
+typedef union tagMeepPortLogic9
+{
+
+ struct
+ {
+ UINT32 amba_multi_outbound_decomp_np : 1 ;
+ UINT32 amba_obnp_ctrl : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC9_U;
+
+
+
+
+typedef union tagMeepPortLogic12
+{
+
+ struct
+ {
+ UINT32 transmitposteddatafccredits : 12 ;
+ UINT32 transmitpostedheaderfccredits : 8 ;
+ UINT32 tx_pfc_status : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC12_U;
+
+
+
+
+typedef union tagMeepPortLogic13
+{
+
+ struct
+ {
+ UINT32 transmitnon_posteddatafccredits : 12 ;
+ UINT32 transmitnon_postedheaderfccredits : 8 ;
+ UINT32 tx_npfc_status : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC13_U;
+
+
+
+
+typedef union tagMeepPortLogic14
+{
+
+ struct
+ {
+ UINT32 transmitcompletiondatafccredits : 12 ;
+ UINT32 transmitcompletionheaderfccredits : 8 ;
+ UINT32 tx_cplfc_status : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC14_U;
+
+
+
+
+typedef union tagMeepPortLogic15
+{
+
+ struct
+ {
+ UINT32 rx_tlp_fc_credit_not_retured : 1 ;
+ UINT32 tx_retry_buf_not_empty : 1 ;
+ UINT32 rx_queue_not_empty : 1 ;
+ UINT32 Reserved_89 : 13 ;
+ UINT32 fc_latency_timer_override_value : 13 ;
+ UINT32 Reserved_88 : 2 ;
+ UINT32 fc_latency_timer_override_en : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC15_U;
+
+
+
+
+typedef union tagMeepPortLogic16
+{
+
+ struct
+ {
+ UINT32 vc0posteddatacredits : 12 ;
+ UINT32 vc0postedheadercredits : 8 ;
+ UINT32 Reserved_91 : 1 ;
+ UINT32 vc0_postedtlpqueuemode : 1 ;
+ UINT32 vc0postedtlpqueuemode : 1 ;
+ UINT32 vc0postedtlpqueuemo : 1 ;
+ UINT32 Reserved_90 : 6 ;
+ UINT32 tlptypeorderingforvc0 : 1 ;
+ UINT32 rx_pque_ctrl : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC16_U;
+
+
+
+
+typedef union tagMeepPortLogic17
+{
+
+ struct
+ {
+ UINT32 vc0non_posteddatarcredits : 12 ;
+ UINT32 vc0non_postedheadercredits : 8 ;
+ UINT32 Reserved_93 : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC17_U;
+
+
+
+
+typedef union tagMeepPortLogic18
+{
+
+ struct
+ {
+ UINT32 vco_comp_data_credits : 12 ;
+ UINT32 vc0_cpl_header_credt : 8 ;
+ UINT32 Reserved_94 : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC18_U;
+
+
+
+
+typedef union tagMeepPortLogic19
+{
+
+ struct
+ {
+ UINT32 vco_posted_data_que_path : 14 ;
+ UINT32 Reserved_95 : 2 ;
+ UINT32 vco_posted_head_queue_depth : 10 ;
+ UINT32 vc_pbuf_ctrl : 6 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC19_U;
+
+
+
+
+typedef union tagMeepPortLogic20
+{
+
+ struct
+ {
+ UINT32 vco_np_data_que_depth : 14 ;
+ UINT32 Reserved_97 : 2 ;
+ UINT32 vco_np_header_que_depth : 10 ;
+ UINT32 vc_npbuf_ctrl : 6 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC20_U;
+
+
+
+
+typedef union tagMeepPortLogic21
+{
+
+ struct
+ {
+ UINT32 vco_comp_data_queue_depth : 14 ;
+ UINT32 Reserved_99 : 2 ;
+ UINT32 vco_posted_head_queue_depth : 10 ;
+ UINT32 Reserved_98 : 6 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC21_U;
+
+
+
+
+typedef union tagMeepPortLogic22
+{
+
+ struct
+ {
+ UINT32 n_fts : 8 ;
+ UINT32 pre_determ_num_of_lane : 9 ;
+ UINT32 det_sp_change : 1 ;
+ UINT32 config_phy_tx_sw : 1 ;
+ UINT32 config_tx_comp_rcv_bit : 1 ;
+ UINT32 set_emp_level : 1 ;
+ UINT32 Reserved_100 : 11 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC22_U;
+
+
+
+
+typedef union tagMeepPortlogic25
+{
+
+ struct
+ {
+ UINT32 remote_rd_req_size : 3 ;
+ UINT32 Reserved_103 : 5 ;
+ UINT32 remote_max_brd_tag : 8 ;
+ UINT32 Reserved_102 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC25_U;
+
+
+
+
+typedef union tagMeepPortlogic26
+{
+
+ struct
+ {
+ UINT32 resize_master_resp_compser : 1 ;
+ UINT32 axi_ctrl1 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC26_U;
+
+
+
+
+typedef union tagMeepPortlogic55
+{
+
+ struct
+ {
+ UINT32 iatu1_type : 5 ;
+ UINT32 iatu1_tc : 3 ;
+ UINT32 iatu1_td : 1 ;
+ UINT32 iatu1_attr : 2 ;
+ UINT32 Reserved_107 : 5 ;
+ UINT32 iatu1_at : 2 ;
+ UINT32 Reserved_106 : 2 ;
+ UINT32 iatu1_id : 3 ;
+ UINT32 Reserved_105 : 9 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC55_U;
+
+
+
+
+typedef union tagMeepPortlogic56
+{
+
+ struct
+ {
+ UINT32 iatu2_type : 8 ;
+ UINT32 iatu2_bar_num : 3 ;
+ UINT32 Reserved_111 : 3 ;
+ UINT32 iatu2_tc_match_en : 1 ;
+ UINT32 iatu2_td_match_en : 1 ;
+ UINT32 iatu2_attr_match_en : 1 ;
+ UINT32 Reserved_110 : 1 ;
+ UINT32 iatu2_at_match_en : 1 ;
+ UINT32 iatu2_func_num_match_en : 1 ;
+ UINT32 iatu2_virtual_func_num_match_en : 1 ;
+ UINT32 message_code_match_en : 1 ;
+ UINT32 Reserved_109 : 2 ;
+ UINT32 iatu2_response_code : 2 ;
+ UINT32 Reserved_108 : 1 ;
+ UINT32 iatu2_fuzzy_type_match_mode : 1 ;
+ UINT32 iatu2_cfg_shift_mode : 1 ;
+ UINT32 iatu2_ivert_mode : 1 ;
+ UINT32 iatu2_match_mode : 1 ;
+ UINT32 iatu2_region_en : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC56_U;
+
+
+
+
+typedef union tagMeepPortlogic57
+{
+
+ struct
+ {
+ UINT32 iatu_start_low : 12 ;
+ UINT32 iatu_start_high : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC57_U;
+
+
+
+
+typedef union tagMeepPortlogic59
+{
+
+ struct
+ {
+ UINT32 iatu_limit_low : 12 ;
+ UINT32 iatu_limit_high : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC59_U;
+
+
+
+
+typedef union tagMeepPortlogic60
+{
+
+ struct
+ {
+ UINT32 xlated_addr_high : 12 ;
+ UINT32 xlated_addr_low : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC60_U;
+
+
+
+
+typedef union tagMeepPortlogic62
+{
+
+ struct
+ {
+ UINT32 dma_wr_eng_en : 1 ;
+ UINT32 dma_wr_ena : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC62_U;
+
+
+
+
+typedef union tagMeepPortlogic63
+{
+
+ struct
+ {
+ UINT32 wr_doorbell_num : 3 ;
+ UINT32 Reserved_115 : 28 ;
+ UINT32 dma_wr_dbell_stop : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC63_U;
+
+
+
+
+typedef union tagMeepPortlogic64
+{
+
+ struct
+ {
+ UINT32 dma_read_eng_en : 1 ;
+ UINT32 dma_rd_ena : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC64_U;
+
+
+
+
+typedef union tagMeepPortlogic65
+{
+
+ struct
+ {
+ UINT32 rd_doorbell_num : 3 ;
+ UINT32 Reserved_117 : 28 ;
+ UINT32 dma_rd_dbell_stop : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC65_U;
+
+
+
+
+typedef union tagMeepPortlogic66
+{
+
+ struct
+ {
+ UINT32 done_int_status : 1 ;
+ UINT32 Reserved_119 : 15 ;
+ UINT32 abort_int_status : 1 ;
+ UINT32 Reserved_118 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC66_U;
+
+
+
+
+typedef union tagMeepPortlogic67
+{
+
+ struct
+ {
+ UINT32 done_int_mask : 1 ;
+ UINT32 Reserved_122 : 15 ;
+ UINT32 abort_int_mask : 1 ;
+ UINT32 Reserved_121 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC67_U;
+
+
+
+
+typedef union tagMeepPortlogic68
+{
+
+ struct
+ {
+ UINT32 done_int_clr : 1 ;
+ UINT32 Reserved_125 : 15 ;
+ UINT32 abort_int_clr : 1 ;
+ UINT32 Reserved_124 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC68_U;
+
+
+
+
+typedef union tagMeepPortlogic69
+{
+
+ struct
+ {
+ UINT32 app_rd_err_det : 1 ;
+ UINT32 Reserved_127 : 15 ;
+ UINT32 ll_element_fetch_err_det : 1 ;
+ UINT32 Reserved_126 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC69_U;
+
+
+
+
+typedef union tagMeepPortlogic74
+{
+
+ struct
+ {
+ UINT32 dma_wr_c0_imwr_data : 16 ;
+ UINT32 dma_wr_c1_imwr_data : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC74_U;
+
+
+
+
+typedef union tagMeepPortlogic75
+{
+
+ struct
+ {
+ UINT32 wr_ch_ll_remote_abort_int_en : 1 ;
+ UINT32 Reserved_129 : 15 ;
+ UINT32 wr_ch_ll_local_abort_int_en : 1 ;
+ UINT32 Reserved_128 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC75_U;
+
+
+
+
+typedef union tagMeepPortlogic76
+{
+
+ struct
+ {
+ UINT32 done_int_status : 1 ;
+ UINT32 Reserved_132 : 15 ;
+ UINT32 abort_int_status : 1 ;
+ UINT32 Reserved_131 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC76_U;
+
+
+
+
+typedef union tagMeepPortlogic77
+{
+
+ struct
+ {
+ UINT32 done_int_mask : 1 ;
+ UINT32 Reserved_134 : 15 ;
+ UINT32 abort_int_mask : 1 ;
+ UINT32 dma_rd_int_mask : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC77_U;
+
+
+
+
+typedef union tagMeepPortlogic78
+{
+
+ struct
+ {
+ UINT32 done_int_clr : 1 ;
+ UINT32 Reserved_136 : 15 ;
+ UINT32 abort_int_clr : 1 ;
+ UINT32 dma_rd_int_clr : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC78_U;
+
+
+
+
+typedef union tagMeepPortlogic79
+{
+
+ struct
+ {
+ UINT32 app_wr_err_det : 1 ;
+ UINT32 Reserved_137 : 15 ;
+ UINT32 link_list_fetch_err_det : 1 ;
+ UINT32 dma_rd_err_low : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC79_U;
+
+
+
+
+typedef union tagMeepPortlogic80
+{
+
+ struct
+ {
+ UINT32 unspt_request : 8 ;
+ UINT32 completer_abort : 8 ;
+ UINT32 cpl_time_out : 8 ;
+ UINT32 data_poison : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC80_U;
+
+
+
+
+typedef union tagMeepPortlogic81
+{
+
+ struct
+ {
+ UINT32 remote_abort_int_en : 1 ;
+ UINT32 Reserved_139 : 15 ;
+ UINT32 local_abort_int_en : 1 ;
+ UINT32 dma_rd_ll_err_ena : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC81_U;
+
+
+
+
+typedef union tagMeepPortlogic86
+{
+
+ struct
+ {
+ UINT32 channel_dir : 3 ;
+ UINT32 Reserved_143 : 28 ;
+ UINT32 dma_ch_con_idx : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC86_U;
+
+
+
+
+typedef union tagMeepPortlogic87
+{
+
+ struct
+ {
+ UINT32 cycle_bit : 1 ;
+ UINT32 toggle_cycle_bit : 1 ;
+ UINT32 load_link_pointer : 1 ;
+ UINT32 local_int_en : 1 ;
+ UINT32 remote_int_en : 1 ;
+ UINT32 channel_status : 2 ;
+ UINT32 Reserved_147 : 1 ;
+ UINT32 consumer_cycle_state : 1 ;
+ UINT32 linked_list_en : 1 ;
+ UINT32 Reserved_146 : 2 ;
+ UINT32 func_num_dma : 5 ;
+ UINT32 Reserved_145 : 7 ;
+ UINT32 no_snoop : 1 ;
+ UINT32 ro : 1 ;
+ UINT32 td : 1 ;
+ UINT32 tc : 3 ;
+ UINT32 dma_ch_ctrl : 2 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC87_U;
+
+
+
+
+typedef union tagMeepPortlogic93
+{
+
+ struct
+ {
+ UINT32 Reserved_150 : 2 ;
+ UINT32 dma_ll_ptr_low : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC93_U;
+
+
+
+
+typedef union tagMeepPbar23xlatLower
+{
+
+ struct
+ {
+ UINT32 Reserved_151 : 12 ;
+ UINT32 PBAR23_Xlat_Lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PBAR23XLAT_LOWER_U;
+
+
+
+
+typedef union tagMeepPbar45xlatLower
+{
+
+ struct
+ {
+ UINT32 Reserved_153 : 12 ;
+ UINT32 PBAR45_Xlat_Lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PBAR45XLAT_LOWER_U;
+
+
+
+
+typedef union tagMeepPbar23lmtLower
+{
+
+ struct
+ {
+ UINT32 Reserved_154 : 12 ;
+ UINT32 PBAR23_Limit_Lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PBAR23LMT_LOWER_U;
+
+
+
+
+typedef union tagMeepPbar45lmtLower
+{
+
+ struct
+ {
+ UINT32 Reserved_155 : 12 ;
+ UINT32 PBAR45_Limit_Lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PBAR45LMT_LOWER_U;
+
+
+
+
+typedef union tagMeepPbar45lmtUpper
+{
+
+ struct
+ {
+ UINT32 Reserved_156 : 12 ;
+ UINT32 PBAR45_Limit_Upper : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PBAR45LMT_UPPER_U;
+
+
+
+
+typedef union tagMeepB2bBar01xlatLower
+{
+
+ struct
+ {
+ UINT32 Reserved_157 : 17 ;
+ UINT32 B2B_PBAR01_Xlat_Lower : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_B2B_BAR01XLAT_Lower_U;
+
+
+
+
+typedef union tagMeepPpd
+{
+
+ struct
+ {
+ UINT32 port_def : 1 ;
+ UINT32 Reserved_159 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PPD_U;
+
+
+
+
+typedef union tagMeepDeviceVendorId
+{
+
+ struct
+ {
+ UINT32 Vendor_ID : 16 ;
+ UINT32 Device_ID : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_Device_Vendor_ID_U;
+
+
+
+
+typedef union tagMeepPcistsPcicmd
+{
+
+ struct
+ {
+ UINT32 io_space_enable : 1 ;
+ UINT32 memory_space_enable : 1 ;
+ UINT32 bus_master_enable : 1 ;
+ UINT32 specialcycleenable : 1 ;
+ UINT32 memory_write_and_invalidate : 1 ;
+ UINT32 vga_palette_snoop_enable : 1 ;
+ UINT32 parity_error_response : 1 ;
+ UINT32 idsel_stepping_waitcycle_control : 1 ;
+ UINT32 serr_enable : 1 ;
+ UINT32 fastback_to_backenable : 1 ;
+ UINT32 Interrupt_Disable : 1 ;
+ UINT32 Reserved_164 : 5 ;
+ UINT32 Reserved_163 : 3 ;
+ UINT32 intx_status : 1 ;
+ UINT32 capabilitieslist : 1 ;
+ UINT32 pcibus66mhzcapable : 1 ;
+ UINT32 Reserved_162 : 1 ;
+ UINT32 fastback_to_back : 1 ;
+ UINT32 masterdataparityerror : 1 ;
+ UINT32 devsel_timing : 2 ;
+ UINT32 Signaled_Target_Abort : 1 ;
+ UINT32 Received_Target_Abort : 1 ;
+ UINT32 Received_Master_Abort : 1 ;
+ UINT32 Signaled_System_Error : 1 ;
+ UINT32 Detected_Parity_Error : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCISTS_PCICMD_U;
+
+
+
+
+typedef union tagMeepCcrRid
+{
+
+ struct
+ {
+ UINT32 revision_identification : 8 ;
+ UINT32 Reserved_165 : 8 ;
+ UINT32 sub_class : 8 ;
+ UINT32 baseclass : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_CCR_RID_U;
+
+
+
+
+typedef union tagMeepPbar01BaseLower
+{
+
+ struct
+ {
+ UINT32 BAR01_Space_Inicator : 1 ;
+ UINT32 BAR01_Type : 2 ;
+ UINT32 BAR01_Prefetchable : 1 ;
+ UINT32 Reserved_166 : 13 ;
+ UINT32 base_address_register_01_lower : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PBAR01_BASE_LOWER_U;
+
+
+
+
+typedef union tagMeepPbar23BaseLower
+{
+
+ struct
+ {
+ UINT32 BAR23_Space_Inicator : 1 ;
+ UINT32 BAR23_Type : 2 ;
+ UINT32 BAR23_Prefetchable : 1 ;
+ UINT32 Reserved_168 : 8 ;
+ UINT32 Base_Address_Register_23_Lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PBAR23_BASE_LOWER_U;
+
+
+
+
+typedef union tagMeepPbar45BaseLower
+{
+
+ struct
+ {
+ UINT32 BAR45_Space_Inicator : 1 ;
+ UINT32 BAR45_Type : 2 ;
+ UINT32 BAR45_Prefetchable : 1 ;
+ UINT32 Reserved_169 : 8 ;
+ UINT32 Base_Address_Register_45_Lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PBAR45_BASE_LOWER_U;
+
+
+
+
+typedef union tagMeepSubsystemid
+{
+
+ struct
+ {
+ UINT32 SubsystemID : 16 ;
+ UINT32 SubsystemVendorID : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_SubSystemId_U;
+
+
+
+
+typedef union tagMeepCapptr
+{
+
+ struct
+ {
+ UINT32 CapPtr : 8 ;
+ UINT32 Reserved_172 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_CapPtr_U;
+
+
+
+
+typedef union tagMeepInterrupt
+{
+
+ struct
+ {
+ UINT32 Interrupt_Line : 8 ;
+ UINT32 interrupt_pin : 8 ;
+ UINT32 min_grant : 8 ;
+ UINT32 Max_Latency : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_Interrupt_U;
+
+
+
+
+typedef union tagMeepMsiCapabilityRegister
+{
+
+ struct
+ {
+ UINT32 CapabilityID : 8 ;
+ UINT32 Next_Capability_Pointer : 8 ;
+ UINT32 MSI_Enabled : 1 ;
+ UINT32 Multiple_Message_Capable : 3 ;
+ UINT32 Multiple_Message_Enabled : 3 ;
+ UINT32 MSI_64_EN : 1 ;
+ UINT32 PVM_EN : 1 ;
+ UINT32 Message_Control_Register : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_MSI_Capability_Register_U;
+
+
+
+
+typedef union tagMeepMsiLower32Bitaddress
+{
+
+ struct
+ {
+ UINT32 Reserved_175 : 2 ;
+ UINT32 Lower32_bitAddress : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_MSI_Lower32_bitAddress_U;
+
+
+
+
+typedef union tagMeepMsiData
+{
+
+ struct
+ {
+ UINT32 MSI_Data : 16 ;
+ UINT32 Reserved_176 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_MSI_Data_U;
+
+
+
+
+typedef union tagMeepMsiMask
+{
+
+ struct
+ {
+ UINT32 MsiMask : 1 ;
+ UINT32 Reserved_177 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_MSI_MASK_U;
+
+
+
+
+typedef union tagMeepMsiPending
+{
+
+ struct
+ {
+ UINT32 MsiPending : 1 ;
+ UINT32 Reserved_178 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_MSI_Pending_U;
+
+
+
+
+typedef union tagMeepPcieCapabilityRegister
+{
+
+ struct
+ {
+ UINT32 Capability_ID : 8 ;
+ UINT32 Next_Capability_Pointer : 8 ;
+ UINT32 PCIE_Capability_Version : 4 ;
+ UINT32 Device_Port_Type : 4 ;
+ UINT32 Slot_Implemented : 1 ;
+ UINT32 Interrupt_Message_Number : 5 ;
+ UINT32 Reserved_179 : 2 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCIE_Capability_Register_U;
+
+
+
+
+typedef union tagMeepDeviceCapabilitiesRegister
+{
+
+ struct
+ {
+ UINT32 Max_Payload_Size_Supported : 3 ;
+ UINT32 Phantom_Function_Supported : 2 ;
+ UINT32 Extended_TagField_Supported : 1 ;
+ UINT32 Endpoint_L0sAcceptable_Latency : 3 ;
+ UINT32 Endpoint_L1Acceptable_Latency : 3 ;
+ UINT32 Undefined : 3 ;
+ UINT32 Reserved_182 : 3 ;
+ UINT32 Captured_Slot_Power_Limit_Value : 8 ;
+ UINT32 Captured_Slot_Power_Limit_Scale : 2 ;
+ UINT32 Function_Level_Reset : 1 ;
+ UINT32 Reserved_181 : 3 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_Device_Capabilities_Register_U;
+
+
+
+
+typedef union tagMeepDeviceStatusRegister
+{
+
+ struct
+ {
+ UINT32 Correctable_Error_Reporting_Enable : 1 ;
+ UINT32 Non_Fatal_Error_Reporting_Enable : 1 ;
+ UINT32 Fatal_Error_Reporting_Enable : 1 ;
+ UINT32 UREnable : 1 ;
+ UINT32 Enable_Relaxed_Ordering : 1 ;
+ UINT32 Max_Payload_Size : 3 ;
+ UINT32 Extended_TagFieldEnable : 1 ;
+ UINT32 Phantom_Function_Enable : 1 ;
+ UINT32 AUXPowerPMEnable : 1 ;
+ UINT32 EnableNoSnoop : 1 ;
+ UINT32 Max_Read_Request_Size : 3 ;
+ UINT32 Reserved_184 : 1 ;
+ UINT32 CorrectableErrorDetected : 1 ;
+ UINT32 Non_FatalErrordetected : 1 ;
+ UINT32 FatalErrorDetected : 1 ;
+ UINT32 UnsupportedRequestDetected : 1 ;
+ UINT32 AuxPowerDetected : 1 ;
+ UINT32 TransactionPending : 1 ;
+ UINT32 Reserved_183 : 10 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_Device_Status_Register_U;
+
+
+
+
+typedef union tagMeepLinkCapability
+{
+
+ struct
+ {
+ UINT32 Max_Link_Speed : 4 ;
+ UINT32 Max_Link_Width : 6 ;
+ UINT32 Active_State_Power_Management : 2 ;
+ UINT32 L0s_ExitLatency : 3 ;
+ UINT32 L1_Exit_Latency : 3 ;
+ UINT32 Clock_Power_Management : 1 ;
+ UINT32 Surprise_Down_Error_Report_Cap : 1 ;
+ UINT32 Data_Link_Layer_Active_Report_Cap : 1 ;
+ UINT32 Link_Bandwidth_Noti_Cap : 1 ;
+ UINT32 ASPM_Option_Compliance : 1 ;
+ UINT32 Reserved_185 : 1 ;
+ UINT32 Port_Number : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_Link_Capability_U;
+
+
+
+
+typedef union tagMeepLinkControlStatus
+{
+
+ struct
+ {
+ UINT32 active_state_power_management : 2 ;
+ UINT32 Reserved_188 : 1 ;
+ UINT32 rcb : 1 ;
+ UINT32 link_disable : 1 ;
+ UINT32 retrain_link : 1 ;
+ UINT32 common_clock_config : 1 ;
+ UINT32 extended_sync : 1 ;
+ UINT32 enable_clock_pwr_management : 1 ;
+ UINT32 hw_auto_width_disable : 1 ;
+ UINT32 link_bandwidth_management_int_en : 1 ;
+ UINT32 link_auto_bandwidth_int_en : 1 ;
+ UINT32 Reserved_187 : 4 ;
+ UINT32 current_link_speed : 4 ;
+ UINT32 negotiated_link_width : 6 ;
+ UINT32 Reserved_186 : 1 ;
+ UINT32 link_training : 1 ;
+ UINT32 slot_clock_configration : 1 ;
+ UINT32 data_link_layer_active : 1 ;
+ UINT32 link_bandwidth_management_status : 1 ;
+ UINT32 link_auto_bandwidth_status : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_Link_Control_Status_U;
+
+
+
+
+typedef union tagMeepAerCapHeader
+{
+
+ struct
+ {
+ UINT32 PCIE_Extended_Capability_ID : 16 ;
+ UINT32 Capability_Version : 4 ;
+ UINT32 Next_Capability_Offset : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_AER_Cap_header_U;
+
+
+
+
+typedef union tagMeepUcErrorStatus
+{
+
+ struct
+ {
+ UINT32 Reserved_193 : 1 ;
+ UINT32 Reserved_192 : 3 ;
+ UINT32 DataLinkProtocolErrorStatus : 1 ;
+ UINT32 SurpriseDownErrorStatus : 1 ;
+ UINT32 Reserved_191 : 6 ;
+ UINT32 PoisonedTLPStatus : 1 ;
+ UINT32 FlowControlProtocolErrorStatus : 1 ;
+ UINT32 CompletionTimeoutStatus : 1 ;
+ UINT32 CompleterAbortStatus : 1 ;
+ UINT32 UnexpectedCompletionStatus : 1 ;
+ UINT32 ReceiverOverflowStatus : 1 ;
+ UINT32 MalformedTLPStatus : 1 ;
+ UINT32 ECRCErrorStatus : 1 ;
+ UINT32 UnsupportedRequestErrorStatus : 1 ;
+ UINT32 Reserved_190 : 11 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_UC_Error_Status_U;
+
+
+
+
+typedef union tagMeepUcErrorMask
+{
+
+ struct
+ {
+ UINT32 Reserved_197 : 1 ;
+ UINT32 Reserved_196 : 3 ;
+ UINT32 DataLinkProtocolErrorMask : 1 ;
+ UINT32 SurpriseDownErrorMask : 1 ;
+ UINT32 Reserved_195 : 6 ;
+ UINT32 PoisonedTLPMask : 1 ;
+ UINT32 FlowControlProtocolErrorMask : 1 ;
+ UINT32 CompletionTimeoutMask : 1 ;
+ UINT32 CompleterAbortMask : 1 ;
+ UINT32 UnexpectedCompletionMask : 1 ;
+ UINT32 ReceiverOverflowMask : 1 ;
+ UINT32 MalformedTLPMask : 1 ;
+ UINT32 ECRCErrorMask : 1 ;
+ UINT32 UnsupportedRequestErrorMask : 1 ;
+ UINT32 Reserved_194 : 11 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_UC_Error_Mask_U;
+
+
+
+
+typedef union tagMeepUcErrorSeverity
+{
+
+ struct
+ {
+ UINT32 Reserved_201 : 1 ;
+ UINT32 Reserved_200 : 3 ;
+ UINT32 DataLinkProtocolErrorSeverity : 1 ;
+ UINT32 SurpriseDownErrorSeverity : 1 ;
+ UINT32 Reserved_199 : 6 ;
+ UINT32 PoisonedTLPSeverity : 1 ;
+ UINT32 FlowControlProtocolErrorSeverity : 1 ;
+ UINT32 CompletionTimeoutSeverity : 1 ;
+ UINT32 CompleterAbortSeverity : 1 ;
+ UINT32 UnexpectedCompletionSeverity : 1 ;
+ UINT32 ReceiverOverflowSeverity : 1 ;
+ UINT32 MalformedTLPSeverity : 1 ;
+ UINT32 ECRCErrorSeverity : 1 ;
+ UINT32 UnsupportedRequestErrorSeverity : 1 ;
+ UINT32 Reserved_198 : 11 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_UC_Error_Severity_U;
+
+
+
+
+typedef union tagMeepCErrorStatus
+{
+
+ struct
+ {
+ UINT32 Receiver_Error_Status : 1 ;
+ UINT32 Reserved_204 : 5 ;
+ UINT32 Bad_TLP_Status : 1 ;
+ UINT32 Bad_DLLP_Status : 1 ;
+ UINT32 REPLAY_NUM_Rollover_Status : 1 ;
+ UINT32 Reserved_203 : 3 ;
+ UINT32 Replay_Timer_Timeout_Status : 1 ;
+ UINT32 Advisory_Non_Fatal_Error_Status : 1 ;
+ UINT32 Reserved_202 : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_C_Error_Status_U;
+
+
+
+
+typedef union tagMeepCErrorMask
+{
+
+ struct
+ {
+ UINT32 Receiver_Error_Mask : 1 ;
+ UINT32 Reserved_207 : 5 ;
+ UINT32 Bad_TLP_Mask : 1 ;
+ UINT32 Bad_DLLP_Mask : 1 ;
+ UINT32 REPLAY_NUMRollover_Mask : 1 ;
+ UINT32 Reserved_206 : 3 ;
+ UINT32 Replay_Timer_Timeout_Mask : 1 ;
+ UINT32 Advisory_Non_Fatal_Error_Mask : 1 ;
+ UINT32 Reserved_205 : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_C_Error_Mask_U;
+
+
+
+
+typedef union tagMeepAdvancedErrorCapabilitiesAndControl
+{
+
+ struct
+ {
+ UINT32 First_Error_Pointer : 5 ;
+ UINT32 ECRC_Generation_Capability : 1 ;
+ UINT32 ECRC_Generation_Enable : 1 ;
+ UINT32 ECRC_Check_Capable : 1 ;
+ UINT32 ECRC_Check_Enable : 1 ;
+ UINT32 Reserved_209 : 2 ;
+ UINT32 TLP_Prefix_Log_Present : 1 ;
+ UINT32 Reserved_208 : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_Advanced_Error_Capabilities_and_Control_U;
+
+
+
+
+typedef union tagMeepNtbIepBar01Ctrl
+{
+
+ struct
+ {
+ UINT32 bar01_type : 5 ;
+ UINT32 bar01_tc : 3 ;
+ UINT32 bar01_td : 1 ;
+ UINT32 bar01_attr : 2 ;
+ UINT32 Reserved_213 : 5 ;
+ UINT32 bar01_at : 2 ;
+ UINT32 bar01_match_en : 1 ;
+ UINT32 Reserved_212 : 13 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_NTB_IEP_BAR01_CTRL_U;
+
+
+
+
+typedef union tagMeepNtbIepBar23Ctrl
+{
+
+ struct
+ {
+ UINT32 bar23_type : 5 ;
+ UINT32 bar23_tc : 3 ;
+ UINT32 bar23_td : 1 ;
+ UINT32 bar23_attr : 2 ;
+ UINT32 Reserved_215 : 5 ;
+ UINT32 bar23_at : 2 ;
+ UINT32 bar23_match_en : 1 ;
+ UINT32 Reserved_214 : 13 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_NTB_IEP_BAR23_CTRL_U;
+
+
+
+
+typedef union tagMeepNtbIepBar45Ctrl
+{
+
+ struct
+ {
+ UINT32 bar45_type : 5 ;
+ UINT32 bar45_tc : 3 ;
+ UINT32 bar45_td : 1 ;
+ UINT32 bar45_attr : 2 ;
+ UINT32 Reserved_217 : 5 ;
+ UINT32 bar45_at : 2 ;
+ UINT32 bar45_match_en : 1 ;
+ UINT32 Reserved_216 : 13 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_NTB_IEP_BAR45_CTRL_U;
+
+
+
+
+typedef union tagMeepMsiCtrlIntEn
+{
+
+ struct
+ {
+ UINT32 msi_int_en : 1 ;
+ UINT32 Reserved_218 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_MSI_CTRL_INT_EN_U;
+
+
+
+
+typedef union tagMeepMsiCtrlInt0Mask
+{
+
+ struct
+ {
+ UINT32 msi_int_mask : 1 ;
+ UINT32 Reserved_219 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_MSI_CTRL_INT0_MASK_U;
+
+
+
+
+typedef union tagMeepMsiCtrlIntStatus
+{
+
+ struct
+ {
+ UINT32 msi_int : 1 ;
+ UINT32 Reserved_220 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_MSI_CTRL_INT_STATUS_U;
+
+
+
+
+typedef union tagMeepDbiRoWrEn
+{
+
+ struct
+ {
+ UINT32 dbi_ro_wr_en : 1 ;
+ UINT32 Reserved_221 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_DBI_RO_WR_EN_U;
+
+
+
+
+typedef union tagAxiErrResponse
+{
+
+ struct
+ {
+ UINT32 err_resp_mode : 4 ;
+ UINT32 Reserved_222 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_AXI_ERR_RESPONSE_U;
+
+
+
+
+
+
+
+#define PCIE_MIEP_PBAR23XLAT_LOWER_REG (0x0)
+#define PCIE_MIEP_PBAR23XLAT_UPPER_REG (0x4)
+#define PCIE_MIEP_PBAR45XLAT_LOWER_REG (0x8)
+#define PCIE_MIEP_PBAR45XLAT_UPPER_REG (0xC)
+#define PCIE_MIEP_PBAR23LMT_LOWER_REG (0x10)
+#define PCIE_MIEP_PBAR23LMT_UPPER_REG (0x14)
+#define PCIE_MIEP_PBAR45LMT_LOWER_REG (0x18)
+#define PCIE_MIEP_PBAR45LMT_UPPER_REG (0x1C)
+#define PCIE_MIEP_PDOORBELL_REG (0x20)
+#define PCIE_MIEP_PDOORBELL_MASK_REG (0x24)
+#define PCIE_MIEP_B2B_BAR01XLAT_LOWER_REG (0x28)
+#define PCIE_MIEP_B2B_BAR01XLAT_UPPER_REG (0x2C)
+#define PCIE_MIEP_B2BDOORBELL_REG (0x30)
+#define PCIE_MIEP_SPAD0_REG (0x38)
+#define PCIE_MIEP_SPAD1_REG (0x3C)
+#define PCIE_MIEP_SPAD2_REG (0x40)
+#define PCIE_MIEP_SPAD3_REG (0x44)
+#define PCIE_MIEP_SPAD4_REG (0x48)
+#define PCIE_MIEP_SPAD5_REG (0x4C)
+#define PCIE_MIEP_SPAD6_REG (0x50)
+#define PCIE_MIEP_SPAD7_REG (0x54)
+#define PCIE_MIEP_SPAD8_REG (0x58)
+#define PCIE_MIEP_SPAD9_REG (0x5C)
+#define PCIE_MIEP_SPAD10_REG (0x60)
+#define PCIE_MIEP_SPAD11_REG (0x64)
+#define PCIE_MIEP_SPAD12_REG (0x68)
+#define PCIE_MIEP_SPAD13_REG (0x6C)
+#define PCIE_MIEP_SPAD14_REG (0x70)
+#define PCIE_MIEP_SPAD15_REG (0x74)
+#define PCIE_MIEP_SPAD16_REG (0x78)
+#define PCIE_MIEP_SPAD17_REG (0x7C)
+#define PCIE_MIEP_SPAD18_REG (0x80)
+#define PCIE_MIEP_SPAD19_REG (0x84)
+#define PCIE_MIEP_SPAD20_REG (0x88)
+#define PCIE_MIEP_SPAD21_REG (0x8C)
+#define PCIE_MIEP_SPAD22_REG (0x90)
+#define PCIE_MIEP_SPAD23_REG (0x94)
+#define PCIE_MIEP_SPAD24_REG (0x98)
+#define PCIE_MIEP_SPAD25_REG (0x9C)
+#define PCIE_MIEP_SPAD26_REG (0xA0)
+#define PCIE_MIEP_SPAD27_REG (0xA4)
+#define PCIE_MIEP_SPAD28_REG (0xA8)
+#define PCIE_MIEP_SPAD29_REG (0xAC)
+#define PCIE_MIEP_SPAD30_REG (0xB0)
+#define PCIE_MIEP_SPAD31_REG (0xB4)
+#define PCIE_MIEP_B2BSPAD0_REG (0xB8)
+#define PCIE_MIEP_B2BSPAD1_REG (0xBC)
+#define PCIE_MIEP_B2BSPAD2_REG (0xC0)
+#define PCIE_MIEP_B2BSPAD3_REG (0xC4)
+#define PCIE_MIEP_B2BSPAD4_REG (0xC8)
+#define PCIE_MIEP_B2BSPAD5_REG (0xCC)
+#define PCIE_MIEP_B2BSPAD6_REG (0xD0)
+#define PCIE_MIEP_B2BSPAD7_REG (0xD4)
+#define PCIE_MIEP_B2BSPAD8_REG (0xD8)
+#define PCIE_MIEP_B2BSPAD9_REG (0xDC)
+#define PCIE_MIEP_B2BSPAD10_REG (0xE0)
+#define PCIE_MIEP_B2BSPAD11_REG (0xE4)
+#define PCIE_MIEP_B2BSPAD12_REG (0xE8)
+#define PCIE_MIEP_B2BSPAD13_REG (0xEC)
+#define PCIE_MIEP_B2BSPAD14_REG (0xF0)
+#define PCIE_MIEP_B2BSPAD15_REG (0xF4)
+#define PCIE_MIEP_B2BSPAD16_REG (0xF8)
+#define PCIE_MIEP_B2BSPAD17_REG (0xFC)
+#define PCIE_MIEP_B2BSPAD18_REG (0x100)
+#define PCIE_MIEP_B2BSPAD19_REG (0x104)
+#define PCIE_MIEP_B2BSPAD20_REG (0x108)
+#define PCIE_MIEP_B2BSPAD21_REG (0x10C)
+#define PCIE_MIEP_B2BSPAD22_REG (0x110)
+#define PCIE_MIEP_B2BSPAD23_REG (0x114)
+#define PCIE_MIEP_B2BSPAD24_REG (0x118)
+#define PCIE_MIEP_B2BSPAD25_REG (0x11C)
+#define PCIE_MIEP_B2BSPAD26_REG (0x120)
+#define PCIE_MIEP_B2BSPAD27_REG (0x124)
+#define PCIE_MIEP_B2BSPAD28_REG (0x128)
+#define PCIE_MIEP_B2BSPAD29_REG (0x12C)
+#define PCIE_MIEP_B2BSPAD30_REG (0x130)
+#define PCIE_MIEP_B2BSPAD31_REG (0x134)
+#define PCIE_MIEP_PPD_REG (0x138)
+#define PCIE_MIEP_P_DEVICE_VENDOR_ID_REG (0x1000)
+#define PCIE_MIEP_P_PCISTS_PCICMD_REG (0x1004)
+#define PCIE_MIEP_P_CCR_RID_REG (0x1008)
+#define PCIE_MIEP_P_BIST_TYPE_REG (0x100C)
+#define PCIE_MIEP_PBAR01_BASE_LOWER_REG (0x1010)
+#define PCIE_MIEP_PBAR01_BASE_UPPER_REG (0x1014)
+#define PCIE_MIEP_PBAR23_BASE_LOWER_REG (0x1018)
+#define PCIE_MIEP_PBAR23_BASE_UPPER_REG (0x101C)
+#define PCIE_MIEP_PBAR45_BASE_LOWER_REG (0x1020)
+#define PCIE_MIEP_PBAR45_BASE_UPPER_REG (0x1024)
+#define PCIE_MIEP_P_SUBSYSTEMID_REG (0x102C)
+#define PCIE_MIEP_P_INTERRUPT_REG (0x103C)
+#define PCIE_MIEP_P_MSI_LOWER32_BITADDRESS_REG (0x1054)
+#define PCIE_MIEP_P_MSI_UPPER32_BIT_ADDRESS_REG (0x1058)
+#define PCIE_MIEP_P_LINK_CAPABILITY_REG (0x107C)
+#define PCIE_MIEP_P_AER_CAP_HEADER_REG (0x1100)
+#define PCIE_MIEP_P_HEADER_LOG_REGISTERS_1_REG (0x111C)
+#define PCIE_MIEP_P_HEADER_LOG_REGISTERS_2_REG (0x1120)
+#define PCIE_MIEP_P_HEADER_LOG_REGISTERS_3_REG (0x1124)
+#define PCIE_MIEP_P_HEADER_LOG_REGISTERS_4_REG (0x1128)
+#define PCIE_MIEP_P_TLP_PREFIX_LOGREGISTERS_1_REG (0x1130)
+#define PCIE_MIEP_P_TLP_PREFIX_LOGREGISTERS_2_REG (0x1134)
+#define PCIE_MIEP_P_TLP_PREFIX_LOGREGISTERS_3_REG (0x1138)
+#define PCIE_MIEP_P_TLP_PREFIX_LOGREGISTERS_4_REG (0x113C)
+#define PCIE_MIEP_P_NTB_IEP_CONFIG_SPACE_LOWER_REG (0x1700)
+#define PCIE_MIEP_P_NTB_IEP_CONFIG_SPACE_UPPER_REG (0x1704)
+#define PCIE_MIEP_P_MSI_CTRL_ADDRESS_LOWER_REG (0x1714)
+#define PCIE_MIEP_P_MSI_CTRL_ADDRESS_UPPER_REG (0x1718)
+#define PCIE_MIEP_SBAR23XLAT_LOWER_REG (0x8000)
+#define PCIE_MIEP_SBAR23XLAT_UPPER_REG (0x8004)
+#define PCIE_MIEP_SBAR45XLAT_LOWER_REG (0x8008)
+#define PCIE_MIEP_SBAR45XLAT_UPPER_REG (0x800C)
+#define PCIE_MIEP_SBAR23LMT_LOWER_REG (0x8010)
+#define PCIE_MIEP_SBAR23LMT_UPPER_REG (0x8014)
+#define PCIE_MIEP_SBAR45LMT_LOWER_REG (0x8018)
+#define PCIE_MIEP_SBAR45LMT_UPPER_REG (0x801C)
+#define PCIE_MIEP_SDOORBELL_REG (0x8020)
+#define PCIE_MIEP_SDOORBELL_MASK_REG (0x8024)
+#define PCIE_MIEP_CBDF_SBDF_REG (0x8028)
+#define PCIE_MIEP_PCI_CFG_HDR0_REG (0x9000)
+#define PCIE_MIEP_PCI_CFG_HDR1_REG (0x9004)
+#define PCIE_MIEP_PCI_CFG_HDR9_REG (0x9024)
+#define PCIE_MIEP_PCI_CFG_HDR10_REG (0x9028)
+#define PCIE_MIEP_PCI_CFG_HDR11_REG (0x902C)
+#define PCIE_MIEP_PCI_CFG_HDR12_REG (0x9030)
+#define PCIE_MIEP_PCI_CFG_HDR13_REG (0x9034)
+#define PCIE_MIEP_PCI_CFG_HDR14_REG (0x9038)
+#define PCIE_MIEP_PCI_CFG_HDR15_REG (0x903C)
+#define PCIE_MIEP_PCI_PM_CAP0_REG (0x9040)
+#define PCIE_MIEP_PCI_PM_CAP1_REG (0x9044)
+#define PCIE_MIEP_PCI_MSI_CAP0_REG (0x9050)
+#define PCIE_MIEP_PCI_MSI_CAP1_REG (0x9054)
+#define PCIE_MIEP_PCI_MSI_CAP2_REG (0x9058)
+#define PCIE_MIEP_PCI_MSI_CAP3_REG (0x905C)
+#define PCIE_MIEP_PCIE_CAP0_REG (0x9070)
+#define PCIE_MIEP_PCIE_CAP1_REG (0x9074)
+#define PCIE_MIEP_PCIE_CAP2_REG (0x9078)
+#define PCIE_MIEP_PCIE_CAP3_REG (0x907C)
+#define PCIE_MIEP_PCIE_CAP4_REG (0x9080)
+#define PCIE_MIEP_PCIE_CAP5_REG (0x9084)
+#define PCIE_MIEP_PCIE_CAP6_REG (0x9088)
+#define PCIE_MIEP_PCIE_CAP7_REG (0x908C)
+#define PCIE_MIEP_PCIE_CAP8_REG (0x9090)
+#define PCIE_MIEP_PCIE_CAP9_REG (0x9094)
+#define PCIE_MIEP_PCIE_CAP10_REG (0x9098)
+#define PCIE_MIEP_PCIE_CAP11_REG (0x909C)
+#define PCIE_MIEP_PCIE_CAP12_REG (0x90A0)
+#define PCIE_MIEP_SLOT_CAP_REG (0x90C0)
+#define PCIE_MIEP_AER_CAP0_REG (0x9100)
+#define PCIE_MIEP_AER_CAP1_REG (0x9104)
+#define PCIE_MIEP_AER_CAP2_REG (0x9108)
+#define PCIE_MIEP_AER_CAP3_REG (0x910C)
+#define PCIE_MIEP_AER_CAP4_REG (0x9110)
+#define PCIE_MIEP_AER_CAP5_REG (0x9114)
+#define PCIE_MIEP_AER_CAP6_REG (0x9118)
+#define PCIE_MIEP_AER_CAP7_REG (0x911C)
+#define PCIE_MIEP_AER_CAP8_REG (0x9120)
+#define PCIE_MIEP_AER_CAP9_REG (0x9124)
+#define PCIE_MIEP_AER_CAP10_REG (0x9128)
+#define PCIE_MIEP_AER_CAP11_REG (0x912C)
+#define PCIE_MIEP_AER_CAP12_REG (0x9130)
+#define PCIE_MIEP_AER_CAP13_REG (0x9134)
+#define PCIE_MIEP_VC_CAP0_REG (0x9140)
+#define PCIE_MIEP_VC_CAP1_REG (0x9144)
+#define PCIE_MIEP_VC_CAP2_REG (0x9148)
+#define PCIE_MIEP_VC_CAP3_REG (0x914C)
+#define PCIE_MIEP_VC_CAP4_REG (0x9150)
+#define PCIE_MIEP_VC_CAP5_REG (0x9154)
+#define PCIE_MIEP_VC_CAP6_REG (0x9158)
+#define PCIE_MIEP_VC_CAP7_REG (0x915C)
+#define PCIE_MIEP_VC_CAP8_REG (0x9160)
+#define PCIE_MIEP_VC_CAP9_REG (0x9164)
+#define PCIE_MIEP_PORT_LOGIC0_REG (0x9700)
+#define PCIE_MIEP_PORT_LOGIC1_REG (0x9704)
+#define PCIE_MIEP_PORT_LOGIC2_REG (0x9708)
+#define PCIE_MIEP_PORT_LOGIC3_REG (0x970C)
+#define PCIE_MIEP_PORT_LOGIC4_REG (0x9710)
+#define PCIE_MIEP_PORT_LOGIC5_REG (0x9714)
+#define PCIE_MIEP_PORT_LOGIC6_REG (0x9718)
+#define PCIE_MIEP_PORT_LOGIC7_REG (0x971C)
+#define PCIE_MIEP_PORT_LOGIC8_REG (0x9720)
+#define PCIE_MIEP_PORT_LOGIC9_REG (0x9724)
+#define PCIE_MIEP_PORT_LOGIC10_REG (0x9728)
+#define PCIE_MIEP_PORT_LOGIC11_REG (0x972C)
+#define PCIE_MIEP_PORT_LOGIC12_REG (0x9730)
+#define PCIE_MIEP_PORT_LOGIC13_REG (0x9734)
+#define PCIE_MIEP_PORT_LOGIC14_REG (0x9738)
+#define PCIE_MIEP_PORT_LOGIC15_REG (0x973C)
+#define PCIE_MIEP_PORT_LOGIC16_REG (0x9748)
+#define PCIE_MIEP_PORT_LOGIC17_REG (0x974C)
+#define PCIE_MIEP_PORT_LOGIC18_REG (0x9750)
+#define PCIE_MIEP_PORT_LOGIC19_REG (0x97A8)
+#define PCIE_MIEP_PORT_LOGIC20_REG (0x97AC)
+#define PCIE_MIEP_PORT_LOGIC21_REG (0x97B0)
+#define PCIE_MIEP_PORT_LOGIC22_REG (0x980C)
+#define PCIE_MIEP_PORTLOGIC23_REG (0x9810)
+#define PCIE_MIEP_PORTLOGIC24_REG (0x9814)
+#define PCIE_MIEP_PORTLOGIC25_REG (0x9818)
+#define PCIE_MIEP_PORTLOGIC26_REG (0x981C)
+#define PCIE_MIEP_PORTLOGIC27_REG (0x9820)
+#define PCIE_MIEP_PORTLOGIC28_REG (0x9824)
+#define PCIE_MIEP_PORTLOGIC29_REG (0x9828)
+#define PCIE_MIEP_PORTLOGIC30_REG (0x982C)
+#define PCIE_MIEP_PORTLOGIC31_REG (0x9830)
+#define PCIE_MIEP_PORTLOGIC32_REG (0x9834)
+#define PCIE_MIEP_PORTLOGIC33_REG (0x9838)
+#define PCIE_MIEP_PORTLOGIC34_REG (0x983C)
+#define PCIE_MIEP_PORTLOGIC35_REG (0x9840)
+#define PCIE_MIEP_PORTLOGIC36_REG (0x9844)
+#define PCIE_MIEP_PORTLOGIC37_REG (0x9848)
+#define PCIE_MIEP_PORTLOGIC38_REG (0x984C)
+#define PCIE_MIEP_PORTLOGIC39_REG (0x9850)
+#define PCIE_MIEP_PORTLOGIC40_REG (0x9854)
+#define PCIE_MIEP_PORTLOGIC41_REG (0x9858)
+#define PCIE_MIEP_PORTLOGIC42_REG (0x985C)
+#define PCIE_MIEP_PORTLOGIC43_REG (0x9860)
+#define PCIE_MIEP_PORTLOGIC44_REG (0x9864)
+#define PCIE_MIEP_PORTLOGIC45_REG (0x9868)
+#define PCIE_MIEP_PORTLOGIC46_REG (0x986C)
+#define PCIE_MIEP_PORTLOGIC47_REG (0x9870)
+#define PCIE_MIEP_PORTLOGIC48_REG (0x9874)
+#define PCIE_MIEP_PORTLOGIC49_REG (0x9878)
+#define PCIE_MIEP_PORTLOGIC50_REG (0x987C)
+#define PCIE_MIEP_PORTLOGIC51_REG (0x9880)
+#define PCIE_MIEP_PORTLOGIC52_REG (0x9884)
+#define PCIE_MIEP_PORTLOGIC53_REG (0x9888)
+#define PCIE_MIEP_PORTLOGIC54_REG (0x9900)
+#define PCIE_MIEP_PORTLOGIC55_REG (0x9904)
+#define PCIE_MIEP_PORTLOGIC56_REG (0x9908)
+#define PCIE_MIEP_PORTLOGIC57_REG (0x990C)
+#define PCIE_MIEP_PORTLOGIC58_REG (0x9910)
+#define PCIE_MIEP_PORTLOGIC59_REG (0x9914)
+#define PCIE_MIEP_PORTLOGIC60_REG (0x9918)
+#define PCIE_MIEP_PORTLOGIC61_REG (0x991C)
+#define PCIE_MIEP_PORTLOGIC62_REG (0x997C)
+#define PCIE_MIEP_PORTLOGIC63_REG (0x9980)
+#define PCIE_MIEP_PORTLOGIC64_REG (0x999C)
+#define PCIE_MIEP_PORTLOGIC65_REG (0x99A0)
+#define PCIE_MIEP_PORTLOGIC66_REG (0x99BC)
+#define PCIE_MIEP_PORTLOGIC67_REG (0x99C4)
+#define PCIE_MIEP_PORTLOGIC68_REG (0x99C8)
+#define PCIE_MIEP_PORTLOGIC69_REG (0x99CC)
+#define PCIE_MIEP_PORTLOGIC70_REG (0x99D0)
+#define PCIE_MIEP_PORTLOGIC71_REG (0x99D4)
+#define PCIE_MIEP_PORTLOGIC72_REG (0x99D8)
+#define PCIE_MIEP_PORTLOGIC73_REG (0x99DC)
+#define PCIE_MIEP_PORTLOGIC74_REG (0x99E0)
+#define PCIE_MIEP_PORTLOGIC75_REG (0x9A00)
+#define PCIE_MIEP_PORTLOGIC76_REG (0x9A10)
+#define PCIE_MIEP_PORTLOGIC77_REG (0x9A18)
+#define PCIE_MIEP_PORTLOGIC78_REG (0x9A1C)
+#define PCIE_MIEP_PORTLOGIC79_REG (0x9A24)
+#define PCIE_MIEP_PORTLOGIC80_REG (0x9A28)
+#define PCIE_MIEP_PORTLOGIC81_REG (0x9A34)
+#define PCIE_MIEP_PORTLOGIC82_REG (0x9A3C)
+#define PCIE_MIEP_PORTLOGIC83_REG (0x9A40)
+#define PCIE_MIEP_PORTLOGIC84_REG (0x9A44)
+#define PCIE_MIEP_PORTLOGIC85_REG (0x9A48)
+#define PCIE_MIEP_PORTLOGIC86_REG (0x9A6C)
+#define PCIE_MIEP_PORTLOGIC87_REG (0x9A70)
+#define PCIE_MIEP_PORTLOGIC88_REG (0x9A78)
+#define PCIE_MIEP_PORTLOGIC89_REG (0x9A7C)
+#define PCIE_MIEP_PORTLOGIC90_REG (0x9A80)
+#define PCIE_MIEP_PORTLOGIC91_REG (0x9A84)
+#define PCIE_MIEP_PORTLOGIC92_REG (0x9A88)
+#define PCIE_MIEP_PORTLOGIC93_REG (0x9A8C)
+#define PCIE_MIEP_PORTLOGIC94_REG (0x9A90)
+
+
+
+
+typedef union tagMiepPbar23xlatLower
+{
+
+ struct
+ {
+ UINT32 Reserved_0 : 12 ;
+ UINT32 pbar23_xlat_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PBAR23XLAT_LOWER_U;
+
+
+
+
+typedef union tagMiepPbar45xlatLower
+{
+
+ struct
+ {
+ UINT32 Reserved_1 : 12 ;
+ UINT32 pbar45_xlat_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PBAR45XLAT_LOWER_U;
+
+
+
+
+typedef union tagMiepPbar23lmtLower
+{
+
+ struct
+ {
+ UINT32 Reserved_2 : 12 ;
+ UINT32 pbar23_limit_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PBAR23LMT_LOWER_U;
+
+
+
+
+typedef union tagMiepPbar45lmtLower
+{
+
+ struct
+ {
+ UINT32 Reserved_3 : 12 ;
+ UINT32 pbar45_limit_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PBAR45LMT_LOWER_U;
+
+
+
+
+typedef union tagMiepB2bBar01xlatLower
+{
+
+ struct
+ {
+ UINT32 Reserved_4 : 17 ;
+ UINT32 b2b_pbar01_xlat_lower : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_B2B_BAR01XLAT_LOWER_U;
+
+
+
+
+typedef union tagMiepPpd
+{
+
+ struct
+ {
+ UINT32 port_def : 1 ;
+ UINT32 Reserved_6 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PPD_U;
+
+
+
+
+typedef union tagMiepPDeviceVendorId
+{
+
+ struct
+ {
+ UINT32 vendor_id : 16 ;
+ UINT32 device_id : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_P_DEVICE_VENDOR_ID_U;
+
+
+
+
+typedef union tagMiepPPcistsPcicmd
+{
+
+ struct
+ {
+ UINT32 io_space_enable : 1 ;
+ UINT32 memory_space_enable : 1 ;
+ UINT32 bus_master_enable : 1 ;
+ UINT32 specialcycleenable : 1 ;
+ UINT32 memory_write_and_invalidate : 1 ;
+ UINT32 vga_palette_snoop_enable : 1 ;
+ UINT32 parity_error_response : 1 ;
+ UINT32 idsel_stepping_waitcycle_control : 1 ;
+ UINT32 serr_enable : 1 ;
+ UINT32 fastback_to_backenable : 1 ;
+ UINT32 interrupt_disable : 1 ;
+ UINT32 Reserved_10 : 5 ;
+ UINT32 Reserved_9 : 3 ;
+ UINT32 intx_status : 1 ;
+ UINT32 capabilitieslist : 1 ;
+ UINT32 pcibus66mhzcapable : 1 ;
+ UINT32 Reserved_8 : 1 ;
+ UINT32 fastback_to_back : 1 ;
+ UINT32 masterdataparityerror : 1 ;
+ UINT32 devsel_timing : 2 ;
+ UINT32 signaled_target_abort : 1 ;
+ UINT32 received_target_abort : 1 ;
+ UINT32 received_master_abort : 1 ;
+ UINT32 signaled_system_error : 1 ;
+ UINT32 detected_parity_error : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_P_PCISTS_PCICMD_U;
+
+
+
+
+typedef union tagMiepPCcrRid
+{
+
+ struct
+ {
+ UINT32 revision_id : 8 ;
+ UINT32 Reserved_11 : 8 ;
+ UINT32 cfg_sub_class : 8 ;
+ UINT32 cfg_base_class : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_P_CCR_RID_U;
+
+
+
+
+typedef union tagMiepPBistType
+{
+
+ struct
+ {
+ UINT32 cache_line_size : 8 ;
+ UINT32 primary_latency_timer : 8 ;
+ UINT32 cfg_hdr_type : 8 ;
+ UINT32 bist : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_P_BIST_TYPE_U;
+
+
+
+
+typedef union tagMiepPbar01BaseLower
+{
+
+ struct
+ {
+ UINT32 cfg_iep_bar0_io : 1 ;
+ UINT32 cfg_iep_bar0_type : 2 ;
+ UINT32 cfg_iep_bar0_pref : 1 ;
+ UINT32 Reserved_12 : 13 ;
+ UINT32 bar0_low : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PBAR01_BASE_LOWER_U;
+
+
+
+
+typedef union tagMiepPbar23BaseLower
+{
+
+ struct
+ {
+ UINT32 cfg_iep_bar2_io : 1 ;
+ UINT32 cfg_iep_bar2_type : 2 ;
+ UINT32 cfg_iep_bar2_pref : 1 ;
+ UINT32 Reserved_13 : 8 ;
+ UINT32 bar2_low : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PBAR23_BASE_LOWER_U;
+
+
+
+
+typedef union tagMiepPbar45BaseLower
+{
+
+ struct
+ {
+ UINT32 cfg_iep_bar4_io : 1 ;
+ UINT32 cfg_iep_bar4_type : 2 ;
+ UINT32 cfg_iep_bar4_pref : 1 ;
+ UINT32 Reserved_14 : 8 ;
+ UINT32 bar4_low : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PBAR45_BASE_LOWER_U;
+
+
+
+
+typedef union tagMiepPSubsystemid
+{
+
+ struct
+ {
+ UINT32 subsystem_device_id : 16 ;
+ UINT32 subsystem_vendor_id : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_P_SUBSYSTEMID_U;
+
+
+
+
+typedef union tagMiepPInterrupt
+{
+
+ struct
+ {
+ UINT32 int_line_reg : 8 ;
+ UINT32 cfg_int_pin : 8 ;
+ UINT32 min_gnt : 8 ;
+ UINT32 max_lat : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_P_INTERRUPT_U;
+
+
+
+
+typedef union tagMiepPMsiLower32Bitaddress
+{
+
+ struct
+ {
+ UINT32 Reserved_17 : 2 ;
+ UINT32 iep_msi_addr_low32 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_P_MSI_LOWER32_BITADDRESS_U;
+
+
+
+
+typedef union tagMiepPLinkCapability
+{
+
+ struct
+ {
+ UINT32 cfg_pcie_max_link_speed : 4 ;
+ UINT32 cfg_pcie_max_link_width : 6 ;
+ UINT32 active_state_power_management : 2 ;
+ UINT32 l0s_exit_latency : 3 ;
+ UINT32 l1_exit_latency : 3 ;
+ UINT32 clock_power_management : 1 ;
+ UINT32 surprise_down_error_report_cap : 1 ;
+ UINT32 data_link_layer_active_report_cap : 1 ;
+ UINT32 link_bandwidth_noti_cap : 1 ;
+ UINT32 aspm_option_compliance : 1 ;
+ UINT32 Reserved_19 : 1 ;
+ UINT32 cfg_pcie_port_num : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_P_LINK_CAPABILITY_U;
+
+
+
+
+typedef union tagMiepPAerCapHeader
+{
+
+ struct
+ {
+ UINT32 PCIE_Extended_Capability_ID : 16 ;
+ UINT32 Capability_Version : 4 ;
+ UINT32 Next_Capability_Offset : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_P_AER_CAP_HEADER_U;
+
+
+
+
+typedef union tagMiepSbar23xlatLower
+{
+
+ struct
+ {
+ UINT32 Reserved_26 : 12 ;
+ UINT32 sbar23_xlat_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_SBAR23XLAT_LOWER_U;
+
+
+
+
+typedef union tagMiepSbar45xlatLower
+{
+
+ struct
+ {
+ UINT32 Reserved_28 : 12 ;
+ UINT32 sbar45_xlat_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_SBAR45XLAT_LOWER_U;
+
+
+
+
+typedef union tagMiepSbar23lmtLower
+{
+
+ struct
+ {
+ UINT32 Reserved_29 : 12 ;
+ UINT32 sbar23_limit_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_SBAR23LMT_LOWER_U;
+
+
+
+
+typedef union tagMiepSbar45lmtLower
+{
+
+ struct
+ {
+ UINT32 Reserved_30 : 12 ;
+ UINT32 sbar45_limit_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_SBAR45LMT_LOWER_U;
+
+
+
+
+typedef union tagMiepSbar45lmtUpper
+{
+
+ struct
+ {
+ UINT32 Reserved_31 : 12 ;
+ UINT32 sbar45_limit_upper : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_SBAR45LMT_UPPER_U;
+
+
+
+
+typedef union tagMiepCbdfSbdf
+{
+
+ struct
+ {
+ UINT32 sfunc : 3 ;
+ UINT32 sdev : 5 ;
+ UINT32 sbus : 8 ;
+ UINT32 cap_sfunc_num : 3 ;
+ UINT32 cap_sdev_num : 5 ;
+ UINT32 cap_sbus_num : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_CBDF_SBDF_U;
+
+
+
+
+typedef union tagMiepPciCfgHdr0
+{
+
+ struct
+ {
+ UINT32 vendor_id : 16 ;
+ UINT32 device_id : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCI_CFG_HDR0_U;
+
+
+
+
+typedef union tagMiepPciCfgHdr1
+{
+
+ struct
+ {
+ UINT32 io_space_enable : 1 ;
+ UINT32 memory_space_enable : 1 ;
+ UINT32 bus_master_enable : 1 ;
+ UINT32 specialcycleenable : 1 ;
+ UINT32 memory_write_and_invalidate : 1 ;
+ UINT32 vga_palette_snoop_enable : 1 ;
+ UINT32 parity_error_response : 1 ;
+ UINT32 idsel_stepping_waitcycle_control : 1 ;
+ UINT32 serr_enable : 1 ;
+ UINT32 fastback_to_backenable : 1 ;
+ UINT32 interrupt_disable : 1 ;
+ UINT32 Reserved_35 : 5 ;
+ UINT32 Reserved_34 : 3 ;
+ UINT32 intx_status : 1 ;
+ UINT32 capabilitieslist : 1 ;
+ UINT32 pcibus66mhzcapable : 1 ;
+ UINT32 Reserved_33 : 1 ;
+ UINT32 fastback_to_back : 1 ;
+ UINT32 masterdataparityerror : 1 ;
+ UINT32 devsel_timing : 2 ;
+ UINT32 signaled_target_abort : 1 ;
+ UINT32 received_target_abort : 1 ;
+ UINT32 received_master_abort : 1 ;
+ UINT32 signaled_system_error : 1 ;
+ UINT32 detected_perr : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCI_CFG_HDR1_U;
+
+
+
+
+typedef union tagMiepPciCfgHdr11
+{
+
+ struct
+ {
+ UINT32 subsystem_vendor_id : 16 ;
+ UINT32 subsystemid : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCI_CFG_HDR11_U;
+
+
+
+
+typedef union tagMiepPciCfgHdr13
+{
+
+ struct
+ {
+ UINT32 capptr : 8 ;
+ UINT32 Reserved_37 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCI_CFG_HDR13_U;
+
+
+
+
+typedef union tagMiepPciCfgHdr15
+{
+
+ struct
+ {
+ UINT32 int_line : 8 ;
+ UINT32 int_pin : 8 ;
+ UINT32 min_grant : 8 ;
+ UINT32 max_latency : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCI_CFG_HDR15_U;
+
+
+
+
+typedef union tagMiepPciMsiCap0
+{
+
+ struct
+ {
+ UINT32 msi_cap_id : 8 ;
+ UINT32 next_capability_pointer : 8 ;
+ UINT32 msi_enabled : 1 ;
+ UINT32 multiple_message_capable : 3 ;
+ UINT32 multiple_message_enabled : 3 ;
+ UINT32 msi_64_en : 1 ;
+ UINT32 pvm_en : 1 ;
+ UINT32 message_control_register : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCI_MSI_CAP0_U;
+
+
+
+
+typedef union tagMiepPciMsiCap1
+{
+
+ struct
+ {
+ UINT32 Reserved_42 : 2 ;
+ UINT32 msi_addr_low : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCI_MSI_CAP1_U;
+
+
+
+
+typedef union tagMiepPciMsiCap3
+{
+
+ struct
+ {
+ UINT32 msi_data : 16 ;
+ UINT32 Reserved_43 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCI_MSI_CAP3_U;
+
+
+
+
+typedef union tagMiepPcieCap0
+{
+
+ struct
+ {
+ UINT32 pcie_cap_id : 8 ;
+ UINT32 pcie_next_ptr : 8 ;
+ UINT32 pcie_capability_version : 4 ;
+ UINT32 device_port_type : 4 ;
+ UINT32 slot_implemented : 1 ;
+ UINT32 interrupt_message_number : 5 ;
+ UINT32 Reserved_44 : 2 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCIE_CAP0_U;
+
+
+
+
+typedef union tagMiepPcieCap1
+{
+
+ struct
+ {
+ UINT32 max_payload_size_supported : 3 ;
+ UINT32 phantom_function_supported : 2 ;
+ UINT32 extended_tagfield_supported : 1 ;
+ UINT32 endpoint_l0sacceptable_latency : 3 ;
+ UINT32 endpoint_l1acceptable_latency : 3 ;
+ UINT32 undefined : 3 ;
+ UINT32 Reserved_47 : 3 ;
+ UINT32 captured_slot_power_limit_value : 8 ;
+ UINT32 captured_slot_power_limit_scale : 2 ;
+ UINT32 function_level_reset : 1 ;
+ UINT32 Reserved_46 : 3 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCIE_CAP1_U;
+
+
+
+
+typedef union tagMiepPcieCap2
+{
+
+ struct
+ {
+ UINT32 correctable_error_reporting_enable : 1 ;
+ UINT32 non_fatal_error_reporting_enable : 1 ;
+ UINT32 fatal_error_reporting_enable : 1 ;
+ UINT32 urenable : 1 ;
+ UINT32 enable_relaxed_ordering : 1 ;
+ UINT32 max_payload_size : 3 ;
+ UINT32 extended_tagfieldenable : 1 ;
+ UINT32 phantom_function_enable : 1 ;
+ UINT32 auxpowerpmenable : 1 ;
+ UINT32 enablenosnoop : 1 ;
+ UINT32 max_read_request_size : 3 ;
+ UINT32 Reserved_49 : 1 ;
+ UINT32 correctableerrordetected : 1 ;
+ UINT32 non_fatalerrordetected : 1 ;
+ UINT32 fatalerrordetected : 1 ;
+ UINT32 unsupportedrequestdetected : 1 ;
+ UINT32 auxpowerdetected : 1 ;
+ UINT32 transactionpending : 1 ;
+ UINT32 Reserved_48 : 10 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCIE_CAP2_U;
+
+
+
+
+typedef union tagMiepPcieCap3
+{
+
+ struct
+ {
+ UINT32 max_link_speed : 4 ;
+ UINT32 max_link_width : 6 ;
+ UINT32 active_state_power_management : 2 ;
+ UINT32 l0s_exitlatency : 3 ;
+ UINT32 l1_exit_latency : 3 ;
+ UINT32 clock_power_management : 1 ;
+ UINT32 surprise_down_error_report_cap : 1 ;
+ UINT32 data_link_layer_active_report_cap : 1 ;
+ UINT32 link_bandwidth_noti_cap : 1 ;
+ UINT32 aspm_option_compliance : 1 ;
+ UINT32 Reserved_50 : 1 ;
+ UINT32 port_number : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCIE_CAP3_U;
+
+
+
+
+typedef union tagMiepPcieCap4
+{
+
+ struct
+ {
+ UINT32 active_state_power_management : 2 ;
+ UINT32 Reserved_53 : 1 ;
+ UINT32 rcb : 1 ;
+ UINT32 link_disable : 1 ;
+ UINT32 retrain_link : 1 ;
+ UINT32 common_clock_config : 1 ;
+ UINT32 extended_sync : 1 ;
+ UINT32 enable_clock_pwr_management : 1 ;
+ UINT32 hw_auto_width_disable : 1 ;
+ UINT32 link_bandwidth_management_int_en : 1 ;
+ UINT32 link_auto_bandwidth_int_en : 1 ;
+ UINT32 Reserved_52 : 4 ;
+ UINT32 current_link_speed : 4 ;
+ UINT32 negotiated_link_width : 6 ;
+ UINT32 Reserved_51 : 1 ;
+ UINT32 link_training : 1 ;
+ UINT32 slot_clock_configration : 1 ;
+ UINT32 data_link_layer_active : 1 ;
+ UINT32 link_bandwidth_management_status : 1 ;
+ UINT32 link_auto_bandwidth_status : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCIE_CAP4_U;
+
+
+
+
+typedef union tagMiepPcieCap5
+{
+
+ struct
+ {
+ UINT32 attentioonbuttonpresent : 1 ;
+ UINT32 powercontrollerpresent : 1 ;
+ UINT32 mrlsensorpresent : 1 ;
+ UINT32 attentionindicatorpresent : 1 ;
+ UINT32 powerindicatorpresent : 1 ;
+ UINT32 hot_plugsurprise : 1 ;
+ UINT32 hot_plugcapable : 1 ;
+ UINT32 slotpowerlimitvalue : 8 ;
+ UINT32 slotpowerlimitscale : 2 ;
+ UINT32 electromechanicalinterlockpresen : 1 ;
+ UINT32 no_cmd_complete_support : 1 ;
+ UINT32 phy_slot_number : 13 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCIE_CAP5_U;
+
+
+
+
+typedef union tagMiepPcieCap6
+{
+
+ struct
+ {
+ UINT32 attentionbuttonpressedenable : 1 ;
+ UINT32 powerfaultdetectedenable : 1 ;
+ UINT32 mrlsensorchangedenable : 1 ;
+ UINT32 presencedetectchangedenable : 1 ;
+ UINT32 commandcompletedinterruptenable : 1 ;
+ UINT32 hot_pluginterruptenable : 1 ;
+ UINT32 attentionindicatorcontrol : 2 ;
+ UINT32 powerindicatorcontrol : 2 ;
+ UINT32 powercontrollercontrol : 1 ;
+ UINT32 electromechanicalinterlockcontrol : 1 ;
+ UINT32 datalinklayerstatechangedenable : 1 ;
+ UINT32 Reserved_54 : 3 ;
+ UINT32 attentionbuttonpressed : 1 ;
+ UINT32 powerfaultdetected : 1 ;
+ UINT32 mrlsensorchanged : 1 ;
+ UINT32 presencedetectchanged : 1 ;
+ UINT32 commandcompleted : 1 ;
+ UINT32 mrlsensorstate : 1 ;
+ UINT32 presencedetectstate : 1 ;
+ UINT32 electromechanicalinterlockstatus : 1 ;
+ UINT32 datalinklayerstatechanged : 1 ;
+ UINT32 slot_ctrl_status : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCIE_CAP6_U;
+
+
+
+
+typedef union tagMiepPcieCap7
+{
+
+ struct
+ {
+ UINT32 systemerroroncorrectableerrorenable : 1 ;
+ UINT32 systemerroronnon_fatalerrorenable : 1 ;
+ UINT32 systemerroronfatalerrorenable : 1 ;
+ UINT32 pmeinterruptenable : 1 ;
+ UINT32 crssoftwarevisibilityenable : 1 ;
+ UINT32 Reserved_55 : 11 ;
+ UINT32 crssoftwarevisibility : 1 ;
+ UINT32 root_cap : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCIE_CAP7_U;
+
+
+
+
+typedef union tagMiepPcieCap8
+{
+
+ struct
+ {
+ UINT32 pmerequesterid : 16 ;
+ UINT32 pmestatus : 1 ;
+ UINT32 pmepending : 1 ;
+ UINT32 root_status : 14 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCIE_CAP8_U;
+
+
+
+
+typedef union tagMiepPcieCap9
+{
+
+ struct
+ {
+ UINT32 completiontimeoutrangessupported : 4 ;
+ UINT32 completiontimeoutdisablesupported : 1 ;
+ UINT32 ariforwardingsupported : 1 ;
+ UINT32 atomicoproutingsupported : 1 ;
+ UINT32 _2_bitatomicopcompletersupported : 1 ;
+ UINT32 _4_bitatomicopcompletersupported : 1 ;
+ UINT32 _28_bitcascompletersupported : 1 ;
+ UINT32 noro_enabledpr_prpassing : 1 ;
+ UINT32 Reserved_56 : 1 ;
+ UINT32 tphcompletersupported : 2 ;
+ UINT32 dev_cap2 : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCIE_CAP9_U;
+
+
+
+
+typedef union tagMiepPcieCap10
+{
+
+ struct
+ {
+ UINT32 completiontimeoutvalue : 4 ;
+ UINT32 completiontimeoutdisable : 1 ;
+ UINT32 ariforwardingsupported : 1 ;
+ UINT32 atomicoprequesterenable : 1 ;
+ UINT32 atomicopegressblocking : 1 ;
+ UINT32 idorequestenable : 1 ;
+ UINT32 idocompletionenable : 1 ;
+ UINT32 dev_ctrl2 : 22 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCIE_CAP10_U;
+
+
+
+
+typedef union tagMiepPcieCap11
+{
+
+ struct
+ {
+ UINT32 Reserved_58 : 1 ;
+ UINT32 gen1_suport : 1 ;
+ UINT32 gen2_suport : 1 ;
+ UINT32 gen3_suport : 1 ;
+ UINT32 Reserved_57 : 4 ;
+ UINT32 crosslink_supported : 1 ;
+ UINT32 link_cap2 : 23 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCIE_CAP11_U;
+
+
+
+
+typedef union tagMiepPcieCap12
+{
+
+ struct
+ {
+ UINT32 targetlinkspeed : 4 ;
+ UINT32 entercompliance : 1 ;
+ UINT32 hardwareautonomousspeeddisa : 1 ;
+ UINT32 selectablede_empha : 1 ;
+ UINT32 transmitmargin : 3 ;
+ UINT32 _entermodifiedcompliance : 1 ;
+ UINT32 compliancesos : 1 ;
+ UINT32 de_emphasislevel : 4 ;
+ UINT32 currentde_emphasislevel : 1 ;
+ UINT32 equalizationcomplete : 1 ;
+ UINT32 equalizationphase1successful : 1 ;
+ UINT32 equalizationphase2successful : 1 ;
+ UINT32 equalizationphase3successful : 1 ;
+ UINT32 linkequalizationrequest : 1 ;
+ UINT32 link_ctrl2_status2 : 10 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCIE_CAP12_U;
+
+
+
+
+typedef union tagMiepSlotCap
+{
+
+ struct
+ {
+ UINT32 slotnumberingcapabilitiesid : 8 ;
+ UINT32 nextcapabilitypointer : 8 ;
+ UINT32 add_incardslotsprovided : 5 ;
+ UINT32 firstinchassis : 1 ;
+ UINT32 Reserved_59 : 2 ;
+ UINT32 slot_cap : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_SLOT_CAP_U;
+
+
+
+
+typedef union tagMiepAerCap0
+{
+
+ struct
+ {
+ UINT32 pciexpressextendedcapabilityid : 16 ;
+ UINT32 capabilityversion : 4 ;
+ UINT32 aer_cap_hdr : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_AER_CAP0_U;
+
+
+
+
+typedef union tagMiepAerCap1
+{
+
+ struct
+ {
+ UINT32 Reserved_65 : 1 ;
+ UINT32 Reserved_64 : 3 ;
+ UINT32 datalinkprotocolerrorsta : 1 ;
+ UINT32 surprisedownerrorstatus : 1 ;
+ UINT32 Reserved_63 : 6 ;
+ UINT32 poisonedtlpstatu : 1 ;
+ UINT32 flowcontrolprotocolerrorst : 1 ;
+ UINT32 completiontimeouts : 1 ;
+ UINT32 completerabortstatus : 1 ;
+ UINT32 receiveroverflowstatus : 1 ;
+ UINT32 malformedtlpstatus : 1 ;
+ UINT32 ecrcerrorstatus : 1 ;
+ UINT32 ecrcerrorstat : 1 ;
+ UINT32 unsupportedrequesterrorstatus : 1 ;
+ UINT32 Reserved_62 : 3 ;
+ UINT32 atomicopegressblockedstatus : 1 ;
+ UINT32 uncorr_err_status : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_AER_CAP1_U;
+
+
+
+
+typedef union tagMiepAerCap2
+{
+
+ struct
+ {
+ UINT32 Reserved_69 : 1 ;
+ UINT32 Reserved_68 : 3 ;
+ UINT32 datalinkprotocolerrormask : 1 ;
+ UINT32 surprisedownerrormask : 1 ;
+ UINT32 Reserved_67 : 6 ;
+ UINT32 poisonedtlpmask : 1 ;
+ UINT32 flowcontrolprotocolerrormask : 1 ;
+ UINT32 completiontimeoutmask : 1 ;
+ UINT32 completerabortmask : 1 ;
+ UINT32 unexpectedcompletionmask : 1 ;
+ UINT32 receiveroverflowmask : 1 ;
+ UINT32 malformedtlpmask : 1 ;
+ UINT32 ecrcerrormask : 1 ;
+ UINT32 unsupportedrequesterrormask : 1 ;
+ UINT32 Reserved_66 : 3 ;
+ UINT32 atomicopegressblockedmask : 1 ;
+ UINT32 uncorr_err_mask : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_AER_CAP2_U;
+
+
+
+
+typedef union tagMiepAerCap3
+{
+
+ struct
+ {
+ UINT32 Reserved_73 : 1 ;
+ UINT32 Reserved_72 : 3 ;
+ UINT32 datalinkprotocolerrorsever : 1 ;
+ UINT32 surprisedownerrorseverity : 1 ;
+ UINT32 Reserved_71 : 6 ;
+ UINT32 poisonedtlpseverity : 1 ;
+ UINT32 flowcontrolprotocolerrorseveri : 1 ;
+ UINT32 completiontimeoutseverity : 1 ;
+ UINT32 completerabortseverity : 1 ;
+ UINT32 unexpectedcompletionseverity : 1 ;
+ UINT32 receiveroverflowseverity : 1 ;
+ UINT32 malformedtlpseverity : 1 ;
+ UINT32 ecrcerrorseverity : 1 ;
+ UINT32 unsupportedrequesterrorseverity : 1 ;
+ UINT32 Reserved_70 : 3 ;
+ UINT32 atomicopegressblockedseverity : 1 ;
+ UINT32 uncorr_err_ser : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_AER_CAP3_U;
+
+
+
+
+typedef union tagMiepAerCap4
+{
+
+ struct
+ {
+ UINT32 receivererrorstatus : 1 ;
+ UINT32 Reserved_75 : 5 ;
+ UINT32 badtlpstatus : 1 ;
+ UINT32 baddllpstatus : 1 ;
+ UINT32 replay_numrolloverstatus : 1 ;
+ UINT32 Reserved_74 : 3 ;
+ UINT32 replytimertimeoutstatus : 1 ;
+ UINT32 advisorynon_fatalerrorstatus : 1 ;
+ UINT32 corr_err_status : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_AER_CAP4_U;
+
+
+
+
+typedef union tagMiepAerCap5
+{
+
+ struct
+ {
+ UINT32 receivererrormask : 1 ;
+ UINT32 Reserved_77 : 5 ;
+ UINT32 badtlpmask : 1 ;
+ UINT32 baddllpmask : 1 ;
+ UINT32 replay_numrollovermask : 1 ;
+ UINT32 Reserved_76 : 3 ;
+ UINT32 replytimertimeoutmask : 1 ;
+ UINT32 advisorynon_fatalerrormask : 1 ;
+ UINT32 corr_err_mask : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_AER_CAP5_U;
+
+
+
+
+typedef union tagMiepAerCap6
+{
+
+ struct
+ {
+ UINT32 firsterrorpointer : 5 ;
+ UINT32 ecrcgenerationcapability : 1 ;
+ UINT32 ecrcgenerationenable : 1 ;
+ UINT32 ecrccheckcapable : 1 ;
+ UINT32 ecrccheckenable : 1 ;
+ UINT32 adv_cap_ctrl : 23 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_AER_CAP6_U;
+
+
+
+
+typedef union tagMiepAerCap11
+{
+
+ struct
+ {
+ UINT32 correctableerrorreportingenable : 1 ;
+ UINT32 non_fatalerrorreportingenable : 1 ;
+ UINT32 fatalerrorreportingenable : 1 ;
+ UINT32 root_err_cmd : 29 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_AER_CAP11_U;
+
+
+
+
+typedef union tagMiepAerCap12
+{
+
+ struct
+ {
+ UINT32 err_correceived : 1 ;
+ UINT32 multipleerr_correceived : 1 ;
+ UINT32 err_fatal_nonfatalreceived : 1 ;
+ UINT32 multipleerr_fatal_nonfatalreceived : 1 ;
+ UINT32 firstuncorrectablefatal : 1 ;
+ UINT32 non_fatalerrormessagesreceived : 1 ;
+ UINT32 fatalerrormessagesreceived : 1 ;
+ UINT32 Reserved_78 : 20 ;
+ UINT32 root_err_status : 5 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_AER_CAP12_U;
+
+
+
+
+typedef union tagMiepAerCap13
+{
+
+ struct
+ {
+ UINT32 err_corsourceidentification : 16 ;
+ UINT32 err_src_id : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_AER_CAP13_U;
+
+
+
+
+typedef union tagMiepVcCap0
+{
+
+ struct
+ {
+ UINT32 pciexpressextendedcapabilityid : 16 ;
+ UINT32 capabilityversion : 4 ;
+ UINT32 vc_cap_hdr : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_VC_CAP0_U;
+
+
+
+
+typedef union tagMiepVcCap1
+{
+
+ struct
+ {
+ UINT32 extendedvccount : 3 ;
+ UINT32 Reserved_81 : 1 ;
+ UINT32 lowpriorityextendedvccount : 3 ;
+ UINT32 Reserved_80 : 1 ;
+ UINT32 referenceclock : 2 ;
+ UINT32 portarbitrationtableentrysize : 2 ;
+ UINT32 vc_cap1 : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_VC_CAP1_U;
+
+
+
+
+typedef union tagMiepVcCap2
+{
+
+ struct
+ {
+ UINT32 vcarbitrationcapability : 8 ;
+ UINT32 Reserved_82 : 16 ;
+ UINT32 vc_cap2 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_VC_CAP2_U;
+
+
+
+
+typedef union tagMiepVcCap3
+{
+
+ struct
+ {
+ UINT32 loadvcarbitrationtable : 1 ;
+ UINT32 vcarbitrationselect : 3 ;
+ UINT32 Reserved_84 : 12 ;
+ UINT32 arbitrationtablestatus : 1 ;
+ UINT32 Reserved_83 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_VC_CAP3_U;
+
+
+
+
+typedef union tagMiepVcCap4
+{
+
+ struct
+ {
+ UINT32 portarbitrationcapability : 8 ;
+ UINT32 Reserved_87 : 6 ;
+ UINT32 Reserved_86 : 1 ;
+ UINT32 rejectsnooptransactions : 1 ;
+ UINT32 maximumtimeslots : 7 ;
+ UINT32 Reserved_85 : 1 ;
+ UINT32 vc_res_cap : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_VC_CAP4_U;
+
+
+
+
+typedef union tagMiepVcCap5
+{
+
+ struct
+ {
+ UINT32 tc_vcmap : 8 ;
+ UINT32 Reserved_90 : 8 ;
+ UINT32 loadportarbitrationtable : 1 ;
+ UINT32 portarbitrationselec : 3 ;
+ UINT32 Reserved_89 : 4 ;
+ UINT32 vcid : 3 ;
+ UINT32 Reserved_88 : 4 ;
+ UINT32 vc_res_ctrl : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_VC_CAP5_U;
+
+
+
+
+typedef union tagMiepVcCap6
+{
+
+ struct
+ {
+ UINT32 Reserved_91 : 16 ;
+ UINT32 portarbitrationtablestatus : 1 ;
+ UINT32 vcnegotiationpending : 1 ;
+ UINT32 vc_res_status : 14 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_VC_CAP6_U;
+
+
+
+
+typedef union tagMiepVcCap7
+{
+
+ struct
+ {
+ UINT32 portarbitrationcapability : 8 ;
+ UINT32 Reserved_94 : 6 ;
+ UINT32 Reserved_93 : 1 ;
+ UINT32 rejectsnooptransactions : 1 ;
+ UINT32 maximumtimeslots : 7 ;
+ UINT32 Reserved_92 : 1 ;
+ UINT32 vc_res_cap0 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_VC_CAP7_U;
+
+
+
+
+typedef union tagMiepVcCap8
+{
+
+ struct
+ {
+ UINT32 tc_vcmap : 8 ;
+ UINT32 Reserved_97 : 8 ;
+ UINT32 loadportarbitrationtable : 1 ;
+ UINT32 portarbitrationselect : 3 ;
+ UINT32 Reserved_96 : 4 ;
+ UINT32 vcid : 3 ;
+ UINT32 Reserved_95 : 4 ;
+ UINT32 vc_res_ctrl0 : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_VC_CAP8_U;
+
+
+
+
+typedef union tagMiepVcCap9
+{
+
+ struct
+ {
+ UINT32 Reserved_98 : 16 ;
+ UINT32 arbitrationtablestatus : 1 ;
+ UINT32 vcnegotiationpending : 1 ;
+ UINT32 vc_res_status0 : 14 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_VC_CAP9_U;
+
+
+
+
+typedef union tagMiepPortLogic0
+{
+
+ struct
+ {
+ UINT32 ack_lat_timer : 16 ;
+ UINT32 replay_timer : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC0_U;
+
+
+
+
+typedef union tagMiepPortLogic2
+{
+
+ struct
+ {
+ UINT32 linknumber : 8 ;
+ UINT32 Reserved_101 : 7 ;
+ UINT32 forcelink : 1 ;
+ UINT32 linkstate : 6 ;
+ UINT32 Reserved_100 : 2 ;
+ UINT32 port_force_link : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC2_U;
+
+
+
+
+typedef union tagMiepPortLogic3
+{
+
+ struct
+ {
+ UINT32 ackfrequency : 8 ;
+ UINT32 n_fts : 8 ;
+ UINT32 commonclockn_fts : 8 ;
+ UINT32 l0sentrancelatency : 3 ;
+ UINT32 l1entrancelatency : 3 ;
+ UINT32 enteraspml1withoutreceiveinl0s : 1 ;
+ UINT32 ack_aspm : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC3_U;
+
+
+
+
+typedef union tagMiepPortLogic4
+{
+
+ struct
+ {
+ UINT32 vendorspecificdllprequest : 1 ;
+ UINT32 scrambledisable : 1 ;
+ UINT32 loopbackenable : 1 ;
+ UINT32 resetassert : 1 ;
+ UINT32 Reserved_104 : 1 ;
+ UINT32 dlllinkenable : 1 ;
+ UINT32 Reserved_103 : 1 ;
+ UINT32 fastlinkmode : 1 ;
+ UINT32 Reserved_102 : 8 ;
+ UINT32 linkmodeenable : 6 ;
+ UINT32 crosslinkenable : 1 ;
+ UINT32 crosslinkactive : 1 ;
+ UINT32 port_link_ctrl : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC4_U;
+
+
+
+
+typedef union tagMiepPortLogic5
+{
+
+ struct
+ {
+ UINT32 insertlaneskewfortransmit : 24 ;
+ UINT32 flowcontroldisable : 1 ;
+ UINT32 ack_nakdisable : 1 ;
+ UINT32 Reserved_105 : 5 ;
+ UINT32 lane_skew : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC5_U;
+
+
+
+
+typedef union tagMiepPortLogic6
+{
+
+ struct
+ {
+ UINT32 numberoftssymbols : 4 ;
+ UINT32 Reserved_107 : 4 ;
+ UINT32 numberofskpsymbols : 3 ;
+ UINT32 Reserved_106 : 3 ;
+ UINT32 timermodifierforreplaytimer : 5 ;
+ UINT32 timermodifierforack_naklatencytimer : 5 ;
+ UINT32 timermodifierforflowcontrolwatchdogtimer : 5 ;
+ UINT32 sym_num : 3 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC6_U;
+
+
+
+
+typedef union tagMiepPortLogic7
+{
+
+ struct
+ {
+ UINT32 vc0posteddataqueuedepth : 11 ;
+ UINT32 Reserved_108 : 4 ;
+ UINT32 sym_timer : 1 ;
+ UINT32 maskfunctionmismatchfilteringfo : 1 ;
+ UINT32 maskpoisonedtlpfiltering : 1 ;
+ UINT32 maskbarmatchfiltering : 1 ;
+ UINT32 masktype1configurationrequestfiltering : 1 ;
+ UINT32 masklockedrequestfiltering : 1 ;
+ UINT32 masktagerrorrulesforreceivedcompletions : 1 ;
+ UINT32 maskrequesteridmismatcherrorforreceivedcompletions : 1 ;
+ UINT32 maskfunctionmismatcherrorforreceivedcompletions : 1 ;
+ UINT32 mask_traffic_classmis_match_error_forreceived_completions : 1 ;
+ UINT32 mask_attributesmismatcherrorforreceivedcompletions : 1 ;
+ UINT32 mask_length_mismatch_error_forreceive_dcompletions : 1 ;
+ UINT32 maske_crcerror_filtering : 1 ;
+ UINT32 maske_crcerror_filtering_forcompletions : 1 ;
+ UINT32 message_control : 1 ;
+ UINT32 maskfilteringofreceived : 1 ;
+ UINT32 flt_mask1 : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC7_U;
+
+
+
+
+typedef union tagMiepPortLogic8
+{
+
+ struct
+ {
+ UINT32 cx_flt_mask_venmsg0_drop : 1 ;
+ UINT32 cx_flt_mask_venmsg1_drop : 1 ;
+ UINT32 cx_flt_mask_dabort_4ucpl : 1 ;
+ UINT32 cx_flt_mask_handle_flush : 1 ;
+ UINT32 flt_mask2 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC8_U;
+
+
+
+
+typedef union tagMiepPortLogic9
+{
+
+ struct
+ {
+ UINT32 amba_multi_outbound_decomp_np : 1 ;
+ UINT32 amba_obnp_ctrl : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC9_U;
+
+
+
+
+typedef union tagMiepPortLogic12
+{
+
+ struct
+ {
+ UINT32 transmitposteddatafccredits : 12 ;
+ UINT32 transmitpostedheaderfccredits : 8 ;
+ UINT32 tx_pfc_status : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC12_U;
+
+
+
+
+typedef union tagMiepPortLogic13
+{
+
+ struct
+ {
+ UINT32 transmitnon_posteddatafccredits : 12 ;
+ UINT32 transmitnon_postedheaderfccredits : 8 ;
+ UINT32 tx_npfc_status : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC13_U;
+
+
+
+
+typedef union tagMiepPortLogic14
+{
+
+ struct
+ {
+ UINT32 transmitcompletiondatafccredits : 12 ;
+ UINT32 transmitcompletionheaderfccredits : 8 ;
+ UINT32 tx_cplfc_status : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC14_U;
+
+
+
+
+typedef union tagMiepPortLogic15
+{
+
+ struct
+ {
+ UINT32 rx_tlp_fc_credit_not_retured : 1 ;
+ UINT32 tx_retry_buf_not_empty : 1 ;
+ UINT32 rx_queue_not_empty : 1 ;
+ UINT32 Reserved_110 : 13 ;
+ UINT32 fc_latency_timer_override_value : 13 ;
+ UINT32 Reserved_109 : 2 ;
+ UINT32 fc_latency_timer_override_en : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC15_U;
+
+
+
+
+typedef union tagMiepPortLogic16
+{
+
+ struct
+ {
+ UINT32 vc0posteddatacredits : 12 ;
+ UINT32 vc0postedheadercredits : 8 ;
+ UINT32 Reserved_112 : 1 ;
+ UINT32 vc0_postedtlpqueuemode : 1 ;
+ UINT32 vc0postedtlpqueuemode : 1 ;
+ UINT32 vc0postedtlpqueuemo : 1 ;
+ UINT32 Reserved_111 : 6 ;
+ UINT32 tlptypeorderingforvc0 : 1 ;
+ UINT32 rx_pque_ctrl : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC16_U;
+
+
+
+
+typedef union tagMiepPortLogic17
+{
+
+ struct
+ {
+ UINT32 vc0non_posteddatacredits : 12 ;
+ UINT32 vc0non_postedheadercredits : 8 ;
+ UINT32 rx_npque_ctrl : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC17_U;
+
+
+
+
+typedef union tagMiepPortLogic18
+{
+
+ struct
+ {
+ UINT32 vco_comp_data_credits : 12 ;
+ UINT32 vc0_cpl_header_credt : 8 ;
+ UINT32 Reserved_114 : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC18_U;
+
+
+
+
+typedef union tagMiepPortLogic19
+{
+
+ struct
+ {
+ UINT32 vco_posted_data_que_path : 14 ;
+ UINT32 Reserved_115 : 2 ;
+ UINT32 vco_posted_head_queue_depth : 10 ;
+ UINT32 vc_pbuf_ctrl : 6 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC19_U;
+
+
+
+
+typedef union tagMiepPortLogic20
+{
+
+ struct
+ {
+ UINT32 vco_np_data_que_depth : 14 ;
+ UINT32 Reserved_117 : 2 ;
+ UINT32 vco_np_header_que_depth : 10 ;
+ UINT32 vc_npbuf_ctrl : 6 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC20_U;
+
+
+
+
+typedef union tagMiepPortLogic21
+{
+
+ struct
+ {
+ UINT32 vco_comp_data_queue_depth : 14 ;
+ UINT32 Reserved_119 : 2 ;
+ UINT32 vco_posted_head_queue_depth : 10 ;
+ UINT32 Reserved_118 : 6 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC21_U;
+
+
+
+
+typedef union tagMiepPortLogic22
+{
+
+ struct
+ {
+ UINT32 n_fts : 8 ;
+ UINT32 pre_determ_num_of_lane : 9 ;
+ UINT32 det_sp_change : 1 ;
+ UINT32 config_phy_tx_sw : 1 ;
+ UINT32 config_tx_comp_rcv_bit : 1 ;
+ UINT32 set_emp_level : 1 ;
+ UINT32 Reserved_120 : 11 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC22_U;
+
+
+
+
+typedef union tagMiepPortlogic25
+{
+
+ struct
+ {
+ UINT32 remote_rd_req_size : 3 ;
+ UINT32 Reserved_123 : 5 ;
+ UINT32 remote_max_brd_tag : 8 ;
+ UINT32 Reserved_122 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC25_U;
+
+
+
+
+typedef union tagMiepPortlogic26
+{
+
+ struct
+ {
+ UINT32 resize_master_resp_compser : 1 ;
+ UINT32 axi_ctrl1 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC26_U;
+
+
+
+
+typedef union tagMiepPortlogic54
+{
+
+ struct
+ {
+ UINT32 region_index : 4 ;
+ UINT32 Reserved_124 : 27 ;
+ UINT32 iatu_view : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC54_U;
+
+
+
+
+typedef union tagMiepPortlogic55
+{
+
+ struct
+ {
+ UINT32 iatu1_type : 5 ;
+ UINT32 iatu1_tc : 3 ;
+ UINT32 iatu1_td : 1 ;
+ UINT32 iatu1_attr : 2 ;
+ UINT32 Reserved_128 : 5 ;
+ UINT32 iatu1_at : 2 ;
+ UINT32 Reserved_127 : 2 ;
+ UINT32 iatu1_id : 3 ;
+ UINT32 Reserved_126 : 9 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC55_U;
+
+
+
+
+typedef union tagMiepPortlogic56
+{
+
+ struct
+ {
+ UINT32 iatu2_type : 8 ;
+ UINT32 iatu2_bar_num : 3 ;
+ UINT32 Reserved_132 : 3 ;
+ UINT32 iatu2_tc_match_en : 1 ;
+ UINT32 iatu2_td_match_en : 1 ;
+ UINT32 iatu2_attr_match_en : 1 ;
+ UINT32 Reserved_131 : 1 ;
+ UINT32 iatu2_at_match_en : 1 ;
+ UINT32 iatu2_func_num_match_en : 1 ;
+ UINT32 iatu2_virtual_func_num_match_en : 1 ;
+ UINT32 message_code_match_en : 1 ;
+ UINT32 Reserved_130 : 2 ;
+ UINT32 iatu2_response_code : 2 ;
+ UINT32 Reserved_129 : 1 ;
+ UINT32 iatu2_fuzzy_type_match_mode : 1 ;
+ UINT32 iatu2_cfg_shift_mode : 1 ;
+ UINT32 iatu2_ivert_mode : 1 ;
+ UINT32 iatu2_match_mode : 1 ;
+ UINT32 iatu2_region_en : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC56_U;
+
+
+
+
+typedef union tagMiepPortlogic57
+{
+
+ struct
+ {
+ UINT32 iatu_start_low : 12 ;
+ UINT32 iatu_start_high : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC57_U;
+
+
+
+
+typedef union tagMiepPortlogic59
+{
+
+ struct
+ {
+ UINT32 iatu_limit_low : 12 ;
+ UINT32 iatu_limit_high : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC59_U;
+
+
+
+
+typedef union tagMiepPortlogic60
+{
+
+ struct
+ {
+ UINT32 xlated_addr_high : 12 ;
+ UINT32 xlated_addr_low : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC60_U;
+
+
+
+
+typedef union tagMiepPortlogic62
+{
+
+ struct
+ {
+ UINT32 dma_wr_eng_en : 1 ;
+ UINT32 dma_wr_ena : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC62_U;
+
+
+
+
+typedef union tagMiepPortlogic63
+{
+
+ struct
+ {
+ UINT32 wr_doorbell_num : 3 ;
+ UINT32 Reserved_134 : 28 ;
+ UINT32 dma_wr_dbell_stop : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC63_U;
+
+
+
+
+typedef union tagMiepPortlogic64
+{
+
+ struct
+ {
+ UINT32 dma_read_eng_en : 1 ;
+ UINT32 Reserved_135 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC64_U;
+
+
+
+
+typedef union tagMiepPortlogic65
+{
+
+ struct
+ {
+ UINT32 rd_doorbell_num : 3 ;
+ UINT32 Reserved_137 : 28 ;
+ UINT32 dma_rd_dbell_stop : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC65_U;
+
+
+
+
+typedef union tagMiepPortlogic66
+{
+
+ struct
+ {
+ UINT32 done_int_status : 8 ;
+ UINT32 Reserved_139 : 8 ;
+ UINT32 abort_int_status : 8 ;
+ UINT32 Reserved_138 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC66_U;
+
+
+
+
+typedef union tagMiepPortlogic67
+{
+
+ struct
+ {
+ UINT32 done_int_mask : 8 ;
+ UINT32 Reserved_142 : 8 ;
+ UINT32 abort_int_mask : 8 ;
+ UINT32 Reserved_141 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC67_U;
+
+
+
+
+typedef union tagMiepPortlogic68
+{
+
+ struct
+ {
+ UINT32 done_int_clr : 8 ;
+ UINT32 Reserved_145 : 8 ;
+ UINT32 abort_int_clr : 8 ;
+ UINT32 Reserved_144 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC68_U;
+
+
+
+
+typedef union tagMiepPortlogic69
+{
+
+ struct
+ {
+ UINT32 app_rd_err_det : 8 ;
+ UINT32 Reserved_147 : 8 ;
+ UINT32 ll_element_fetch_err_det : 8 ;
+ UINT32 Reserved_146 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC69_U;
+
+
+
+
+typedef union tagMiepPortlogic74
+{
+
+ struct
+ {
+ UINT32 dma_wr_c0_imwr_data : 16 ;
+ UINT32 dma_wr_c1_imwr_data : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC74_U;
+
+
+
+
+typedef union tagMiepPortlogic75
+{
+
+ struct
+ {
+ UINT32 wr_ch_ll_remote_abort_int_en : 8 ;
+ UINT32 Reserved_149 : 8 ;
+ UINT32 wr_ch_ll_local_abort_int_en : 8 ;
+ UINT32 Reserved_148 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC75_U;
+
+
+
+
+typedef union tagMiepPortlogic76
+{
+
+ struct
+ {
+ UINT32 done_int_status : 8 ;
+ UINT32 Reserved_152 : 8 ;
+ UINT32 abort_int_status : 8 ;
+ UINT32 Reserved_151 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC76_U;
+
+
+
+
+typedef union tagMiepPortlogic77
+{
+
+ struct
+ {
+ UINT32 done_int_mask : 8 ;
+ UINT32 Reserved_154 : 8 ;
+ UINT32 abort_int_mask : 8 ;
+ UINT32 dma_rd_int_mask : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC77_U;
+
+
+
+
+typedef union tagMiepPortlogic78
+{
+
+ struct
+ {
+ UINT32 done_int_clr : 8 ;
+ UINT32 Reserved_156 : 8 ;
+ UINT32 abort_int_clr : 8 ;
+ UINT32 dma_rd_int_clr : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC78_U;
+
+
+
+
+typedef union tagMiepPortlogic79
+{
+
+ struct
+ {
+ UINT32 app_wr_err_det : 8 ;
+ UINT32 Reserved_157 : 8 ;
+ UINT32 link_list_fetch_err_det : 8 ;
+ UINT32 dma_rd_err_low : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC79_U;
+
+
+
+
+typedef union tagMiepPortlogic80
+{
+
+ struct
+ {
+ UINT32 unspt_request : 8 ;
+ UINT32 completer_abort : 8 ;
+ UINT32 cpl_time_out : 8 ;
+ UINT32 dma_rd_err_high : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC80_U;
+
+
+
+
+typedef union tagMiepPortlogic81
+{
+
+ struct
+ {
+ UINT32 remote_abort_int_en : 8 ;
+ UINT32 Reserved_159 : 8 ;
+ UINT32 local_abort_int_en : 8 ;
+ UINT32 dma_rd_ll_err_ena : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC81_U;
+
+
+
+
+typedef union tagMiepPortlogic86
+{
+
+ struct
+ {
+ UINT32 channel_dir : 3 ;
+ UINT32 Reserved_162 : 28 ;
+ UINT32 dma_ch_con_idx : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC86_U;
+
+
+
+
+typedef union tagMiepPortlogic87
+{
+
+ struct
+ {
+ UINT32 cycle_bit : 1 ;
+ UINT32 toggle_cycle_bit : 1 ;
+ UINT32 load_link_pointer : 1 ;
+ UINT32 local_int_en : 1 ;
+ UINT32 remote_int_en : 1 ;
+ UINT32 channel_status : 2 ;
+ UINT32 Reserved_166 : 1 ;
+ UINT32 consumer_cycle_state : 1 ;
+ UINT32 linked_list_en : 1 ;
+ UINT32 Reserved_165 : 2 ;
+ UINT32 func_num_dma : 5 ;
+ UINT32 Reserved_164 : 7 ;
+ UINT32 no_snoop : 1 ;
+ UINT32 ro : 1 ;
+ UINT32 td : 1 ;
+ UINT32 tc : 3 ;
+ UINT32 dma_ch_ctrl : 2 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC87_U;
+
+
+
+
+typedef union tagMiepPortlogic93
+{
+
+ struct
+ {
+ UINT32 Reserved_168 : 2 ;
+ UINT32 dma_ll_ptr_low : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC93_U;
+
+
+
+#define PCIE_IEP_BASE (0x00000000)
+
+
+
+
+#define PCIE_IEP_DEVICE_VENDOR_ID_REG (PCIE_IEP_BASE + 0x0)
+#define PCIE_IEP_PCISTS_PCICMD_REG (PCIE_IEP_BASE + 0x4)
+#define PCIE_IEP_CCR_RID_REG (PCIE_IEP_BASE + 0x8)
+#define PCIE_IEP_PBAR01_BASE_LOWER_REG (PCIE_IEP_BASE + 0x10)
+#define PCIE_IEP_PBAR01_BASE_UPPER_REG (PCIE_IEP_BASE + 0x14)
+#define PCIE_IEP_PBAR23_BASE_LOWER_REG (PCIE_IEP_BASE + 0x18)
+#define PCIE_IEP_PBAR23_BASE_UPPER_REG (PCIE_IEP_BASE + 0x1C)
+#define PCIE_IEP_PBAR45_BASE_LOWER_REG (PCIE_IEP_BASE + 0x20)
+#define PCIE_IEP_PBAR45_BASE_UPPER_REG (PCIE_IEP_BASE + 0x24)
+#define PCIE_IEP_CARDBUSCISPTR_REG (PCIE_IEP_BASE + 0x28)
+#define PCIE_IEP_SUBSYSTEMID_REG (PCIE_IEP_BASE + 0x2C)
+#define PCIE_IEP_EXPANSIONROM_BASE_ADDR_REG (PCIE_IEP_BASE + 0x30)
+#define PCIE_IEP_CAPPTR_REG (PCIE_IEP_BASE + 0x34)
+#define PCIE_IEP_INTERRUPT_REG (PCIE_IEP_BASE + 0x3C)
+#define PCIE_IEP_MSI_CAPABILITY_REGISTER_REG (PCIE_IEP_BASE + 0x50)
+#define PCIE_IEP_MSI_LOWER32_BITADDRESS_REG (PCIE_IEP_BASE + 0x54)
+#define PCIE_IEP_MSI_UPPER32_BIT_ADDRESS_REG (PCIE_IEP_BASE + 0x58)
+#define PCIE_IEP_MSI_DATA_REG (PCIE_IEP_BASE + 0x5C)
+#define PCIE_IEP_MSI_MASK_REG (PCIE_IEP_BASE + 0x60)
+#define PCIE_IEP_MSI_PENDING_REG (PCIE_IEP_BASE + 0x64)
+#define PCIE_IEP_PCIE_CAPABILITY_REGISTER_REG (PCIE_IEP_BASE + 0x70)
+#define PCIE_IEP_DEVICE_CAPABILITIES_REGISTER_REG (PCIE_IEP_BASE + 0x74)
+#define PCIE_IEP_DEVICE_STATUS_REGISTER_REG (PCIE_IEP_BASE + 0x78)
+#define PCIE_IEP_LINK_CAPABILITY_REG (PCIE_IEP_BASE + 0x7C)
+#define PCIE_IEP_LINK_CONTROL_STATUS_REG (PCIE_IEP_BASE + 0x80)
+#define PCIE_IEP_AER_CAP_HEADER_REG (PCIE_IEP_BASE + 0x100)
+#define PCIE_IEP_UC_ERROR_STATUS_REG (PCIE_IEP_BASE + 0x104)
+#define PCIE_IEP_UC_ERROR_MASK_REG (PCIE_IEP_BASE + 0x108)
+#define PCIE_IEP_UC_ERROR_SEVERITY_REG (PCIE_IEP_BASE + 0x10C)
+#define PCIE_IEP_C_ERROR_STATUS_REG (PCIE_IEP_BASE + 0x110)
+#define PCIE_IEP_C_ERROR_MASK_REG (PCIE_IEP_BASE + 0x114)
+#define PCIE_IEP_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_REG (PCIE_IEP_BASE + 0x118)
+#define PCIE_IEP_HEADER_LOG_REGISTERS_1_REG (PCIE_IEP_BASE + 0x11C)
+#define PCIE_IEP_HEADER_LOG_REGISTERS_2_REG (PCIE_IEP_BASE + 0x120)
+#define PCIE_IEP_HEADER_LOG_REGISTERS_3_REG (PCIE_IEP_BASE + 0x124)
+#define PCIE_IEP_HEADER_LOG_REGISTERS_4_REG (PCIE_IEP_BASE + 0x128)
+#define PCIE_IEP_TLP_PREFIX_LOGREGISTERS_1_REG (PCIE_IEP_BASE + 0x130)
+#define PCIE_IEP_TLP_PREFIX_LOGREGISTERS_2_REG (PCIE_IEP_BASE + 0x134)
+#define PCIE_IEP_TLP_PREFIX_LOGREGISTERS_3_REG (PCIE_IEP_BASE + 0x138)
+#define PCIE_IEP_TLP_PREFIX_LOGREGISTERS_4_REG (PCIE_IEP_BASE + 0x13C)
+#define PCIE_IEP_NTB_IEP_CFG_SPACE_LOWER_REG (PCIE_IEP_BASE + 0x700)
+#define PCIE_IEP_NTB_IEP_CFG_SPACE_UPPER_REG (PCIE_IEP_BASE + 0x704)
+#define PCIE_IEP_NTB_IEP_BAR01_CTRL_REG (PCIE_IEP_BASE + 0x708)
+#define PCIE_IEP_NTB_IEP_BAR23_CTRL_REG (PCIE_IEP_BASE + 0x70C)
+#define PCIE_IEP_NTB_IEP_BAR45_CTRL_REG (PCIE_IEP_BASE + 0x710)
+#define PCIE_IEP_MSI_CTRL_ADDRESS_LOWER_REG (PCIE_IEP_BASE + 0x714)
+#define PCIE_IEP_MSI_CTRL_ADDRESS_UPPER_REG (PCIE_IEP_BASE + 0x718)
+#define PCIE_IEP_MSI_CTRL_INT_EN_REG (PCIE_IEP_BASE + 0x71C)
+#define PCIE_IEP_MSI_CTRL_INT0_MASK_REG (PCIE_IEP_BASE + 0x720)
+#define PCIE_IEP_MSI_CTRL_INT_STATUS_REG (PCIE_IEP_BASE + 0x724)
+
+
+
+typedef union tagIepDeviceVendorId
+{
+
+ struct
+ {
+ UINT32 Vendor_ID : 16 ;
+ UINT32 Device_ID : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_DEVICE_VENDOR_ID_U;
+
+
+
+
+typedef union tagIepPcistsPcicmd
+{
+
+ struct
+ {
+ UINT32 IO_Space_Enable : 1 ;
+ UINT32 Memory_Space_Enable : 1 ;
+ UINT32 Bus_Master_Enable : 1 ;
+ UINT32 SpecialCycleEnable : 1 ;
+ UINT32 Memory_Write_and_Invalidate : 1 ;
+ UINT32 VGA_palette_snoop_Enable : 1 ;
+ UINT32 Parity_Error_Response : 1 ;
+ UINT32 IDSEL_Stepping_WaitCycle_Control : 1 ;
+ UINT32 SERR_Enable : 1 ;
+ UINT32 FastBack_to_BackEnable : 1 ;
+ UINT32 Interrupt_Disable : 1 ;
+ UINT32 Reserved_2 : 5 ;
+ UINT32 Reserved_1 : 3 ;
+ UINT32 INTx_Status : 1 ;
+ UINT32 CapabilitiesList : 1 ;
+ UINT32 pcibus66MHzcapable : 1 ;
+ UINT32 Reserved_0 : 1 ;
+ UINT32 FastBack_to_Back : 1 ;
+ UINT32 MasterDataParityError : 1 ;
+ UINT32 DEVSEL_Timing : 2 ;
+ UINT32 Signaled_Target_Abort : 1 ;
+ UINT32 Received_Target_Abort : 1 ;
+ UINT32 Received_Master_Abort : 1 ;
+ UINT32 Signaled_System_Error : 1 ;
+ UINT32 Detected_Parity_Error : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_PCISTS_PCICMD_U;
+
+
+
+
+typedef union tagIepCcrRid
+{
+
+ struct
+ {
+ UINT32 Revision_Identification : 8 ;
+ UINT32 Reserved_3 : 8 ;
+ UINT32 Sub_Class : 8 ;
+ UINT32 BaseClass : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_CCR_RID_U;
+
+
+
+
+typedef union tagIepPbar01BaseLower
+{
+
+ struct
+ {
+ UINT32 BAR01_Space_Inicator : 1 ;
+ UINT32 BAR01_Type : 2 ;
+ UINT32 BAR01_Prefetchable : 1 ;
+ UINT32 Reserved_4 : 12 ;
+ UINT32 pbar01_lower : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_PBAR01_BASE_LOWER_U;
+
+
+
+
+typedef union tagIepPbar23BaseLower
+{
+
+ struct
+ {
+ UINT32 pbar23_space_inicator : 1 ;
+ UINT32 pbar23_type : 2 ;
+ UINT32 pbar23_prefetchable : 1 ;
+ UINT32 Reserved_6 : 8 ;
+ UINT32 pbar23_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_PBAR23_BASE_LOWER_U;
+
+
+
+
+typedef union tagIepPbar45BaseLower
+{
+
+ struct
+ {
+ UINT32 pbar45_space_inicator : 1 ;
+ UINT32 pbar45_type : 2 ;
+ UINT32 pbar45_prefetchable : 1 ;
+ UINT32 Reserved_7 : 8 ;
+ UINT32 pbar45_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_PBAR45_BASE_LOWER_U;
+
+
+
+
+typedef union tagIepSubsystemid
+{
+
+ struct
+ {
+ UINT32 SubsystemID : 16 ;
+ UINT32 SubsystemVendorID : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_SubSystemId_U;
+
+
+
+
+typedef union tagIepCapptr
+{
+
+ struct
+ {
+ UINT32 CapPtr : 8 ;
+ UINT32 Reserved_10 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_CapPtr_U;
+
+
+
+
+typedef union tagIepInterrupt
+{
+
+ struct
+ {
+ UINT32 Interrupt_Line : 8 ;
+ UINT32 Interrupt_Pin : 8 ;
+ UINT32 Min_Grant : 8 ;
+ UINT32 Max_Latency : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_Interrupt_U;
+
+
+
+
+typedef union tagIepMsiCapabilityRegister
+{
+
+ struct
+ {
+ UINT32 CapabilityID : 8 ;
+ UINT32 Next_Capability_Pointer : 8 ;
+ UINT32 MSI_Enabled : 1 ;
+ UINT32 Multiple_Message_Capable : 3 ;
+ UINT32 Multiple_Message_Enabled : 3 ;
+ UINT32 MSI_64_EN : 1 ;
+ UINT32 PVM_EN : 1 ;
+ UINT32 Message_Control_Register : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_MSI_Capability_Register_U;
+
+
+
+
+typedef union tagIepMsiLower32Bitaddress
+{
+
+ struct
+ {
+ UINT32 Reserved_13 : 2 ;
+ UINT32 Lower32_bitAddress : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_MSI_Lower32_bitAddress_U;
+
+
+
+
+typedef union tagIepMsiData
+{
+
+ struct
+ {
+ UINT32 MSI_Data : 16 ;
+ UINT32 Reserved_14 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_MSI_Data_U;
+
+
+
+
+typedef union tagIepMsiMask
+{
+
+ struct
+ {
+ UINT32 MsiMask : 1 ;
+ UINT32 Reserved_15 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_MSI_MASK_U;
+
+
+
+
+typedef union tagIepMsiPending
+{
+
+ struct
+ {
+ UINT32 MsiPending : 1 ;
+ UINT32 Reserved_16 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_MSI_Pending_U;
+
+
+
+
+typedef union tagIepPcieCapabilityRegister
+{
+
+ struct
+ {
+ UINT32 Capability_ID : 8 ;
+ UINT32 Next_Capability_Pointer : 8 ;
+ UINT32 PCIE_Capability_Version : 4 ;
+ UINT32 Device_Port_Type : 4 ;
+ UINT32 Slot_Implemented : 1 ;
+ UINT32 Interrupt_Message_Number : 5 ;
+ UINT32 Reserved_17 : 2 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_PCIE_Capability_Register_U;
+
+
+
+
+typedef union tagIepDeviceCapabilitiesRegister
+{
+
+ struct
+ {
+ UINT32 Max_Payload_Size_Supported : 3 ;
+ UINT32 Phantom_Function_Supported : 2 ;
+ UINT32 Extended_TagField_Supported : 1 ;
+ UINT32 Endpoint_L0sAcceptable_Latency : 3 ;
+ UINT32 Endpoint_L1Acceptable_Latency : 3 ;
+ UINT32 Undefined : 3 ;
+ UINT32 Reserved_20 : 3 ;
+ UINT32 Captured_Slot_Power_Limit_Value : 8 ;
+ UINT32 Captured_Slot_Power_Limit_Scale : 2 ;
+ UINT32 Function_Level_Reset : 1 ;
+ UINT32 Reserved_19 : 3 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_Device_Capabilities_Register_U;
+
+
+
+
+typedef union tagIepDeviceStatusRegister
+{
+
+ struct
+ {
+ UINT32 Correctable_Error_Reporting_Enable : 1 ;
+ UINT32 Non_Fatal_Error_Reporting_Enable : 1 ;
+ UINT32 Fatal_Error_Reporting_Enable : 1 ;
+ UINT32 UREnable : 1 ;
+ UINT32 Enable_Relaxed_Ordering : 1 ;
+ UINT32 Max_Payload_Size : 3 ;
+ UINT32 Extended_TagFieldEnable : 1 ;
+ UINT32 Phantom_Function_Enable : 1 ;
+ UINT32 AUXPowerPMEnable : 1 ;
+ UINT32 EnableNoSnoop : 1 ;
+ UINT32 Max_Read_Request_Size : 3 ;
+ UINT32 Reserved_22 : 1 ;
+ UINT32 CorrectableErrorDetected : 1 ;
+ UINT32 Non_FatalErrordetected : 1 ;
+ UINT32 FatalErrorDetected : 1 ;
+ UINT32 UnsupportedRequestDetected : 1 ;
+ UINT32 AuxPowerDetected : 1 ;
+ UINT32 TransactionPending : 1 ;
+ UINT32 Reserved_21 : 10 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_Device_Status_Register_U;
+
+
+
+
+typedef union tagIepLinkCapability
+{
+
+ struct
+ {
+ UINT32 Max_Link_Speed : 4 ;
+ UINT32 Max_Link_Width : 6 ;
+ UINT32 Active_State_Power_Management : 2 ;
+ UINT32 L0s_ExitLatency : 3 ;
+ UINT32 L1_Exit_Latency : 3 ;
+ UINT32 Clock_Power_Management : 1 ;
+ UINT32 Surprise_Down_Error_Report_Cap : 1 ;
+ UINT32 Data_Link_Layer_Active_Report_Cap : 1 ;
+ UINT32 Link_Bandwidth_Noti_Cap : 1 ;
+ UINT32 ASPM_Option_Compliance : 1 ;
+ UINT32 Reserved_23 : 1 ;
+ UINT32 Port_Number : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_Link_Capability_U;
+
+
+
+
+typedef union tagIepLinkControlStatus
+{
+
+ struct
+ {
+ UINT32 Active_State_Power_Management : 2 ;
+ UINT32 Reserved_26 : 1 ;
+ UINT32 RCB : 1 ;
+ UINT32 Link_Disable : 1 ;
+ UINT32 Retrain_Link : 1 ;
+ UINT32 Common_Clock_Config : 1 ;
+ UINT32 Extended_Sync : 1 ;
+ UINT32 Enable_Clock_Pwr_Management : 1 ;
+ UINT32 Hw_Auto_Width_Disable : 1 ;
+ UINT32 Link_Bandwidth_Management_Int_En : 1 ;
+ UINT32 Link_Auto_Bandwidth_Int_En : 1 ;
+ UINT32 Reserved_25 : 4 ;
+ UINT32 current_link_speed : 4 ;
+ UINT32 negotiated_link_width : 6 ;
+ UINT32 Reserved_24 : 1 ;
+ UINT32 link_training : 1 ;
+ UINT32 slot_clock_config : 1 ;
+ UINT32 data_link_layer_active : 1 ;
+ UINT32 link_bandwidth_management_status : 1 ;
+ UINT32 link_auto_bandwidth_status : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_Link_Control_Status_U;
+
+
+
+
+typedef union tagIepAerCapHeader
+{
+
+ struct
+ {
+ UINT32 PCIE_Extended_Capability_ID : 16 ;
+ UINT32 Capability_Version : 4 ;
+ UINT32 Next_Capability_Offset : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_AER_Cap_header_U;
+
+
+
+
+typedef union tagIepUcErrorStatus
+{
+
+ struct
+ {
+ UINT32 Reserved_31 : 1 ;
+ UINT32 Reserved_30 : 3 ;
+ UINT32 DataLinkProtocolErrorStatus : 1 ;
+ UINT32 SurpriseDownErrorStatus : 1 ;
+ UINT32 Reserved_29 : 6 ;
+ UINT32 PoisonedTLPStatus : 1 ;
+ UINT32 FlowControlProtocolErrorStatus : 1 ;
+ UINT32 CompletionTimeoutStatus : 1 ;
+ UINT32 CompleterAbortStatus : 1 ;
+ UINT32 UnexpectedCompletionStatus : 1 ;
+ UINT32 ReceiverOverflowStatus : 1 ;
+ UINT32 MalformedTLPStatus : 1 ;
+ UINT32 ECRCErrorStatus : 1 ;
+ UINT32 UnsupportedRequestErrorStatus : 1 ;
+ UINT32 Reserved_28 : 11 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_UC_Error_Status_U;
+
+
+
+
+typedef union tagIepUcErrorMask
+{
+
+ struct
+ {
+ UINT32 Reserved_35 : 1 ;
+ UINT32 Reserved_34 : 3 ;
+ UINT32 DataLinkProtocolErrorMask : 1 ;
+ UINT32 SurpriseDownErrorMask : 1 ;
+ UINT32 Reserved_33 : 6 ;
+ UINT32 PoisonedTLPMask : 1 ;
+ UINT32 FlowControlProtocolErrorMask : 1 ;
+ UINT32 CompletionTimeoutMask : 1 ;
+ UINT32 CompleterAbortMask : 1 ;
+ UINT32 UnexpectedCompletionMask : 1 ;
+ UINT32 ReceiverOverflowMask : 1 ;
+ UINT32 MalformedTLPMask : 1 ;
+ UINT32 ECRCErrorMask : 1 ;
+ UINT32 UnsupportedRequestErrorMask : 1 ;
+ UINT32 Reserved_32 : 11 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_UC_Error_Mask_U;
+
+
+
+
+typedef union tagIepUcErrorSeverity
+{
+
+ struct
+ {
+ UINT32 Reserved_39 : 1 ;
+ UINT32 Reserved_38 : 3 ;
+ UINT32 DataLinkProtocolErrorSeverity : 1 ;
+ UINT32 SurpriseDownErrorSeverity : 1 ;
+ UINT32 Reserved_37 : 6 ;
+ UINT32 PoisonedTLPSeverity : 1 ;
+ UINT32 FlowControlProtocolErrorSeverity : 1 ;
+ UINT32 CompletionTimeoutSeverity : 1 ;
+ UINT32 CompleterAbortSeverity : 1 ;
+ UINT32 UnexpectedCompletionSeverity : 1 ;
+ UINT32 ReceiverOverflowSeverity : 1 ;
+ UINT32 MalformedTLPSeverity : 1 ;
+ UINT32 ECRCErrorSeverity : 1 ;
+ UINT32 UnsupportedRequestErrorSeverity : 1 ;
+ UINT32 Reserved_36 : 11 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_UC_Error_Severity_U;
+
+
+
+
+typedef union tagIepCErrorStatus
+{
+
+ struct
+ {
+ UINT32 Receiver_Error_Status : 1 ;
+ UINT32 Reserved_42 : 5 ;
+ UINT32 Bad_TLP_Status : 1 ;
+ UINT32 Bad_DLLP_Status : 1 ;
+ UINT32 REPLAY_NUM_Rollover_Status : 1 ;
+ UINT32 Reserved_41 : 3 ;
+ UINT32 Replay_Timer_Timeout_Status : 1 ;
+ UINT32 Advisory_Non_Fatal_Error_Status : 1 ;
+ UINT32 Reserved_40 : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_C_Error_Status_U;
+
+
+
+
+typedef union tagIepCErrorMask
+{
+
+ struct
+ {
+ UINT32 Receiver_Error_Mask : 1 ;
+ UINT32 Reserved_45 : 5 ;
+ UINT32 Bad_TLP_Mask : 1 ;
+ UINT32 Bad_DLLP_Mask : 1 ;
+ UINT32 REPLAY_NUMRollover_Mask : 1 ;
+ UINT32 Reserved_44 : 3 ;
+ UINT32 Replay_Timer_Timeout_Mask : 1 ;
+ UINT32 Advisory_Non_Fatal_Error_Mask : 1 ;
+ UINT32 Reserved_43 : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_C_Error_Mask_U;
+
+
+
+
+typedef union tagIepAdvancedErrorCapabilitiesAndControl
+{
+
+ struct
+ {
+ UINT32 First_Error_Pointer : 5 ;
+ UINT32 ECRC_Generation_Capability : 1 ;
+ UINT32 ECRC_Generation_Enable : 1 ;
+ UINT32 ECRC_Check_Capable : 1 ;
+ UINT32 ECRC_Check_Enable : 1 ;
+ UINT32 Reserved_47 : 2 ;
+ UINT32 TLP_Prefix_Log_Present : 1 ;
+ UINT32 Reserved_46 : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_Advanced_Error_Capabilities_and_Control_U;
+
+
+
+
+typedef union tagIepNtbIepBar01Ctrl
+{
+
+ struct
+ {
+ UINT32 bar01_type : 5 ;
+ UINT32 bar01_tc : 3 ;
+ UINT32 bar01_td : 1 ;
+ UINT32 bar01_attr : 2 ;
+ UINT32 Reserved_51 : 5 ;
+ UINT32 bar01_at : 2 ;
+ UINT32 bar01_match_en : 1 ;
+ UINT32 Reserved_50 : 13 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_NTB_IEP_BAR01_CTRL_U;
+
+
+
+
+typedef union tagIepNtbIepBar23Ctrl
+{
+
+ struct
+ {
+ UINT32 bar23_type : 5 ;
+ UINT32 bar23_tc : 3 ;
+ UINT32 bar23_td : 1 ;
+ UINT32 bar23_attr : 2 ;
+ UINT32 Reserved_53 : 5 ;
+ UINT32 bar23_at : 2 ;
+ UINT32 bar23_match_en : 1 ;
+ UINT32 Reserved_52 : 13 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_NTB_IEP_BAR23_CTRL_U;
+
+
+
+
+typedef union tagIepNtbIepBar45Ctrl
+{
+
+ struct
+ {
+ UINT32 bar45_type : 5 ;
+ UINT32 bar45_tc : 3 ;
+ UINT32 bar45_td : 1 ;
+ UINT32 bar45_attr : 2 ;
+ UINT32 Reserved_55 : 5 ;
+ UINT32 bar45_at : 2 ;
+ UINT32 bar45_match_en : 1 ;
+ UINT32 Reserved_54 : 13 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_NTB_IEP_BAR45_CTRL_U;
+
+
+
+
+typedef union tagIepMsiCtrlIntEn
+{
+
+ struct
+ {
+ UINT32 msi_int_en : 1 ;
+ UINT32 Reserved_56 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_MSI_CTRL_INT_EN_U;
+
+
+
+
+typedef union tagIepMsiCtrlInt0Mask
+{
+
+ struct
+ {
+ UINT32 msi_int_mask : 1 ;
+ UINT32 Reserved_57 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_MSI_CTRL_INT0_MASK_U;
+
+
+
+
+typedef union tagIepMsiCtrlIntStatus
+{
+
+ struct
+ {
+ UINT32 msi_int : 1 ;
+ UINT32 Reserved_58 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_MSI_CTRL_INT_STATUS_U;
+
+
+#define PCI_SYS_BASE (0x00000000)
+
+
+
+
+#define PCIE_CTRL_0_REG (PCI_SYS_BASE + 0xF8)
+#define PCIE_CTRL_1_REG (PCI_SYS_BASE + 0xFC)
+#define PCIE_CTRL_2_REG (PCI_SYS_BASE + 0x100)
+#define PCIE_CTRL_3_REG (PCI_SYS_BASE + 0x104)
+#define PCIE_CTRL_4_REG (PCI_SYS_BASE + 0x108)
+#define PCIE_CTRL_5_REG (PCI_SYS_BASE + 0x10C)
+#define PCIE_CTRL_6_REG (PCI_SYS_BASE + 0x110)
+#define PCIE_CTRL_7_REG (PCI_SYS_BASE + 0x114)
+#define PCIE_CTRL_9_REG (PCI_SYS_BASE + 0x11C)
+#define PCIE_CTRL_10_REG (PCI_SYS_BASE + 0x120)
+#define PCIE_CTRL_11_REG (PCI_SYS_BASE + 0x124)
+#define PCIE_SYS_CTRL12_REG (PCI_SYS_BASE + 0x0)
+#define PCIE_SYS_CTRL13_REG (PCI_SYS_BASE + 0x4)
+#define PCIE_SYS_CTRL14_REG (PCI_SYS_BASE + 0x8)
+#define PCIE_SYS_CTRL15_REG (PCI_SYS_BASE + 0xC)
+#define PCIE_SYS_CTRL16_REG (PCI_SYS_BASE + 0x10)
+#define PCIE_SYS_CTRL17_REG (PCI_SYS_BASE + 0x14)
+#define PCIE_SYS_CTRL18_REG (PCI_SYS_BASE + 0x18)
+#define PCIE_SYS_CTRL19_REG (PCI_SYS_BASE + 0x1C)
+#define PCIE_SYS_CTRL20_REG (PCI_SYS_BASE + 0x20)
+#define PCIE_RD_TAB_SEL BIT31
+#define PCIE_RD_TAB_EN BIT30
+#define PCIE_SYS_CTRL21_REG (PCI_SYS_BASE + 0x24)
+#define PCIE_SYS_CTRL22_REG (PCI_SYS_BASE + 0x28)
+#define PCIE_SYS_CTRL23_REG (PCI_SYS_BASE + 0x2C)
+#define PCIE_SYS_CTRL24_REG (PCI_SYS_BASE + 0x1b4)
+#define PCIE_SYS_CTRL28_REG (PCI_SYS_BASE + 0x1c4)
+#define PCIE_SYS_CTRL29_REG (PCI_SYS_BASE + 0x1c8)
+#define PCIE_SYS_CTRL54_REG (PCI_SYS_BASE + 0x274)
+#define PCIE_SYS_STATE4_REG (PCI_SYS_BASE + 0x31C)
+#define PCIE_SYS_STATE5_REG (PCI_SYS_BASE + 0x30)
+#define PCIE_SYS_STATE6_REG (PCI_SYS_BASE + 0x34)
+#define PCIE_SYS_STATE7_REG (PCI_SYS_BASE + 0x38)
+#define PCIE_SYS_STATE8_REG (PCI_SYS_BASE + 0x3C)
+#define PCIE_SYS_STATE9_REG (PCI_SYS_BASE + 0x40)
+#define PCIE_SYS_STATE10_REG (PCI_SYS_BASE + 0x44)
+#define PCIE_SYS_STATE11_REG (PCI_SYS_BASE + 0x48)
+#define PCIE_SYS_STATE12_REG (PCI_SYS_BASE + 0x4C)
+#define PCIE_SYS_STATE13_REG (PCI_SYS_BASE + 0x50)
+#define PCIE_SYS_STATE14_REG (PCI_SYS_BASE + 0x54)
+#define PCIE_SYS_STATE15_REG (PCI_SYS_BASE + 0x58)
+#define PCIE_SYS_STATE16_REG (PCI_SYS_BASE + 0x5C)
+#define PCIE_SYS_STATE17_REG (PCI_SYS_BASE + 0x60)
+#define PCIE_SYS_STATE18_REG (PCI_SYS_BASE + 0x64)
+#define PCIE_SYS_STATE19_REG (PCI_SYS_BASE + 0x68)
+#define PCIE_SYS_STATE20_REG (PCI_SYS_BASE + 0x6C)
+#define PCIE_SYS_STATE21_REG (PCI_SYS_BASE + 0x70)
+#define PCIE_SYS_STATE22_REG (PCI_SYS_BASE + 0x74)
+#define PCIE_SYS_STATE23_REG (PCI_SYS_BASE + 0x78)
+#define PCIE_SYS_STATE24_REG (PCI_SYS_BASE + 0x7C)
+#define PCIE_SYS_STATE25_REG (PCI_SYS_BASE + 0x80)
+#define PCIE_SYS_STATE26_REG (PCI_SYS_BASE + 0x84)
+#define PCIE_SYS_STATE27_REG (PCI_SYS_BASE + 0x88)
+#define PCIE_SYS_STATE28_REG (PCI_SYS_BASE + 0x8C)
+#define PCIE_SYS_STATE29_REG (PCI_SYS_BASE + 0x90)
+#define PCIE_SYS_STATE30_REG (PCI_SYS_BASE + 0x94)
+#define PCIE_SYS_STATE31_REG (PCI_SYS_BASE + 0x98)
+#define PCIE_SYS_STATE32_REG (PCI_SYS_BASE + 0x9C)
+#define PCIE_SYS_STATE33_REG (PCI_SYS_BASE + 0xA0)
+#define PCIE_SYS_STATE34_REG (PCI_SYS_BASE + 0xA4)
+#define PCIE_SYS_STATE35_REG (PCI_SYS_BASE + 0xA8)
+#define PCIE_SYS_STATE36_REG (PCI_SYS_BASE + 0xAC)
+#define PCIE_SYS_STATE37_REG (PCI_SYS_BASE + 0xB0)
+#define PCIE_SYS_STATE38_REG (PCI_SYS_BASE + 0xB4)
+#define PCIE_SYS_STATE39_REG (PCI_SYS_BASE + 0xB8)
+#define PCIE_SYS_STATE40_REG (PCI_SYS_BASE + 0xBC)
+#define PCIE_SYS_STATE41_REG (PCI_SYS_BASE + 0xC0)
+#define PCIE_SYS_STATE42_REG (PCI_SYS_BASE + 0xC4)
+#define PCIE_SYS_STATE43_REG (PCI_SYS_BASE + 0xC8)
+#define PCIE_SYS_STATE44_REG (PCI_SYS_BASE + 0xCC)
+#define PCIE_SYS_STATE45_REG (PCI_SYS_BASE + 0xD0)
+#define PCIE_SYS_STATE46_REG (PCI_SYS_BASE + 0xD4)
+#define PCIE_SYS_STATE47_REG (PCI_SYS_BASE + 0xD8)
+#define PCIE_SYS_STATE48_REG (PCI_SYS_BASE + 0xDC)
+#define PCIE_SYS_STATE49_REG (PCI_SYS_BASE + 0xE0)
+#define PCIE_SYS_STATE50_REG (PCI_SYS_BASE + 0xE4)
+#define PCIE_SYS_STATE51_REG (PCI_SYS_BASE + 0xE8)
+#define PCIE_SYS_STATE52_REG (PCI_SYS_BASE + 0xEC)
+#define PCIE_SYS_STATE53_REG (PCI_SYS_BASE + 0xF0)
+#define PCIE_SYS_STATE54_REG (PCI_SYS_BASE + 0xF4)
+#define PCIE_STAT_0_REG (PCI_SYS_BASE + 0x0)
+#define PCIE_STAT_1_REG (PCI_SYS_BASE + 0x0)
+#define PCIE_STAT_2_REG (PCI_SYS_BASE + 0x0)
+#define PCIE_STAT_3_REG (PCI_SYS_BASE + 0x0)
+#define PCIE_STAT_4_REG (PCI_SYS_BASE + 0x0)
+
+
+
+typedef union tagPcieCtrl0
+{
+
+ struct
+ {
+ UINT32 pcie2_slv_awmisc_info : 22 ;
+ UINT32 pcie2_slv_resp_err_map : 6 ;
+ UINT32 pcie2_slv_device_type : 4 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_CTRL_0_U;
+
+
+
+
+typedef union tagPcieCtrl1
+{
+
+ struct
+ {
+ UINT32 pcie2_slv_armisc_info : 22 ;
+ UINT32 pcie2_common_clocks : 1 ;
+ UINT32 pcie2_app_clk_req_n : 1 ;
+ UINT32 pcie2_ven_msg_code : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_CTRL_1_U;
+
+
+
+
+typedef union tagPcieCtrl2
+{
+
+ struct
+ {
+ UINT32 pcie2_mstr_bmisc_info : 14 ;
+ UINT32 pcie2_mstr_rmisc_info : 12 ;
+ UINT32 pcie2_ven_msi_req : 1 ;
+ UINT32 pcie2_ven_msi_vector : 5 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_CTRL_2_U;
+
+
+
+
+typedef union tagPcieCtrl3
+{
+
+ struct
+ {
+ UINT32 pcie2_ven_msg_req : 1 ;
+ UINT32 pcie2_ven_msg_fmt : 2 ;
+ UINT32 pcie2_ven_msg_type : 5 ;
+ UINT32 pcie2_ven_msg_td : 1 ;
+ UINT32 pcie2_ven_msg_ep : 1 ;
+ UINT32 pcie2_ven_msg_attr : 2 ;
+ UINT32 pcie2_ven_msg_len : 10 ;
+ UINT32 pcie2_ven_msg_tag : 8 ;
+ UINT32 pcie_mstr_rresp_int_enable : 1 ;
+ UINT32 pcie_mstr_bresp_int_enable : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_CTRL_3_U;
+
+
+
+
+typedef union tagPcieCtrl7
+{
+
+ struct
+ {
+ UINT32 pcie2_app_init_rst : 1 ;
+ UINT32 pcie2_app_req_entr_l1 : 1 ;
+ UINT32 pcie2_app_ready_entr_l23 : 1 ;
+ UINT32 pcie2_app_req_exit_l1 : 1 ;
+ UINT32 pcie2_app_req_retry_en : 1 ;
+ UINT32 pcie2_sys_int : 1 ;
+ UINT32 pcie2_outband_pwrup_cmd : 1 ;
+ UINT32 pcie2_app_unlock_msg : 1 ;
+ UINT32 pcie2_apps_pm_xmt_turnoff : 1 ;
+ UINT32 pcie2_apps_pm_xmt_pme : 1 ;
+ UINT32 pcie2_sys_aux_pwr_det : 1 ;
+ UINT32 pcie2_app_ltssm_enable : 1 ;
+ UINT32 pcie2_cfg_pwr_ctrler_ctrl_pol : 1 ;
+ UINT32 Reserved_7 : 1 ;
+ UINT32 pcie2_sys_mrl_sensor_state : 1 ;
+ UINT32 pcie2_sys_pwr_fault_det : 1 ;
+ UINT32 pcie2_sys_mrl_sensor_chged : 1 ;
+ UINT32 Reserved_6 : 1 ;
+ UINT32 pcie2_sys_cmd_cpled_int : 1 ;
+ UINT32 pcie2_sys_eml_interlock_engaged : 1 ;
+ UINT32 pcie2_cfg_l1_clk_removal_en : 1 ;
+ UINT32 pcie0_int_ctrl : 8 ;
+ UINT32 pcie_linkdown_auto_rstn_enable : 1 ;
+ UINT32 pcie_err_bresp_enable : 1 ;
+ UINT32 pcie_err_rresp_enable : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_CTRL_7_U;
+
+
+
+
+typedef union tagPcieCtrl9
+{
+
+ struct
+ {
+ UINT32 cfg_l1_aux_clk_switch_core_clk_gate_en : 1 ;
+ UINT32 cfg_l1_mac_powerdown_override_to_p2_en : 1 ;
+ UINT32 Reserved_9 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_CTRL_9_U;
+
+
+
+
+typedef union tagPcieCtrl10
+{
+
+ struct
+ {
+ UINT32 cfg_aer_rc_err_msi_mask : 1 ;
+ UINT32 cfg_sys_err_rc_mask : 1 ;
+ UINT32 radm_correctable_err_mask : 1 ;
+ UINT32 radm_nonfatal_err_mask : 1 ;
+ UINT32 radm_fatal_err_mask : 1 ;
+ UINT32 radm_pm_pme_mask : 1 ;
+ UINT32 radm_pm_to_ack_mask : 1 ;
+ UINT32 ven_msi_int_mask : 1 ;
+ UINT32 radm_cpl_timeout_mask : 1 ;
+ UINT32 radm_msg_unlock_mask : 1 ;
+ UINT32 cfg_pme_msi_mask : 1 ;
+ UINT32 bridge_flush_not_mask : 1 ;
+ UINT32 link_req_rst_not_mask : 1 ;
+ UINT32 pcie_p2_exit_int_mask : 1 ;
+ UINT32 pcie_rx_lane_flip_en_tmp : 1 ;
+ UINT32 pcie_tx_lane_flip_en_tmp : 1 ;
+ UINT32 radm_pm_turnoff_mask : 1 ;
+ UINT32 Reserved_11 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_CTRL_10_U;
+
+
+
+
+typedef union tagPcieCtrl11
+{
+
+ struct
+ {
+ UINT32 cfg_aer_rc_err_msi_clr : 1 ;
+ UINT32 cfg_sys_err_rc_clr : 1 ;
+ UINT32 radm_correctable_err_clr : 1 ;
+ UINT32 radm_nonfatal_err_clr : 1 ;
+ UINT32 radm_fatal_err_clr : 1 ;
+ UINT32 radm_pm_pme_clr : 1 ;
+ UINT32 radm_pm_to_ack_clr : 1 ;
+ UINT32 ven_msi_int_clr : 1 ;
+ UINT32 radm_cpl_timeout_clr : 1 ;
+ UINT32 radm_msg_unlock_clr : 1 ;
+ UINT32 cfg_pme_msi_clr : 1 ;
+ UINT32 bridge_flush_not_clr : 1 ;
+ UINT32 link_req_rst_not_clr : 1 ;
+ UINT32 pcie_p2_exit_int_clr : 1 ;
+ UINT32 pcie_slv_err_int_clr : 1 ;
+ UINT32 pcie_mstr_err_int_clr : 1 ;
+ UINT32 radm_pm_turnoff_clr : 1 ;
+ UINT32 cfg_ntb_mode : 1 ;
+ UINT32 Reserved_13 : 14 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_CTRL_11_U;
+
+
+
+
+typedef union tagPcieSysCtrl12
+{
+
+ struct
+ {
+ UINT32 slv_awmisc_info_func_num : 1 ;
+ UINT32 slv_awmisc_info_vfunc_active : 1 ;
+ UINT32 slv_awmisc_info_vfunc_num : 1 ;
+ UINT32 Reserved_17 : 1 ;
+ UINT32 slv_armisc_info_func_num : 1 ;
+ UINT32 slv_armisc_info_vfunc_active : 1 ;
+ UINT32 slv_armisc_info_vfunc_num : 1 ;
+ UINT32 Reserved_16 : 1 ;
+ UINT32 slv_awmisc_info_nw : 1 ;
+ UINT32 slv_awmisc_info_ats : 2 ;
+ UINT32 slv_armisc_info_nw : 1 ;
+ UINT32 slv_armisc_info_ats : 2 ;
+ UINT32 mstr_bmisc_info_ats : 2 ;
+ UINT32 mstr_rmisc_info_ats : 2 ;
+ UINT32 pcie_rfs_ctrl : 6 ;
+ UINT32 pcie_rft_ctrl : 7 ;
+ UINT32 Reserved_15 : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_CTRL12_U;
+
+
+
+
+typedef union tagPcieSysCtrl16
+{
+
+ struct
+ {
+ UINT32 app_flr_pf_done : 1 ;
+ UINT32 app_flr_vf_done : 2 ;
+ UINT32 Reserved_23 : 5 ;
+ UINT32 ven_msi_vfunc_active : 1 ;
+ UINT32 ven_msi_vfunc_num : 1 ;
+ UINT32 ven_msg_vfunc_active : 1 ;
+ UINT32 ven_msg_vfunc_num : 1 ;
+ UINT32 Reserved_22 : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_CTRL16_U;
+
+
+
+
+typedef union tagPcieSysCtrl20
+{
+
+ struct
+ {
+ UINT32 ro_sel : 1 ;
+ UINT32 dbi_func_num : 1 ;
+ UINT32 dbi_vfunc_num : 1 ;
+ UINT32 dbi_vfunc_active : 1 ;
+ UINT32 dbi_addr_h20 : 20 ;
+ UINT32 dbi_bar_num : 3 ;
+ UINT32 dbi_rom_access : 1 ;
+ UINT32 dbi_io_access : 1 ;
+ UINT32 memicg_bypass : 1 ;
+ UINT32 Reserved_28 : 2 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_CTRL20_U;
+
+
+
+
+typedef union tagPcieSysCtrl21
+{
+
+ struct
+ {
+ UINT32 pcie_sys_pre_det_state : 1 ;
+ UINT32 pcie_sys_atten_button_pressed : 1 ;
+ UINT32 Reserved_30 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_CTRL21_U;
+
+
+
+
+typedef union tagPcieSysCtrl23
+{
+
+ struct
+ {
+ UINT32 Reserved_35 : 2 ;
+ UINT32 Reserved_34 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_CTRL23_U;
+
+
+
+
+typedef union tagPcieSysState5
+{
+
+ struct
+ {
+ UINT32 mstr_awmisc_info_func_num : 1 ;
+ UINT32 mstr_awmisc_info_vfunc_active : 1 ;
+ UINT32 mstr_awmisc_info_vfunc_num : 1 ;
+ UINT32 Reserved_39 : 1 ;
+ UINT32 mstr_armisc_info_func_num : 1 ;
+ UINT32 mstr_armisc_info_vfunc_active : 1 ;
+ UINT32 mstr_armisc_info_vfunc_num : 1 ;
+ UINT32 Reserved_38 : 1 ;
+ UINT32 mstr_awmisc_info_nw : 1 ;
+ UINT32 mstr_awmisc_info_ats : 2 ;
+ UINT32 mstr_armisc_info_nw : 1 ;
+ UINT32 mstr_armisc_info_ats : 2 ;
+ UINT32 slv_bmisc_info_ats : 2 ;
+ UINT32 slv_rmisc_info_ats : 2 ;
+ UINT32 Reserved_37 : 14 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE5_U;
+
+
+
+
+typedef union tagPcieSysState6
+{
+
+ struct
+ {
+ UINT32 cfg_flr_pf_active : 1 ;
+ UINT32 cfg_flr_vf_active : 2 ;
+ UINT32 Reserved_41 : 29 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE6_U;
+
+
+
+
+typedef union tagPcieSysState7
+{
+
+ struct
+ {
+ UINT32 radm_timeout_vfunc_active : 1 ;
+ UINT32 radm_timeout_vfunc_num : 1 ;
+ UINT32 trgt_timeout_cpl_vfunc_active : 1 ;
+ UINT32 trgt_timeout_cpl_vfunc_num : 1 ;
+ UINT32 Reserved_43 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE7_U;
+
+
+
+
+typedef union tagPcieSysState11
+{
+
+ struct
+ {
+ UINT32 cfg_msi_64 : 1 ;
+ UINT32 cfg_vf_msi_en : 2 ;
+ UINT32 cfg_vf_msi_64 : 2 ;
+ UINT32 cfg_multi_msi_en : 3 ;
+ UINT32 cfg_vf_multi_msi_en : 6 ;
+ UINT32 Reserved_48 : 2 ;
+ UINT32 cfg_msi_data : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE11_U;
+
+
+
+
+typedef union tagPcieSysState12
+{
+
+ struct
+ {
+ UINT32 cfg_vf_en : 1 ;
+ UINT32 cfg_ari_fwd_en : 1 ;
+ UINT32 cfg_vf_bme : 2 ;
+ UINT32 Reserved_51 : 4 ;
+ UINT32 cfg_num_vf : 16 ;
+ UINT32 Reserved_50 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE12_U;
+
+
+
+
+typedef union tagPcieSysState20
+{
+
+ struct
+ {
+ UINT32 slv_bmisc_info : 11 ;
+ UINT32 slv_rmisc_info : 11 ;
+ UINT32 rtlh_rfc_upd : 1 ;
+ UINT32 Reserved_60 : 9 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE20_U;
+
+
+
+
+typedef union tagPcieSysState21
+{
+
+ struct
+ {
+ UINT32 cfg_msix_en : 1 ;
+ UINT32 cfg_msix_func_mask : 1 ;
+ UINT32 cfg_vf_msix_func_mask : 2 ;
+ UINT32 cfg_vf_msix_en : 2 ;
+ UINT32 Reserved_62 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE21_U;
+
+
+
+
+typedef union tagPcieSysState22
+{
+
+ struct
+ {
+ UINT32 lbc_ext_vfunc_active : 1 ;
+ UINT32 lbc_ext_vfunc_num : 1 ;
+ UINT32 lbc_dbi_ack : 1 ;
+ UINT32 pcie_mstr_awmisc_info : 24 ;
+ UINT32 Reserved_64 : 5 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE22_U;
+
+
+
+
+typedef union tagPcieSysState27
+{
+
+ struct
+ {
+ UINT32 trgt_cpl_timeout : 1 ;
+ UINT32 trgt_timeout_cpl_func_num : 1 ;
+ UINT32 trgt_timeout_cpl_tc : 3 ;
+ UINT32 trgt_timeout_cpl_attr : 2 ;
+ UINT32 trgt_timeout_cpl_len : 12 ;
+ UINT32 trgt_lookup_empty : 1 ;
+ UINT32 Reserved_70 : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE27_U;
+
+
+
+
+typedef union tagPcieSysState28
+{
+
+ struct
+ {
+ UINT32 trgt_timeout_lookup_id : 8 ;
+ UINT32 trgt_lookup_id : 8 ;
+ UINT32 radm_timeout_cpl_tag : 8 ;
+ UINT32 Reserved_72 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE28_U;
+
+
+
+
+typedef union tagPcieSysState29
+{
+
+ struct
+ {
+ UINT32 trgt_cpl_timeout : 1 ;
+ UINT32 radm_timeout_func_num : 1 ;
+ UINT32 radm_timeout_cpl_tc : 3 ;
+ UINT32 radm_timeout_cpl_attr : 2 ;
+ UINT32 radm_timeout_cpl_len : 12 ;
+ UINT32 radm_pm_turnoff : 1 ;
+ UINT32 Reserved_74 : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE29_U;
+
+
+
+
+typedef union tagPcieSysState30
+{
+
+ struct
+ {
+ UINT32 cfg_pbus_num : 8 ;
+ UINT32 cfg_pbus_dev_num : 5 ;
+ UINT32 cfg_link_auto_bw_int : 1 ;
+ UINT32 cfg_bw_mgt_int : 1 ;
+ UINT32 Reserved_76 : 17 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE30_U;
+
+
+
+
+typedef union tagPcieSysState32
+{
+
+ struct
+ {
+ UINT32 mstr_awmisc_info_dma : 6 ;
+ UINT32 mstr_armisc_info_dma : 6 ;
+ UINT32 cfg_hw_auto_sp_dis : 1 ;
+ UINT32 link_timeout_flush_not : 1 ;
+ UINT32 mac_phy_clk_req_n : 1 ;
+ UINT32 wake_ref_rst_n : 1 ;
+ UINT32 pcie_wake : 1 ;
+ UINT32 Reserved_79 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE32_U;
+
+
+
+
+typedef union tagPcieSysState39
+{
+
+ struct
+ {
+ UINT32 radm_msg_unlock_reqid : 16 ;
+ UINT32 radm_nonfatal_err_reqid : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE39_U;
+
+
+
+
+typedef union tagPcieSysState44
+{
+
+ struct
+ {
+ UINT32 radm_unlock_reqid : 16 ;
+ UINT32 radm_nonfatal_err_reqid : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE44_U;
+
+
+
+
+typedef union tagPcieSysState49
+{
+
+ struct
+ {
+ UINT32 radm_pm_pme_reqid : 16 ;
+ UINT32 radm_pm_ack_to_reqid : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE49_U;
+
+
+
+
+typedef union tagPcieStat0
+{
+
+ struct
+ {
+ UINT32 pcie2_gm_cmposer_lookup_err : 1 ;
+ UINT32 pcie2_radmx_cmposer_lookup_err : 1 ;
+ UINT32 pcie2_cfg_pwr_ind : 2 ;
+ UINT32 pcie2_cfg_atten_ind : 2 ;
+ UINT32 pcie2_cfg_pwr_ctrler_ctrl : 1 ;
+ UINT32 pcie2_pm_xtlh_block_tlp : 1 ;
+ UINT32 pcie2_cfg_mem_space_en : 1 ;
+ UINT32 pcie2_cfg_rcb : 1 ;
+ UINT32 pcie2_rdlh_link_up : 1 ;
+ UINT32 pcie2_pm_curnt_state : 3 ;
+ UINT32 pcie2_cfg_aer_rc_err_int : 1 ;
+ UINT32 Reserved_106 : 1 ;
+ UINT32 pcie2_cfg_aer_int_msg_num : 5 ;
+ UINT32 Reserved_105 : 1 ;
+ UINT32 pcie2_xmlh_link_up : 1 ;
+ UINT32 pcie2_wake : 1 ;
+ UINT32 pcie2_cfg_eml_control : 1 ;
+ UINT32 pcie2_hp_pme : 1 ;
+ UINT32 pcie2_hp_int : 1 ;
+ UINT32 pcie2_hp_msi : 1 ;
+ UINT32 pcie2_pm_status : 1 ;
+ UINT32 pcie2_ref_clk_req_n : 1 ;
+ UINT32 Reserved_104 : 2 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_STAT_0_U;
+
+
+
+
+typedef union tagPcieStat1
+{
+
+ struct
+ {
+ UINT32 axi_parity_errs_reg : 4 ;
+ UINT32 app_parity_errs_reg : 3 ;
+ UINT32 pm_linkst_in_l1 : 1 ;
+ UINT32 pm_linkst_in_l2 : 1 ;
+ UINT32 pm_linkst_l2_exit : 1 ;
+ UINT32 mac_phy_power_down : 2 ;
+ UINT32 radm_correctabl_err_reg : 1 ;
+ UINT32 radm_nonfatal_err_reg : 1 ;
+ UINT32 radm_fatal_err_reg : 1 ;
+ UINT32 radm_pm_to_pme_reg : 1 ;
+ UINT32 radm_pm_to_ack_reg : 1 ;
+ UINT32 radm_cpl_timeout_reg : 1 ;
+ UINT32 radm_msg_unlock_reg : 1 ;
+ UINT32 cfg_pme_msi_reg : 1 ;
+ UINT32 bridge_flush_not_reg : 1 ;
+ UINT32 link_req_rst_not_reg : 1 ;
+ UINT32 pcie2_cfg_aer_rc_err_msi : 1 ;
+ UINT32 pcie2_cfg_sys_err_rc : 1 ;
+ UINT32 Reserved_107 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_STAT_1_U;
+
+
+
+
+typedef union tagPcieStat3
+{
+
+ struct
+ {
+ UINT32 radm_msg_req_id : 16 ;
+ UINT32 Reserved_108 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_STAT_3_U;
+
+
+
+
+typedef union tagPcieStat4
+{
+
+ struct
+ {
+ UINT32 ltssm_state : 6 ;
+ UINT32 mac_phy_rate : 2 ;
+ UINT32 pcie_slv_err_int_state : 1 ;
+ UINT32 retry_sram_addr : 10 ;
+ UINT32 pcie_mstr_rresp_int_state : 1 ;
+ UINT32 pcie_mstr_bresp_int_state : 1 ;
+ UINT32 pcie_radm_inta_int_state : 1 ;
+ UINT32 pcie_radm_intb_int_state : 1 ;
+ UINT32 pcie_radm_intc_int_state : 1 ;
+ UINT32 pcie_radm_intd_int_state : 1 ;
+ UINT32 pme_int_state : 1 ;
+ UINT32 radm_vendr_msg_int_state : 1 ;
+ UINT32 Reserved_109 : 5 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_STAT_4_U;
+
+
+#define PCIE_MUL_BASE (0x1000)
+
+
+
+
+#define PCIE_MUL_MC_CTRL_REG (PCIE_MUL_BASE + 0x0)
+#define PCIE_MUL_CFG_WIN0_BAR_LOWER_REG (PCIE_MUL_BASE + 0x4)
+#define PCIE_MUL_CFG_WIN0_BAR_UPPER_REG (PCIE_MUL_BASE + 0x8)
+#define PCIE_MUL_CFG_WIN1_BAR_LOWER_REG (PCIE_MUL_BASE + 0xC)
+#define PCIE_MUL_CFG_WIN1_BAR_UPPER_REG (PCIE_MUL_BASE + 0x10)
+#define PCIE_MUL_CFG_WIN2_BAR_LOWER_REG (PCIE_MUL_BASE + 0x14)
+#define PCIE_MUL_CFG_WIN2_BAR_UPPER_REG (PCIE_MUL_BASE + 0x18)
+#define PCIE_MUL_CFG_WIN3_BAR_LOWER_REG (PCIE_MUL_BASE + 0x1C)
+#define PCIE_MUL_CFG_WIN3_BAR_UPPER_REG (PCIE_MUL_BASE + 0x20)
+#define PCIE_MUL_CFG_WIN4_BAR_LOWER_REG (PCIE_MUL_BASE + 0x24)
+#define PCIE_MUL_CFG_WIN4_BAR_UPPER_REG (PCIE_MUL_BASE + 0x28)
+#define PCIE_MUL_CFG_WIN5_BAR_LOWER_REG (PCIE_MUL_BASE + 0x2C)
+#define PCIE_MUL_CFG_WIN5_BAR_UPPER_REG (PCIE_MUL_BASE + 0x30)
+#define PCIE_MUL_CFG_WIN6_BAR_LOWER_REG (PCIE_MUL_BASE + 0x34)
+#define PCIE_MUL_CFG_WIN6_BAR_UPPER_REG (PCIE_MUL_BASE + 0x38)
+#define PCIE_MUL_CFG_WIN7_BAR_LOWER_REG (PCIE_MUL_BASE + 0x3C)
+#define PCIE_MUL_CFG_WIN7_BAR_UPPER_REG (PCIE_MUL_BASE + 0x40)
+#define PCIE_MUL_CFG_WIN8_BAR_LOWER_REG (PCIE_MUL_BASE + 0x44)
+#define PCIE_MUL_CFG_WIN8_BAR_UPPER_REG (PCIE_MUL_BASE + 0x48)
+#define PCIE_MUL_CFG_WIN9_BAR_LOWER_REG (PCIE_MUL_BASE + 0x4C)
+#define PCIE_MUL_CFG_WIN9_BAR_UPPER_REG (PCIE_MUL_BASE + 0x50)
+#define PCIE_MUL_CFG_WIN10_BAR_LOWER_REG (PCIE_MUL_BASE + 0x54)
+#define PCIE_MUL_CFG_WIN10_BAR_UPPER_REG (PCIE_MUL_BASE + 0x58)
+#define PCIE_MUL_CFG_WIN11_BAR_LOWER_REG (PCIE_MUL_BASE + 0x5C)
+#define PCIE_MUL_CFG_WIN11_BAR_UPPER_REG (PCIE_MUL_BASE + 0x60)
+#define PCIE_MUL_CFG_WIN12_BAR_LOWER_REG (PCIE_MUL_BASE + 0x64)
+#define PCIE_MUL_CFG_WIN12_BAR_UPPER_REG (PCIE_MUL_BASE + 0x68)
+#define PCIE_MUL_CFG_WIN13_BAR_LOWER_REG (PCIE_MUL_BASE + 0x6C)
+#define PCIE_MUL_CFG_WIN13_BAR_UPPER_REG (PCIE_MUL_BASE + 0x70)
+#define PCIE_MUL_CFG_WIN14_BAR_LOWER_REG (PCIE_MUL_BASE + 0x74)
+#define PCIE_MUL_CFG_WIN14_BAR_UPPER_REG (PCIE_MUL_BASE + 0x78)
+#define PCIE_MUL_CFG_WIN15_BAR_LOWER_REG (PCIE_MUL_BASE + 0x7C)
+#define PCIE_MUL_CFG_WIN15_BAR_UPPER_REG (PCIE_MUL_BASE + 0x80)
+#define PCIE_MUL_CFG_WIN0_SIZE_REG (PCIE_MUL_BASE + 0x84)
+#define PCIE_MUL_CFG_WIN1_SIZE_REG (PCIE_MUL_BASE + 0x88)
+#define PCIE_MUL_CFG_WIN2_SIZE_REG (PCIE_MUL_BASE + 0x8C)
+#define PCIE_MUL_CFG_WIN3_SIZE_REG (PCIE_MUL_BASE + 0x90)
+#define PCIE_MUL_CFG_WIN4_SIZE_REG (PCIE_MUL_BASE + 0x94)
+#define PCIE_MUL_CFG_WIN5_SIZE_REG (PCIE_MUL_BASE + 0x98)
+#define PCIE_MUL_CFG_WIN6_SIZE_REG (PCIE_MUL_BASE + 0x9C)
+#define PCIE_MUL_CFG_WIN7_SIZE_REG (PCIE_MUL_BASE + 0xA0)
+#define PCIE_MUL_CFG_WIN8_SIZE_REG (PCIE_MUL_BASE + 0xA4)
+#define PCIE_MUL_CFG_WIN9_SIZE_REG (PCIE_MUL_BASE + 0xA8)
+#define PCIE_MUL_CFG_WIN10_SIZE_REG (PCIE_MUL_BASE + 0xAC)
+#define PCIE_MUL_CFG_WIN11_SIZE_REG (PCIE_MUL_BASE + 0xB0)
+#define PCIE_MUL_CFG_WIN12_SIZE_REG (PCIE_MUL_BASE + 0xB4)
+#define PCIE_MUL_CFG_WIN13_SIZE_REG (PCIE_MUL_BASE + 0xB8)
+#define PCIE_MUL_CFG_WIN14_SIZE_REG (PCIE_MUL_BASE + 0xBC)
+#define PCIE_MUL_CFG_WIN15_SIZE_REG (PCIE_MUL_BASE + 0xC0)
+#define PCIE_MUL_CFG_WIN0_XLAT_BASE_LOWER_REG (PCIE_MUL_BASE + 0xC4)
+#define PCIE_MUL_CFG_WIN0_XLAT_BASE_UPPER_REG (PCIE_MUL_BASE + 0xC8)
+#define PCIE_MUL_CFG_WIN1_XLAT_BASE_LOWER_REG (PCIE_MUL_BASE + 0xCC)
+#define PCIE_MUL_CFG_WIN1_XLAT_BASE_UPPER_REG (PCIE_MUL_BASE + 0xD0)
+#define PCIE_MUL_CFG_WIN2_XLAT_BASE_LOWER_REG (PCIE_MUL_BASE + 0xD4)
+#define PCIE_MUL_CFG_WIN2_XLAT_BASE_UPPER_REG (PCIE_MUL_BASE + 0xD8)
+#define PCIE_MUL_CFG_WIN3_XLAT_BASE_LOWER_REG (PCIE_MUL_BASE + 0xDC)
+#define PCIE_MUL_CFG_WIN3_XLAT_BASE_UPPER_REG (PCIE_MUL_BASE + 0xE0)
+#define PCIE_MUL_CFG_WIN4_XLAT_BASE_LOWER_REG (PCIE_MUL_BASE + 0xE4)
+#define PCIE_MUL_CFG_WIN4_XLAT_BASE_UPPER_REG (PCIE_MUL_BASE + 0xE8)
+#define PCIE_MUL_CFG_WIN5_XLAT_BASE_LOWER_REG (PCIE_MUL_BASE + 0xEC)
+#define PCIE_MUL_CFG_WIN5_XLAT_BASE_UPPER_REG (PCIE_MUL_BASE + 0xF0)
+#define PCIE_MUL_CFG_WIN6_XLAT_BASE_LOWER_REG (PCIE_MUL_BASE + 0xF4)
+#define PCIE_MUL_CFG_WIN6_XLAT_BASE_UPPER_REG (PCIE_MUL_BASE + 0xF8)
+#define PCIE_MUL_CFG_WIN7_XLAT_LOWER_REG (PCIE_MUL_BASE + 0xFC)
+#define PCIE_MUL_CFG_WIN7_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x100)
+#define PCIE_MUL_CFG_WIN8_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x104)
+#define PCIE_MUL_CFG_WIN8_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x108)
+#define PCIE_MUL_CFG_WIN9_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x10C)
+#define PCIE_MUL_CFG_WIN9_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x110)
+#define PCIE_MUL_CFG_WIN10_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x114)
+#define PCIE_MUL_CFG_WIN10_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x118)
+#define PCIE_MUL_CFG_WIN11_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x11C)
+#define PCIE_MUL_CFG_WIN11_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x120)
+#define PCIE_MUL_CFG_WIN12_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x124)
+#define PCIE_MUL_CFG_WIN12_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x128)
+#define PCIE_MUL_CFG_WIN13_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x12C)
+#define PCIE_MUL_CFG_WIN13_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x130)
+#define PCIE_MUL_CFG_WIN14_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x134)
+#define PCIE_MUL_CFG_WIN14_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x138)
+#define PCIE_MUL_CFG_WIN15_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x13C)
+#define PCIE_MUL_CFG_WIN15_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x140)
+#define PCIE_MUL_CFG_WIN_XLAT_EN_REG (PCIE_MUL_BASE + 0x144)
+#define PCIE_MUL_CFG_MCAST_CMD_TIMEOUT_REG (PCIE_MUL_BASE + 0x148)
+#define PCIE_MUL_CFG_INT_STATUS_REG (PCIE_MUL_BASE + 0x14C)
+#define PCIE_MUL_CFG_INJECT_ECC_ERR_REG (PCIE_MUL_BASE + 0x150)
+
+
+
+
+typedef union tagMcCtrl
+{
+
+ struct
+ {
+ UINT32 cfg_mcast_en : 1 ;
+ UINT32 cfg_win0_mcast_en : 1 ;
+ UINT32 cfg_win1_mcast_en : 1 ;
+ UINT32 cfg_win2_mcast_en : 1 ;
+ UINT32 cfg_win3_mcast_en : 1 ;
+ UINT32 cfg_win4_mcast_en : 1 ;
+ UINT32 cfg_win5_mcast_en : 1 ;
+ UINT32 cfg_win6_mcast_en : 1 ;
+ UINT32 cfg_win7_mcast_en : 1 ;
+ UINT32 cfg_win8_mcast_en : 1 ;
+ UINT32 cfg_win9_mcast_en : 1 ;
+ UINT32 cfg_win10_mcast_en : 1 ;
+ UINT32 cfg_win11_mcast_en : 1 ;
+ UINT32 cfg_win12_mcast_en : 1 ;
+ UINT32 cfg_win13_mcast_en : 1 ;
+ UINT32 cfg_win14_mcast_en : 1 ;
+ UINT32 cfg_win15_mcast_en : 1 ;
+ UINT32 Reserved_0 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_mc_ctrl_u;
+
+
+
+
+typedef union tagCfgWin0Size
+{
+
+ struct
+ {
+ UINT32 cfg_win0_size : 6 ;
+ UINT32 Reserved_1 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win0_size_u;
+
+
+
+
+typedef union tagCfgWin1Size
+{
+
+ struct
+ {
+ UINT32 cfg_win1_size : 6 ;
+ UINT32 Reserved_2 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win1_size_u;
+
+
+
+
+typedef union tagCfgWin2Size
+{
+
+ struct
+ {
+ UINT32 cfg_win2_size : 6 ;
+ UINT32 Reserved_3 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win2_size_u;
+
+
+
+
+typedef union tagCfgWin3Size
+{
+
+ struct
+ {
+ UINT32 cfg_win3_size : 6 ;
+ UINT32 Reserved_4 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win3_size_u;
+
+
+
+
+typedef union tagCfgWin4Size
+{
+
+ struct
+ {
+ UINT32 cfg_win4_size : 6 ;
+ UINT32 Reserved_5 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win4_size_u;
+
+
+
+
+typedef union tagCfgWin5Size
+{
+
+ struct
+ {
+ UINT32 cfg_win5_size : 6 ;
+ UINT32 Reserved_6 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win5_size_u;
+
+
+
+
+typedef union tagCfgWin6Size
+{
+
+ struct
+ {
+ UINT32 cfg_win6_size : 6 ;
+ UINT32 Reserved_7 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win6_size_u;
+
+
+
+
+typedef union tagCfgWin7Size
+{
+
+ struct
+ {
+ UINT32 cfg_win7_size : 6 ;
+ UINT32 Reserved_8 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win7_size_u;
+
+
+
+
+typedef union tagCfgWin8Size
+{
+
+ struct
+ {
+ UINT32 cfg_win8_size : 6 ;
+ UINT32 Reserved_9 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win8_size_u;
+
+
+
+
+typedef union tagCfgWin9Size
+{
+
+ struct
+ {
+ UINT32 cfg_win9_size : 6 ;
+ UINT32 Reserved_10 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win9_size_u;
+
+
+
+
+typedef union tagCfgWin10Size
+{
+
+ struct
+ {
+ UINT32 cfg_win10_size : 6 ;
+ UINT32 Reserved_11 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win10_size_u;
+
+
+
+
+typedef union tagCfgWin11Size
+{
+
+ struct
+ {
+ UINT32 cfg_win11_size : 6 ;
+ UINT32 Reserved_12 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win11_size_u;
+
+
+
+
+typedef union tagCfgWin12Size
+{
+
+ struct
+ {
+ UINT32 cfg_win12_size : 6 ;
+ UINT32 Reserved_13 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win12_size_u;
+
+
+
+
+typedef union tagCfgWin13Size
+{
+
+ struct
+ {
+ UINT32 cfg_win13_size : 6 ;
+ UINT32 Reserved_14 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win13_size_u;
+
+
+
+
+typedef union tagCfgWin14Size
+{
+
+ struct
+ {
+ UINT32 cfg_win14_size : 6 ;
+ UINT32 Reserved_15 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win14_size_u;
+
+
+
+
+typedef union tagCfgWin15Size
+{
+
+ struct
+ {
+ UINT32 cfg_win15_size : 6 ;
+ UINT32 Reserved_16 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win15_size_u;
+
+
+
+
+typedef union tagCfgWinXlatEn
+{
+
+ struct
+ {
+ UINT32 cfg_win0_xlat_en : 1 ;
+ UINT32 cfg_win1_xlat_en : 1 ;
+ UINT32 cfg_win2_xlat_en : 1 ;
+ UINT32 cfg_win3_xlat_en : 1 ;
+ UINT32 cfg_win4_xlat_en : 1 ;
+ UINT32 cfg_win5_xlat_en : 1 ;
+ UINT32 cfg_win6_xlat_en : 1 ;
+ UINT32 cfg_win7_xlat_en : 1 ;
+ UINT32 cfg_win8_xlat_en : 1 ;
+ UINT32 cfg_win9_xlat_en : 1 ;
+ UINT32 cfg_win10_xlat_en : 1 ;
+ UINT32 cfg_win11_xlat_en : 1 ;
+ UINT32 cfg_win12_xlat_en : 1 ;
+ UINT32 cfg_win13_xlat_en : 1 ;
+ UINT32 cfg_win14_xlat_en : 1 ;
+ UINT32 cfg_win15_xlat_en : 1 ;
+ UINT32 Reserved_17 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win_xlat_en_u;
+
+
+
+
+typedef union tagCfgMcastCmdTimeout
+{
+
+ struct
+ {
+ UINT32 cfg_mcast_cmd_timeout : 10 ;
+ UINT32 Reserved_18 : 22 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_mcast_cmd_timeout_u;
+
+
+
+
+typedef union tagCfgIntStatus
+{
+
+ struct
+ {
+ UINT32 timeout_int : 1 ;
+ UINT32 ecc_err1_int : 1 ;
+ UINT32 ecc_err2_int : 1 ;
+ UINT32 Reserved_19 : 29 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_int_status_u;
+
+
+
+
+typedef union tagCfgInjectEccErr
+{
+
+ struct
+ {
+ UINT32 ecc_err_inject_en : 1 ;
+ UINT32 Reserved_20 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_inject_ecc_err_u;
+
+
+#define PCIE_EP_BASE (0x00000000)
+
+
+
+
+#define PCIE_EP_PCI_CFG_HDR0_REG (PCIE_EP_BASE + 0x0)
+#define PCIE_EP_PCI_CFG_HDR1_REG (PCIE_EP_BASE + 0x4)
+#define PCIE_EP_PCI_CFG_HDR2_REG (PCIE_EP_BASE + 0x8)
+#define PCIE_EP_PCI_CFG_HDR3_REG (PCIE_EP_BASE + 0xC)
+#define PCIE_EP_PCI_CFG_HDR4_REG (PCIE_EP_BASE + 0x10)
+#define PCIE_EP_PCI_CFG_HDR5_REG (PCIE_EP_BASE + 0x14)
+#define PCIE_EP_PCI_CFG_HDR6_REG (PCIE_EP_BASE + 0x18)
+#define PCIE_EP_PCI_CFG_HDR7_REG (PCIE_EP_BASE + 0x1C)
+#define PCIE_EP_PCI_CFG_HDR8_REG (PCIE_EP_BASE + 0x20)
+#define PCIE_EP_PCI_CFG_HDR9_REG (PCIE_EP_BASE + 0x24)
+#define PCIE_EP_PCI_CFG_HDR10_REG (PCIE_EP_BASE + 0x28)
+#define PCIE_EP_PCI_CFG_HDR11_REG (PCIE_EP_BASE + 0x2C)
+#define PCIE_EP_PCI_CFG_HDR12_REG (PCIE_EP_BASE + 0x30)
+#define PCIE_EP_PCI_CFG_HDR13_REG (PCIE_EP_BASE + 0x34)
+#define PCIE_EP_PCI_CFG_HDR14_REG (PCIE_EP_BASE + 0x38)
+#define PCIE_EP_PCI_CFG_HDR15_REG (PCIE_EP_BASE + 0x3C)
+#define PCIE_EP_PCI_PM_CAP0_REG (PCIE_EP_BASE + 0x40)
+#define PCIE_EP_PCI_PM_CAP1_REG (PCIE_EP_BASE + 0x44)
+#define PCIE_EP_PCI_MSI_CAP0_REG (PCIE_EP_BASE + 0x50)
+#define PCIE_EP_PCI_MSI_CAP1_REG (PCIE_EP_BASE + 0x54)
+#define PCIE_EP_PCI_MSI_CAP2_REG (PCIE_EP_BASE + 0x58)
+#define PCIE_EP_PCI_MSI_CAP3_REG (PCIE_EP_BASE + 0x5C)
+#define PCIE_EP_PCIE_CAP0_REG (PCIE_EP_BASE + 0x70)
+#define PCIE_EP_PCIE_CAP1_REG (PCIE_EP_BASE + 0x74)
+#define PCIE_EP_PCIE_CAP2_REG (PCIE_EP_BASE + 0x78)
+#define PCIE_EP_PCIE_CAP3_REG (PCIE_EP_BASE + 0x7C)
+#define PCIE_EP_PCIE_CAP4_REG (PCIE_EP_BASE + 0x80)
+#define PCIE_EP_PCIE_CAP5_REG (PCIE_EP_BASE + 0x84)
+#define PCIE_EP_PCIE_CAP6_REG (PCIE_EP_BASE + 0x88)
+#define PCIE_EP_PCIE_CAP7_REG (PCIE_EP_BASE + 0x8C)
+#define PCIE_EP_PCIE_CAP8_REG (PCIE_EP_BASE + 0x90)
+#define PCIE_EP_PCIE_CAP9_REG (PCIE_EP_BASE + 0x94)
+#define PCIE_EP_PCIE_CAP10_REG (PCIE_EP_BASE + 0x98)
+#define PCIE_EP_PCIE_CAP11_REG (PCIE_EP_BASE + 0x9C)
+#define PCIE_EP_PCIE_CAP12_REG (PCIE_EP_BASE + 0xA0)
+#define PCIE_EP_SLOT_CAP_REG (PCIE_EP_BASE + 0xC0)
+#define PCIE_EP_AER_CAP0_REG (PCIE_EP_BASE + 0x100)
+#define PCIE_EP_AER_CAP1_REG (PCIE_EP_BASE + 0x104)
+#define PCIE_EP_AER_CAP2_REG (PCIE_EP_BASE + 0x108)
+#define PCIE_EP_AER_CAP3_REG (PCIE_EP_BASE + 0x10C)
+#define PCIE_EP_AER_CAP4_REG (PCIE_EP_BASE + 0x110)
+#define PCIE_EP_AER_CAP5_REG (PCIE_EP_BASE + 0x114)
+#define PCIE_EP_AER_CAP6_REG (PCIE_EP_BASE + 0x118)
+#define PCIE_EP_AER_CAP7_REG (PCIE_EP_BASE + 0x11C)
+#define PCIE_EP_AER_CAP8_REG (PCIE_EP_BASE + 0x120)
+#define PCIE_EP_AER_CAP9_REG (PCIE_EP_BASE + 0x124)
+#define PCIE_EP_AER_CAP10_REG (PCIE_EP_BASE + 0x128)
+#define PCIE_EP_AER_CAP11_REG (PCIE_EP_BASE + 0x12C)
+#define PCIE_EP_AER_CAP12_REG (PCIE_EP_BASE + 0x130)
+#define PCIE_EP_AER_CAP13_REG (PCIE_EP_BASE + 0x134)
+#define PCIE_EP_VC_CAP0_REG (PCIE_EP_BASE + 0x140)
+#define PCIE_EP_VC_CAP1_REG (PCIE_EP_BASE + 0x144)
+#define PCIE_EP_VC_CAP2_REG (PCIE_EP_BASE + 0x148)
+#define PCIE_EP_VC_CAP3_REG (PCIE_EP_BASE + 0x14C)
+#define PCIE_EP_VC_CAP4_REG (PCIE_EP_BASE + 0x150)
+#define PCIE_EP_VC_CAP5_REG (PCIE_EP_BASE + 0x154)
+#define PCIE_EP_VC_CAP6_REG (PCIE_EP_BASE + 0x158)
+#define PCIE_EP_VC_CAP7_REG (PCIE_EP_BASE + 0x15C)
+#define PCIE_EP_VC_CAP8_REG (PCIE_EP_BASE + 0x160)
+#define PCIE_EP_VC_CAP9_REG (PCIE_EP_BASE + 0x164)
+#define PCIE_EP_PORT_LOGIC0_REG (PCIE_EP_BASE + 0x700)
+#define PCIE_EP_PORT_LOGIC1_REG (PCIE_EP_BASE + 0x704)
+#define PCIE_EP_PORT_LOGIC2_REG (PCIE_EP_BASE + 0x708)
+#define PCIE_EP_PORT_LOGIC3_REG (PCIE_EP_BASE + 0x0)
+#define PCIE_EP_PORT_LOGIC4_REG (PCIE_EP_BASE + 0x710)
+#define PCIE_EP_PORT_LOGIC5_REG (PCIE_EP_BASE + 0x714)
+#define PCIE_EP_PORT_LOGIC6_REG (PCIE_EP_BASE + 0x718)
+#define PCIE_EP_PORT_LOGIC7_REG (PCIE_EP_BASE + 0x71C)
+#define PCIE_EP_PORT_LOGIC8_REG (PCIE_EP_BASE + 0x720)
+#define PCIE_EP_PORT_LOGIC9_REG (PCIE_EP_BASE + 0x724)
+#define PCIE_EP_PORT_LOGIC10_REG (PCIE_EP_BASE + 0x728)
+#define PCIE_EP_PORT_LOGIC11_REG (PCIE_EP_BASE + 0x72C)
+#define PCIE_EP_PORT_LOGIC12_REG (PCIE_EP_BASE + 0x730)
+#define PCIE_EP_PORT_LOGIC13_REG (PCIE_EP_BASE + 0x734)
+#define PCIE_EP_PORT_LOGIC14_REG (PCIE_EP_BASE + 0x738)
+#define PCIE_EP_PORT_LOGIC15_REG (PCIE_EP_BASE + 0x73C)
+#define PCIE_EP_PORT_LOGIC16_REG (PCIE_EP_BASE + 0x748)
+#define PCIE_EP_PORT_LOGIC17_REG (PCIE_EP_BASE + 0x74C)
+#define PCIE_EP_PORT_LOGIC18_REG (PCIE_EP_BASE + 0x750)
+#define PCIE_EP_PORT_LOGIC19_REG (PCIE_EP_BASE + 0x7A8)
+#define PCIE_EP_PORT_LOGIC20_REG (PCIE_EP_BASE + 0x7AC)
+#define PCIE_EP_PORT_LOGIC21_REG (PCIE_EP_BASE + 0x7B0)
+#define PCIE_EP_PORT_LOGIC22_REG (PCIE_EP_BASE + 0x80C)
+#define PCIE_EP_PORTLOGIC23_REG (PCIE_EP_BASE + 0x810)
+#define PCIE_EP_PORTLOGIC24_REG (PCIE_EP_BASE + 0x814)
+#define PCIE_EP_PORTLOGIC25_REG (PCIE_EP_BASE + 0x818)
+#define PCIE_EP_PORTLOGIC26_REG (PCIE_EP_BASE + 0x81C)
+#define PCIE_EP_PORTLOGIC27_REG (PCIE_EP_BASE + 0x820)
+#define PCIE_EP_PORTLOGIC28_REG (PCIE_EP_BASE + 0x824)
+#define PCIE_EP_PORTLOGIC29_REG (PCIE_EP_BASE + 0x828)
+#define PCIE_EP_PORTLOGIC30_REG (PCIE_EP_BASE + 0x82C)
+#define PCIE_EP_PORTLOGIC31_REG (PCIE_EP_BASE + 0x830)
+#define PCIE_EP_PORTLOGIC32_REG (PCIE_EP_BASE + 0x834)
+#define PCIE_EP_PORTLOGIC33_REG (PCIE_EP_BASE + 0x838)
+#define PCIE_EP_PORTLOGIC34_REG (PCIE_EP_BASE + 0x83C)
+#define PCIE_EP_PORTLOGIC35_REG (PCIE_EP_BASE + 0x840)
+#define PCIE_EP_PORTLOGIC36_REG (PCIE_EP_BASE + 0x844)
+#define PCIE_EP_PORTLOGIC37_REG (PCIE_EP_BASE + 0x848)
+#define PCIE_EP_PORTLOGIC38_REG (PCIE_EP_BASE + 0x84C)
+#define PCIE_EP_PORTLOGIC39_REG (PCIE_EP_BASE + 0x850)
+#define PCIE_EP_PORTLOGIC40_REG (PCIE_EP_BASE + 0x854)
+#define PCIE_EP_PORTLOGIC41_REG (PCIE_EP_BASE + 0x858)
+#define PCIE_EP_PORTLOGIC42_REG (PCIE_EP_BASE + 0x85C)
+#define PCIE_EP_PORTLOGIC43_REG (PCIE_EP_BASE + 0x860)
+#define PCIE_EP_PORTLOGIC44_REG (PCIE_EP_BASE + 0x864)
+#define PCIE_EP_PORTLOGIC45_REG (PCIE_EP_BASE + 0x868)
+#define PCIE_EP_PORTLOGIC46_REG (PCIE_EP_BASE + 0x86C)
+#define PCIE_EP_PORTLOGIC47_REG (PCIE_EP_BASE + 0x870)
+#define PCIE_EP_PORTLOGIC48_REG (PCIE_EP_BASE + 0x874)
+#define PCIE_EP_PORTLOGIC49_REG (PCIE_EP_BASE + 0x878)
+#define PCIE_EP_PORTLOGIC50_REG (PCIE_EP_BASE + 0x87C)
+#define PCIE_EP_PORTLOGIC51_REG (PCIE_EP_BASE + 0x880)
+#define PCIE_EP_PORTLOGIC52_REG (PCIE_EP_BASE + 0x884)
+#define PCIE_EP_PORTLOGIC53_REG (PCIE_EP_BASE + 0x888)
+#define PCIE_EP_LINK_TIMEOUT_OFF_REG (PCIE_EP_BASE + 0x8d4)
+#define PCIE_EP_PORTLOGIC54_REG (PCIE_EP_BASE + 0x900)
+#define PCIE_EP_PORTLOGIC55_REG (PCIE_EP_BASE + 0x904)
+#define PCIE_EP_PORTLOGIC56_REG (PCIE_EP_BASE + 0x908)
+#define PCIE_EP_PORTLOGIC57_REG (PCIE_EP_BASE + 0x90C)
+#define PCIE_EP_PORTLOGIC58_REG (PCIE_EP_BASE + 0x910)
+#define PCIE_EP_PORTLOGIC59_REG (PCIE_EP_BASE + 0x914)
+#define PCIE_EP_PORTLOGIC60_REG (PCIE_EP_BASE + 0x918)
+#define PCIE_EP_PORTLOGIC61_REG (PCIE_EP_BASE + 0x91C)
+#define PCIE_EP_PORTLOGIC62_REG (PCIE_EP_BASE + 0x97C)
+#define PCIE_EP_PORTLOGIC63_REG (PCIE_EP_BASE + 0x980)
+#define PCIE_EP_PORTLOGIC64_REG (PCIE_EP_BASE + 0x99C)
+#define PCIE_EP_PORTLOGIC65_REG (PCIE_EP_BASE + 0x9A0)
+#define PCIE_EP_PORTLOGIC66_REG (PCIE_EP_BASE + 0x9BC)
+#define PCIE_EP_PORTLOGIC67_REG (PCIE_EP_BASE + 0x9C4)
+#define PCIE_EP_PORTLOGIC68_REG (PCIE_EP_BASE + 0x9C8)
+#define PCIE_EP_PORTLOGIC69_REG (PCIE_EP_BASE + 0x9CC)
+#define PCIE_EP_PORTLOGIC70_REG (PCIE_EP_BASE + 0x9D0)
+#define PCIE_EP_PORTLOGIC71_REG (PCIE_EP_BASE + 0x9D4)
+#define PCIE_EP_PORTLOGIC72_REG (PCIE_EP_BASE + 0x9D8)
+#define PCIE_EP_PORTLOGIC73_REG (PCIE_EP_BASE + 0x9DC)
+#define PCIE_EP_PORTLOGIC74_REG (PCIE_EP_BASE + 0x9E0)
+#define PCIE_EP_PORTLOGIC75_REG (PCIE_EP_BASE + 0xA00)
+#define PCIE_EP_PORTLOGIC76_REG (PCIE_EP_BASE + 0xA10)
+#define PCIE_EP_PORTLOGIC77_REG (PCIE_EP_BASE + 0xA18)
+#define PCIE_EP_PORTLOGIC78_REG (PCIE_EP_BASE + 0xA1C)
+#define PCIE_EP_PORTLOGIC79_REG (PCIE_EP_BASE + 0xA24)
+#define PCIE_EP_PORTLOGIC80_REG (PCIE_EP_BASE + 0xA28)
+#define PCIE_EP_PORTLOGIC81_REG (PCIE_EP_BASE + 0xA34)
+#define PCIE_EP_PORTLOGIC82_REG (PCIE_EP_BASE + 0xA3C)
+#define PCIE_EP_PORTLOGIC83_REG (PCIE_EP_BASE + 0xA40)
+#define PCIE_EP_PORTLOGIC84_REG (PCIE_EP_BASE + 0xA44)
+#define PCIE_EP_PORTLOGIC85_REG (PCIE_EP_BASE + 0xA48)
+#define PCIE_EP_PORTLOGIC86_REG (PCIE_EP_BASE + 0xA6C)
+#define PCIE_EP_PORTLOGIC87_REG (PCIE_EP_BASE + 0xA70)
+#define PCIE_EP_PORTLOGIC88_REG (PCIE_EP_BASE + 0xA78)
+#define PCIE_EP_PORTLOGIC89_REG (PCIE_EP_BASE + 0xA7C)
+#define PCIE_EP_PORTLOGIC90_REG (PCIE_EP_BASE + 0xA80)
+#define PCIE_EP_PORTLOGIC91_REG (PCIE_EP_BASE + 0xA84)
+#define PCIE_EP_PORTLOGIC92_REG (PCIE_EP_BASE + 0xA88)
+#define PCIE_EP_PORTLOGIC93_REG (PCIE_EP_BASE + 0xA8C)
+#define PCIE_EP_PORTLOGIC94_REG (PCIE_EP_BASE + 0xA90)
+
+
+
+typedef union tagPciCfgHdr0
+{
+
+ struct
+ {
+ UINT32 vendor_id : 16 ;
+ UINT32 device_id : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCI_CFG_HDR0_U;
+
+
+
+
+typedef union tagPciCfgHdr1
+{
+
+ struct
+ {
+ UINT32 io_space_enable : 1 ;
+ UINT32 memory_space_enable : 1 ;
+ UINT32 bus_master_enable : 1 ;
+ UINT32 specialcycleenable : 1 ;
+ UINT32 memory_write_and_invalidate : 1 ;
+ UINT32 vga_palette_snoop_enable : 1 ;
+ UINT32 parity_error_response : 1 ;
+ UINT32 idsel_stepping_waitcycle_control : 1 ;
+ UINT32 serr_enable : 1 ;
+ UINT32 fastback_to_backenable : 1 ;
+ UINT32 interrupt_disable : 1 ;
+ UINT32 Reserved_2 : 5 ;
+ UINT32 Reserved_1 : 3 ;
+ UINT32 intx_status : 1 ;
+ UINT32 capabilitieslist : 1 ;
+ UINT32 pcibus66mhzcapable : 1 ;
+ UINT32 Reserved_0 : 1 ;
+ UINT32 fastback_to_back : 1 ;
+ UINT32 masterdataparityerror : 1 ;
+ UINT32 devsel_timing : 2 ;
+ UINT32 signaled_target_abort : 1 ;
+ UINT32 received_target_abort : 1 ;
+ UINT32 received_master_abort : 1 ;
+ UINT32 signaled_system_error : 1 ;
+ UINT32 detected_parity_error : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCI_CFG_HDR1_U;
+
+
+
+
+typedef union tagPciCfgHdr2
+{
+
+ struct
+ {
+ UINT32 revision_identification : 8 ;
+ UINT32 Reserved_3 : 8 ;
+ UINT32 sub_class : 8 ;
+ UINT32 baseclass : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCI_CFG_HDR2_U;
+
+
+
+
+typedef union tagPciCfgHdr3
+{
+
+ struct
+ {
+ UINT32 cache_line_size : 8 ;
+ UINT32 mstr_lat_tmr : 8 ;
+ UINT32 multi_function_device : 7 ;
+ UINT32 hdr_type : 1 ;
+ UINT32 bist : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCI_CFG_HDR3_U;
+
+
+
+
+typedef union tagPciCfgHdr4
+{
+
+ struct
+ {
+ UINT32 sbar01_space_inicator : 1 ;
+ UINT32 sbar01_type : 2 ;
+ UINT32 sbar01_prefetchable : 1 ;
+ UINT32 sbar01_lower : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCI_CFG_HDR4_U;
+
+
+
+
+typedef union tagPciCfgHdr6
+{
+
+ struct
+ {
+ UINT32 sbar23_space_inicator : 1 ;
+ UINT32 sbar23_type : 2 ;
+ UINT32 sbar23_prefetchable : 1 ;
+ UINT32 Reserved_4 : 8 ;
+ UINT32 sbar23_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCI_CFG_HDR6_U;
+
+typedef union tagPciLinkTimeOut
+{
+
+ struct
+ {
+ UINT32 link_timeout_prepriod_default : 8 ;
+ UINT32 link_timeout_enable_default : 1 ;
+ UINT32 Reserved_4 : 23 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_LINK_TIMEOUT_OFF_U;
+
+
+
+
+
+typedef union tagPciCfgHdr8
+{
+
+ struct
+ {
+ UINT32 sbar45_space_inicator : 1 ;
+ UINT32 sbar45_type : 2 ;
+ UINT32 sbar45_prefetchable : 1 ;
+ UINT32 Reserved_5 : 8 ;
+ UINT32 sbar45_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCI_CFG_HDR8_U;
+
+
+
+
+typedef union tagPciCfgHdr11
+{
+
+ struct
+ {
+ UINT32 subsystem_vendor_id : 16 ;
+ UINT32 subsystemid : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCI_CFG_HDR11_U;
+
+
+
+
+typedef union tagPciCfgHdr13
+{
+
+ struct
+ {
+ UINT32 capptr : 8 ;
+ UINT32 Reserved_6 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCI_CFG_HDR13_U;
+
+
+
+
+typedef union tagPciCfgHdr15
+{
+
+ struct
+ {
+ UINT32 int_line : 8 ;
+ UINT32 int_pin : 8 ;
+ UINT32 Min_Grant : 8 ;
+ UINT32 Max_Latency : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCI_CFG_HDR15_U;
+
+
+
+
+typedef union tagPciMsiCap0
+{
+
+ struct
+ {
+ UINT32 msi_cap_id : 8 ;
+ UINT32 next_capability_pointer : 8 ;
+ UINT32 msi_enabled : 1 ;
+ UINT32 multiple_message_capable : 3 ;
+ UINT32 multiple_message_enabled : 3 ;
+ UINT32 msi_64_en : 1 ;
+ UINT32 pvm_en : 1 ;
+ UINT32 message_control_register : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCI_MSI_CAP0_U;
+
+
+
+
+typedef union tagPciMsiCap1
+{
+
+ struct
+ {
+ UINT32 Reserved_11 : 2 ;
+ UINT32 msi_addr_low : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCI_MSI_CAP1_U;
+
+
+
+
+typedef union tagPciMsiCap3
+{
+
+ struct
+ {
+ UINT32 msi_data : 16 ;
+ UINT32 Reserved_12 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCI_MSI_CAP3_U;
+
+
+
+
+typedef union tagPcieCap0
+{
+
+ struct
+ {
+ UINT32 pcie_cap_id : 8 ;
+ UINT32 pcie_next_ptr : 8 ;
+ UINT32 pcie_capability_version : 4 ;
+ UINT32 device_port_type : 4 ;
+ UINT32 slot_implemented : 1 ;
+ UINT32 interrupt_message_number : 5 ;
+ UINT32 Reserved_13 : 2 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCIE_CAP0_U;
+
+
+
+
+typedef union tagPcieCap1
+{
+
+ struct
+ {
+ UINT32 max_payload_size_supported : 3 ;
+ UINT32 phantom_function_supported : 2 ;
+ UINT32 extended_tagfield_supported : 1 ;
+ UINT32 endpoint_l0sacceptable_latency : 3 ;
+ UINT32 endpoint_l1acceptable_latency : 3 ;
+ UINT32 undefined : 3 ;
+ UINT32 Reserved_16 : 3 ;
+ UINT32 captured_slot_power_limit_value : 8 ;
+ UINT32 captured_slot_power_limit_scale : 2 ;
+ UINT32 function_level_reset : 1 ;
+ UINT32 Reserved_15 : 3 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCIE_CAP1_U;
+
+
+
+
+typedef union tagPcieCap2
+{
+
+ struct
+ {
+ UINT32 correctable_error_reporting_enable : 1 ;
+ UINT32 non_fatal_error_reporting_enable : 1 ;
+ UINT32 fatal_error_reporting_enable : 1 ;
+ UINT32 urenable : 1 ;
+ UINT32 enable_relaxed_ordering : 1 ;
+ UINT32 max_payload_size : 3 ;
+ UINT32 extended_tagfieldenable : 1 ;
+ UINT32 phantom_function_enable : 1 ;
+ UINT32 auxpowerpmenable : 1 ;
+ UINT32 enablenosnoop : 1 ;
+ UINT32 max_read_request_size : 3 ;
+ UINT32 Reserved_18 : 1 ;
+ UINT32 correctableerrordetected : 1 ;
+ UINT32 non_fatalerrordetected : 1 ;
+ UINT32 fatalerrordetected : 1 ;
+ UINT32 unsupportedrequestdetected : 1 ;
+ UINT32 auxpowerdetected : 1 ;
+ UINT32 transactionpending : 1 ;
+ UINT32 Reserved_17 : 10 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCIE_CAP2_U;
+
+
+
+
+typedef union tagPcieCap3
+{
+
+ struct
+ {
+ UINT32 max_link_speed : 4 ;
+ UINT32 max_link_width : 6 ;
+ UINT32 active_state_power_management : 2 ;
+ UINT32 l0s_exitlatency : 3 ;
+ UINT32 l1_exit_latency : 3 ;
+ UINT32 clock_power_management : 1 ;
+ UINT32 surprise_down_error_report_cap : 1 ;
+ UINT32 data_link_layer_active_report_cap : 1 ;
+ UINT32 link_bandwidth_noti_cap : 1 ;
+ UINT32 aspm_option_compliance : 1 ;
+ UINT32 Reserved_19 : 1 ;
+ UINT32 port_number : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCIE_CAP3_U;
+
+
+
+
+typedef union tagPcieCap4
+{
+
+ struct
+ {
+ UINT32 active_state_power_management : 2 ;
+ UINT32 Reserved_22 : 1 ;
+ UINT32 rcb : 1 ;
+ UINT32 link_disable : 1 ;
+ UINT32 retrain_link : 1 ;
+ UINT32 common_clock_config : 1 ;
+ UINT32 extended_sync : 1 ;
+ UINT32 enable_clock_pwr_management : 1 ;
+ UINT32 hw_auto_width_disable : 1 ;
+ UINT32 link_bandwidth_management_int_en : 1 ;
+ UINT32 link_auto_bandwidth_int_en : 1 ;
+ UINT32 Reserved_21 : 4 ;
+ UINT32 current_link_speed : 4 ;
+ UINT32 negotiated_link_width : 6 ;
+ UINT32 Reserved_20 : 1 ;
+ UINT32 link_training : 1 ;
+ UINT32 slot_clock_configration : 1 ;
+ UINT32 data_link_layer_active : 1 ;
+ UINT32 link_bandwidth_management_status : 1 ;
+ UINT32 link_auto_bandwidth_status : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCIE_CAP4_U;
+
+
+
+
+typedef union tagPcieCap5
+{
+
+ struct
+ {
+ UINT32 attentioonbuttonpresent : 1 ;
+ UINT32 powercontrollerpresent : 1 ;
+ UINT32 mrlsensorpresent : 1 ;
+ UINT32 attentionindicatorpresent : 1 ;
+ UINT32 powerindicatorpresent : 1 ;
+ UINT32 hot_plugsurprise : 1 ;
+ UINT32 hot_plugcapable : 1 ;
+ UINT32 slotpowerlimitvalue : 8 ;
+ UINT32 slotpowerlimitscale : 2 ;
+ UINT32 electromechanicalinterlockpresen : 1 ;
+ UINT32 no_cmd_complete_support : 1 ;
+ UINT32 phy_slot_number : 13 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCIE_CAP5_U;
+
+
+
+
+
+typedef union tagPcieCap6
+{
+
+ struct
+ {
+ UINT32 attentionbuttonpressedenable : 1 ;
+ UINT32 powerfaultdetectedenable : 1 ;
+ UINT32 mrlsensorchangedenable : 1 ;
+ UINT32 presencedetectchangedenable : 1 ;
+ UINT32 commandcompletedinterruptenable : 1 ;
+ UINT32 hot_pluginterruptenable : 1 ;
+ UINT32 attentionindicatorcontrol : 2 ;
+ UINT32 powerindicatorcontrol : 2 ;
+ UINT32 powercontrollercontrol : 1 ;
+ UINT32 electromechanicalinterlockcontrol : 1 ;
+ UINT32 datalinklayerstatechangedenable : 1 ;
+ UINT32 Reserved_23 : 3 ;
+ UINT32 attentionbuttonpressed : 1 ;
+ UINT32 powerfaultdetected : 1 ;
+ UINT32 mrlsensorchanged : 1 ;
+ UINT32 presencedetectchanged : 1 ;
+ UINT32 commandcompleted : 1 ;
+ UINT32 mrlsensorstate : 1 ;
+ UINT32 presencedetectstate : 1 ;
+ UINT32 electromechanicalinterlockstatus : 1 ;
+ UINT32 datalinklayerstatechanged : 1 ;
+ UINT32 slot_ctrl_status : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCIE_CAP6_U;
+
+
+
+
+typedef union tagPcieCap7
+{
+
+ struct
+ {
+ UINT32 systemerroroncorrectableerrorenable : 1 ;
+ UINT32 systemerroronnon_fatalerrorenable : 1 ;
+ UINT32 systemerroronfatalerrorenable : 1 ;
+ UINT32 pmeinterruptenable : 1 ;
+ UINT32 crssoftwarevisibilityenable : 1 ;
+ UINT32 Reserved_24 : 11 ;
+ UINT32 crssoftwarevisibility : 1 ;
+ UINT32 root_cap : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCIE_CAP7_U;
+
+
+
+
+typedef union tagPcieCap8
+{
+
+ struct
+ {
+ UINT32 pmerequesterid : 16 ;
+ UINT32 pmestatus : 1 ;
+ UINT32 pmepending : 1 ;
+ UINT32 root_status : 14 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCIE_CAP8_U;
+
+
+
+
+typedef union tagPcieCap9
+{
+
+ struct
+ {
+ UINT32 completiontimeoutrangessupported : 4 ;
+ UINT32 completiontimeoutdisablesupported : 1 ;
+ UINT32 ariforwardingsupported : 1 ;
+ UINT32 atomicoproutingsupported : 1 ;
+ UINT32 _2_bitatomicopcompletersupported : 1 ;
+ UINT32 _4_bitatomicopcompletersupported : 1 ;
+ UINT32 _28_bitcascompletersupported : 1 ;
+ UINT32 noro_enabledpr_prpassing : 1 ;
+ UINT32 Reserved_25 : 1 ;
+ UINT32 tphcompletersupported : 2 ;
+ UINT32 dev_cap2 : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCIE_CAP9_U;
+
+
+
+
+typedef union tagPcieCap10
+{
+
+ struct
+ {
+ UINT32 completiontimeoutvalue : 4 ;
+ UINT32 completiontimeoutdisable : 1 ;
+ UINT32 ariforwardingsupported : 1 ;
+ UINT32 atomicoprequesterenable : 1 ;
+ UINT32 atomicopegressblocking : 1 ;
+ UINT32 idorequestenable : 1 ;
+ UINT32 idocompletionenable : 1 ;
+ UINT32 dev_ctrl2 : 22 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCIE_CAP10_U;
+
+
+
+
+typedef union tagPcieCap11
+{
+
+ struct
+ {
+ UINT32 Reserved_27 : 1 ;
+ UINT32 gen1_suport : 1 ;
+ UINT32 gen2_suport : 1 ;
+ UINT32 gen3_suport : 1 ;
+ UINT32 Reserved_26 : 4 ;
+ UINT32 crosslink_supported : 1 ;
+ UINT32 link_cap2 : 23 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCIE_CAP11_U;
+
+
+
+
+typedef union tagPcieCap12
+{
+
+ struct
+ {
+ UINT32 targetlinkspeed : 4 ;
+ UINT32 entercompliance : 1 ;
+ UINT32 hardwareautonomousspeeddisa : 1 ;
+ UINT32 selectablede_empha : 1 ;
+ UINT32 transmitmargin : 3 ;
+ UINT32 _entermodifiedcompliance : 1 ;
+ UINT32 compliancesos : 1 ;
+ UINT32 de_emphasislevel : 4 ;
+ UINT32 currentde_emphasislevel : 1 ;
+ UINT32 equalizationcomplete : 1 ;
+ UINT32 equalizationphase1successful : 1 ;
+ UINT32 equalizationphase2successful : 1 ;
+ UINT32 equalizationphase3successful : 1 ;
+ UINT32 linkequalizationrequest : 1 ;
+ UINT32 link_ctrl2_status2 : 10 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCIE_CAP12_U;
+
+
+
+
+typedef union tagSlotCap
+{
+
+ struct
+ {
+ UINT32 slotnumberingcapabilitiesid : 8 ;
+ UINT32 nextcapabilitypointer : 8 ;
+ UINT32 add_incardslotsprovided : 5 ;
+ UINT32 firstinchassis : 1 ;
+ UINT32 Reserved_28 : 2 ;
+ UINT32 slot_cap : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_SLOT_CAP_U;
+
+
+
+
+typedef union tagAerCap0
+{
+
+ struct
+ {
+ UINT32 pciexpressextendedcapabilityid : 16 ;
+ UINT32 capabilityversion : 4 ;
+ UINT32 aer_cap_hdr : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_AER_CAP0_U;
+
+
+
+
+typedef union tagAerCap1
+{
+
+ struct
+ {
+ UINT32 Reserved_34 : 1 ;
+ UINT32 Reserved_33 : 3 ;
+ UINT32 datalinkprotocolerrorsta : 1 ;
+ UINT32 surprisedownerrorstatus : 1 ;
+ UINT32 Reserved_32 : 6 ;
+ UINT32 poisonedtlpstatu : 1 ;
+ UINT32 flowcontrolprotocolerrorst : 1 ;
+ UINT32 completiontimeouts : 1 ;
+ UINT32 completerabortstatus : 1 ;
+ UINT32 receiveroverflowstatus : 1 ;
+ UINT32 malformedtlpstatus : 1 ;
+ UINT32 ecrcerrorstatus : 1 ;
+ UINT32 ecrcerrorstat : 1 ;
+ UINT32 unsupportedrequesterrorstatus : 1 ;
+ UINT32 Reserved_31 : 3 ;
+ UINT32 atomicopegressblockedstatus : 1 ;
+ UINT32 uncorr_err_status : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_AER_CAP1_U;
+
+
+
+
+typedef union tagAerCap2
+{
+
+ struct
+ {
+ UINT32 Reserved_38 : 1 ;
+ UINT32 Reserved_37 : 3 ;
+ UINT32 datalinkprotocolerrormask : 1 ;
+ UINT32 surprisedownerrormask : 1 ;
+ UINT32 Reserved_36 : 6 ;
+ UINT32 poisonedtlpmask : 1 ;
+ UINT32 flowcontrolprotocolerrormask : 1 ;
+ UINT32 completiontimeoutmask : 1 ;
+ UINT32 completerabortmask : 1 ;
+ UINT32 unexpectedcompletionmask : 1 ;
+ UINT32 receiveroverflowmask : 1 ;
+ UINT32 malformedtlpmask : 1 ;
+ UINT32 ecrcerrormask : 1 ;
+ UINT32 unsupportedrequesterrormask : 1 ;
+ UINT32 Reserved_35 : 3 ;
+ UINT32 atomicopegressblockedmask : 1 ;
+ UINT32 uncorr_err_mask : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_AER_CAP2_U;
+
+
+
+
+typedef union tagAerCap3
+{
+
+ struct
+ {
+ UINT32 Reserved_42 : 1 ;
+ UINT32 Reserved_41 : 3 ;
+ UINT32 datalinkprotocolerrorsever : 1 ;
+ UINT32 surprisedownerrorseverity : 1 ;
+ UINT32 Reserved_40 : 6 ;
+ UINT32 poisonedtlpseverity : 1 ;
+ UINT32 flowcontrolprotocolerrorseveri : 1 ;
+ UINT32 completiontimeoutseverity : 1 ;
+ UINT32 completerabortseverity : 1 ;
+ UINT32 unexpectedcompletionseverity : 1 ;
+ UINT32 receiveroverflowseverity : 1 ;
+ UINT32 malformedtlpseverity : 1 ;
+ UINT32 ecrcerrorseverity : 1 ;
+ UINT32 unsupportedrequesterrorseverity : 1 ;
+ UINT32 Reserved_39 : 3 ;
+ UINT32 atomicopegressblockedseverity : 1 ;
+ UINT32 uncorr_err_ser : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_AER_CAP3_U;
+
+
+
+
+typedef union tagAerCap4
+{
+
+ struct
+ {
+ UINT32 receivererrorstatus : 1 ;
+ UINT32 Reserved_44 : 5 ;
+ UINT32 badtlpstatus : 1 ;
+ UINT32 baddllpstatus : 1 ;
+ UINT32 replay_numrolloverstatus : 1 ;
+ UINT32 Reserved_43 : 3 ;
+ UINT32 replytimertimeoutstatus : 1 ;
+ UINT32 advisorynon_fatalerrorstatus : 1 ;
+ UINT32 corr_err_status : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_AER_CAP4_U;
+
+
+
+
+typedef union tagAerCap5
+{
+
+ struct
+ {
+ UINT32 receivererrormask : 1 ;
+ UINT32 Reserved_46 : 5 ;
+ UINT32 badtlpmask : 1 ;
+ UINT32 baddllpmask : 1 ;
+ UINT32 replay_numrollovermask : 1 ;
+ UINT32 Reserved_45 : 3 ;
+ UINT32 replytimertimeoutmask : 1 ;
+ UINT32 advisorynon_fatalerrormask : 1 ;
+ UINT32 corr_err_mask : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_AER_CAP5_U;
+
+
+
+
+typedef union tagAerCap6
+{
+
+ struct
+ {
+ UINT32 firsterrorpointer : 5 ;
+ UINT32 ecrcgenerationcapability : 1 ;
+ UINT32 ecrcgenerationenable : 1 ;
+ UINT32 ecrccheckcapable : 1 ;
+ UINT32 ecrccheckenable : 1 ;
+ UINT32 adv_cap_ctrl : 23 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_AER_CAP6_U;
+
+
+
+
+typedef union tagAerCap11
+{
+
+ struct
+ {
+ UINT32 correctableerrorreportingenable : 1 ;
+ UINT32 non_fatalerrorreportingenable : 1 ;
+ UINT32 fatalerrorreportingenable : 1 ;
+ UINT32 root_err_cmd : 29 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_AER_CAP11_U;
+
+
+
+
+typedef union tagAerCap12
+{
+
+ struct
+ {
+ UINT32 err_correceived : 1 ;
+ UINT32 multipleerr_correceived : 1 ;
+ UINT32 err_fatal_nonfatalreceived : 1 ;
+ UINT32 multipleerr_fatal_nonfatalreceived : 1 ;
+ UINT32 firstuncorrectablefatal : 1 ;
+ UINT32 non_fatalerrormessagesreceived : 1 ;
+ UINT32 fatalerrormessagesreceived : 1 ;
+ UINT32 Reserved_47 : 20 ;
+ UINT32 root_err_status : 5 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_AER_CAP12_U;
+
+
+
+
+typedef union tagAerCap13
+{
+
+ struct
+ {
+ UINT32 err_corsourceidentification : 16 ;
+ UINT32 err_src_id : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_AER_CAP13_U;
+
+
+
+
+typedef union tagVcCap0
+{
+
+ struct
+ {
+ UINT32 pciexpressextendedcapabilityid : 16 ;
+ UINT32 capabilityversion : 4 ;
+ UINT32 vc_cap_hdr : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_VC_CAP0_U;
+
+
+
+
+typedef union tagVcCap1
+{
+
+ struct
+ {
+ UINT32 extendedvccount : 3 ;
+ UINT32 Reserved_50 : 1 ;
+ UINT32 lowpriorityextendedvccount : 3 ;
+ UINT32 Reserved_49 : 1 ;
+ UINT32 referenceclock : 2 ;
+ UINT32 portarbitrationtableentrysize : 2 ;
+ UINT32 vc_cap1 : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_VC_CAP1_U;
+
+
+
+
+typedef union tagVcCap2
+{
+
+ struct
+ {
+ UINT32 vcarbitrationcapability : 8 ;
+ UINT32 Reserved_51 : 16 ;
+ UINT32 vc_cap2 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_VC_CAP2_U;
+
+
+
+
+typedef union tagVcCap3
+{
+
+ struct
+ {
+ UINT32 loadvcarbitrationtable : 1 ;
+ UINT32 vcarbitrationselect : 3 ;
+ UINT32 Reserved_53 : 12 ;
+ UINT32 arbitrationtablestatus : 1 ;
+ UINT32 Reserved_52 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_VC_CAP3_U;
+
+
+
+
+typedef union tagVcCap4
+{
+
+ struct
+ {
+ UINT32 portarbitrationcapability : 8 ;
+ UINT32 Reserved_56 : 6 ;
+ UINT32 Reserved_55 : 1 ;
+ UINT32 rejectsnooptransactions : 1 ;
+ UINT32 maximumtimeslots : 7 ;
+ UINT32 Reserved_54 : 1 ;
+ UINT32 vc_res_cap : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_VC_CAP4_U;
+
+
+
+
+typedef union tagVcCap5
+{
+
+ struct
+ {
+ UINT32 tc_vcmap : 8 ;
+ UINT32 Reserved_59 : 8 ;
+ UINT32 loadportarbitrationtable : 1 ;
+ UINT32 portarbitrationselec : 3 ;
+ UINT32 Reserved_58 : 4 ;
+ UINT32 vcid : 3 ;
+ UINT32 Reserved_57 : 4 ;
+ UINT32 vc_res_ctrl : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_VC_CAP5_U;
+
+
+
+
+typedef union tagVcCap6
+{
+
+ struct
+ {
+ UINT32 Reserved_60 : 16 ;
+ UINT32 portarbitrationtablestatus : 1 ;
+ UINT32 vcnegotiationpending : 1 ;
+ UINT32 vc_res_status : 14 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_VC_CAP6_U;
+
+
+
+
+typedef union tagVcCap7
+{
+
+ struct
+ {
+ UINT32 portarbitrationcapability : 8 ;
+ UINT32 Reserved_63 : 6 ;
+ UINT32 Reserved_62 : 1 ;
+ UINT32 rejectsnooptransactions : 1 ;
+ UINT32 maximumtimeslots : 7 ;
+ UINT32 Reserved_61 : 1 ;
+ UINT32 vc_res_cap0 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_VC_CAP7_U;
+
+
+
+
+typedef union tagVcCap8
+{
+
+ struct
+ {
+ UINT32 tc_vcmap : 8 ;
+ UINT32 Reserved_66 : 8 ;
+ UINT32 loadportarbitrationtable : 1 ;
+ UINT32 portarbitrationselect : 3 ;
+ UINT32 Reserved_65 : 4 ;
+ UINT32 vcid : 3 ;
+ UINT32 Reserved_64 : 4 ;
+ UINT32 vc_res_ctrl0 : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_VC_CAP8_U;
+
+
+
+
+typedef union tagVcCap9
+{
+
+ struct
+ {
+ UINT32 Reserved_67 : 16 ;
+ UINT32 arbitrationtablestatus : 1 ;
+ UINT32 vcnegotiationpending : 1 ;
+ UINT32 vc_res_status0 : 14 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_VC_CAP9_U;
+
+
+
+
+typedef union tagPortLogic0
+{
+
+ struct
+ {
+ UINT32 ack_lat_timer : 16 ;
+ UINT32 replay_timer : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC0_U;
+
+
+
+
+typedef union tagPortLogic2
+{
+
+ struct
+ {
+ UINT32 linknumber : 8 ;
+ UINT32 Reserved_70 : 7 ;
+ UINT32 forcelink : 1 ;
+ UINT32 linkstate : 6 ;
+ UINT32 Reserved_69 : 2 ;
+ UINT32 port_force_link : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC2_U;
+
+
+
+
+typedef union tagPortLogic3
+{
+
+ struct
+ {
+ UINT32 ackfrequency : 8 ;
+ UINT32 n_fts : 8 ;
+ UINT32 commonclockn_fts : 8 ;
+ UINT32 l0sentrancelatency : 3 ;
+ UINT32 l1entrancelatency : 3 ;
+ UINT32 enteraspml1withoutreceiveinl0s : 1 ;
+ UINT32 ack_aspm : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC3_U;
+
+
+
+
+typedef union tagPortLogic4
+{
+
+ struct
+ {
+ UINT32 vendorspecificdllprequest : 1 ;
+ UINT32 scrambledisable : 1 ;
+ UINT32 loopbackenable : 1 ;
+ UINT32 resetassert : 1 ;
+ UINT32 Reserved_73 : 1 ;
+ UINT32 dlllinkenable : 1 ;
+ UINT32 Reserved_72 : 1 ;
+ UINT32 fastlinkmode : 1 ;
+ UINT32 Reserved_71 : 8 ;
+ UINT32 linkmodeenable : 6 ;
+ UINT32 crosslinkenable : 1 ;
+ UINT32 crosslinkactive : 1 ;
+ UINT32 port_link_ctrl : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC4_U;
+
+
+
+
+typedef union tagPortLogic5
+{
+
+ struct
+ {
+ UINT32 insertlaneskewfortransmit : 24 ;
+ UINT32 flowcontroldisable : 1 ;
+ UINT32 ack_nakdisable : 1 ;
+ UINT32 Reserved_75 : 5 ;
+ UINT32 lane_skew : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC5_U;
+
+
+
+
+typedef union tagPortLogic6
+{
+
+ struct
+ {
+ UINT32 numberoftssymbols : 4 ;
+ UINT32 Reserved_77 : 4 ;
+ UINT32 numberofskpsymbols : 3 ;
+ UINT32 Reserved_76 : 3 ;
+ UINT32 timermodifierforreplaytimer : 5 ;
+ UINT32 timermodifierforack_naklatencytimer : 5 ;
+ UINT32 timermodifierforflowcontrolwatchdogtimer : 5 ;
+ UINT32 sym_num : 3 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC6_U;
+
+
+
+
+typedef union tagPortLogic7
+{
+
+ struct
+ {
+ UINT32 vc0posteddataqueuedepth : 11 ;
+ UINT32 Reserved_78 : 4 ;
+ UINT32 sym_timer : 1 ;
+ UINT32 maskfunctionmismatchfilteringfo : 1 ;
+ UINT32 maskpoisonedtlpfiltering : 1 ;
+ UINT32 maskbarmatchfiltering : 1 ;
+ UINT32 masktype1configurationrequestfiltering : 1 ;
+ UINT32 masklockedrequestfiltering : 1 ;
+ UINT32 masktagerrorrulesforreceivedcompletions : 1 ;
+ UINT32 maskrequesteridmismatcherrorforreceivedcompletions : 1 ;
+ UINT32 maskfunctionmismatcherrorforreceivedcompletions : 1 ;
+ UINT32 mask_traffic_classmis_match_error_forreceived_completions : 1 ;
+ UINT32 mask_attributesmismatcherrorforreceivedcompletions : 1 ;
+ UINT32 mask_length_mismatch_error_forreceive_dcompletions : 1 ;
+ UINT32 maske_crcerror_filtering : 1 ;
+ UINT32 maske_crcerror_filtering_forcompletions : 1 ;
+ UINT32 message_control : 1 ;
+ UINT32 maskfilteringofreceived : 1 ;
+ UINT32 flt_mask1 : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC7_U;
+
+
+
+
+typedef union tagPortLogic8
+{
+
+ struct
+ {
+ UINT32 cx_flt_mask_venmsg0_drop : 1 ;
+ UINT32 cx_flt_mask_venmsg1_drop : 1 ;
+ UINT32 cx_flt_mask_dabort_4ucpl : 1 ;
+ UINT32 cx_flt_mask_handle_flush : 1 ;
+ UINT32 flt_mask2 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC8_U;
+
+
+
+
+typedef union tagPortLogic9
+{
+
+ struct
+ {
+ UINT32 amba_multi_outbound_decomp_np : 1 ;
+ UINT32 amba_obnp_ctrl : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC9_U;
+
+
+
+
+typedef union tagPortLogic12
+{
+
+ struct
+ {
+ UINT32 transmitposteddatafccredits : 12 ;
+ UINT32 transmitpostedheaderfccredits : 8 ;
+ UINT32 tx_pfc_status : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC12_U;
+
+
+
+
+typedef union tagPortLogic13
+{
+
+ struct
+ {
+ UINT32 transmitnon_posteddatafccredits : 12 ;
+ UINT32 transmitnon_postedheaderfccredits : 8 ;
+ UINT32 tx_npfc_status : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC13_U;
+
+
+
+
+typedef union tagPortLogic14
+{
+
+ struct
+ {
+ UINT32 transmitcompletiondatafccredits : 12 ;
+ UINT32 transmitcompletionheaderfccredits : 8 ;
+ UINT32 tx_cplfc_status : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC14_U;
+
+
+
+
+typedef union tagPortLogic15
+{
+
+ struct
+ {
+ UINT32 rx_tlp_fc_credit_not_retured : 1 ;
+ UINT32 tx_retry_buf_not_empty : 1 ;
+ UINT32 rx_queue_not_empty : 1 ;
+ UINT32 Reserved_80 : 13 ;
+ UINT32 fc_latency_timer_override_value : 13 ;
+ UINT32 Reserved_79 : 2 ;
+ UINT32 fc_latency_timer_override_en : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC15_U;
+
+
+
+
+typedef union tagPortLogic16
+{
+
+ struct
+ {
+ UINT32 vc0posteddatacredits : 12 ;
+ UINT32 vc0postedheadercredits : 8 ;
+ UINT32 Reserved_82 : 1 ;
+ UINT32 vc0_postedtlpqueuemode : 1 ;
+ UINT32 vc0postedtlpqueuemode : 1 ;
+ UINT32 vc0postedtlpqueuemo : 1 ;
+ UINT32 Reserved_81 : 6 ;
+ UINT32 tlptypeorderingforvc0 : 1 ;
+ UINT32 rx_pque_ctrl : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC16_U;
+
+
+
+
+typedef union tagPortLogic17
+{
+
+ struct
+ {
+ UINT32 vc0non_posteddatacredits : 12 ;
+ UINT32 vc0non_postedheadercredits : 8 ;
+ UINT32 rx_npque_ctrl : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC17_U;
+
+
+
+
+typedef union tagPortLogic18
+{
+
+ struct
+ {
+ UINT32 vco_comp_data_credits : 12 ;
+ UINT32 vc0_cpl_header_credt : 8 ;
+ UINT32 Reserved_84 : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC18_U;
+
+
+
+
+typedef union tagPortLogic19
+{
+
+ struct
+ {
+ UINT32 vco_posted_data_que_path : 14 ;
+ UINT32 Reserved_85 : 2 ;
+ UINT32 vco_posted_head_queue_depth : 10 ;
+ UINT32 vc_pbuf_ctrl : 6 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC19_U;
+
+
+
+
+typedef union tagPortLogic20
+{
+
+ struct
+ {
+ UINT32 vco_np_data_que_depth : 14 ;
+ UINT32 Reserved_87 : 2 ;
+ UINT32 vco_np_header_que_depth : 10 ;
+ UINT32 vc_npbuf_ctrl : 6 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC20_U;
+
+
+
+
+typedef union tagPortLogic21
+{
+
+ struct
+ {
+ UINT32 vco_comp_data_queue_depth : 14 ;
+ UINT32 Reserved_89 : 2 ;
+ UINT32 vco_posted_head_queue_depth : 10 ;
+ UINT32 Reserved_88 : 6 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC21_U;
+
+
+
+
+typedef union tagPortLogic22
+{
+
+ struct
+ {
+ UINT32 n_fts : 8 ;
+ UINT32 pre_determ_num_of_lane : 9 ;
+ UINT32 det_sp_change : 1 ;
+ UINT32 config_phy_tx_sw : 1 ;
+ UINT32 config_tx_comp_rcv_bit : 1 ;
+ UINT32 set_emp_level : 1 ;
+ UINT32 Reserved_90 : 11 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC22_U;
+
+
+
+
+typedef union tagPortlogic25
+{
+
+ struct
+ {
+ UINT32 remote_rd_req_size : 3 ;
+ UINT32 Reserved_93 : 5 ;
+ UINT32 remote_max_brd_tag : 8 ;
+ UINT32 Reserved_92 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC25_U;
+
+
+
+
+typedef union tagPortlogic26
+{
+
+ struct
+ {
+ UINT32 resize_master_resp_compser : 1 ;
+ UINT32 axi_ctrl1 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC26_U;
+
+
+
+
+typedef union tagPortlogic54
+{
+
+ struct
+ {
+ UINT32 region_index : 4 ;
+ UINT32 Reserved_94 : 27 ;
+ UINT32 iatu_view : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC54_U;
+
+
+
+
+typedef union tagPortlogic55
+{
+
+ struct
+ {
+ UINT32 iatu1_type : 5 ;
+ UINT32 iatu1_tc : 3 ;
+ UINT32 iatu1_td : 1 ;
+ UINT32 iatu1_attr : 2 ;
+ UINT32 Reserved_98 : 5 ;
+ UINT32 iatu1_at : 2 ;
+ UINT32 Reserved_97 : 2 ;
+ UINT32 iatu1_id : 3 ;
+ UINT32 Reserved_96 : 9 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC55_U;
+
+
+
+
+typedef union tagPortlogic56
+{
+
+ struct
+ {
+ UINT32 iatu2_type : 8 ;
+ UINT32 iatu2_bar_num : 3 ;
+ UINT32 Reserved_102 : 3 ;
+ UINT32 iatu2_tc_match_en : 1 ;
+ UINT32 iatu2_td_match_en : 1 ;
+ UINT32 iatu2_attr_match_en : 1 ;
+ UINT32 Reserved_101 : 1 ;
+ UINT32 iatu2_at_match_en : 1 ;
+ UINT32 iatu2_func_num_match_en : 1 ;
+ UINT32 iatu2_virtual_func_num_match_en : 1 ;
+ UINT32 message_code_match_en : 1 ;
+ UINT32 Reserved_100 : 2 ;
+ UINT32 iatu2_response_code : 2 ;
+ UINT32 Reserved_99 : 1 ;
+ UINT32 iatu2_fuzzy_type_match_mode : 1 ;
+ UINT32 iatu2_cfg_shift_mode : 1 ;
+ UINT32 iatu2_ivert_mode : 1 ;
+ UINT32 iatu2_match_mode : 1 ;
+ UINT32 iatu2_region_en : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC56_U;
+
+
+
+
+typedef union tagPortlogic57
+{
+
+ struct
+ {
+ UINT32 iatu_start_low : 12 ;
+ UINT32 iatu_start_high : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC57_U;
+
+
+
+
+typedef union tagPortlogic59
+{
+
+ struct
+ {
+ UINT32 iatu_limit_low : 12 ;
+ UINT32 iatu_limit_high : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC59_U;
+
+
+
+
+typedef union tagPortlogic60
+{
+
+ struct
+ {
+ UINT32 xlated_addr_high : 12 ;
+ UINT32 xlated_addr_low : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC60_U;
+
+
+
+
+typedef union tagPortlogic62
+{
+
+ struct
+ {
+ UINT32 dma_wr_eng_en : 1 ;
+ UINT32 dma_wr_ena : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC62_U;
+
+
+
+
+typedef union tagPortlogic63
+{
+
+ struct
+ {
+ UINT32 wr_doorbell_num : 3 ;
+ UINT32 Reserved_104 : 28 ;
+ UINT32 dma_wr_dbell_stop : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC63_U;
+
+
+
+
+typedef union tagPortlogic64
+{
+
+ struct
+ {
+ UINT32 dma_read_eng_en : 1 ;
+ UINT32 Reserved_105 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC64_U;
+
+
+
+
+typedef union tagPortlogic65
+{
+
+ struct
+ {
+ UINT32 rd_doorbell_num : 3 ;
+ UINT32 Reserved_107 : 28 ;
+ UINT32 dma_rd_dbell_stop : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC65_U;
+
+
+
+
+typedef union tagPortlogic66
+{
+
+ struct
+ {
+ UINT32 done_int_status : 8 ;
+ UINT32 Reserved_109 : 8 ;
+ UINT32 abort_int_status : 8 ;
+ UINT32 Reserved_108 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC66_U;
+
+
+
+
+typedef union tagPortlogic67
+{
+
+ struct
+ {
+ UINT32 done_int_mask : 8 ;
+ UINT32 Reserved_112 : 8 ;
+ UINT32 abort_int_mask : 8 ;
+ UINT32 Reserved_111 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC67_U;
+
+
+
+
+typedef union tagPortlogic68
+{
+
+ struct
+ {
+ UINT32 done_int_clr : 8 ;
+ UINT32 Reserved_115 : 8 ;
+ UINT32 abort_int_clr : 8 ;
+ UINT32 Reserved_114 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC68_U;
+
+
+
+
+typedef union tagPortlogic69
+{
+
+ struct
+ {
+ UINT32 app_rd_err_det : 8 ;
+ UINT32 Reserved_117 : 8 ;
+ UINT32 ll_element_fetch_err_det : 8 ;
+ UINT32 Reserved_116 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC69_U;
+
+
+
+
+typedef union tagPortlogic74
+{
+
+ struct
+ {
+ UINT32 dma_wr_c0_imwr_data : 16 ;
+ UINT32 dma_wr_c1_imwr_data : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC74_U;
+
+
+
+
+typedef union tagPortlogic75
+{
+
+ struct
+ {
+ UINT32 wr_ch_ll_remote_abort_int_en : 8 ;
+ UINT32 Reserved_119 : 8 ;
+ UINT32 wr_ch_ll_local_abort_int_en : 8 ;
+ UINT32 Reserved_118 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC75_U;
+
+
+
+
+typedef union tagPortlogic76
+{
+
+ struct
+ {
+ UINT32 done_int_status : 8 ;
+ UINT32 Reserved_122 : 8 ;
+ UINT32 abort_int_status : 8 ;
+ UINT32 Reserved_121 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC76_U;
+
+
+
+
+typedef union tagPortlogic77
+{
+
+ struct
+ {
+ UINT32 done_int_mask : 8 ;
+ UINT32 Reserved_124 : 8 ;
+ UINT32 abort_int_mask : 8 ;
+ UINT32 dma_rd_int_mask : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC77_U;
+
+
+
+
+typedef union tagPortlogic78
+{
+
+ struct
+ {
+ UINT32 done_int_clr : 8 ;
+ UINT32 Reserved_126 : 8 ;
+ UINT32 abort_int_clr : 8 ;
+ UINT32 dma_rd_int_clr : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC78_U;
+
+
+
+
+typedef union tagPortlogic79
+{
+
+ struct
+ {
+ UINT32 app_wr_err_det : 8 ;
+ UINT32 Reserved_127 : 8 ;
+ UINT32 link_list_fetch_err_det : 8 ;
+ UINT32 dma_rd_err_low : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC79_U;
+
+
+
+
+typedef union tagPortlogic80
+{
+
+ struct
+ {
+ UINT32 unspt_request : 8 ;
+ UINT32 completer_abort : 8 ;
+ UINT32 cpl_time_out : 8 ;
+ UINT32 data_poison : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC80_U;
+
+
+
+
+typedef union tagPortlogic81
+{
+
+ struct
+ {
+ UINT32 remote_abort_int_en : 8 ;
+ UINT32 Reserved_129 : 8 ;
+ UINT32 local_abort_int_en : 8 ;
+ UINT32 dma_rd_ll_err_ena : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC81_U;
+
+
+
+
+typedef union tagPortlogic86
+{
+
+ struct
+ {
+ UINT32 channel_dir : 3 ;
+ UINT32 Reserved_132 : 28 ;
+ UINT32 dma_ch_con_idx : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC86_U;
+
+
+
+
+typedef union tagPortlogic87
+{
+
+ struct
+ {
+ UINT32 cycle_bit : 1 ;
+ UINT32 toggle_cycle_bit : 1 ;
+ UINT32 load_link_pointer : 1 ;
+ UINT32 local_int_en : 1 ;
+ UINT32 remote_int_en : 1 ;
+ UINT32 channel_status : 2 ;
+ UINT32 Reserved_136 : 1 ;
+ UINT32 consumer_cycle_state : 1 ;
+ UINT32 linked_list_en : 1 ;
+ UINT32 Reserved_135 : 2 ;
+ UINT32 func_num_dma : 5 ;
+ UINT32 Reserved_134 : 7 ;
+ UINT32 no_snoop : 1 ;
+ UINT32 ro : 1 ;
+ UINT32 td : 1 ;
+ UINT32 tc : 3 ;
+ UINT32 dma_ch_ctrl : 2 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC87_U;
+
+
+
+
+typedef union tagPortlogic93
+{
+
+ struct
+ {
+ UINT32 Reserved_138 : 2 ;
+ UINT32 dma_ll_ptr_low : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC93_U;
+
+
+#define PCIE_SUBCTRL_BASE (0x0)
+
+
+
+
+
+#define PCIE_SUBCTRL_SC_PCIE0_CLK_EN_REG (PCIE_SUBCTRL_BASE + 0x300)
+#define PCIE_SUBCTRL_SC_PCIE0_2_CLK_EN_REG(port_id) \
+ (PCIE_SUBCTRL_SC_PCIE0_CLK_EN_REG + (port_id << 3))
+#define PCIE_SUBCTRL_SC_PCIE0_CLK_DIS_REG (PCIE_SUBCTRL_BASE + 0x304)
+#define PCIE_SUBCTRL_SC_PCIE0_2_CLK_DIS_REG(port_id) \
+ (PCIE_SUBCTRL_SC_PCIE0_CLK_DIS_REG + (port_id << 3))
+#define PCIE_SUBCTRL_SC_PCIE1_CLK_EN_REG (PCIE_SUBCTRL_BASE + 0x308)
+#define PCIE_SUBCTRL_SC_PCIE1_CLK_DIS_REG (PCIE_SUBCTRL_BASE + 0x30C)
+#define PCIE_SUBCTRL_SC_PCIE2_CLK_EN_REG (PCIE_SUBCTRL_BASE + 0x310)
+#define PCIE_SUBCTRL_SC_PCIE2_CLK_DIS_REG (PCIE_SUBCTRL_BASE + 0x314)
+#define PCIE_SUBCTRL_SC_SAS_CLK_EN_REG (PCIE_SUBCTRL_BASE + 0x318)
+#define PCIE_SUBCTRL_SC_SAS_CLK_DIS_REG (PCIE_SUBCTRL_BASE + 0x31C)
+#define PCIE_SUBCTRL_SC_PCIE3_CLK_EN_REG (PCIE_SUBCTRL_BASE + 0x320)
+#define PCIE_SUBCTRL_SC_PCIE3_CLK_DIS_REG (PCIE_SUBCTRL_BASE + 0x324)
+#define PCIE_SUBCTRL_SC_ITS_CLK_EN_REG (PCIE_SUBCTRL_BASE + 0x328)
+#define PCIE_SUBCTRL_SC_ITS_CLK_DIS_REG (PCIE_SUBCTRL_BASE + 0x32C)
+#define PCIE_SUBCTRL_SC_SLLC_CLK_EN_REG (PCIE_SUBCTRL_BASE + 0x360)
+#define PCIE_SUBCTRL_SC_SLLC_CLK_DIS_REG (PCIE_SUBCTRL_BASE + 0x364)
+#define PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA00)
+#define PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA04)
+#define PCIE_SUBCTRL_SC_PCIE1_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA08)
+#define PCIE_SUBCTRL_SC_PCIE1_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA0C)
+#define PCIE_SUBCTRL_SC_PCIE2_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA10)
+#define PCIE_SUBCTRL_SC_PCIE2_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA14)
+#define PCIE_SUBCTRL_SC_SAS_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA18)
+#define PCIE_SUBCTRL_SC_SAS_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA1C)
+#define PCIE_SUBCTRL_SC_MCTP0_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA20)
+#define PCIE_SUBCTRL_SC_MCTP0_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA24)
+#define PCIE_SUBCTRL_SC_MCTP1_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA28)
+#define PCIE_SUBCTRL_SC_MCTP1_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA2C)
+#define PCIE_SUBCTRL_SC_MCTP2_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA30)
+#define PCIE_SUBCTRL_SC_MCTP2_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA34)
+#define PCIE_SUBCTRL_SC_SLLC_TSVRX_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA58)
+#define PCIE_SUBCTRL_SC_SLLC_TSVRX_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA5C)
+#define PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA60)
+#define PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA64)
+#define PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA68)
+#define PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA6C)
+#define PCIE_SUBCTRL_SC_MCTP3_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA70)
+#define PCIE_SUBCTRL_SC_MCTP3_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA74)
+#define PCIE_SUBCTRL_SC_ITS_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA80)
+#define PCIE_SUBCTRL_SC_ITS_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA84)
+#define PCIE_SUBCTRL_SC_SLLC_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xAA0)
+#define PCIE_SUBCTRL_SC_SLLC_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xAA4)
+#define PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xAC0)
+#define PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xAC4)
+#define PCIE_SUBCTRL_SC_PCS_APB_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xAC8)
+#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG (PCIE_SUBCTRL_BASE + 0x1000)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY0_REG (PCIE_SUBCTRL_BASE + 0x1004)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY1_REG (PCIE_SUBCTRL_BASE + 0x1008)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY2_REG (PCIE_SUBCTRL_BASE + 0x100C)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG (PCIE_SUBCTRL_BASE + 0x1010)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG (PCIE_SUBCTRL_BASE + 0x1014)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG (PCIE_SUBCTRL_BASE + 0x1018)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG (PCIE_SUBCTRL_BASE + 0x101C)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY7_REG (PCIE_SUBCTRL_BASE + 0x1020)
+#define PCIE_SUBCTRL_SC_DISPATCH_RETRY_CONTROL_REG (PCIE_SUBCTRL_BASE + 0x1030)
+#define PCIE_SUBCTRL_SC_DISPATCH_INTMASK_REG (PCIE_SUBCTRL_BASE + 0x1100)
+#define PCIE_SUBCTRL_SC_DISPATCH_RAWINT_REG (PCIE_SUBCTRL_BASE + 0x1104)
+#define PCIE_SUBCTRL_SC_DISPATCH_INTSTAT_REG (PCIE_SUBCTRL_BASE + 0x1108)
+#define PCIE_SUBCTRL_SC_DISPATCH_INTCLR_REG (PCIE_SUBCTRL_BASE + 0x110C)
+#define PCIE_SUBCTRL_SC_DISPATCH_ERRSTAT_REG (PCIE_SUBCTRL_BASE + 0x1110)
+#define PCIE_SUBCTRL_SC_REMAP_CTRL_REG (PCIE_SUBCTRL_BASE + 0x1200)
+#define PCIE_SUBCTRL_SC_FTE_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2200)
+#define PCIE_SUBCTRL_SC_HILINK0_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2300)
+#define PCIE_SUBCTRL_SC_HILINK1_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2304)
+#define PCIE_SUBCTRL_SC_HILINK2_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2308)
+#define PCIE_SUBCTRL_SC_HILINK5_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2314)
+#define PCIE_SUBCTRL_SC_HILINK1_AHB_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2324)
+#define PCIE_SUBCTRL_SC_HILINK2_AHB_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2328)
+#define PCIE_SUBCTRL_SC_HILINK5_AHB_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2334)
+#define PCIE_SUBCTRL_SC_HILINK5_LRSTB_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2340)
+#define PCIE_SUBCTRL_SC_HILINK6_LRSTB_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2344)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_SS_REFCLK_REG (PCIE_SUBCTRL_BASE + 0x2400)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_CS_REFCLK_DIRSEL_REG (PCIE_SUBCTRL_BASE + 0x2404)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_LIFECLK2DIG_SEL_REG (PCIE_SUBCTRL_BASE + 0x2408)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_CORE_CLK_SELEXT_REG (PCIE_SUBCTRL_BASE + 0x240C)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_CORE_CLK_SEL_REG (PCIE_SUBCTRL_BASE + 0x2410)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_CTRL_BUS_MODE_REG (PCIE_SUBCTRL_BASE + 0x2414)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_MACROPWRDB_REG (PCIE_SUBCTRL_BASE + 0x2418)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_GRSTB_REG (PCIE_SUBCTRL_BASE + 0x241C)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_BIT_SLIP_REG (PCIE_SUBCTRL_BASE + 0x2420)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_LRSTB_REG (PCIE_SUBCTRL_BASE + 0x2424)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_SS_REFCLK_REG (PCIE_SUBCTRL_BASE + 0x2500)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_CS_REFCLK_DIRSEL_REG (PCIE_SUBCTRL_BASE + 0x2504)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_LIFECLK2DIG_SEL_REG (PCIE_SUBCTRL_BASE + 0x2508)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_CORE_CLK_SELEXT_REG (PCIE_SUBCTRL_BASE + 0x250C)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_CORE_CLK_SEL_REG (PCIE_SUBCTRL_BASE + 0x2510)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_CTRL_BUS_MODE_REG (PCIE_SUBCTRL_BASE + 0x2514)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_MACROPWRDB_REG (PCIE_SUBCTRL_BASE + 0x2518)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_GRSTB_REG (PCIE_SUBCTRL_BASE + 0x251C)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_BIT_SLIP_REG (PCIE_SUBCTRL_BASE + 0x2520)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_LRSTB_REG (PCIE_SUBCTRL_BASE + 0x2524)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_SS_REFCLK_REG (PCIE_SUBCTRL_BASE + 0x2600)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_CS_REFCLK_DIRSEL_REG (PCIE_SUBCTRL_BASE + 0x2604)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_LIFECLK2DIG_SEL_REG (PCIE_SUBCTRL_BASE + 0x2608)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_CORE_CLK_SELEXT_REG (PCIE_SUBCTRL_BASE + 0x260C)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_CORE_CLK_SEL_REG (PCIE_SUBCTRL_BASE + 0x2610)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_CTRL_BUS_MODE_REG (PCIE_SUBCTRL_BASE + 0x2614)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_MACROPWRDB_REG (PCIE_SUBCTRL_BASE + 0x2618)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_GRSTB_REG (PCIE_SUBCTRL_BASE + 0x261C)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_BIT_SLIP_REG (PCIE_SUBCTRL_BASE + 0x2620)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_LRSTB_REG (PCIE_SUBCTRL_BASE + 0x2624)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_SS_REFCLK_REG (PCIE_SUBCTRL_BASE + 0x2700)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_CS_REFCLK_DIRSEL_REG (PCIE_SUBCTRL_BASE + 0x2704)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_LIFECLK2DIG_SEL_REG (PCIE_SUBCTRL_BASE + 0x2708)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_CORE_CLK_SELEXT_REG (PCIE_SUBCTRL_BASE + 0x270C)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_CORE_CLK_SEL_REG (PCIE_SUBCTRL_BASE + 0x2710)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_CTRL_BUS_MODE_REG (PCIE_SUBCTRL_BASE + 0x2714)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_MACROPWRDB_REG (PCIE_SUBCTRL_BASE + 0x2718)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_GRSTB_REG (PCIE_SUBCTRL_BASE + 0x271C)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_BIT_SLIP_REG (PCIE_SUBCTRL_BASE + 0x2720)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_LRSTB_REG (PCIE_SUBCTRL_BASE + 0x2724)
+#define PCIE_SUBCTRL_SC_PCIE0_CLKREQ_REG (PCIE_SUBCTRL_BASE + 0x2800)
+#define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_WR_CFG_REG (PCIE_SUBCTRL_BASE + 0x2880)
+#define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_RD_CFG_REG (PCIE_SUBCTRL_BASE + 0x2890)
+#define PCIE_SUBCTRL_SC_PCIE1_CLKREQ_REG (PCIE_SUBCTRL_BASE + 0x2900)
+#define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_WR_CFG_REG (PCIE_SUBCTRL_BASE + 0x2980)
+#define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_RD_CFG_REG (PCIE_SUBCTRL_BASE + 0x2990)
+#define PCIE_SUBCTRL_SC_PCIE2_CLKREQ_REG (PCIE_SUBCTRL_BASE + 0x2A00)
+#define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_WR_CFG_REG (PCIE_SUBCTRL_BASE + 0x2A80)
+#define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_RD_CFG_REG (PCIE_SUBCTRL_BASE + 0x2A90)
+#define PCIE_SUBCTRL_SC_PCIE3_CLKREQ_REG (PCIE_SUBCTRL_BASE + 0x2B00)
+#define PCIE_SUBCTRL_SC_SMMU_MEM_CTRL0_REG (PCIE_SUBCTRL_BASE + 0x3000)
+#define PCIE_SUBCTRL_SC_SMMU_MEM_CTRL1_REG (PCIE_SUBCTRL_BASE + 0x3004)
+#define PCIE_SUBCTRL_SC_SMMU_MEM_CTRL2_REG (PCIE_SUBCTRL_BASE + 0x3008)
+#define PCIE_SUBCTRL_SC_SLLC0_MEM_CTRL_REG (PCIE_SUBCTRL_BASE + 0x3010)
+#define PCIE_SUBCTRL_SC_SAS_MEM_CTRL_REG (PCIE_SUBCTRL_BASE + 0x3030)
+#define PCIE_SUBCTRL_SC_PCIE_MEM_CTRL0_REG (PCIE_SUBCTRL_BASE + 0x3040)
+#define PCIE_SUBCTRL_SC_PCIE_MEM_CTRL1_REG (PCIE_SUBCTRL_BASE + 0x3044)
+#define PCIE_SUBCTRL_SC_PCIE_MEM_CTRL2_REG (PCIE_SUBCTRL_BASE + 0x3048)
+#define PCIE_SUBCTRL_SC_SKEW_COMMON_0_REG (PCIE_SUBCTRL_BASE + 0x3400)
+#define PCIE_SUBCTRL_SC_SKEW_COMMON_1_REG (PCIE_SUBCTRL_BASE + 0x3404)
+#define PCIE_SUBCTRL_SC_SKEW_COMMON_2_REG (PCIE_SUBCTRL_BASE + 0x3408)
+#define PCIE_SUBCTRL_SC_SKEW_A_0_REG (PCIE_SUBCTRL_BASE + 0x3500)
+#define PCIE_SUBCTRL_SC_SKEW_A_1_REG (PCIE_SUBCTRL_BASE + 0x3504)
+#define PCIE_SUBCTRL_SC_SKEW_A_2_REG (PCIE_SUBCTRL_BASE + 0x3508)
+#define PCIE_SUBCTRL_SC_SKEW_A_3_REG (PCIE_SUBCTRL_BASE + 0x350C)
+#define PCIE_SUBCTRL_SC_SKEW_A_4_REG (PCIE_SUBCTRL_BASE + 0x3510)
+#define PCIE_SUBCTRL_SC_SKEW_A_5_REG (PCIE_SUBCTRL_BASE + 0x3514)
+#define PCIE_SUBCTRL_SC_SKEW_A_6_REG (PCIE_SUBCTRL_BASE + 0x3518)
+#define PCIE_SUBCTRL_SC_SKEW_A_7_REG (PCIE_SUBCTRL_BASE + 0x351C)
+#define PCIE_SUBCTRL_SC_SKEW_A_8_REG (PCIE_SUBCTRL_BASE + 0x3520)
+#define PCIE_SUBCTRL_SC_SKEW_B_0_REG (PCIE_SUBCTRL_BASE + 0x3600)
+#define PCIE_SUBCTRL_SC_SKEW_B_1_REG (PCIE_SUBCTRL_BASE + 0x3604)
+#define PCIE_SUBCTRL_SC_SKEW_B_2_REG (PCIE_SUBCTRL_BASE + 0x3608)
+#define PCIE_SUBCTRL_SC_SKEW_B_3_REG (PCIE_SUBCTRL_BASE + 0x360C)
+#define PCIE_SUBCTRL_SC_SKEW_B_4_REG (PCIE_SUBCTRL_BASE + 0x3610)
+#define PCIE_SUBCTRL_SC_SKEW_B_5_REG (PCIE_SUBCTRL_BASE + 0x3614)
+#define PCIE_SUBCTRL_SC_SKEW_B_6_REG (PCIE_SUBCTRL_BASE + 0x3618)
+#define PCIE_SUBCTRL_SC_SKEW_B_7_REG (PCIE_SUBCTRL_BASE + 0x361C)
+#define PCIE_SUBCTRL_SC_SKEW_B_8_REG (PCIE_SUBCTRL_BASE + 0x3620)
+#define PCIE_SUBCTRL_SC_PCIE0_CLK_ST_REG (PCIE_SUBCTRL_BASE + 0x5300)
+#define PCIE_SUBCTRL_SC_PCIE0_2_CLK_ST_REG(port_id) \
+ (PCIE_SUBCTRL_SC_PCIE0_CLK_ST_REG + (port_id << 2))
+#define PCIE_SUBCTRL_SC_PCIE1_CLK_ST_REG (PCIE_SUBCTRL_BASE + 0x5304)
+#define PCIE_SUBCTRL_SC_PCIE2_CLK_ST_REG (PCIE_SUBCTRL_BASE + 0x5308)
+#define PCIE_SUBCTRL_SC_SAS_CLK_ST_REG (PCIE_SUBCTRL_BASE + 0x530C)
+#define PCIE_SUBCTRL_SC_PCIE3_CLK_ST_REG (PCIE_SUBCTRL_BASE + 0x5310)
+#define PCIE_SUBCTRL_SC_ITS_CLK_ST_REG (PCIE_SUBCTRL_BASE + 0x5314)
+#define PCIE_SUBCTRL_SC_SLLC_CLK_ST_REG (PCIE_SUBCTRL_BASE + 0x5330)
+#define PCIE_SUBCTRL_SC_PCIE0_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A00)
+#define PCIE_SUBCTRL_SC_PCIE1_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A04)
+#define PCIE_SUBCTRL_SC_PCIE2_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A08)
+#define PCIE_SUBCTRL_SC_SAS_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A0C)
+#define PCIE_SUBCTRL_SC_MCTP0_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A10)
+#define PCIE_SUBCTRL_SC_MCTP1_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A14)
+#define PCIE_SUBCTRL_SC_MCTP2_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A18)
+#define PCIE_SUBCTRL_SC_SLLC_TSVRX_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A2C)
+#define PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A30)
+#define PCIE_SUBCTRL_SC_PCIE3_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A34)
+#define PCIE_SUBCTRL_SC_MCTP3_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A38)
+#define PCIE_SUBCTRL_SC_ITS_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A40)
+#define PCIE_SUBCTRL_SC_SLLC_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A50)
+#define PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A60)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_PLLOUTOFLOCK_REG (PCIE_SUBCTRL_BASE + 0x6400)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_PRBS_ERR_REG (PCIE_SUBCTRL_BASE + 0x6404)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_LOS_REG (PCIE_SUBCTRL_BASE + 0x6408)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_PLLOUTOFLOCK_REG (PCIE_SUBCTRL_BASE + 0x6500)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_PRBS_ERR_REG (PCIE_SUBCTRL_BASE + 0x6504)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_LOS_REG (PCIE_SUBCTRL_BASE + 0x6508)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_PLLOUTOFLOCK_REG (PCIE_SUBCTRL_BASE + 0x6600)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_PRBS_ERR_REG (PCIE_SUBCTRL_BASE + 0x6604)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_LOS_REG (PCIE_SUBCTRL_BASE + 0x6608)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_PLLOUTOFLOCK_REG (PCIE_SUBCTRL_BASE + 0x6700)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_PRBS_ERR_REG (PCIE_SUBCTRL_BASE + 0x6704)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_LOS_REG (PCIE_SUBCTRL_BASE + 0x6708)
+#define PCIE_SUBCTRL_SC_PCIE0_RXEQINPRO_STAT_REG (PCIE_SUBCTRL_BASE + 0x6800)
+#define PCIE_SUBCTRL_SC_PCIE0_LINKINT_RCVRY_STAT_REG (PCIE_SUBCTRL_BASE + 0x6804)
+#define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE0_REG (PCIE_SUBCTRL_BASE + 0x6808)
+#define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE1_REG (PCIE_SUBCTRL_BASE + 0x680C)
+#define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE2_REG (PCIE_SUBCTRL_BASE + 0x6810)
+#define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE3_REG (PCIE_SUBCTRL_BASE + 0x6814)
+#define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG (PCIE_SUBCTRL_BASE + 0x6818)
+#define PCIE_LTSSM_STATE_MASK (0x3f)
+#define PCIE_LTSSM_CFG_LANENUM_ACPT 0x0a
+#define PCIE_LTSSM_CFG_COMPLETE 0x0b
+#define PCIE_LTSSM_LINKUP_STATE (0x11)
+#define LTSSM_ENABLE BIT11
+#define MAX_TRY_LINK_NUM 5
+#define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_WR_STS0_REG (PCIE_SUBCTRL_BASE + 0x6880)
+#define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_WR_STS1_REG (PCIE_SUBCTRL_BASE + 0x6884)
+#define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_RD_STS0_REG (PCIE_SUBCTRL_BASE + 0x6890)
+#define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_RD_STS1_REG (PCIE_SUBCTRL_BASE + 0x6894)
+#define PCIE_SUBCTRL_SC_PCIE0_DSIZE_BRG_ECC_ERR_REG (PCIE_SUBCTRL_BASE + 0x68A0)
+#define PCIE_SUBCTRL_SC_PCIE0_PCIEPHY_CTRL_ERROR_REG (PCIE_SUBCTRL_BASE + 0x68C0)
+#define PCIE_SUBCTRL_SC_PCIE1_RXEQINPRO_STAT_REG (PCIE_SUBCTRL_BASE + 0x6900)
+#define PCIE_SUBCTRL_SC_PCIE1_LINKINT_RCVRY_STAT_REG (PCIE_SUBCTRL_BASE + 0x6904)
+#define PCIE_SUBCTRL_SC_PCIE1_SYS_STATE0_REG (PCIE_SUBCTRL_BASE + 0x6908)
+#define PCIE_SUBCTRL_SC_PCIE1_SYS_STATE1_REG (PCIE_SUBCTRL_BASE + 0x690C)
+#define PCIE_SUBCTRL_SC_PCIE1_SYS_STATE2_REG (PCIE_SUBCTRL_BASE + 0x6910)
+#define PCIE_SUBCTRL_SC_PCIE1_SYS_STATE3_REG (PCIE_SUBCTRL_BASE + 0x6914)
+#define PCIE_SUBCTRL_SC_PCIE1_SYS_STATE4_REG (PCIE_SUBCTRL_BASE + 0x6918)
+#define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_WR_STS0_REG (PCIE_SUBCTRL_BASE + 0x6980)
+#define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_WR_STS1_REG (PCIE_SUBCTRL_BASE + 0x6984)
+#define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_RD_STS0_REG (PCIE_SUBCTRL_BASE + 0x6990)
+#define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_RD_STS1_REG (PCIE_SUBCTRL_BASE + 0x6994)
+#define PCIE_SUBCTRL_SC_PCIE1_DSIZE_BRG_ECC_ERR_REG (PCIE_SUBCTRL_BASE + 0x69A0)
+#define PCIE_SUBCTRL_SC_PCIE1_PCIEPHY_CTRL_ERROR_REG (PCIE_SUBCTRL_BASE + 0x69C0)
+#define PCIE_SUBCTRL_SC_PCIE2_RXEQINPRO_STAT_REG (PCIE_SUBCTRL_BASE + 0x6A00)
+#define PCIE_SUBCTRL_SC_PCIE2_LINKINT_RCVRY_STAT_REG (PCIE_SUBCTRL_BASE + 0x6A04)
+#define PCIE_SUBCTRL_SC_PCIE2_SYS_STATE0_REG (PCIE_SUBCTRL_BASE + 0x6A08)
+#define PCIE_SUBCTRL_SC_PCIE2_SYS_STATE1_REG (PCIE_SUBCTRL_BASE + 0x6A0C)
+#define PCIE_SUBCTRL_SC_PCIE2_SYS_STATE2_REG (PCIE_SUBCTRL_BASE + 0x6A10)
+#define PCIE_SUBCTRL_SC_PCIE2_SYS_STATE3_REG (PCIE_SUBCTRL_BASE + 0x6A14)
+#define PCIE_SUBCTRL_SC_PCIE2_SYS_STATE4_REG (PCIE_SUBCTRL_BASE + 0x6A18)
+#define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_WR_STS0_REG (PCIE_SUBCTRL_BASE + 0x6A80)
+#define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_WR_STS1_REG (PCIE_SUBCTRL_BASE + 0x6A84)
+#define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_RD_STS0_REG (PCIE_SUBCTRL_BASE + 0x6A90)
+#define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_RD_STS1_REG (PCIE_SUBCTRL_BASE + 0x6A94)
+#define PCIE_SUBCTRL_SC_PCIE2_DSIZE_BRG_ECC_ERR_REG (PCIE_SUBCTRL_BASE + 0x6AA0)
+#define PCIE_SUBCTRL_SC_PCIE2_PCIEPHY_CTRL_ERROR_REG (PCIE_SUBCTRL_BASE + 0x6AC0)
+#define PCIE_SUBCTRL_SC_PCIE3_SYS_STATE0_REG (PCIE_SUBCTRL_BASE + 0x6B08)
+#define PCIE_SUBCTRL_SC_PCIE3_SYS_STATE1_REG (PCIE_SUBCTRL_BASE + 0x6B0C)
+#define PCIE_SUBCTRL_SC_PCIE3_SYS_STATE2_REG (PCIE_SUBCTRL_BASE + 0x6B10)
+#define PCIE_SUBCTRL_SC_PCIE3_SYS_STATE3_REG (PCIE_SUBCTRL_BASE + 0x6B14)
+#define PCIE_SUBCTRL_SC_PCIE3_SYS_STATE4_REG (PCIE_SUBCTRL_BASE + 0x6B18)
+#define PCIE_SUBCTRL_SC_PCIE3_PCIEPHY_CTRL_ERROR_REG (PCIE_SUBCTRL_BASE + 0x6BC0)
+#define PCIE_SUBCTRL_SC_SKEW_ST_0_REG (PCIE_SUBCTRL_BASE + 0x7400)
+#define PCIE_SUBCTRL_SC_SKEW_ST_A_0_REG (PCIE_SUBCTRL_BASE + 0x7500)
+#define PCIE_SUBCTRL_SC_SKEW_ST_A_1_REG (PCIE_SUBCTRL_BASE + 0x7504)
+#define PCIE_SUBCTRL_SC_SKEW_ST_A_2_REG (PCIE_SUBCTRL_BASE + 0x7508)
+#define PCIE_SUBCTRL_SC_SKEW_ST_A_3_REG (PCIE_SUBCTRL_BASE + 0x750C)
+#define PCIE_SUBCTRL_SC_SKEW_ST_B_0_REG (PCIE_SUBCTRL_BASE + 0x7600)
+#define PCIE_SUBCTRL_SC_SKEW_ST_B_1_REG (PCIE_SUBCTRL_BASE + 0x7604)
+#define PCIE_SUBCTRL_SC_SKEW_ST_B_2_REG (PCIE_SUBCTRL_BASE + 0x7608)
+#define PCIE_SUBCTRL_SC_SKEW_ST_B_3_REG (PCIE_SUBCTRL_BASE + 0x760C)
+#define PCIE_SUBCTRL_SC_ECO_RSV0_REG (PCIE_SUBCTRL_BASE + 0x8000)
+#define PCIE_SUBCTRL_SC_ECO_RSV1_REG (PCIE_SUBCTRL_BASE + 0x8004)
+#define PCIE_SUBCTRL_SC_ECO_RSV2_REG (PCIE_SUBCTRL_BASE + 0x8008)
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_pcie0_enb : 1 ;
+ UINT32 clk_pcie0_pipe_enb : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_clk_en;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_pcie0_dsb : 1 ;
+ UINT32 clk_pcie0_pipe_dsb : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_clk_dis;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_pcie1_enb : 1 ;
+ UINT32 clk_pcie1_pipe_enb : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_clk_en;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_pcie1_dsb : 1 ;
+ UINT32 clk_pcie1_pipe_dsb : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_clk_dis;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_pcie2_enb : 1 ;
+ UINT32 clk_pcie2_pipe_enb : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_clk_en;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_pcie2_dsb : 1 ;
+ UINT32 clk_pcie2_pipe_dsb : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_clk_dis;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_sas_enb : 1 ;
+ UINT32 clk_sas_mem_enb : 1 ;
+ UINT32 clk_sas_ahb_enb : 1 ;
+ UINT32 clk_sas_oob_enb : 1 ;
+ UINT32 clk_sas_ch0_rx_enb : 1 ;
+ UINT32 clk_sas_ch1_rx_enb : 1 ;
+ UINT32 clk_sas_ch2_rx_enb : 1 ;
+ UINT32 clk_sas_ch3_rx_enb : 1 ;
+ UINT32 clk_sas_ch4_rx_enb : 1 ;
+ UINT32 clk_sas_ch5_rx_enb : 1 ;
+ UINT32 clk_sas_ch6_rx_enb : 1 ;
+ UINT32 clk_sas_ch7_rx_enb : 1 ;
+ UINT32 clk_sas_ch0_tx_enb : 1 ;
+ UINT32 clk_sas_ch1_tx_enb : 1 ;
+ UINT32 clk_sas_ch2_tx_enb : 1 ;
+ UINT32 clk_sas_ch3_tx_enb : 1 ;
+ UINT32 clk_sas_ch4_tx_enb : 1 ;
+ UINT32 clk_sas_ch5_tx_enb : 1 ;
+ UINT32 clk_sas_ch6_tx_enb : 1 ;
+ UINT32 clk_sas_ch7_tx_enb : 1 ;
+ UINT32 reserved_0 : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sas_clk_en;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_sas_dsb : 1 ;
+ UINT32 clk_sas_mem_dsb : 1 ;
+ UINT32 clk_sas_ahb_dsb : 1 ;
+ UINT32 clk_sas_oob_dsb : 1 ;
+ UINT32 clk_sas_ch0_rx_dsb : 1 ;
+ UINT32 clk_sas_ch1_rx_dsb : 1 ;
+ UINT32 clk_sas_ch2_rx_dsb : 1 ;
+ UINT32 clk_sas_ch3_rx_dsb : 1 ;
+ UINT32 clk_sas_ch4_rx_dsb : 1 ;
+ UINT32 clk_sas_ch5_rx_dsb : 1 ;
+ UINT32 clk_sas_ch6_rx_dsb : 1 ;
+ UINT32 clk_sas_ch7_rx_dsb : 1 ;
+ UINT32 clk_sas_ch0_tx_dsb : 1 ;
+ UINT32 clk_sas_ch1_tx_dsb : 1 ;
+ UINT32 clk_sas_ch2_tx_dsb : 1 ;
+ UINT32 clk_sas_ch3_tx_dsb : 1 ;
+ UINT32 clk_sas_ch4_tx_dsb : 1 ;
+ UINT32 clk_sas_ch5_tx_dsb : 1 ;
+ UINT32 clk_sas_ch6_tx_dsb : 1 ;
+ UINT32 clk_sas_ch7_tx_dsb : 1 ;
+ UINT32 reserved_0 : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sas_clk_dis;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_pcie3_enb : 1 ;
+ UINT32 clk_pcie3_pipe_enb : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie3_clk_en;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_pcie3_dsb : 1 ;
+ UINT32 clk_pcie3_pipe_dsb : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie3_clk_dis;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_its_enb : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_its_clk_en;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_its_dsb : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_its_clk_dis;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_sllc_enb : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sllc_clk_en;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_sllc_dsb : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sllc_clk_dis;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_srst_req : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_reset_req;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_srst_dreq : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_reset_dreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1_srst_req : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_reset_req;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1_srst_dreq : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_reset_dreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2_srst_req : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_reset_req;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2_srst_dreq : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_reset_dreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 sas_srst_req : 1 ;
+ UINT32 sas_oob_srst_req : 1 ;
+ UINT32 sas_ahb_srst_req : 1 ;
+ UINT32 sas_ch0_rx_srst_req : 1 ;
+ UINT32 sas_ch1_rx_srst_req : 1 ;
+ UINT32 sas_ch2_rx_srst_req : 1 ;
+ UINT32 sas_ch3_rx_srst_req : 1 ;
+ UINT32 sas_ch4_rx_srst_req : 1 ;
+ UINT32 sas_ch5_rx_srst_req : 1 ;
+ UINT32 sas_ch6_rx_srst_req : 1 ;
+ UINT32 sas_ch7_rx_srst_req : 1 ;
+ UINT32 sas_ch0_tx_srst_req : 1 ;
+ UINT32 sas_ch1_tx_srst_req : 1 ;
+ UINT32 sas_ch2_tx_srst_req : 1 ;
+ UINT32 sas_ch3_tx_srst_req : 1 ;
+ UINT32 sas_ch4_tx_srst_req : 1 ;
+ UINT32 sas_ch5_tx_srst_req : 1 ;
+ UINT32 sas_ch6_tx_srst_req : 1 ;
+ UINT32 sas_ch7_tx_srst_req : 1 ;
+ UINT32 reserved_0 : 13 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sas_reset_req;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 sas_srst_dreq : 1 ;
+ UINT32 sas_oob_srst_dreq : 1 ;
+ UINT32 sas_ahb_srst_dreq : 1 ;
+ UINT32 sas_ch0_rx_srst_dreq : 1 ;
+ UINT32 sas_ch1_rx_srst_dreq : 1 ;
+ UINT32 sas_ch2_rx_srst_dreq : 1 ;
+ UINT32 sas_ch3_rx_srst_dreq : 1 ;
+ UINT32 sas_ch4_rx_srst_dreq : 1 ;
+ UINT32 sas_ch5_rx_srst_dreq : 1 ;
+ UINT32 sas_ch6_rx_srst_dreq : 1 ;
+ UINT32 sas_ch7_rx_srst_dreq : 1 ;
+ UINT32 sas_ch0_tx_srst_dreq : 1 ;
+ UINT32 sas_ch1_tx_srst_dreq : 1 ;
+ UINT32 sas_ch2_tx_srst_dreq : 1 ;
+ UINT32 sas_ch3_tx_srst_dreq : 1 ;
+ UINT32 sas_ch4_tx_srst_dreq : 1 ;
+ UINT32 sas_ch5_tx_srst_dreq : 1 ;
+ UINT32 sas_ch6_tx_srst_dreq : 1 ;
+ UINT32 sas_ch7_tx_srst_dreq : 1 ;
+ UINT32 reserved_0 : 13 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sas_reset_dreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 mctp0_srst_req : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_mctp0_reset_req;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 mctp0_srst_dreq : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_mctp0_reset_dreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 mctp1_srst_req : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_mctp1_reset_req;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 mctp1_srst_dreq : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_mctp1_reset_dreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 mctp2_srst_req : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_mctp2_reset_req;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 mctp2_srst_dreq : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_mctp2_reset_dreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 sllc_tsvrx0_srst_req : 1 ;
+ UINT32 sllc_tsvrx1_srst_req : 1 ;
+ UINT32 sllc_tsvrx2_srst_req : 1 ;
+ UINT32 sllc_tsvrx3_srst_req : 1 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sllc_tsvrx_reset_req;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 sllc_tsvrx0_srst_dreq : 1 ;
+ UINT32 sllc_tsvrx1_srst_dreq : 1 ;
+ UINT32 sllc_tsvrx2_srst_dreq : 1 ;
+ UINT32 sllc_tsvrx3_srst_dreq : 1 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sllc_tsvrx_reset_dreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_hilink_pcs_lane0_srst_req : 1 ;
+ UINT32 pcie0_hilink_pcs_lane1_srst_req : 1 ;
+ UINT32 pcie0_hilink_pcs_lane2_srst_req : 1 ;
+ UINT32 pcie0_hilink_pcs_lane3_srst_req : 1 ;
+ UINT32 pcie0_hilink_pcs_lane4_srst_req : 1 ;
+ UINT32 pcie0_hilink_pcs_lane5_srst_req : 1 ;
+ UINT32 pcie0_hilink_pcs_lane6_srst_req : 1 ;
+ UINT32 pcie0_hilink_pcs_lane7_srst_req : 1 ;
+ UINT32 pcie1_hilink_pcs_lane0_srst_req : 1 ;
+ UINT32 pcie1_hilink_pcs_lane1_srst_req : 1 ;
+ UINT32 pcie1_hilink_pcs_lane2_srst_req : 1 ;
+ UINT32 pcie1_hilink_pcs_lane3_srst_req : 1 ;
+ UINT32 pcie1_hilink_pcs_lane4_srst_req : 1 ;
+ UINT32 pcie1_hilink_pcs_lane5_srst_req : 1 ;
+ UINT32 pcie1_hilink_pcs_lane6_srst_req : 1 ;
+ UINT32 pcie1_hilink_pcs_lane7_srst_req : 1 ;
+ UINT32 pcie2_hilink_pcs_lane0_srst_req : 1 ;
+ UINT32 pcie2_hilink_pcs_lane1_srst_req : 1 ;
+ UINT32 pcie2_hilink_pcs_lane2_srst_req : 1 ;
+ UINT32 pcie2_hilink_pcs_lane3_srst_req : 1 ;
+ UINT32 pcie2_hilink_pcs_lane4_srst_req : 1 ;
+ UINT32 pcie2_hilink_pcs_lane5_srst_req : 1 ;
+ UINT32 pcie2_hilink_pcs_lane6_srst_req : 1 ;
+ UINT32 pcie2_hilink_pcs_lane7_srst_req : 1 ;
+ UINT32 pcie3_hilink_pcs_lane0_srst_req : 1 ;
+ UINT32 pcie3_hilink_pcs_lane1_srst_req : 1 ;
+ UINT32 pcie3_hilink_pcs_lane2_srst_req : 1 ;
+ UINT32 pcie3_hilink_pcs_lane3_srst_req : 1 ;
+ UINT32 pcie3_hilink_pcs_lane4_srst_req : 1 ;
+ UINT32 pcie3_hilink_pcs_lane5_srst_req : 1 ;
+ UINT32 pcie3_hilink_pcs_lane6_srst_req : 1 ;
+ UINT32 pcie3_hilink_pcs_lane7_srst_req : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie_hilink_pcs_reset_req;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_hilink_pcs_lane0_srst_dreq : 1 ;
+ UINT32 pcie0_hilink_pcs_lane1_srst_dreq : 1 ;
+ UINT32 pcie0_hilink_pcs_lane2_srst_dreq : 1 ;
+ UINT32 pcie0_hilink_pcs_lane3_srst_dreq : 1 ;
+ UINT32 pcie0_hilink_pcs_lane4_srst_dreq : 1 ;
+ UINT32 pcie0_hilink_pcs_lane5_srst_dreq : 1 ;
+ UINT32 pcie0_hilink_pcs_lane6_srst_dreq : 1 ;
+ UINT32 pcie0_hilink_pcs_lane7_srst_dreq : 1 ;
+ UINT32 pcie1_hilink_pcs_lane0_srst_dreq : 1 ;
+ UINT32 pcie1_hilink_pcs_lane1_srst_dreq : 1 ;
+ UINT32 pcie1_hilink_pcs_lane2_srst_dreq : 1 ;
+ UINT32 pcie1_hilink_pcs_lane3_srst_dreq : 1 ;
+ UINT32 pcie1_hilink_pcs_lane4_srst_dreq : 1 ;
+ UINT32 pcie1_hilink_pcs_lane5_srst_dreq : 1 ;
+ UINT32 pcie1_hilink_pcs_lane6_srst_dreq : 1 ;
+ UINT32 pcie1_hilink_pcs_lane7_srst_dreq : 1 ;
+ UINT32 pcie2_hilink_pcs_lane0_srst_dreq : 1 ;
+ UINT32 pcie2_hilink_pcs_lane1_srst_dreq : 1 ;
+ UINT32 pcie2_hilink_pcs_lane2_srst_dreq : 1 ;
+ UINT32 pcie2_hilink_pcs_lane3_srst_dreq : 1 ;
+ UINT32 pcie2_hilink_pcs_lane4_srst_dreq : 1 ;
+ UINT32 pcie2_hilink_pcs_lane5_srst_dreq : 1 ;
+ UINT32 pcie2_hilink_pcs_lane6_srst_dreq : 1 ;
+ UINT32 pcie2_hilink_pcs_lane7_srst_dreq : 1 ;
+ UINT32 pcie3_hilink_pcs_lane0_srst_dreq : 1 ;
+ UINT32 pcie3_hilink_pcs_lane1_srst_dreq : 1 ;
+ UINT32 pcie3_hilink_pcs_lane2_srst_dreq : 1 ;
+ UINT32 pcie3_hilink_pcs_lane3_srst_dreq : 1 ;
+ UINT32 pcie3_hilink_pcs_lane4_srst_dreq : 1 ;
+ UINT32 pcie3_hilink_pcs_lane5_srst_dreq : 1 ;
+ UINT32 pcie3_hilink_pcs_lane6_srst_dreq : 1 ;
+ UINT32 pcie3_hilink_pcs_lane7_srst_dreq : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie_hilink_pcs_reset_dreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie3_srst_req : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie3_reset_req;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie3_srst_dreq : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie3_reset_dreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 mctp3_srst_req : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_mctp3_reset_req;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 mctp3_srst_dreq : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_mctp3_reset_dreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 its_srst_req : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_its_reset_req;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 its_srst_dreq : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_its_reset_dreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 sllc_srst_req : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sllc_reset_req;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 sllc_srst_dreq : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sllc_reset_dreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_pcs_local_srst_req : 1 ;
+ UINT32 pcie1_pcs_local_srst_req : 1 ;
+ UINT32 pcie2_pcs_local_srst_req : 1 ;
+ UINT32 pcie3_pcs_local_srst_req : 1 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcs_local_reset_req;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_pcs_local_srst_dreq : 1 ;
+ UINT32 pcie1_pcs_local_srst_dreq : 1 ;
+ UINT32 pcie2_pcs_local_srst_dreq : 1 ;
+ UINT32 pcie3_pcs_local_srst_dreq : 1 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcs_local_reset_dreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 dispatch_daw_en : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_disp_daw_en;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 daw_array0_did : 3 ;
+ UINT32 daw_array0_size : 5 ;
+ UINT32 daw_array0_sync : 1 ;
+ UINT32 reserved_0 : 4 ;
+ UINT32 daw_array0_addr : 19 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_dispatch_daw_array0;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 daw_array1_did : 3 ;
+ UINT32 daw_array1_size : 5 ;
+ UINT32 daw_array1_sync : 1 ;
+ UINT32 reserved_0 : 4 ;
+ UINT32 daw_array1_addr : 19 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_dispatch_daw_array1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 daw_array2_did : 3 ;
+ UINT32 daw_array2_size : 5 ;
+ UINT32 daw_array2_sync : 1 ;
+ UINT32 reserved_0 : 4 ;
+ UINT32 daw_array2_addr : 19 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_dispatch_daw_array2;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 daw_array3_did : 3 ;
+ UINT32 daw_array3_size : 5 ;
+ UINT32 daw_array3_sync : 1 ;
+ UINT32 reserved_0 : 4 ;
+ UINT32 daw_array3_addr : 19 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_dispatch_daw_array3;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 daw_array4_did : 3 ;
+ UINT32 daw_array4_size : 5 ;
+ UINT32 daw_array4_sync : 1 ;
+ UINT32 reserved_0 : 4 ;
+ UINT32 daw_array4_addr : 19 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_dispatch_daw_array4;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 daw_array5_did : 3 ;
+ UINT32 daw_array5_size : 5 ;
+ UINT32 daw_array5_sync : 1 ;
+ UINT32 reserved_0 : 4 ;
+ UINT32 daw_array5_addr : 19 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_dispatch_daw_array5;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 daw_array6_did : 3 ;
+ UINT32 daw_array6_size : 5 ;
+ UINT32 daw_array6_sync : 1 ;
+ UINT32 reserved_0 : 4 ;
+ UINT32 daw_array6_addr : 19 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_dispatch_daw_array6;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 daw_array7_did : 3 ;
+ UINT32 daw_array7_size : 5 ;
+ UINT32 daw_array7_sync : 1 ;
+ UINT32 reserved_0 : 4 ;
+ UINT32 daw_array7_addr : 19 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_dispatch_daw_array7;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 retry_num_limit : 16 ;
+ UINT32 retry_en : 1 ;
+ UINT32 reserved_0 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_dispatch_retry_control;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 intmask : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_dispatch_intmask;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 rawint : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_dispatch_rawint;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 intsts : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_dispatch_intstat;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 intclr : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_dispatch_intclr;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 err_opcode : 5 ;
+ UINT32 err_addr : 17 ;
+ UINT32 reserved_0 : 10 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_dispatch_errstat;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 sys_remap_vld : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_remap_ctrl;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 mux_sel_fte : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_fte_mux_ctrl;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink0_mux_sel : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink0_mux_ctrl;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_mux_sel : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_mux_ctrl;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink2_mux_sel : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink2_mux_ctrl;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_mux_sel : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_mux_ctrl;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_ahb_mux_sel : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_ahb_mux_ctrl;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink2_ahb_mux_sel : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink2_ahb_mux_ctrl;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_ahb_mux_sel : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_ahb_mux_ctrl;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_lrstb_mux_sel : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_lrstb_mux_ctrl;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink6_lrstb_mux_sel : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink6_lrstb_mux_ctrl;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink0_ss_refclk0_x2s : 2 ;
+ UINT32 hilink0_ss_refclk0_x2n : 2 ;
+ UINT32 hilink0_ss_refclk0_x2e : 2 ;
+ UINT32 hilink0_ss_refclk0_x2w : 2 ;
+ UINT32 hilink0_ss_refclk1_x2s : 2 ;
+ UINT32 hilink0_ss_refclk1_x2n : 2 ;
+ UINT32 hilink0_ss_refclk1_x2e : 2 ;
+ UINT32 hilink0_ss_refclk1_x2w : 2 ;
+ UINT32 reserved_0 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink0_macro_ss_refclk;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink0_cs_refclk0_dirsel0 : 2 ;
+ UINT32 hilink0_cs_refclk0_dirsel1 : 2 ;
+ UINT32 hilink0_cs_refclk0_dirsel2 : 2 ;
+ UINT32 hilink0_cs_refclk0_dirsel3 : 2 ;
+ UINT32 hilink0_cs_refclk0_dirsel4 : 2 ;
+ UINT32 hilink0_cs_refclk1_dirsel0 : 2 ;
+ UINT32 hilink0_cs_refclk1_dirsel1 : 2 ;
+ UINT32 hilink0_cs_refclk1_dirsel2 : 2 ;
+ UINT32 hilink0_cs_refclk1_dirsel3 : 2 ;
+ UINT32 hilink0_cs_refclk1_dirsel4 : 2 ;
+ UINT32 reserved_0 : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink0_macro_cs_refclk_dirsel;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink0_lifeclk2dig_sel : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink0_macro_lifeclk2dig_sel;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink0_core_clk_selext : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink0_macro_core_clk_selext;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink0_core_clk_sel : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink0_macro_core_clk_sel;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink0_ctrl_bus_mode : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink0_macro_ctrl_bus_mode;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink0_macropwrdb : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink0_macro_macropwrdb;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink0_grstb : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink0_macro_grstb;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink0_bit_slip : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink0_macro_bit_slip;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink0_lrstb : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink0_macro_lrstb;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_ss_refclk0_x2s : 2 ;
+ UINT32 hilink1_ss_refclk0_x2n : 2 ;
+ UINT32 hilink1_ss_refclk0_x2e : 2 ;
+ UINT32 hilink1_ss_refclk0_x2w : 2 ;
+ UINT32 hilink1_ss_refclk1_x2s : 2 ;
+ UINT32 hilink1_ss_refclk1_x2n : 2 ;
+ UINT32 hilink1_ss_refclk1_x2e : 2 ;
+ UINT32 hilink1_ss_refclk1_x2w : 2 ;
+ UINT32 reserved_0 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_macro_ss_refclk;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_cs_refclk0_dirsel0 : 2 ;
+ UINT32 hilink1_cs_refclk0_dirsel1 : 2 ;
+ UINT32 hilink1_cs_refclk0_dirsel2 : 2 ;
+ UINT32 hilink1_cs_refclk0_dirsel3 : 2 ;
+ UINT32 hilink1_cs_refclk0_dirsel4 : 2 ;
+ UINT32 hilink1_cs_refclk1_dirsel0 : 2 ;
+ UINT32 hilink1_cs_refclk1_dirsel1 : 2 ;
+ UINT32 hilink1_cs_refclk1_dirsel2 : 2 ;
+ UINT32 hilink1_cs_refclk1_dirsel3 : 2 ;
+ UINT32 hilink1_cs_refclk1_dirsel4 : 2 ;
+ UINT32 reserved_0 : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_macro_cs_refclk_dirsel;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_lifeclk2dig_sel : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_macro_lifeclk2dig_sel;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_core_clk_selext : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_macro_core_clk_selext;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_core_clk_sel : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_macro_core_clk_sel;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_ctrl_bus_mode : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_macro_ctrl_bus_mode;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_macropwrdb : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_macro_macropwrdb;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_grstb : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_macro_grstb;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_bit_slip : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_macro_bit_slip;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_lrstb : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_macro_lrstb;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_ss_refclk0_x2s : 2 ;
+ UINT32 hilink5_ss_refclk0_x2n : 2 ;
+ UINT32 hilink5_ss_refclk0_x2e : 2 ;
+ UINT32 hilink5_ss_refclk0_x2w : 2 ;
+ UINT32 hilink5_ss_refclk1_x2s : 2 ;
+ UINT32 hilink5_ss_refclk1_x2n : 2 ;
+ UINT32 hilink5_ss_refclk1_x2e : 2 ;
+ UINT32 hilink5_ss_refclk1_x2w : 2 ;
+ UINT32 reserved_0 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_macro_ss_refclk;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_cs_refclk0_dirsel0 : 2 ;
+ UINT32 hilink5_cs_refclk0_dirsel1 : 2 ;
+ UINT32 hilink5_cs_refclk0_dirsel2 : 2 ;
+ UINT32 hilink5_cs_refclk0_dirsel3 : 2 ;
+ UINT32 hilink5_cs_refclk0_dirsel4 : 2 ;
+ UINT32 hilink5_cs_refclk1_dirsel0 : 2 ;
+ UINT32 hilink5_cs_refclk1_dirsel1 : 2 ;
+ UINT32 hilink5_cs_refclk1_dirsel2 : 2 ;
+ UINT32 hilink5_cs_refclk1_dirsel3 : 2 ;
+ UINT32 hilink5_cs_refclk1_dirsel4 : 2 ;
+ UINT32 reserved_0 : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_macro_cs_refclk_dirsel;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_lifeclk2dig_sel : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_macro_lifeclk2dig_sel;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_core_clk_selext : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_macro_core_clk_selext;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_core_clk_sel : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_macro_core_clk_sel;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_ctrl_bus_mode : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_macro_ctrl_bus_mode;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_macropwrdb : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_macro_macropwrdb;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_grstb : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_macro_grstb;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_bit_slip : 4 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_macro_bit_slip;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_lrstb : 4 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_macro_lrstb;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink6_ss_refclk0_x2s : 2 ;
+ UINT32 hilink6_ss_refclk0_x2n : 2 ;
+ UINT32 hilink6_ss_refclk0_x2e : 2 ;
+ UINT32 hilink6_ss_refclk0_x2w : 2 ;
+ UINT32 hilink6_ss_refclk1_x2s : 2 ;
+ UINT32 hilink6_ss_refclk1_x2n : 2 ;
+ UINT32 hilink6_ss_refclk1_x2e : 2 ;
+ UINT32 hilink6_ss_refclk1_x2w : 2 ;
+ UINT32 reserved_0 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink6_macro_ss_refclk;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink6_cs_refclk0_dirsel0 : 2 ;
+ UINT32 hilink6_cs_refclk0_dirsel1 : 2 ;
+ UINT32 hilink6_cs_refclk0_dirsel2 : 2 ;
+ UINT32 hilink6_cs_refclk0_dirsel3 : 2 ;
+ UINT32 hilink6_cs_refclk0_dirsel4 : 2 ;
+ UINT32 hilink6_cs_refclk1_dirsel0 : 2 ;
+ UINT32 hilink6_cs_refclk1_dirsel1 : 2 ;
+ UINT32 hilink6_cs_refclk1_dirsel2 : 2 ;
+ UINT32 hilink6_cs_refclk1_dirsel3 : 2 ;
+ UINT32 hilink6_cs_refclk1_dirsel4 : 2 ;
+ UINT32 reserved_0 : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink6_macro_cs_refclk_dirsel;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink6_lifeclk2dig_sel : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink6_macro_lifeclk2dig_sel;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink6_core_clk_selext : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink6_macro_core_clk_selext;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink6_core_clk_sel : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink6_macro_core_clk_sel;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink6_ctrl_bus_mode : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink6_macro_ctrl_bus_mode;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink6_macropwrdb : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink6_macro_macropwrdb;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink6_grstb : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink6_macro_grstb;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink6_bit_slip : 4 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink6_macro_bit_slip;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink6_lrstb : 4 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink6_macro_lrstb;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_phy_clk_req_n : 1 ;
+ UINT32 pcie0_apb_cfg_sel : 2 ;
+ UINT32 reserved_0 : 29 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_clkreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_cfg_max_wr_trans : 6 ;
+ UINT32 reserved_0 : 2 ;
+ UINT32 pcie0_wr_rate_limit : 4 ;
+ UINT32 pcie0_ctrl_lat_stat_wr_en : 1 ;
+ UINT32 reserved_1 : 3 ;
+ UINT32 pcie0_en_device_wr_ooo : 1 ;
+ UINT32 reserved_2 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_axi_mstr_ooo_wr_cfg;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_cfg_max_rd_trans : 6 ;
+ UINT32 reserved_0 : 2 ;
+ UINT32 pcie0_rd_rate_limit : 4 ;
+ UINT32 pcie0_ctrl_lat_stat_rd_en : 1 ;
+ UINT32 reserved_1 : 3 ;
+ UINT32 pcie0_en_device_rd_ooo : 1 ;
+ UINT32 reserved_2 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_axi_mstr_ooo_rd_cfg;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1hilink_phy_clk_req_n : 1 ;
+ UINT32 pcie1vsemi_phy_clk_req_n : 1 ;
+ UINT32 pcie1_apb_cfg_sel : 2 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_clkreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1_cfg_max_wr_trans : 6 ;
+ UINT32 reserved_0 : 2 ;
+ UINT32 pcie1_wr_rate_limit : 4 ;
+ UINT32 pcie1_ctrl_lat_stat_wr_en : 1 ;
+ UINT32 reserved_1 : 3 ;
+ UINT32 pcie1_en_device_wr_ooo : 1 ;
+ UINT32 reserved_2 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_axi_mstr_ooo_wr_cfg;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1_cfg_max_rd_trans : 6 ;
+ UINT32 reserved_0 : 2 ;
+ UINT32 pcie1_rd_rate_limit : 4 ;
+ UINT32 pcie1_ctrl_lat_stat_rd_en : 1 ;
+ UINT32 reserved_1 : 3 ;
+ UINT32 pcie1_en_device_rd_ooo : 1 ;
+ UINT32 reserved_2 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_axi_mstr_ooo_rd_cfg;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2hilink_phy_clk_req_n : 1 ;
+ UINT32 pcie2vsemi_phy_clk_req_n : 1 ;
+ UINT32 pcie2_apb_cfg_sel : 2 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_clkreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2_cfg_max_wr_trans : 6 ;
+ UINT32 reserved_0 : 2 ;
+ UINT32 pcie2_wr_rate_limit : 4 ;
+ UINT32 pcie2_ctrl_lat_stat_wr_en : 1 ;
+ UINT32 reserved_1 : 3 ;
+ UINT32 pcie2_en_device_wr_ooo : 1 ;
+ UINT32 reserved_2 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_axi_mstr_ooo_wr_cfg;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2_cfg_max_rd_trans : 6 ;
+ UINT32 reserved_0 : 2 ;
+ UINT32 pcie2_rd_rate_limit : 4 ;
+ UINT32 pcie2_ctrl_lat_stat_rd_en : 1 ;
+ UINT32 reserved_1 : 3 ;
+ UINT32 pcie2_en_device_rd_ooo : 1 ;
+ UINT32 reserved_2 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_axi_mstr_ooo_rd_cfg;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie3_phy_clk_req_n : 1 ;
+ UINT32 pcie3_apb_cfg_sel : 2 ;
+ UINT32 reserved_0 : 29 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie3_clkreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 ctrl_rfs_smmu : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_smmu_mem_ctrl0;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 tsel_hc_smmu : 3 ;
+ UINT32 reserved_0 : 29 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_smmu_mem_ctrl1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 test_hc_smmu : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_smmu_mem_ctrl2;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 ctrl_rft_sllc0 : 10 ;
+ UINT32 reserved_0 : 22 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sllc0_mem_ctrl;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 ctrl_rfs_sas : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sas_mem_ctrl;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 ctrl_rft_pcie : 10 ;
+ UINT32 reserved_0 : 22 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie_mem_ctrl0;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 ctrl_rashsd_pcie : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie_mem_ctrl1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 ctrl_rfs_pcie : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie_mem_ctrl2;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_en : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_common_0;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_addr_offset : 5 ;
+ UINT32 reserved_0 : 27 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_common_1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_config_in : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_common_2;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_bypass_a : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_a_0;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_config_in_a : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_a_1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_out_delay_sel_a : 2 ;
+ UINT32 skew_in_delay_sel_a : 2 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_a_2;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_sel_a_1 : 1 ;
+ UINT32 skew_sel_a_0 : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_a_3;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_update_en_a : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_a_4;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_varible_set_a : 16 ;
+ UINT32 reserved_0 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_a_5;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_dcell_set_a_h : 4 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_a_7;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_sel_osc_a : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_a_8;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_bypass_b : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_b_0;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_config_in_b : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_b_1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_out_delay_sel_b : 2 ;
+ UINT32 skew_in_delay_sel_b : 2 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_b_2;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_sel_b_1 : 1 ;
+ UINT32 skew_sel_b_0 : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_b_3;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_update_en_b : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_b_4;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_varible_set_b : 16 ;
+ UINT32 reserved_0 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_b_5;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_dcell_set_b_h : 4 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_b_7;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_sel_osc_b : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_b_8;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_pcie0_st : 1 ;
+ UINT32 clk_pcie0_pipe_st : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_clk_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_pcie1_st : 1 ;
+ UINT32 clk_pcie1_pipe_st : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_clk_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_pcie2_st : 1 ;
+ UINT32 clk_pcie2_pipe_st : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_clk_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_sas_st : 1 ;
+ UINT32 clk_sas_mem_st : 1 ;
+ UINT32 clk_sas_ahb_st : 1 ;
+ UINT32 clk_sas_oob_st : 1 ;
+ UINT32 clk_sas_ch0_rx_st : 1 ;
+ UINT32 clk_sas_ch1_rx_st : 1 ;
+ UINT32 clk_sas_ch2_rx_st : 1 ;
+ UINT32 clk_sas_ch3_rx_st : 1 ;
+ UINT32 clk_sas_ch4_rx_st : 1 ;
+ UINT32 clk_sas_ch5_rx_st : 1 ;
+ UINT32 clk_sas_ch6_rx_st : 1 ;
+ UINT32 clk_sas_ch7_rx_st : 1 ;
+ UINT32 clk_sas_ch0_tx_st : 1 ;
+ UINT32 clk_sas_ch1_tx_st : 1 ;
+ UINT32 clk_sas_ch2_tx_st : 1 ;
+ UINT32 clk_sas_ch3_tx_st : 1 ;
+ UINT32 clk_sas_ch4_tx_st : 1 ;
+ UINT32 clk_sas_ch5_tx_st : 1 ;
+ UINT32 clk_sas_ch6_tx_st : 1 ;
+ UINT32 clk_sas_ch7_tx_st : 1 ;
+ UINT32 reserved_0 : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sas_clk_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_pcie3_st : 1 ;
+ UINT32 clk_pcie3_pipe_st : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie3_clk_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_its_st : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_its_clk_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_sllc_st : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sllc_clk_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_srst_st : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_reset_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1_srst_st : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_reset_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2_srst_st : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_reset_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 sas_srst_st : 1 ;
+ UINT32 sas_oob_srst_st : 1 ;
+ UINT32 sas_ahb_srst_st : 1 ;
+ UINT32 sas_ch0_rx_srst_st : 1 ;
+ UINT32 sas_ch1_rx_srst_st : 1 ;
+ UINT32 sas_ch2_rx_srst_st : 1 ;
+ UINT32 sas_ch3_rx_srst_st : 1 ;
+ UINT32 sas_ch4_rx_srst_st : 1 ;
+ UINT32 sas_ch5_rx_srst_st : 1 ;
+ UINT32 sas_ch6_rx_srst_st : 1 ;
+ UINT32 sas_ch7_rx_srst_st : 1 ;
+ UINT32 sas_ch0_tx_srst_st : 1 ;
+ UINT32 sas_ch1_tx_srst_st : 1 ;
+ UINT32 sas_ch2_tx_srst_st : 1 ;
+ UINT32 sas_ch3_tx_srst_st : 1 ;
+ UINT32 sas_ch4_tx_srst_st : 1 ;
+ UINT32 sas_ch5_tx_srst_st : 1 ;
+ UINT32 sas_ch6_tx_srst_st : 1 ;
+ UINT32 sas_ch7_tx_srst_st : 1 ;
+ UINT32 reserved_0 : 13 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sas_reset_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 mctp0_srst_st : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_mctp0_reset_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 mctp1_srst_st : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_mctp1_reset_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 mctp2_srst_st : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_mctp2_reset_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 sllc_tsvrx0_srst_st : 1 ;
+ UINT32 sllc_tsvrx1_srst_st : 1 ;
+ UINT32 sllc_tsvrx2_srst_st : 1 ;
+ UINT32 sllc_tsvrx3_srst_st : 1 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sllc_tsvrx_reset_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_hilink_pcs_lane0_srst_st : 1 ;
+ UINT32 pcie0_hilink_pcs_lane1_srst_st : 1 ;
+ UINT32 pcie0_hilink_pcs_lane2_srst_st : 1 ;
+ UINT32 pcie0_hilink_pcs_lane3_srst_st : 1 ;
+ UINT32 pcie0_hilink_pcs_lane4_srst_st : 1 ;
+ UINT32 pcie0_hilink_pcs_lane5_srst_st : 1 ;
+ UINT32 pcie0_hilink_pcs_lane6_srst_st : 1 ;
+ UINT32 pcie0_hilink_pcs_lane7_srst_st : 1 ;
+ UINT32 pcie1_hilink_pcs_lane0_srst_st : 1 ;
+ UINT32 pcie1_hilink_pcs_lane1_srst_st : 1 ;
+ UINT32 pcie1_hilink_pcs_lane2_srst_st : 1 ;
+ UINT32 pcie1_hilink_pcs_lane3_srst_st : 1 ;
+ UINT32 pcie1_hilink_pcs_lane4_srst_st : 1 ;
+ UINT32 pcie1_hilink_pcs_lane5_srst_st : 1 ;
+ UINT32 pcie1_hilink_pcs_lane6_srst_st : 1 ;
+ UINT32 pcie1_hilink_pcs_lane7_srst_st : 1 ;
+ UINT32 pcie2_hilink_pcs_lane0_srst_st : 1 ;
+ UINT32 pcie2_hilink_pcs_lane1_srst_st : 1 ;
+ UINT32 pcie2_hilink_pcs_lane2_srst_st : 1 ;
+ UINT32 pcie2_hilink_pcs_lane3_srst_st : 1 ;
+ UINT32 pcie2_hilink_pcs_lane4_srst_st : 1 ;
+ UINT32 pcie2_hilink_pcs_lane5_srst_st : 1 ;
+ UINT32 pcie2_hilink_pcs_lane6_srst_st : 1 ;
+ UINT32 pcie2_hilink_pcs_lane7_srst_st : 1 ;
+ UINT32 pcie3_hilink_pcs_lane0_srst_st : 1 ;
+ UINT32 pcie3_hilink_pcs_lane1_srst_st : 1 ;
+ UINT32 pcie3_hilink_pcs_lane2_srst_st : 1 ;
+ UINT32 pcie3_hilink_pcs_lane3_srst_st : 1 ;
+ UINT32 pcie3_hilink_pcs_lane4_srst_st : 1 ;
+ UINT32 pcie3_hilink_pcs_lane5_srst_st : 1 ;
+ UINT32 pcie3_hilink_pcs_lane6_srst_st : 1 ;
+ UINT32 pcie3_hilink_pcs_lane7_srst_st : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie_hilink_pcs_reset_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie3_srst_st : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie3_reset_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 mctp3_srst_st : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_mctp3_reset_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 its_srst_st : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_its_reset_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 sllc_srst_st : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sllc_reset_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_pcs_local_srst_st : 1 ;
+ UINT32 pcie1_pcs_local_srst_st : 1 ;
+ UINT32 pcie2_pcs_local_srst_st : 1 ;
+ UINT32 pcie3_pcs_local_srst_st : 1 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcs_local_reset_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink0_plloutoflock : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink0_macro_plloutoflock;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink0_prbs_err : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink0_macro_prbs_err;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink0_los : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink0_macro_los;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_plloutoflock : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_macro_plloutoflock;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_prbs_err : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_macro_prbs_err;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_los : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_macro_los;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_plloutoflock : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_macro_plloutoflock;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_prbs_err : 4 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_macro_prbs_err;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_los : 4 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_macro_los;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink6_plloutoflock : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink6_macro_plloutoflock;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink6_prbs_err : 4 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink6_macro_prbs_err;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink6_los : 4 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink6_macro_los;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_mac_phy_rxeqinprogress : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_rxeqinpro_stat;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_cfg_link_eq_req_int : 1 ;
+ UINT32 pcie0_xmlh_ltssm_state_rcvry_eq : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_linkint_rcvry_stat;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_gm_cmposer_lookup_err : 1 ;
+ UINT32 pcie0_radmx_cmposer_lookup_err : 1 ;
+ UINT32 pcie0_pm_xtlh_block_tlp : 1 ;
+ UINT32 pcie0_cfg_mem_space_en : 1 ;
+ UINT32 pcie0_cfg_rcb : 1 ;
+ UINT32 pcie0_rdlh_link_up : 1 ;
+ UINT32 pcie0_pm_curnt_state : 3 ;
+ UINT32 pcie0_cfg_aer_rc_err_int : 1 ;
+ UINT32 pcie0_cfg_aer_int_msg_num : 5 ;
+ UINT32 pcie0_xmlh_link_up : 1 ;
+ UINT32 pcie0_wake : 1 ;
+ UINT32 pcie0_cfg_eml_control : 1 ;
+ UINT32 pcie0_hp_pme : 1 ;
+ UINT32 pcie0_hp_int : 1 ;
+ UINT32 pcie0_hp_msi : 1 ;
+ UINT32 pcie0_pm_status : 1 ;
+ UINT32 pcie0_ref_clk_req_n : 1 ;
+ UINT32 pcie0_p2_exit_reg : 1 ;
+ UINT32 pcie0_radm_msg_req_id_low : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+}U_SC_PCIE0_SYS_STATE0;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_axi_parity_errs_reg : 4 ;
+ UINT32 pcie0_app_parity_errs_reg : 3 ;
+ UINT32 pcie0_pm_linkst_in_l1 : 1 ;
+ UINT32 pcie0_pm_linkst_in_l2 : 1 ;
+ UINT32 pcie0_pm_linkst_l2_exit : 1 ;
+ UINT32 pcie0_mac_phy_power_down : 2 ;
+ UINT32 pcie0_radm_correctabl_err_reg : 1 ;
+ UINT32 pcie0_radm_nonfatal_err_reg : 1 ;
+ UINT32 pcie0_radm_fatal_err_reg : 1 ;
+ UINT32 pcie0_radm_pm_to_pme_reg : 1 ;
+ UINT32 pcie0_radm_pm_to_ack_reg : 1 ;
+ UINT32 pcie0_radm_cpl_timeout_reg : 1 ;
+ UINT32 pcie0_radm_msg_unlock_reg : 1 ;
+ UINT32 pcie0_cfg_pme_msi_reg : 1 ;
+ UINT32 pcie0_bridge_flush_not_reg : 1 ;
+ UINT32 pcie0_link_req_rst_not_reg : 1 ;
+ UINT32 pcie0_cfg_aer_rc_err_msi : 1 ;
+ UINT32 pcie0_cfg_sys_err_rc : 1 ;
+ UINT32 pcie0_radm_msg_req_id_high : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} U_SC_PCIE0_SYS_STATE1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_ltssm_state : 6 ;
+ UINT32 pcie0_mac_phy_rate : 2 ;
+ UINT32 pcie0_slv_err_int : 1 ;
+ UINT32 pcie0_retry_sram_addr : 10 ;
+ UINT32 pcie0_mstr_rresp_int : 1 ;
+ UINT32 pcie0_mstr_bresp_int : 1 ;
+ UINT32 pcie0_radm_inta_reg : 1 ;
+ UINT32 pcie0_radm_intb_reg : 1 ;
+ UINT32 pcie0_radm_intc_reg : 1 ;
+ UINT32 pcie0_radm_intd_reg : 1 ;
+ UINT32 pcie0_cfg_pme_int_reg : 1 ;
+ UINT32 pcie0_radm_vendor_msg_reg : 1 ;
+ UINT32 pcie0_bridge_flush_not : 1 ;
+ UINT32 pcie0_link_req_rst_not : 1 ;
+ UINT32 reserved_0 : 3 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} U_SC_PCIE0_SYS_STATE4;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_curr_wr_latency : 16 ;
+ UINT32 pcie0_curr_wr_port_sts : 1 ;
+ UINT32 reserved_0 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_axi_mstr_ooo_wr_sts1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_curr_rd_latency : 16 ;
+ UINT32 pcie0_curr_rd_port_sts : 1 ;
+ UINT32 reserved_0 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_axi_mstr_ooo_rd_sts1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_rob_ecc_err_detect : 1 ;
+ UINT32 pcie0_rob_ecc_err_multpl : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_dsize_brg_ecc_err;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_pciephy_ctrl_error : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_pciephy_ctrl_error;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1_mac_phy_rxeqinprogress : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_rxeqinpro_stat;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1_cfg_link_eq_req_int : 1 ;
+ UINT32 pcie1_xmlh_ltssm_state_rcvry_eq : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_linkint_rcvry_stat;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1_gm_cmposer_lookup_err : 1 ;
+ UINT32 pcie1_radmx_cmposer_lookup_err : 1 ;
+ UINT32 pcie1_pm_xtlh_block_tlp : 1 ;
+ UINT32 pcie1_cfg_mem_space_en : 1 ;
+ UINT32 pcie1_cfg_rcb : 1 ;
+ UINT32 pcie1_rdlh_link_up : 1 ;
+ UINT32 pcie1_pm_curnt_state : 3 ;
+ UINT32 pcie1_cfg_aer_rc_err_int : 1 ;
+ UINT32 pcie1_cfg_aer_int_msg_num : 5 ;
+ UINT32 pcie1_xmlh_link_up : 1 ;
+ UINT32 pcie1_wake : 1 ;
+ UINT32 pcie1_cfg_eml_control : 1 ;
+ UINT32 pcie1_hp_pme : 1 ;
+ UINT32 pcie1_hp_int : 1 ;
+ UINT32 pcie1_hp_msi : 1 ;
+ UINT32 pcie1_pm_status : 1 ;
+ UINT32 pcie1_ref_clk_req_n : 1 ;
+ UINT32 pcie1_p2_exit_reg : 1 ;
+ UINT32 pcie1_radm_msg_req_id_low : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_sys_state0;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1_axi_parity_errs_reg : 4 ;
+ UINT32 pcie1_app_parity_errs_reg : 3 ;
+ UINT32 pcie1_pm_linkst_in_l1 : 1 ;
+ UINT32 pcie1_pm_linkst_in_l2 : 1 ;
+ UINT32 pcie1_pm_linkst_l2_exit : 1 ;
+ UINT32 pcie1_mac_phy_power_down : 2 ;
+ UINT32 pcie1_radm_correctabl_err_reg : 1 ;
+ UINT32 pcie1_radm_nonfatal_err_reg : 1 ;
+ UINT32 pcie1_radm_fatal_err_reg : 1 ;
+ UINT32 pcie1_radm_pm_to_pme_reg : 1 ;
+ UINT32 pcie1_radm_pm_to_ack_reg : 1 ;
+ UINT32 pcie1_radm_cpl_timeout_reg : 1 ;
+ UINT32 pcie1_radm_msg_unlock_reg : 1 ;
+ UINT32 pcie1_cfg_pme_msi_reg : 1 ;
+ UINT32 pcie1_bridge_flush_not_reg : 1 ;
+ UINT32 pcie1_link_req_rst_not_reg : 1 ;
+ UINT32 pcie1_cfg_aer_rc_err_msi : 1 ;
+ UINT32 pcie1_cfg_sys_err_rc : 1 ;
+ UINT32 pcie1_radm_msg_req_id_high : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_sys_state1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1_ltssm_state : 6 ;
+ UINT32 pcie1_mac_phy_rate : 2 ;
+ UINT32 pcie1_slv_err_int : 1 ;
+ UINT32 pcie1_retry_sram_addr : 10 ;
+ UINT32 pcie1_mstr_rresp_int : 1 ;
+ UINT32 pcie1_mstr_bresp_int : 1 ;
+ UINT32 pcie1_radm_inta_reg : 1 ;
+ UINT32 pcie1_radm_intb_reg : 1 ;
+ UINT32 pcie1_radm_intc_reg : 1 ;
+ UINT32 pcie1_radm_intd_reg : 1 ;
+ UINT32 pcie1_cfg_pme_int_reg : 1 ;
+ UINT32 pcie1_radm_vendor_msg_reg : 1 ;
+ UINT32 pcie1_bridge_flush_not : 1 ;
+ UINT32 pcie1_link_req_rst_not : 1 ;
+ UINT32 reserved_0 : 3 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_sys_state4;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1_curr_wr_latency : 16 ;
+ UINT32 pcie1_curr_wr_port_sts : 1 ;
+ UINT32 reserved_0 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_axi_mstr_ooo_wr_sts1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1_curr_rd_latency : 16 ;
+ UINT32 pcie1_curr_rd_port_sts : 1 ;
+ UINT32 reserved_0 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_axi_mstr_ooo_rd_sts1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1_rob_ecc_err_detect : 1 ;
+ UINT32 pcie1_rob_ecc_err_multpl : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_dsize_brg_ecc_err;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1_pciephy_ctrl_error : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_pciephy_ctrl_error;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2_mac_phy_rxeqinprogress : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_rxeqinpro_stat;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2_cfg_link_eq_req_int : 1 ;
+ UINT32 pcie2_xmlh_ltssm_state_rcvry_eq : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_linkint_rcvry_stat;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2_gm_cmposer_lookup_err : 1 ;
+ UINT32 pcie2_radmx_cmposer_lookup_err : 1 ;
+ UINT32 pcie2_pm_xtlh_block_tlp : 1 ;
+ UINT32 pcie2_cfg_mem_space_en : 1 ;
+ UINT32 pcie2_cfg_rcb : 1 ;
+ UINT32 pcie2_rdlh_link_up : 1 ;
+ UINT32 pcie2_pm_curnt_state : 3 ;
+ UINT32 pcie2_cfg_aer_rc_err_int : 1 ;
+ UINT32 pcie2_cfg_aer_int_msg_num : 5 ;
+ UINT32 pcie2_xmlh_link_up : 1 ;
+ UINT32 pcie2_wake : 1 ;
+ UINT32 pcie2_cfg_eml_control : 1 ;
+ UINT32 pcie2_hp_pme : 1 ;
+ UINT32 pcie2_hp_int : 1 ;
+ UINT32 pcie2_hp_msi : 1 ;
+ UINT32 pcie2_pm_status : 1 ;
+ UINT32 pcie2_ref_clk_req_n : 1 ;
+ UINT32 pcie2_p2_exit_reg : 1 ;
+ UINT32 pcie2_radm_msg_req_id_low : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_sys_state0;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2_axi_parity_errs_reg : 4 ;
+ UINT32 pcie2_app_parity_errs_reg : 3 ;
+ UINT32 pcie2_pm_linkst_in_l1 : 1 ;
+ UINT32 pcie2_pm_linkst_in_l2 : 1 ;
+ UINT32 pcie2_pm_linkst_l2_exit : 1 ;
+ UINT32 pcie2_mac_phy_power_down : 2 ;
+ UINT32 pcie2_radm_correctabl_err_reg : 1 ;
+ UINT32 pcie2_radm_nonfatal_err_reg : 1 ;
+ UINT32 pcie2_radm_fatal_err_reg : 1 ;
+ UINT32 pcie2_radm_pm_to_pme_reg : 1 ;
+ UINT32 pcie2_radm_pm_to_ack_reg : 1 ;
+ UINT32 pcie2_radm_cpl_timeout_reg : 1 ;
+ UINT32 pcie2_radm_msg_unlock_reg : 1 ;
+ UINT32 pcie2_cfg_pme_msi_reg : 1 ;
+ UINT32 pcie2_bridge_flush_not_reg : 1 ;
+ UINT32 pcie2_link_req_rst_not_reg : 1 ;
+ UINT32 pcie2_cfg_aer_rc_err_msi : 1 ;
+ UINT32 pcie2_cfg_sys_err_rc : 1 ;
+ UINT32 pcie2_radm_msg_req_id_high : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_sys_state1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2_ltssm_state : 6 ;
+ UINT32 pcie2_mac_phy_rate : 2 ;
+ UINT32 pcie2_slv_err_int : 1 ;
+ UINT32 pcie2_retry_sram_addr : 10 ;
+ UINT32 pcie2_mstr_rresp_int : 1 ;
+ UINT32 pcie2_mstr_bresp_int : 1 ;
+ UINT32 pcie2_radm_inta_reg : 1 ;
+ UINT32 pcie2_radm_intb_reg : 1 ;
+ UINT32 pcie2_radm_intc_reg : 1 ;
+ UINT32 pcie2_radm_intd_reg : 1 ;
+ UINT32 pcie2_cfg_pme_int_reg : 1 ;
+ UINT32 pcie2_radm_vendor_msg_reg : 1 ;
+ UINT32 pcie2_bridge_flush_not : 1 ;
+ UINT32 pcie2_link_req_rst_not : 1 ;
+ UINT32 reserved_0 : 3 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_sys_state4;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2_curr_wr_latency : 16 ;
+ UINT32 pcie2_curr_wr_port_sts : 1 ;
+ UINT32 reserved_0 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_axi_mstr_ooo_wr_sts1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2_curr_rd_latency : 16 ;
+ UINT32 pcie2_curr_rd_port_sts : 1 ;
+ UINT32 reserved_0 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_axi_mstr_ooo_rd_sts1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2_rob_ecc_err_detect : 1 ;
+ UINT32 pcie2_rob_ecc_err_multpl : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_dsize_brg_ecc_err;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2_pciephy_ctrl_error : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_pciephy_ctrl_error;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie3_gm_cmposer_lookup_err : 1 ;
+ UINT32 pcie3_radmx_cmposer_lookup_err : 1 ;
+ UINT32 pcie3_pm_xtlh_block_tlp : 1 ;
+ UINT32 pcie3_cfg_mem_space_en : 1 ;
+ UINT32 pcie3_cfg_rcb : 1 ;
+ UINT32 pcie3_rdlh_link_up : 1 ;
+ UINT32 pcie3_pm_curnt_state : 3 ;
+ UINT32 pcie3_cfg_aer_rc_err_int : 1 ;
+ UINT32 pcie3_cfg_aer_int_msg_num : 5 ;
+ UINT32 pcie3_xmlh_link_up : 1 ;
+ UINT32 pcie3_wake : 1 ;
+ UINT32 pcie3_cfg_eml_control : 1 ;
+ UINT32 pcie3_hp_pme : 1 ;
+ UINT32 pcie3_hp_int : 1 ;
+ UINT32 pcie3_hp_msi : 1 ;
+ UINT32 pcie3_pm_status : 1 ;
+ UINT32 pcie3_ref_clk_req_n : 1 ;
+ UINT32 pcie3_p2_exit_reg : 1 ;
+ UINT32 pcie3_radm_msg_req_id_low : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie3_sys_state0;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie3_axi_parity_errs_reg : 4 ;
+ UINT32 pcie3_app_parity_errs_reg : 3 ;
+ UINT32 pcie3_pm_linkst_in_l1 : 1 ;
+ UINT32 pcie3_pm_linkst_in_l2 : 1 ;
+ UINT32 pcie3_pm_linkst_l2_exit : 1 ;
+ UINT32 pcie3_mac_phy_power_down : 2 ;
+ UINT32 pcie3_radm_correctabl_err_reg : 1 ;
+ UINT32 pcie3_radm_nonfatal_err_reg : 1 ;
+ UINT32 pcie3_radm_fatal_err_reg : 1 ;
+ UINT32 pcie3_radm_pm_to_pme_reg : 1 ;
+ UINT32 pcie3_radm_pm_to_ack_reg : 1 ;
+ UINT32 pcie3_radm_cpl_timeout_reg : 1 ;
+ UINT32 pcie3_radm_msg_unlock_reg : 1 ;
+ UINT32 pcie3_cfg_pme_msi_reg : 1 ;
+ UINT32 pcie3_bridge_flush_not_reg : 1 ;
+ UINT32 pcie3_link_req_rst_not_reg : 1 ;
+ UINT32 pcie3_cfg_aer_rc_err_msi : 1 ;
+ UINT32 pcie3_cfg_sys_err_rc : 1 ;
+ UINT32 pcie3_radm_msg_req_id_high : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie3_sys_state1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie3_ltssm_state : 6 ;
+ UINT32 pcie3_mac_phy_rate : 2 ;
+ UINT32 pcie3_slv_err_int : 1 ;
+ UINT32 pcie3_retry_sram_addr : 10 ;
+ UINT32 pcie3_mstr_rresp_int : 1 ;
+ UINT32 pcie3_mstr_bresp_int : 1 ;
+ UINT32 pcie3_radm_inta_reg : 1 ;
+ UINT32 pcie3_radm_intb_reg : 1 ;
+ UINT32 pcie3_radm_intc_reg : 1 ;
+ UINT32 pcie3_radm_intd_reg : 1 ;
+ UINT32 pcie3_cfg_pme_int_reg : 1 ;
+ UINT32 pcie3_radm_vendor_msg_reg : 1 ;
+ UINT32 pcie3_bridge_flush_not : 1 ;
+ UINT32 pcie3_link_req_rst_not : 1 ;
+ UINT32 reserved_0 : 3 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie3_sys_state4;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie3_pciephy_ctrl_error : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie3_pciephy_ctrl_error;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_lock_a : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_st_a_0;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_varible_out_a : 16 ;
+ UINT32 reserved_0 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_st_a_1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_dcell_out_a_h : 4 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_st_a_3;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_lock_b : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_st_b_0;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_varible_out_b : 16 ;
+ UINT32 reserved_0 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_st_b_1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_dcell_out_b_h : 4 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_st_b_3;
+
+#endif
+
+
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