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-rw-r--r--Silicon/Hisilicon/Library/I2CLib/I2CHw.h269
-rw-r--r--Silicon/Hisilicon/Library/I2CLib/I2CLib.c655
-rw-r--r--Silicon/Hisilicon/Library/I2CLib/I2CLib.inf49
-rw-r--r--Silicon/Hisilicon/Library/I2CLib/I2CLibCommon.c35
-rw-r--r--Silicon/Hisilicon/Library/I2CLib/I2CLibInternal.h29
-rw-r--r--Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.c109
-rw-r--r--Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf51
7 files changed, 1197 insertions, 0 deletions
diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CHw.h b/Silicon/Hisilicon/Library/I2CLib/I2CHw.h
new file mode 100644
index 0000000000..aa561e929c
--- /dev/null
+++ b/Silicon/Hisilicon/Library/I2CLib/I2CHw.h
@@ -0,0 +1,269 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _I2C_HW_H_
+#define _I2C_HW_H_
+
+#include <Uefi.h>
+#include <Library/IoLib.h>
+
+#define I2C_READ_TIMEOUT 500
+#define I2C_DRV_ONCE_WRITE_BYTES_NUM 8
+#define I2C_DRV_ONCE_READ_BYTES_NUM 8
+#define I2C_READ_SIGNAL 0x0100
+#define I2C_TXRX_THRESHOLD 0x7
+#define I2C_SS_SCLHCNT 0x493
+#define I2C_SS_SCLLCNT 0x4fe
+#define I2C_CMD_STOP_BIT BIT9
+
+#define I2C_REG_WRITE(reg,data) \
+ MmioWrite32 ((reg), (data))
+
+#define I2C_REG_READ(reg,result) \
+ (result) = MmioRead32 ((reg))
+
+ #define I2C_CON_OFFSET 0x0
+ #define I2C_TAR_OFFSET 0x4
+ #define I2C_SAR_OFFSET 0x8
+ #define I2C_DATA_CMD_OFFSET 0x10
+ #define I2C_SS_SCL_HCNT_OFFSET 0x14
+ #define I2C_SS_SCL_LCNT_OFFSET 0x18
+ #define I2C_FS_SCL_HCNT_OFFSET 0x1c
+ #define I2C_FS_SCL_LCNT_OFFSET 0x20
+ #define I2C_INTR_STAT_OFFSET 0x2c
+ #define I2C_INTR_MASK_OFFSET 0x30
+ #define I2C_RAW_INTR_STAT_OFFSET 0x34
+ #define I2C_RX_TL_OFFSET 0x38
+ #define I2C_TX_TL_OFFSET 0x3c
+ #define I2C_CLR_INTR_OFFSET 0x40
+ #define I2C_CLR_RX_UNDER_OFFSET 0x44
+ #define I2C_CLR_RX_OVER_OFFSET 0x48
+ #define I2C_CLR_TX_OVER_OFFSET 0x4c
+ #define I2C_CLR_RD_REQ_OFFSET 0x50
+ #define I2C_CLR_TX_ABRT_OFFSET 0x54
+ #define I2C_CLR_RX_DONE_OFFSET 0x58
+ #define I2C_CLR_ACTIVITY_OFFSET 0x5c
+ #define I2C_CLR_STOP_DET_OFFSET 0x60
+ #define I2C_CLR_START_DET_OFFSET 0x64
+ #define I2C_CLR_GEN_CALL_OFFSET 0x68
+ #define I2C_ENABLE_OFFSET 0x6c
+ #define I2C_STATUS_OFFSET 0x70
+ #define I2C_TXFLR_OFFSET 0x74
+ #define I2C_RXFLR_OFFSET 0x78
+ #define I2C_SDA_HOLD 0x7c
+ #define I2C_TX_ABRT_SOURCE_OFFSET 0x80
+ #define I2C_SLV_DATA_ONLY_OFFSET 0x84
+ #define I2C_DMA_CR_OFFSET 0x88
+ #define I2C_DMA_TDLR_OFFSET 0x8c
+ #define I2C_DMA_RDLR_OFFSET 0x90
+ #define I2C_SDA_SETUP_OFFSET 0x94
+ #define I2C_ACK_GENERAL_CALL_OFFSET 0x98
+ #define I2C_ENABLE_STATUS_OFFSET 0x9c
+
+
+ typedef union tagI2c0Con
+ {
+ struct
+ {
+ UINT32 master : 1 ;
+ UINT32 spedd : 2 ;
+ UINT32 slave_10bit : 1 ;
+ UINT32 master_10bit : 1 ;
+ UINT32 restart_en : 1 ;
+ UINT32 slave_disable : 1 ;
+ UINT32 Reserved_0 : 25 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_CON_U;
+
+
+ typedef union tagI2c0Tar
+ {
+ struct
+ {
+ UINT32 ic_tar : 10 ;
+ UINT32 gc_or_start : 1 ;
+ UINT32 special : 1 ;
+ UINT32 ic_10bitaddr_master : 1 ;
+ UINT32 Reserved_1 : 19 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_TAR_U;
+
+
+ typedef union tagI2c0DataCmd
+ {
+ struct
+ {
+ UINT32 dat : 8 ;
+ UINT32 cmd : 1 ;
+ UINT32 Reserved_5 : 23 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_DATA_CMD_U;
+
+
+ typedef union tagI2c0SsSclHcnt
+ {
+ struct
+ {
+ UINT32 ic_ss_scl_hcnt : 16 ;
+ UINT32 Reserved_7 : 16 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_SS_SCL_HCNT_U;
+
+
+ typedef union tagI2c0SsSclLcnt
+ {
+ struct
+ {
+ UINT32 ic_ss_scl_lcnt : 16 ;
+ UINT32 Reserved_9 : 16 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_SS_SCL_LCNT_U;
+
+
+ typedef union tagI2c0FsSclHcnt
+ {
+ struct
+ {
+ UINT32 ic_fs_scl_hcnt : 16 ;
+ UINT32 Reserved_11 : 16 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_FS_SCL_HCNT_U;
+
+
+ typedef union tagI2c0FsSclLcnt
+ {
+ struct
+ {
+ UINT32 ic_fs_scl_lcnt : 16 ;
+ UINT32 Reserved_13 : 16 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_FS_SCL_LCNT_U;
+
+
+ typedef union tagI2c0IntrMask
+ {
+ struct
+ {
+ UINT32 m_rx_under : 1 ;
+ UINT32 m_rx_over : 1 ;
+ UINT32 m_rx_full : 1 ;
+ UINT32 m_tx_over : 1 ;
+ UINT32 m_tx_empty : 1 ;
+ UINT32 m_rd_req : 1 ;
+ UINT32 m_tx_abrt : 1 ;
+ UINT32 m_rx_done : 1 ;
+ UINT32 m_activity : 1 ;
+ UINT32 m_stop_det : 1 ;
+ UINT32 m_start_det : 1 ;
+ UINT32 m_gen_call : 1 ;
+ UINT32 Reserved_17 : 20 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_INTR_MASK_U;
+
+
+ typedef union tagI2c0RxTl
+ {
+ struct
+ {
+ UINT32 rx_tl : 8 ;
+ UINT32 Reserved_21 : 24 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_RX_TL_U;
+
+
+ typedef union tagI2c0TxTl
+ {
+ struct
+ {
+ UINT32 tx_tl : 8 ;
+ UINT32 Reserved_23 : 24 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_TX_TL_U;
+
+
+ typedef union tagI2c0Enable
+ {
+ struct
+ {
+ UINT32 enable : 1 ;
+ UINT32 Reserved_47 : 31 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_ENABLE_U;
+
+
+ typedef union tagI2c0Status
+ {
+ struct
+ {
+ UINT32 activity : 1 ;
+ UINT32 tfnf : 1 ;
+ UINT32 tfe : 1 ;
+ UINT32 rfne : 1 ;
+ UINT32 rff : 1 ;
+ UINT32 mst_activity : 1 ;
+ UINT32 slv_activity : 1 ;
+ UINT32 Reserved_49 : 25 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_STATUS_U;
+
+
+ typedef union tagI2c0Txflr
+ {
+ struct
+ {
+ UINT32 txflr : 4 ;
+ UINT32 Reserved_51 : 28 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_TXFLR_U;
+
+
+ typedef union tagI2c0Rxflr
+ {
+ struct
+ {
+ UINT32 rxflr : 4 ;
+ UINT32 Reserved_53 : 28 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_RXFLR_U;
+
+
+ typedef union tagI2c0EnableStatus
+ {
+ struct
+ {
+ UINT32 ic_en : 1 ;
+ UINT32 slv_disable_while_busy: 1 ;
+ UINT32 slv_rx_data_lost : 1 ;
+ UINT32 Reserved_69 : 29 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_ENABLE_STATUS_U;
+
+
+#endif
diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLib.c b/Silicon/Hisilicon/Library/I2CLib/I2CLib.c
new file mode 100644
index 0000000000..b5b388d756
--- /dev/null
+++ b/Silicon/Hisilicon/Library/I2CLib/I2CLib.c
@@ -0,0 +1,655 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+
+#include <PiDxe.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+#include <Library/I2CLib.h>
+#include <Library/TimerLib.h>
+
+#include <Library/PlatformSysCtrlLib.h>
+
+#include "I2CLibInternal.h"
+#include "I2CHw.h"
+
+VOID I2C_Delay(UINT32 ulCount)
+{
+ MicroSecondDelay(ulCount);
+ return;
+}
+
+
+EFI_STATUS
+EFIAPI
+I2C_Disable(UINT32 Socket,UINT8 Port)
+{
+ UINT32 ulTimeCnt = I2C_READ_TIMEOUT;
+ I2C0_STATUS_U I2cStatusReg;
+ I2C0_ENABLE_U I2cEnableReg;
+ I2C0_ENABLE_STATUS_U I2cEnableStatusReg;
+
+ UINTN Base = GetI2cBase(Socket, Port);
+
+ I2C_REG_READ((Base + I2C_STATUS_OFFSET), I2cStatusReg.Val32);
+
+ while (I2cStatusReg.bits.activity)
+ {
+ I2C_Delay(10000);
+
+ ulTimeCnt--;
+ I2C_REG_READ(Base + I2C_STATUS_OFFSET, I2cStatusReg.Val32);
+ if (0 == ulTimeCnt)
+ {
+ return EFI_DEVICE_ERROR;
+ }
+ }
+
+
+ I2C_REG_READ(Base + I2C_ENABLE_OFFSET, I2cEnableReg.Val32);
+ I2cEnableReg.bits.enable = 0;
+ I2C_REG_WRITE(Base + I2C_ENABLE_OFFSET,I2cEnableReg.Val32);
+
+ I2C_REG_READ(Base + I2C_ENABLE_OFFSET,I2cEnableStatusReg.Val32);
+ if (0 == I2cEnableStatusReg.bits.ic_en)
+ {
+ return EFI_SUCCESS;
+ }
+ else
+ {
+ return EFI_DEVICE_ERROR;
+ }
+}
+
+
+EFI_STATUS
+EFIAPI
+I2C_Enable(UINT32 Socket,UINT8 Port)
+{
+ I2C0_ENABLE_U I2cEnableReg;
+ I2C0_ENABLE_STATUS_U I2cEnableStatusReg;
+
+ UINTN Base = GetI2cBase(Socket, Port);
+
+
+ I2C_REG_READ(Base + I2C_ENABLE_OFFSET, I2cEnableReg.Val32);
+ I2cEnableReg.bits.enable = 1;
+ I2C_REG_WRITE(Base + I2C_ENABLE_OFFSET, I2cEnableReg.Val32);
+
+
+ I2C_REG_READ(Base + I2C_ENABLE_STATUS_OFFSET, I2cEnableStatusReg.Val32);
+ if (1 == I2cEnableStatusReg.bits.ic_en)
+ {
+ return EFI_SUCCESS;
+ }
+ else
+ {
+ return EFI_DEVICE_ERROR;
+ }
+}
+
+void I2C_SetTarget(UINT32 Socket,UINT8 Port,UINT32 I2cDeviceAddr)
+{
+ I2C0_TAR_U I2cTargetReg;
+ UINTN Base = GetI2cBase(Socket, Port);
+
+
+ I2C_REG_READ(Base + I2C_TAR_OFFSET, I2cTargetReg.Val32);
+ I2cTargetReg.bits.ic_tar = I2cDeviceAddr;
+ I2C_REG_WRITE(Base + I2C_TAR_OFFSET, I2cTargetReg.Val32);
+
+ return;
+}
+
+
+EFI_STATUS
+EFIAPI
+I2CInit(UINT32 Socket, UINT32 Port, SPEED_MODE SpeedMode)
+{
+ I2C0_CON_U I2cControlReg;
+ I2C0_SS_SCL_HCNT_U I2cStandardSpeedSclHighCount;
+ I2C0_SS_SCL_LCNT_U I2cStandardSpeedSclLowCount;
+ I2C0_RX_TL_U I2cRxFifoReg;
+ I2C0_TX_TL_U I2cTxFifoReg;
+ I2C0_INTR_MASK_U I2cIntrMask;
+ EFI_STATUS Status;
+
+ UINTN Base = GetI2cBase(Socket, Port);
+
+ if((Socket >= MAX_SOCKET) || (Port >= I2C_PORT_MAX) || (SpeedMode >= SPEED_MODE_MAX)){
+ return EFI_INVALID_PARAMETER;
+ }
+
+
+ Status = I2C_Disable(Socket,Port);
+ if(EFI_ERROR(Status))
+ {
+ return EFI_DEVICE_ERROR;
+ }
+
+
+ I2C_REG_READ(Base + I2C_CON_OFFSET, I2cControlReg.Val32);
+ I2cControlReg.bits.master = 1;
+ I2cControlReg.bits.spedd = 0x1;
+ I2cControlReg.bits.restart_en = 1;
+ I2cControlReg.bits.slave_disable = 1;
+ I2C_REG_WRITE(Base + I2C_CON_OFFSET,I2cControlReg.Val32);
+
+
+ if(Normal == SpeedMode)
+ {
+ I2C_REG_READ(Base + I2C_SS_SCL_HCNT_OFFSET,I2cStandardSpeedSclHighCount.Val32);
+ I2cStandardSpeedSclHighCount.bits.ic_ss_scl_hcnt = I2C_SS_SCLHCNT;
+ I2C_REG_WRITE(Base + I2C_SS_SCL_HCNT_OFFSET, I2cStandardSpeedSclHighCount.Val32);
+ I2C_REG_READ(Base + I2C_SS_SCL_LCNT_OFFSET, I2cStandardSpeedSclLowCount.Val32);
+ I2cStandardSpeedSclLowCount.bits.ic_ss_scl_lcnt = I2C_SS_SCLLCNT;
+ I2C_REG_WRITE(Base + I2C_SS_SCL_LCNT_OFFSET, I2cStandardSpeedSclLowCount.Val32);
+ }
+ else
+ {
+ I2C_REG_READ(Base + I2C_FS_SCL_HCNT_OFFSET,I2cStandardSpeedSclHighCount.Val32);
+ I2cStandardSpeedSclHighCount.bits.ic_ss_scl_hcnt = I2C_SS_SCLHCNT;
+ I2C_REG_WRITE(Base + I2C_FS_SCL_HCNT_OFFSET, I2cStandardSpeedSclHighCount.Val32);
+ I2C_REG_READ(Base + I2C_FS_SCL_LCNT_OFFSET, I2cStandardSpeedSclLowCount.Val32);
+ I2cStandardSpeedSclLowCount.bits.ic_ss_scl_lcnt = I2C_SS_SCLLCNT;
+ I2C_REG_WRITE(Base + I2C_FS_SCL_LCNT_OFFSET, I2cStandardSpeedSclLowCount.Val32);
+ }
+
+
+ I2C_REG_READ(Base + I2C_RX_TL_OFFSET, I2cRxFifoReg.Val32);
+ I2cRxFifoReg.bits.rx_tl = I2C_TXRX_THRESHOLD;
+ I2C_REG_WRITE(Base + I2C_RX_TL_OFFSET, I2cRxFifoReg.Val32);
+ I2C_REG_READ(Base + I2C_TX_TL_OFFSET,I2cTxFifoReg.Val32);
+ I2cTxFifoReg.bits.tx_tl = I2C_TXRX_THRESHOLD;
+ I2C_REG_WRITE(Base + I2C_TX_TL_OFFSET, I2cTxFifoReg.Val32);
+
+
+ I2C_REG_READ(Base + I2C_INTR_MASK_OFFSET, I2cIntrMask.Val32);
+ I2cIntrMask.Val32 = 0x0;
+ I2C_REG_WRITE(Base + I2C_INTR_MASK_OFFSET, I2cIntrMask.Val32);
+
+
+ Status = I2C_Enable(Socket,Port);
+ if(EFI_ERROR(Status))
+ {
+ return EFI_DEVICE_ERROR;
+ }
+
+ return I2cLibRuntimeSetup (Socket, Port);
+}
+
+EFI_STATUS
+EFIAPI
+I2CSdaConfig(UINT32 Socket, UINT32 Port)
+{
+
+ UINTN Base = GetI2cBase(Socket, Port);
+
+ if((Socket >= MAX_SOCKET) || (Port >= I2C_PORT_MAX)){
+ return EFI_INVALID_PARAMETER;
+ }
+
+ I2C_REG_WRITE(Base + I2C_SDA_HOLD, 0x14);
+
+ return EFI_SUCCESS;
+}
+
+
+
+UINT32 I2C_GetTxStatus(UINT32 Socket,UINT8 Port)
+{
+ I2C0_TXFLR_U ulFifo;
+ UINTN Base = GetI2cBase(Socket, Port);
+
+ I2C_REG_READ(Base + I2C_TXFLR_OFFSET, ulFifo.Val32);
+ return ulFifo.bits.txflr;
+}
+
+UINT32
+I2C_GetRxStatus(UINT32 Socket,UINT8 Port)
+{
+ I2C0_RXFLR_U ulFifo;
+ UINTN Base = GetI2cBase(Socket, Port);
+
+ I2C_REG_READ(Base + I2C_RXFLR_OFFSET, ulFifo.Val32);
+ return ulFifo.bits.rxflr;
+}
+
+EFI_STATUS
+EFIAPI
+WriteBeforeRead(I2C_DEVICE *I2cInfo, UINT32 ulLength, UINT8 *pBuf)
+{
+ UINT32 ulFifo;
+ UINT32 ulCnt;
+ UINT32 ulTimes = 0;
+
+ UINTN Base = GetI2cBase(I2cInfo->Socket, I2cInfo->Port);
+
+
+ I2C_SetTarget(I2cInfo->Socket,I2cInfo->Port,I2cInfo->SlaveDeviceAddress);
+
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ while(0 != ulFifo)
+ {
+ I2C_Delay(2);
+ if(++ulTimes > I2C_READ_TIMEOUT)
+ {
+ return EFI_TIMEOUT;
+ }
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ }
+
+ for(ulCnt = 0; ulCnt < ulLength; ulCnt++)
+ {
+ ulTimes = 0;
+ while(ulFifo > I2C_TXRX_THRESHOLD)
+ {
+ I2C_Delay(2);
+ if(++ulTimes > I2C_READ_TIMEOUT)
+ {
+ return EFI_TIMEOUT;
+ }
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ }
+
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, *pBuf++);
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ }
+
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ ulTimes = 0;
+ while(0 != ulFifo)
+ {
+ I2C_Delay(2);
+
+ if(++ulTimes > I2C_READ_TIMEOUT)
+ {
+ return EFI_TIMEOUT;
+ }
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+EFIAPI
+I2CWrite(I2C_DEVICE *I2cInfo, UINT16 InfoOffset, UINT32 ulLength, UINT8 *pBuf)
+{
+ UINT32 ulFifo;
+ UINT32 ulTimes = 0;
+ UINT32 Idx;
+ UINTN Base;
+
+
+ if(I2cInfo->Port >= I2C_PORT_MAX)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Base = GetI2cBase(I2cInfo->Socket, I2cInfo->Port);
+
+ (VOID)I2C_Enable(I2cInfo->Socket, I2cInfo->Port);
+
+ I2C_SetTarget(I2cInfo->Socket,I2cInfo->Port,I2cInfo->SlaveDeviceAddress);
+
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ while(0 != ulFifo)
+ {
+ I2C_Delay(2);
+ if(++ulTimes > I2C_READ_TIMEOUT)
+ {
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_TIMEOUT;
+ }
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ }
+
+
+ if(I2cInfo->DeviceType)
+ {
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 8) & 0xff);
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, InfoOffset & 0xff);
+ }
+ else
+ {
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, InfoOffset & 0xff);
+ }
+
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ ulTimes = 0;
+ while(0 != ulFifo)
+ {
+ I2C_Delay(2);
+ if(++ulTimes > I2C_READ_TIMEOUT)
+ {
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_TIMEOUT;
+ }
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ }
+
+ for(Idx = 0; Idx < ulLength; Idx++)
+ {
+ ulTimes = 0;
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ while(ulFifo > I2C_TXRX_THRESHOLD)
+ {
+ I2C_Delay(2);
+ if(++ulTimes > I2C_READ_TIMEOUT)
+ {
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_TIMEOUT;
+ }
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ }
+
+ if (Idx < ulLength - 1) {
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (*pBuf++));
+ } else {
+ //Send command stop bit for the last transfer
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (*pBuf++) | I2C_CMD_STOP_BIT);
+ }
+ }
+
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ ulTimes = 0;
+ while(0 != ulFifo)
+ {
+ I2C_Delay(2);
+
+ if(++ulTimes > I2C_READ_TIMEOUT)
+ {
+ DEBUG ((EFI_D_ERROR, "I2C Write try to finished,time out!\n"));
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_TIMEOUT;
+ }
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ }
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+I2CRead(I2C_DEVICE *I2cInfo, UINT16 InfoOffset,UINT32 ulRxLen,UINT8 *pBuf)
+{
+ UINT32 ulFifo;
+ UINT32 ulTimes = 0;
+ UINT8 I2CWAddr[2];
+ EFI_STATUS Status;
+ UINT32 Idx = 0;
+ UINTN Base;
+
+
+ if(I2cInfo->Port >= I2C_PORT_MAX)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ (VOID)I2C_Enable(I2cInfo->Socket, I2cInfo->Port);
+ Base = GetI2cBase(I2cInfo->Socket, I2cInfo->Port);
+ if(I2cInfo->DeviceType)
+ {
+ I2CWAddr[0] = (InfoOffset >> 8) & 0xff;
+ I2CWAddr[1] = (InfoOffset & 0xff);
+ Status = WriteBeforeRead(I2cInfo, 2,I2CWAddr);
+ if(EFI_ERROR(Status))
+ {
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_ABORTED;
+ }
+ }
+ else
+ {
+ I2CWAddr[0] = (InfoOffset & 0xff);
+ Status = WriteBeforeRead(I2cInfo, 1,I2CWAddr);
+ if(EFI_ERROR(Status))
+ {
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_ABORTED;
+ }
+ }
+
+ I2C_SetTarget(I2cInfo->Socket,I2cInfo->Port,I2cInfo->SlaveDeviceAddress);
+
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ while(0 != ulFifo)
+ {
+ I2C_Delay(2);
+
+ while(++ulTimes > I2C_READ_TIMEOUT)
+ {
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_TIMEOUT;
+ }
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ }
+
+ while (ulRxLen > 0) {
+ if (ulRxLen > 1) {
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, I2C_READ_SIGNAL);
+ } else {
+ //Send command stop bit for the last transfer
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, I2C_READ_SIGNAL | I2C_CMD_STOP_BIT);
+ }
+
+ ulTimes = 0;
+ do {
+ I2C_Delay(2);
+
+ while(++ulTimes > I2C_READ_TIMEOUT) {
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_TIMEOUT;
+ }
+ ulFifo = I2C_GetRxStatus(I2cInfo->Socket,I2cInfo->Port);
+ }while(0 == ulFifo);
+
+ I2C_REG_READ(Base + I2C_DATA_CMD_OFFSET, pBuf[Idx++]);
+
+ ulRxLen --;
+ }
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+I2CReadMultiByte(I2C_DEVICE *I2cInfo, UINT32 InfoOffset,UINT32 ulRxLen,UINT8 *pBuf)
+{
+ UINT32 ulCnt;
+ UINT16 usTotalLen = 0;
+ UINT32 ulFifo;
+ UINT32 ulTimes = 0;
+ UINT8 I2CWAddr[4];
+ EFI_STATUS Status;
+ UINT32 BytesLeft;
+ UINT32 Idx = 0;
+ UINTN Base;
+
+
+ if(I2cInfo->Port >= I2C_PORT_MAX)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ (VOID)I2C_Enable(I2cInfo->Socket, I2cInfo->Port);
+ Base = GetI2cBase(I2cInfo->Socket, I2cInfo->Port);
+ if(I2cInfo->DeviceType == DEVICE_TYPE_E2PROM)
+ {
+ I2CWAddr[0] = (InfoOffset >> 8) & 0xff;
+ I2CWAddr[1] = (InfoOffset & 0xff);
+ Status = WriteBeforeRead(I2cInfo, 2,I2CWAddr);
+ if(EFI_ERROR(Status))
+ {
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_ABORTED;
+ }
+ }
+
+ else if(I2cInfo->DeviceType == DEVICE_TYPE_CPLD_3BYTE_OPERANDS)
+ {
+ I2CWAddr[0] = (InfoOffset >> 16) & 0xff;
+ I2CWAddr[1] = (InfoOffset >> 8) & 0xff;
+ I2CWAddr[2] = (InfoOffset & 0xff);
+ Status = WriteBeforeRead(I2cInfo, 3,I2CWAddr);
+ if(EFI_ERROR(Status))
+ {
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_ABORTED;
+ }
+ }
+
+ else if(I2cInfo->DeviceType == DEVICE_TYPE_CPLD_4BYTE_OPERANDS)
+ {
+ I2CWAddr[0] = (InfoOffset >> 24) & 0xff;
+ I2CWAddr[1] = (InfoOffset >> 16) & 0xff;
+ I2CWAddr[2] = (InfoOffset >> 8) & 0xff;
+ I2CWAddr[3] = (InfoOffset & 0xff);
+ Status = WriteBeforeRead(I2cInfo, 4,I2CWAddr);
+ if(EFI_ERROR(Status))
+ {
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_ABORTED;
+ }
+ }
+
+ else
+ {
+ I2CWAddr[0] = (InfoOffset & 0xff);
+ Status = WriteBeforeRead(I2cInfo, 1,I2CWAddr);
+ if(EFI_ERROR(Status))
+ {
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_ABORTED;
+ }
+ }
+
+
+ I2C_SetTarget(I2cInfo->Socket,I2cInfo->Port,I2cInfo->SlaveDeviceAddress);
+ usTotalLen = ulRxLen;
+ BytesLeft = usTotalLen;
+
+ for(ulCnt = 0; ulCnt < BytesLeft; ulCnt++) {
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, I2C_READ_SIGNAL);
+ }
+
+
+ for(ulCnt = 0; ulCnt < BytesLeft; ulCnt++) {
+ ulTimes = 0;
+ do {
+ I2C_Delay(2);
+
+ while(++ulTimes > I2C_READ_TIMEOUT) {
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_TIMEOUT;
+ }
+ ulFifo = I2C_GetRxStatus(I2cInfo->Socket,I2cInfo->Port);
+ }while(0 == ulFifo);
+
+ I2C_REG_READ(Base + I2C_DATA_CMD_OFFSET, pBuf[Idx++]);
+ }
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+I2CWriteMultiByte(I2C_DEVICE *I2cInfo, UINT32 InfoOffset, UINT32 ulLength, UINT8 *pBuf)
+{
+ UINT32 ulFifo;
+ UINT32 ulTimes = 0;
+ UINT32 Idx;
+ UINTN Base;
+
+
+ if(I2cInfo->Port >= I2C_PORT_MAX)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Base = GetI2cBase(I2cInfo->Socket, I2cInfo->Port);
+
+ (VOID)I2C_Enable(I2cInfo->Socket, I2cInfo->Port);
+
+ I2C_SetTarget(I2cInfo->Socket,I2cInfo->Port,I2cInfo->SlaveDeviceAddress);
+
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ while(0 != ulFifo)
+ {
+ I2C_Delay(2);
+ if(++ulTimes > I2C_READ_TIMEOUT)
+ {
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_TIMEOUT;
+ }
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ }
+
+
+ if(I2cInfo->DeviceType == DEVICE_TYPE_CPLD_3BYTE_OPERANDS)
+ {
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 16) & 0xff);
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 8) & 0xff);
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, InfoOffset & 0xff);
+ }
+
+ else if(I2cInfo->DeviceType == DEVICE_TYPE_CPLD_4BYTE_OPERANDS)
+ {
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 24) & 0xff);
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 16) & 0xff);
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 8) & 0xff);
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, InfoOffset & 0xff);
+ }
+
+ else
+ {
+
+ }
+
+ ulTimes = 0;
+ for(Idx = 0; Idx < ulLength; Idx++)
+ {
+
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, *pBuf++);
+
+ }
+
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ ulTimes = 0;
+ while(0 != ulFifo)
+ {
+ I2C_Delay(2);
+
+ if(++ulTimes > I2C_READ_TIMEOUT)
+ {
+ DEBUG ((EFI_D_ERROR, "I2C Write try to finished,time out!\n"));
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_TIMEOUT;
+ }
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ }
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLib.inf b/Silicon/Hisilicon/Library/I2CLib/I2CLib.inf
new file mode 100644
index 0000000000..7f9512467a
--- /dev/null
+++ b/Silicon/Hisilicon/Library/I2CLib/I2CLib.inf
@@ -0,0 +1,49 @@
+#/** @file
+#
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = I2CLib
+ FILE_GUID = FC5651CA-55D8-4fd2-B6D3-A284D993ABA2
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = I2CLib
+
+[Sources.common]
+ I2CLib.c
+ I2CLibCommon.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ Silicon/Hisilicon/HisiPkg.dec
+
+
+[LibraryClasses]
+ DebugLib
+ IoLib
+ BaseLib
+ ArmLib
+ TimerLib
+
+ PlatformSysCtrlLib
+
+[BuildOptions]
+
+[Pcd]
+
diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLibCommon.c b/Silicon/Hisilicon/Library/I2CLib/I2CLibCommon.c
new file mode 100644
index 0000000000..499c2d7a22
--- /dev/null
+++ b/Silicon/Hisilicon/Library/I2CLib/I2CLibCommon.c
@@ -0,0 +1,35 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <PiDxe.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseLib.h>
+
+#include <Library/PlatformSysCtrlLib.h>
+#include "I2CLibInternal.h"
+
+UINTN GetI2cBase (UINT32 Socket, UINT8 Port)
+{
+ return PlatformGetI2cBase(Socket, Port);
+}
+
+EFI_STATUS
+I2cLibRuntimeSetup (UINT32 Socket, UINT8 Port)
+{
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLibInternal.h b/Silicon/Hisilicon/Library/I2CLib/I2CLibInternal.h
new file mode 100644
index 0000000000..14297296e9
--- /dev/null
+++ b/Silicon/Hisilicon/Library/I2CLib/I2CLibInternal.h
@@ -0,0 +1,29 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _I2C_LIB_INTERNAL_H_
+#define _I2C_LIB_INTERNAL_H_
+
+#include <PlatformArch.h>
+#include <Library/I2CLib.h>
+
+UINTN GetI2cBase (UINT32 Socket, UINT8 Port);
+
+EFI_STATUS
+I2cLibRuntimeSetup (UINT32 Socket, UINT8 Port);
+
+
+#endif
+
diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.c b/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.c
new file mode 100644
index 0000000000..678b5a0082
--- /dev/null
+++ b/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.c
@@ -0,0 +1,109 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#include <PiDxe.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiRuntimeLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Guid/EventGroup.h>
+
+#include <Library/PlatformSysCtrlLib.h>
+#include "I2CLibInternal.h"
+
+STATIC EFI_EVENT mI2cLibVirtualAddrChangeEvent;
+
+STATIC UINTN gI2cBase[MAX_SOCKET][I2C_PORT_MAX];
+
+UINTN GetI2cBase (UINT32 Socket, UINT8 Port)
+{
+ if (gI2cBase[Socket][Port] == 0) {
+ gI2cBase[Socket][Port] = PlatformGetI2cBase(Socket, Port);
+ }
+
+ return gI2cBase[Socket][Port];
+}
+
+VOID
+EFIAPI
+I2cLibVirtualNotifyEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ UINT32 Socket;
+ UINT8 Port;
+
+ // We assume that all I2C ports used in one runtime driver need to be
+ // converted into virtual address.
+ for (Socket = 0; Socket < MAX_SOCKET; Socket++) {
+ for (Port = 0; Port < I2C_PORT_MAX; Port++) {
+ if (gI2cBase[Socket][Port] != 0) {
+ EfiConvertPointer (0x0, (VOID **)&gI2cBase[Socket][Port]);
+ }
+ }
+ }
+
+ return;
+}
+
+EFI_STATUS
+I2cLibRuntimeSetup (UINT32 Socket, UINT8 Port)
+{
+ EFI_STATUS Status;
+
+ UINTN Base = GetI2cBase (Socket, Port);
+
+ // Declare the controller as EFI_MEMORY_RUNTIME
+ Status = gDS->AddMemorySpace (
+ EfiGcdMemoryTypeMemoryMappedIo,
+ Base, SIZE_64KB,
+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_WARN, "[%a:%d] AddMemorySpace failed: %r\n", __FUNCTION__, __LINE__, Status));
+ }
+
+ Status = gDS->SetMemorySpaceAttributes (Base, SIZE_64KB, EFI_MEMORY_UC | EFI_MEMORY_RUNTIME);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "[%a:%d] SetMemorySpaceAttributes failed: %r\n", __FUNCTION__, __LINE__, Status));
+ return Status;
+ }
+
+ //
+ // Register for the virtual address change event
+ //
+ // Only create event once
+ if (mI2cLibVirtualAddrChangeEvent == NULL) {
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ I2cLibVirtualNotifyEvent,
+ NULL,
+ &gEfiEventVirtualAddressChangeGuid,
+ &mI2cLibVirtualAddrChangeEvent
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "[%a:%d] Create event failed: %r\n", __FUNCTION__, __LINE__, Status));
+ return Status;
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf b/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf
new file mode 100644
index 0000000000..4990072558
--- /dev/null
+++ b/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf
@@ -0,0 +1,51 @@
+#/** @file
+#
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = I2CLibRuntime
+ FILE_GUID = FC5651CA-55D8-4fd2-B6D3-A284D993ABA2
+ MODULE_TYPE = DXE_RUNTIME_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = I2CLib
+
+[Sources.common]
+ I2CLib.c
+ I2CLibRuntime.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ Silicon/Hisilicon/HisiPkg.dec
+
+
+[LibraryClasses]
+ DebugLib
+ IoLib
+ BaseLib
+ ArmLib
+ TimerLib
+ DxeServicesTableLib
+ UefiRuntimeLib
+
+ PlatformSysCtrlLib
+
+[BuildOptions]
+
+[Pcd]
+
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-02 10:40:59 +0000