diff options
Diffstat (limited to 'Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe')
6 files changed, 1885 insertions, 0 deletions
diff --git a/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInit.c b/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInit.c new file mode 100644 index 0000000000..88ad718e62 --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInit.c @@ -0,0 +1,103 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#include "PcieInit.h"
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/PcdLib.h>
+
+extern VOID PcieRegWrite(UINT32 Port, UINTN Offset, UINT32 Value);
+extern EFI_STATUS PciePortReset(UINT32 HostBridgeNum, UINT32 Port);
+extern EFI_STATUS PciePortInit (UINT32 HostBridgeNum, PCIE_DRIVER_CFG *PcieCfg);
+
+PCIE_DRIVER_CFG gastr_pcie_driver_cfg[PCIE_MAX_PORT_NUM] =
+{
+ //Port 0
+ {
+ 0x0, //Portindex
+
+ {
+ PCIE_ROOT_COMPLEX, //PortType
+ PCIE_WITDH_X8, //PortWidth
+ PCIE_GEN3_0, //PortGen
+ }, //PortInfo
+
+ },
+
+ //Port 1
+ {
+ 0x1, //Portindex
+ {
+ PCIE_ROOT_COMPLEX, //PortType
+ PCIE_WITDH_X8, //PortWidth
+ PCIE_GEN3_0, //PortGen
+ },
+
+ },
+
+ //Port 2
+ {
+ 0x2, //Portindex
+ {
+ PCIE_ROOT_COMPLEX, //PortType
+ PCIE_WITDH_X8, //PortWidth
+ PCIE_GEN3_0, //PortGen
+ },
+
+ },
+
+ //Port 3
+ {
+ 0x3, //Portindex
+ {
+ PCIE_ROOT_COMPLEX, //PortType
+ PCIE_WITDH_X8, //PortWidth
+ PCIE_GEN3_0, //PortGen
+ },
+
+ },
+};
+
+EFI_STATUS
+PcieInitEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+
+{
+ UINT32 Port;
+ EFI_STATUS Status = EFI_SUCCESS;
+ UINT32 HostBridgeNum = 0;
+
+ for (HostBridgeNum = 0; HostBridgeNum < PCIE_HOST_BRIDGE_NUM; HostBridgeNum++)
+ {
+ for (Port = 0; Port < PCIE_MAX_PORT_NUM; Port++)
+ {
+ if (!((((PcdGet32(PcdPcieRootBridgeMask) >> (4 * HostBridgeNum))) >> Port) & 0x1))
+ {
+ continue;
+ }
+
+ Status = PciePortInit(HostBridgeNum, &gastr_pcie_driver_cfg[Port]);
+ if(EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "HostBridge %d, Pcie Port %d Init Failed! \n", HostBridgeNum, Port));
+ }
+
+ }
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInit.h b/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInit.h new file mode 100644 index 0000000000..d837416c5c --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInit.h @@ -0,0 +1,93 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __PCIE_INIT_H__
+#define __PCIE_INIT_H__
+
+#include "PcieInitLib.h"
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiLib.h>
+
+extern EFI_GUID gEfiPcieRootBridgeProtocolGuid;
+
+#define PCIE_LOG_ID 1
+
+#define PCIE_CONFIG_SPACE_SIZE 0x1000 //4k
+#define PCIE_MEMORY_SPACE_SIZE 0x800000 //8M
+#define PCIE_IO_SPACE_SIZE 0x800000 //8M
+#define PCIE_TYPE1_MEM_SIZE (PCIE_MEMORY_SPACE_SIZE + PCIE_IO_SPACE_SIZE)
+
+#define CONFIG_SPACE_BASE_ADDR_LOW 0xe2000000
+#define CONFIG_SPACE_BASE_ADDR_HIGH 0x0
+#define CONFIG_SPACE_ADDR_LIMIT (CONFIG_SPACE_BASE_ADDR_LOW + PCIE_CONFIG_SPACE_SIZE - 1)
+
+#define PCIE_MEM_BASE_ADDR_LOW (CONFIG_SPACE_BASE_ADDR_LOW + PCIE_CONFIG_SPACE_SIZE)
+#define PCIE_MEM_BASE_ADDR_HIGH 0x0
+#define PCIE_MEM_ADDR_LIMIT (PCIE_MEM_BASE_ADDR_LOW + PCIE_MEMORY_SPACE_SIZE - PCIE_CONFIG_SPACE_SIZE - 1)
+
+#define PCIE_IO_BASE_ADDR_LOW (PCIE_MEM_ADDR_LIMIT - 1)
+#define PCIE_IO_BASE_ADDR_HIGH 0x0
+#define PCIE_IO_ADDR_LIMIT (PCIE_IO_BASE_ADDR_LOW + PCIE_IO_SPACE_SIZE - 1)
+
+#define PCIE_INBOUND_BASE 0xD0000000
+
+
+#define PCIE_ALL_DMA_BASE (0x100000000)
+#define PCIE0_ALL_DMA_BASE (PCIE_ALL_DMA_BASE)
+#define PCIE0_ALL_DMA_SIZE (0x8000000)
+#define PCIE0_ALL_BAR01_BASE (0x10000000)
+#define PCIE0_ALL_BAR23_BASE (PCIE0_ALL_BAR01_BASE + PCIE_MAX_AXI_SIZE)
+#define PCIE0_ALL_TRANSLATE01_BASE 0x2c0000000 //(HRD_ATTR_TRAN_ADDR_BASE_HOST_ADDR)
+#define PCIE0_ALL_TRANSLATE01_SIZE (PCIE_MAX_AXI_SIZE)
+#define PCIE0_ALL_TRANSLATE23_BASE (PCIE0_ALL_TRANSLATE01_BASE + PCIE0_ALL_TRANSLATE01_SIZE)
+#define PCIE0_ALL_TRANSLATE23_SIZE (PCIE0_ALL_DMA_SIZE)
+
+
+#define PCIE0_REG_BASE (0xb0070000)
+#define PCIE1_REG_BASE (0xb0080000)
+#define PCIE2_REG_BASE (0xb0090000)
+#define PCIE3_REG_BASE (0xb00a0000)
+
+#define PCIE_BASE_BAR (0xf0000000)
+#define PCIE_BAR_SIZE (0x1000000)
+
+
+#define PCIE_AXI_SIZE (0x1000000)
+#define PCIE0_AXI_BASE (0xb3000000)
+#define PCIE1_AXI_BASE (PCIE0_AXI_BASE + PCIE_AXI_SIZE)
+#define PCIE2_AXI_BASE (PCIE1_AXI_BASE + PCIE_AXI_SIZE)
+#define PCIE3_AXI_BASE (PCIE2_AXI_BASE + PCIE_AXI_SIZE)
+
+//#define PCIE_CONFIG_SPACE_SIZE (0x1000)
+#define PCIE0_CONFIG_BASE (PCIE1_AXI_BASE - PCIE_CONFIG_SPACE_SIZE)
+#define PCIE1_CONFIG_BASE (PCIE2_AXI_BASE - PCIE_CONFIG_SPACE_SIZE)
+#define PCIE2_CONFIG_BASE (PCIE3_AXI_BASE - PCIE_CONFIG_SPACE_SIZE)
+#define PCIE3_CONFIG_BASE (PCIE3_AXI_BASE + PCIE_AXI_SIZE - PCIE_CONFIG_SPACE_SIZE)
+
+
+#define PCIE0_TRANSLATE_BASE (0x30000000)
+#define PCIE1_TRANSLATE_BASE (PCIE0_TRANSLATE_BASE + PCIE_TRANSLATE_SIZE)
+#define PCIE2_TRANSLATE_BASE (PCIE1_TRANSLATE_BASE + PCIE_TRANSLATE_SIZE)
+#define PCIE3_TRANSLATE_BASE (PCIE2_TRANSLATE_BASE + PCIE_TRANSLATE_SIZE)
+
+#define PCIE0_BAR_BASE (PCIE0_AXI_BASE)
+#define PCIE1_BAR_BASE (PCIE1_AXI_BASE)
+#define PCIE2_BAR_BASE (PCIE2_AXI_BASE)
+#define PCIE3_BAR_BASE (PCIE3_AXI_BASE)
+
+
+#endif
+
diff --git a/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitDxe.inf b/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitDxe.inf new file mode 100644 index 0000000000..ea50a28111 --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitDxe.inf @@ -0,0 +1,56 @@ +#/** @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PcieInitDxe
+ FILE_GUID = 2D53A704-A544-4A82-83DF-FFECF4B4AA97
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PcieInitEntry
+
+[Sources]
+ PcieInit.c
+ PcieInitLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+ Silicon/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ UefiBootServicesTableLib
+ UefiLib
+ BaseLib
+ DebugLib
+ ArmLib
+ TimerLib
+ PcdLib
+ IoLib
+
+[Protocols]
+
+
+[Pcd]
+ gHisiTokenSpaceGuid.PcdPcieRootBridgeMask
+
+[depex]
+ TRUE
+
+
+
diff --git a/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c b/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c new file mode 100644 index 0000000000..3581b41c90 --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c @@ -0,0 +1,1048 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "PcieInitLib.h"
+#include <Library/DebugLib.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/TimerLib.h>
+
+static PCIE_INIT_CFG mPcieIntCfg;
+UINT64 pcie_subctrl_base[2] = {0xb0000000, BASE_4TB + 0xb0000000};
+UINT64 pcie_serders_base[2][4] = {{0xB2080000,0xB2000000,0xB2100000,0xB2200000},{BASE_4TB + 0xB2080000,BASE_4TB + 0xB2000000,BASE_4TB + 0xB2100000,BASE_4TB + 0xB2200000}};
+UINT64 io_sub0_base = 0xa0000000;
+UINT64 PCIE_APB_SLVAE_BASE[2] = {0xb0070000, BASE_4TB + 0xb0070000};
+#define PCIE_REG_BASE(HostBridgeNum,port) (PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(port * 0x10000))
+UINT32 loop_test_flag[4] = {0,0,0,0};
+UINT64 pcie_dma_des_base = PCIE_ADDR_BASE_HOST_ADDR;
+#define PCIE_GEN1 0 /* PCIE 1.0 */
+#define PCIE_GEN2 1 /* PCIE 2.0 */
+#define PCIE_GEN3 2 /* PCIE 3.0 */
+#define DS_API(lane) ((0x1FF6c + 8*(15-lane))*2)
+
+extern PCIE_DRIVER_CFG gastr_pcie_driver_cfg;
+extern PCIE_IATU gastr_pcie_iatu_cfg;
+extern PCIE_IATU_VA mPcieIatuTable;
+
+VOID PcieRegWrite(UINT32 Port, UINTN Offset, UINT32 Value)
+{
+ RegWrite((UINT64)mPcieIntCfg.RegResource[Port] + Offset, Value);
+
+}
+
+UINT32 PcieRegRead(UINT32 Port, UINTN Offset)
+{
+ UINT32 Value = 0;
+
+ RegRead((UINT64)mPcieIntCfg.RegResource[Port] + Offset, Value);
+ return Value;
+}
+
+VOID PcieMmioWrite(UINT32 Port, UINTN Offset0, UINTN Offset1, UINT32 Value)
+{
+ RegWrite((UINT64)mPcieIntCfg.CfgResource[Port] + Offset0 + Offset1, Value);
+}
+
+UINT32 PcieMmioRead(UINT32 Port, UINTN Offset0, UINTN Offset1)
+{
+ UINT32 Value = 0;
+ RegRead((UINT64)mPcieIntCfg.CfgResource[Port] + Offset0 + Offset1, Value);
+ return Value;
+}
+
+VOID PcieChangeRwMode(UINT32 HostBridgeNum, UINT32 Port, PCIE_RW_MODE Mode)
+{
+ u_sc_pcie0_clkreq pcie0;
+ u_sc_pcie1_clkreq pcie1;
+ u_sc_pcie2_clkreq pcie2;
+ u_sc_pcie3_clkreq pcie3;
+
+ switch(Port)
+ {
+ case 0:
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_CLKREQ_REG, pcie0.UInt32);
+ pcie0.Bits.pcie0_apb_cfg_sel = Mode;
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_CLKREQ_REG, pcie0.UInt32);
+ break;
+ case 1:
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE1_CLKREQ_REG, pcie1.UInt32);
+ pcie1.Bits.pcie1_apb_cfg_sel = Mode;
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE1_CLKREQ_REG, pcie1.UInt32);
+ break;
+ case 2:
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE2_CLKREQ_REG, pcie2.UInt32);
+ pcie2.Bits.pcie2_apb_cfg_sel = Mode;
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE2_CLKREQ_REG, pcie2.UInt32);
+ break;
+ case 3:
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_CLKREQ_REG, pcie3.UInt32);
+ pcie3.Bits.pcie3_apb_cfg_sel = Mode;
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_CLKREQ_REG, pcie3.UInt32);
+ break;
+ default:
+ break;
+ }
+}
+
+
+
+EFI_STATUS PcieEnableItssm(UINT32 HostBridgeNum, UINT32 Port)
+{
+ PCIE_CTRL_7_U pcie_ctrl7;
+
+ if(Port >= PCIE_MAX_PORT_NUM)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if(mPcieIntCfg.PortIsInitilized[Port])
+ {
+ return PCIE_ERR_ALREADY_INIT;
+ }
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+
+ pcie_ctrl7.UInt32 = PcieRegRead(Port, PCIE_CTRL_7_REG);
+ pcie_ctrl7.Bits.pcie2_app_ltssm_enable = 0x1;
+ PcieRegWrite(Port, PCIE_CTRL_7_REG, pcie_ctrl7.UInt32);
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS PcieDisableItssm(UINT32 HostBridgeNum, UINT32 Port)
+{
+ PCIE_CTRL_7_U pcie_ctrl7;
+
+ if(Port >= PCIE_MAX_PORT_NUM)
+ {
+ return PCIE_ERR_PARAM_INVALID;
+ }
+
+
+ if(mPcieIntCfg.PortIsInitilized[Port])
+ {
+ return PCIE_ERR_ALREADY_INIT;
+ }
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+
+ pcie_ctrl7.UInt32 = PcieRegRead(Port, PCIE_CTRL_7_REG);
+ pcie_ctrl7.Bits.pcie2_app_ltssm_enable = 0x0;
+ PcieRegWrite(Port,PCIE_CTRL_7_REG, pcie_ctrl7.UInt32);
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS PcieLinkSpeedSet(UINT32 Port,PCIE_PORT_GEN Speed)
+{
+ PCIE_EP_PCIE_CAP12_U pcie_cap12;
+
+ if(Port >= PCIE_MAX_PORT_NUM)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ pcie_cap12.UInt32 = PcieRegRead(Port, PCIE_EP_PCIE_CAP12_REG);
+ pcie_cap12.Bits.targetlinkspeed = Speed;
+ PcieRegWrite(Port, PCIE_EP_PCIE_CAP12_REG, pcie_cap12.UInt32);
+
+ if(mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_NTB ||
+ mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_RP)
+ {
+ pcie_cap12.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PCIE_CAP12_REG);
+ pcie_cap12.Bits.targetlinkspeed = Speed;
+ PcieMmioWrite(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PCIE_CAP12_REG, pcie_cap12.UInt32);
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS PcieLinkWidthSet(UINT32 Port, PCIE_PORT_WIDTH Width)
+{
+ PCIE_EP_PORT_LOGIC4_U pcie_logic4;
+ PCIE_EP_PORT_LOGIC22_U logic22;
+
+ if(Port >= PCIE_MAX_PORT_NUM)
+ {
+ return PCIE_ERR_PARAM_INVALID;
+ }
+
+ pcie_logic4.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC4_REG);
+ pcie_logic4.Bits.linkmodeenable = Width;
+ pcie_logic4.Bits.crosslinkenable = 0;
+ pcie_logic4.Bits.fastlinkmode = 1;
+ PcieRegWrite(Port, PCIE_EP_PORT_LOGIC4_REG, pcie_logic4.UInt32);
+
+ logic22.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC22_REG);
+ logic22.Bits.n_fts = 0xff;
+ if(Width == PCIE_WITDH_X1)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 1;
+ }
+ else if(Width == PCIE_WITDH_X2)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 2;
+ }
+ else
+ {
+ logic22.Bits.pre_determ_num_of_lane = 3;
+ }
+ PcieRegWrite(Port, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32);
+
+ if(mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_NTB ||
+ mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_RP)
+ {
+ pcie_logic4.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC4_REG);
+ pcie_logic4.Bits.linkmodeenable = Width;
+ pcie_logic4.Bits.crosslinkenable = 0;
+ pcie_logic4.Bits.fastlinkmode = 1;
+ PcieMmioWrite(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC4_REG, pcie_logic4.UInt32);
+
+ logic22.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC22_REG);
+ logic22.Bits.n_fts = 0xff;
+ if(Width == PCIE_WITDH_X1)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 1;
+ }
+ else if(Width == PCIE_WITDH_X2)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 2;
+ }
+ else
+ {
+ logic22.Bits.pre_determ_num_of_lane = 3;
+ }
+ PcieMmioWrite(Port,PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32);
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS PcieSetupRC(UINT32 Port, PCIE_PORT_WIDTH Width)
+{
+ PCIE_EP_PORT_LOGIC22_U logic22;
+ PCIE_EEP_PCI_CFG_HDR15_U hdr15;
+ UINT32 Value = 0;
+ if(Port >= PCIE_MAX_PORT_NUM)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Value = PcieRegRead(Port, PCIE_EP_PORT_LOGIC4_REG);
+ Value &= ~(0x3f<<16);
+
+ if(Width == PCIE_WITDH_X1)
+ {
+ Value |= (0x1 << 16);
+ }
+ else if(Width == PCIE_WITDH_X2)
+ {
+ Value |= (0x3 << 16);
+ }
+ else if(Width == PCIE_WITDH_X4)
+ {
+ Value |= (0x7 << 16);
+ }
+ else if(Width == PCIE_WITDH_X8)
+ {
+ Value |= (0xf << 16);
+ }
+ else
+ {
+ DEBUG((EFI_D_ERROR,"Width is not invalid\n"));
+ }
+
+ PcieRegWrite(Port, PCIE_EP_PORT_LOGIC4_REG, Value);
+
+ logic22.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC22_REG);
+ logic22.UInt32 &= ~(0x1f<<8);
+
+ if(Width == PCIE_WITDH_X1)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 1;
+ }
+ else if(Width == PCIE_WITDH_X2)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 2;
+ }
+ else if(Width == PCIE_WITDH_X4)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 4;
+ }
+ else if(Width == PCIE_WITDH_X8)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 8;
+ }
+ else
+ {
+ DEBUG((EFI_D_ERROR,"Width is not invalid\n"));
+ }
+
+ PcieRegWrite(Port, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32);
+
+ /* setup RC BARs */
+ PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR4_REG, 0x00000004);
+ PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR5_REG, 0x00000000);
+
+ /* setup interrupt pins */
+ hdr15.UInt32 = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR15_REG);
+ hdr15.UInt32 &= 0xffff00ff;
+ hdr15.UInt32 |= 0x00000100;
+ PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR15_REG, hdr15.UInt32);
+
+ /* setup bus numbers */
+ Value = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR6_REG);
+ Value &= 0xff000000;
+ Value |= 0x00010100;
+ PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR6_REG, Value);
+
+ /* setup command register */
+ Value = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR1_REG);
+ Value &= 0xffff0000;
+ Value |= 0x1|0x2|0x4|0x100;
+ PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR1_REG, Value);
+
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS PcieModeSet(UINT32 HostBridgeNum, UINT32 Port, PCIE_PORT_TYPE PcieType)
+{
+ PCIE_CTRL_0_U str_pcie_ctrl_0;
+
+ if(Port >= PCIE_MAX_PORT_NUM)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if(mPcieIntCfg.PortIsInitilized[Port])
+ {
+ return PCIE_ERR_ALREADY_INIT;
+ }
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+
+ str_pcie_ctrl_0.UInt32 = PcieRegRead(Port, PCIE_CTRL_0_REG);
+ if(PcieType == PCIE_END_POINT)
+ {
+ str_pcie_ctrl_0.Bits.pcie2_slv_device_type = PCIE_EP_DEVICE;
+ }
+ else
+ {
+ str_pcie_ctrl_0.Bits.pcie2_slv_device_type = RP_OF_PCIE_RC;
+ }
+ PcieRegWrite(Port, PCIE_CTRL_0_REG, str_pcie_ctrl_0.UInt32);
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+
+ return EFI_SUCCESS;
+}
+
+VOID PciePcsInit(UINT32 HostBridgeNum, UINT32 Port)
+{
+
+ if(Port<=2)
+ {
+ RegWrite(pcie_serders_base[HostBridgeNum][Port] + 0xc088, 0x212);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8020, 0x2026044);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8060, 0x2126044);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80c4, 0x2126044);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80e4, 0x2026044);
+
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80a0, 0x4018);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80a4, 0x804018);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80c0, 0x11201100);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x15c, 0x3);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x158, 0);
+ }
+ else
+
+ {
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x74, 0x46e000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x78, 0x46e000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x7c, 0x46e000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80, 0x46e000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x84, 0x46e000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x88, 0x46e000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8c, 0x46e000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x90, 0x46e000);
+
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x34, 0x1001);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x38, 0x1001);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x3c, 0x1001);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x40, 0x1001);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x44, 0x1001);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x48, 0x1001);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x4c, 0x1001);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x50, 0x1001);
+
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0xe4, 0xffff);
+ }
+
+}
+
+VOID PcieEqualization(UINT32 Port)
+{
+ UINT32 Value;
+
+ PcieRegWrite(Port, 0x890, 0x1400);
+ PcieRegWrite(Port, 0x894, 0xfd7);
+
+ PcieRegWrite(Port, 0x89c, 0x0);
+ PcieRegWrite(Port, 0x898, 0xfc00);
+ PcieRegWrite(Port, 0x89c, 0x1);
+ PcieRegWrite(Port, 0x898, 0xbd00);
+ PcieRegWrite(Port, 0x89c, 0x2);
+ PcieRegWrite(Port, 0x898, 0xccc0);
+ PcieRegWrite(Port, 0x89c, 0x3);
+ PcieRegWrite(Port, 0x898, 0x8dc0);
+ PcieRegWrite(Port, 0x89c, 0x4);
+ PcieRegWrite(Port, 0x898, 0xfc0);
+ PcieRegWrite(Port, 0x89c, 0x5);
+ PcieRegWrite(Port, 0x898, 0xe46);
+ PcieRegWrite(Port, 0x89c, 0x6);
+ PcieRegWrite(Port, 0x898, 0xdc8);
+ PcieRegWrite(Port, 0x89c, 0x7);
+ PcieRegWrite(Port, 0x898, 0xcb46);
+ PcieRegWrite(Port, 0x89c, 0x8);
+ PcieRegWrite(Port, 0x898, 0x8c07);
+ PcieRegWrite(Port, 0x89c, 0x9);
+ PcieRegWrite(Port, 0x898, 0xd0b);
+ PcieRegWrite(Port, 0x8a8, 0x103ff21);
+
+ Value = PcieRegRead(Port, 0x80);
+ Value |= 0x80;
+ PcieRegWrite(Port, 0x80, Value);
+
+ PcieRegWrite(Port, 0x184, 0x44444444);
+ PcieRegWrite(Port, 0x188, 0x44444444);
+ PcieRegWrite(Port, 0x18c, 0x44444444);
+ PcieRegWrite(Port, 0x190, 0x44444444);
+
+}
+
+
+EFI_STATUS PciePortReset(UINT32 HostBridgeNum, UINT32 Port)
+{
+ if(Port >= PCIE_MAX_PORT_NUM)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if(PcieIsLinkUp(HostBridgeNum, Port) && mPcieIntCfg.PortIsInitilized[Port])
+ {
+ (VOID)PcieDisableItssm(HostBridgeNum, Port);
+ }
+
+ mPcieIntCfg.PortIsInitilized[Port] = FALSE;
+ mPcieIntCfg.DmaResource[Port] = (VOID *)NULL;
+ mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_READ] = 0;
+ mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_WRITE] = 0;
+ ZeroMem(&mPcieIntCfg.Dev[Port], sizeof(DRIVER_CFG_U));
+
+ if(Port <= 2)
+ {
+ RegWrite(pcie_subctrl_base[HostBridgeNum]+ PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * Port), 0x1);
+ MicroSecondDelay(0x1000);
+
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * Port), 0x1);
+ MicroSecondDelay(0x1000);
+ }
+ else
+ {
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG,0x1);
+ MicroSecondDelay(0x1000);
+
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG,0x1);
+ MicroSecondDelay(0x1000);
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS AssertPcieCoreReset(UINT32 HostBridgeNum, UINT32 Port)
+{
+ if(Port >= PCIE_MAX_PORT_NUM)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if(PcieIsLinkUp(HostBridgeNum, Port) && mPcieIntCfg.PortIsInitilized[Port])
+ {
+ (VOID)PcieDisableItssm(HostBridgeNum, Port);
+ }
+
+ mPcieIntCfg.PortIsInitilized[Port] = FALSE;
+ mPcieIntCfg.DmaResource[Port] = (VOID *)NULL;
+ mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_READ] = 0;
+ mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_WRITE] = 0;
+ ZeroMem(&mPcieIntCfg.Dev[Port], sizeof(DRIVER_CFG_U));
+
+ if(Port <= 2)
+ {
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * Port), 0x1);
+ MicroSecondDelay(0x1000);
+ }
+ else
+ {
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG,0x1);
+ MicroSecondDelay(0x1000);
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS DeassertPcieCoreReset(UINT32 HostBridgeNum, UINT32 Port)
+{
+ if(Port >= PCIE_MAX_PORT_NUM)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if(PcieIsLinkUp(HostBridgeNum, Port) && mPcieIntCfg.PortIsInitilized[Port])
+ {
+ (VOID)PcieDisableItssm(HostBridgeNum, Port);
+ }
+
+ mPcieIntCfg.PortIsInitilized[Port] = FALSE;
+ mPcieIntCfg.DmaResource[Port] = (VOID *)NULL;
+ mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_READ] = 0;
+ mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_WRITE] = 0;
+ ZeroMem(&mPcieIntCfg.Dev[Port], sizeof(DRIVER_CFG_U));
+
+ if(Port <= 2)
+ {
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * Port), 0x1);
+ MicroSecondDelay(0x1000);
+ }
+ else
+ {
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG,0x1);
+ MicroSecondDelay(0x1000);
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS AssertPciePcsReset(UINT32 HostBridgeNum,UINT32 Port)
+{
+ u_sc_pcie_hilink_pcs_reset_req reset_req;
+ UINT32 pcs_local_reset_status;
+ UINT32 pcs_local_status_checked;
+ UINT32 hilink_reset_status;
+ UINT32 hilink_status_checked;
+ UINT32 count = 0;
+
+ reset_req.UInt32 = 0;
+ reset_req.UInt32 = reset_req.UInt32 | (0x1 << Port);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG, reset_req.UInt32);
+
+ reset_req.UInt32 = 0;
+ reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * Port));
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG, reset_req.UInt32);
+ MicroSecondDelay(0x1000);
+
+ /* read reset status, make sure pcs is reset */
+ do {
+ MicroSecondDelay(1000);
+ count ++;
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_ST_REG, pcs_local_reset_status);
+ pcs_local_status_checked =
+ ((pcs_local_reset_status & (1 << Port)) !=
+ (1 << Port));
+
+ } while ((pcs_local_status_checked) && (count < 1000));
+
+ if (pcs_local_status_checked)
+ DEBUG((EFI_D_ERROR, "pcs local reset status read failed\n"));
+
+ count = 0;
+ do {
+ MicroSecondDelay(1000);
+ count ++;
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_ST_REG, hilink_reset_status);
+ hilink_status_checked =
+ ((hilink_reset_status & (0xff << (Port << 3))) !=
+ (0xff << (Port << 3)));
+ } while ((hilink_status_checked) && (count < 1000));
+
+ if (hilink_status_checked)
+ DEBUG((EFI_D_ERROR, "error:pcs assert reset failed\n"));
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS DeassertPciePcsReset(UINT32 HostBridgeNum, UINT32 Port)
+{
+ u_sc_pcie_hilink_pcs_reset_req reset_req;
+ UINT32 pcs_local_status;
+ UINT32 pcs_local_status_checked;
+ UINT32 hilink_reset_status;
+ UINT32 hilink_status_checked;
+ UINT32 count = 0;
+
+
+ reset_req.UInt32 = 0;
+ reset_req.UInt32 = reset_req.UInt32 | (0x1 << Port);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_DREQ_REG, reset_req.UInt32);
+
+ reset_req.UInt32 = 0;
+ reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * Port));
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_DREQ_REG, reset_req.UInt32);
+
+ /* read reset status, make sure pcs is deassert */
+ do {
+ MicroSecondDelay(1000);
+ count ++;
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_ST_REG, pcs_local_status);
+ pcs_local_status_checked = (pcs_local_status & (1 << Port));
+ } while ((pcs_local_status_checked) && (count < 1000));
+
+ /* get a timeout error */
+ if (pcs_local_status_checked)
+ DEBUG((EFI_D_ERROR, "pcs deassert reset failed!\n"));
+
+ count = 0;
+ do {
+ MicroSecondDelay(1000);
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_ST_REG, hilink_reset_status);
+ hilink_status_checked = (hilink_reset_status &
+ (0xff << (Port << 3)));
+ } while ((hilink_status_checked) && (count < 1000));
+
+ if (hilink_status_checked)
+ DEBUG((EFI_D_ERROR, "pcs deassert reset failed!\n"));
+
+ return EFI_SUCCESS;
+}
+
+VOID PcieGen3Config(UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 val;
+ UINT32 current_speed;
+ UINT32 ltssm_state;
+ UINT32 timeout = 0;
+ UINT32 eq = 0;
+ UINT32 loop = 100000;
+ U_SC_PCIE0_SYS_STATE4 PcieStat;
+
+ while (loop)
+ {
+ MicroSecondDelay(10);
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);
+ val = PcieStat.UInt32;
+ current_speed = (val >> 6) & 0x3;
+ if (current_speed == PCIE_GEN3)
+ break;
+ loop--;
+ }
+ if (!loop) {
+ DEBUG((EFI_D_ERROR, "current_speed GEN%d\n",current_speed + 1));
+ return;
+ }
+
+ ltssm_state = val & PCIE_LTSSM_STATE_MASK;
+ while ((current_speed == PCIE_GEN3) &&
+ (ltssm_state != PCIE_LTSSM_LINKUP_STATE) && (timeout < 200)) {
+ if ((ltssm_state & 0x30) == 0x20)
+ eq = 1;
+
+ if ((ltssm_state == 0xd) && (eq == 1))
+ {
+ MicroSecondDelay(5000);
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);
+ val = PcieStat.UInt32;
+ ltssm_state = val & PCIE_LTSSM_STATE_MASK;
+ current_speed = (val >> 6) & 0x3;
+ if (ltssm_state == 0xd)
+ {
+ DEBUG((EFI_D_ERROR, "Do symbol align reset rate %d ltssm 0x%x\n",current_speed, ltssm_state));
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x74, 0x8000000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x78, 0x8000000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x7c, 0x8000000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80, 0x8000000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x84, 0x8000000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x88, 0x8000000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8c, 0x8000000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x90, 0x8000000);
+
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x74, 0);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x78, 0);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x7c, 0);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80, 0);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x84, 0);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x88, 0);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8c, 0);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x90, 0);
+ }
+ break;
+ }
+
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);
+ val = PcieStat.UInt32;
+ ltssm_state = val & PCIE_LTSSM_STATE_MASK;
+ current_speed = (val >> 6) & 0x3;
+
+ MicroSecondDelay(1000);
+ timeout++;
+ }
+
+ if (timeout >= 200) {
+ DEBUG((EFI_D_ERROR, "current_speed GEN%d\n",current_speed + 1));
+ return;
+ }
+ DEBUG((EFI_D_ERROR, "current_speed GEN%d\n",current_speed + 1));
+}
+
+VOID Gen3DfeEnable(UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 val;
+ UINT32 lane;
+ UINT32 current_speed;
+ U_SC_PCIE0_SYS_STATE4 PcieStat;
+
+ if (Port == 3)
+ return;
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);
+ val = PcieStat.UInt32;
+ current_speed = (val >> 6) & 0x3;
+ if (current_speed != PCIE_GEN3)
+ return;
+ for (lane = 0; lane < 8; lane++)
+ RegWrite(pcie_serders_base[HostBridgeNum][Port] + (UINT32)DS_API(lane) + 4, 0x3851);
+
+ DEBUG((EFI_D_ERROR, "enable DFE success\n"));
+}
+
+EFI_STATUS HisiPcieClockCtrl(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, BOOLEAN Clock)
+{
+ UINT32 reg_clock_disable;
+ UINT32 reg_clock_enable;
+ UINT32 reg_clock_status;
+ UINT32 clock_status;
+ UINT32 clock_status_checked;
+ UINT32 clock_ctrl;
+ UINT32 count = 0;
+
+ if (Port == 3) {
+ reg_clock_disable = PCIE_SUBCTRL_SC_PCIE3_CLK_DIS_REG;
+ reg_clock_enable = PCIE_SUBCTRL_SC_PCIE3_CLK_EN_REG;
+ reg_clock_status = PCIE_SUBCTRL_SC_PCIE3_CLK_ST_REG;
+ } else {
+ reg_clock_disable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_DIS_REG(Port);
+ reg_clock_enable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_EN_REG(Port);
+ reg_clock_status = PCIE_SUBCTRL_SC_PCIE0_2_CLK_ST_REG(Port);
+ }
+
+ if (0x1610 == soctype)
+ {
+ clock_ctrl = 0x7;
+ }
+ else
+ {
+ clock_ctrl = 0x3;
+ if (Clock)
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + reg_clock_enable, clock_ctrl);
+ else
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + reg_clock_disable, clock_ctrl);
+ }
+
+ do {
+ count ++;
+ MicroSecondDelay(1000);
+ RegRead(pcie_subctrl_base[HostBridgeNum] + reg_clock_status, clock_status);
+ if (Clock)
+ clock_status_checked =
+ ((clock_status & clock_ctrl) != clock_ctrl);
+ else
+ clock_status_checked =
+ ((clock_status & clock_ctrl) != 0);
+ } while ((clock_status_checked) && (count < 1000)); //1S
+
+ /* get a timeout error */
+ if (clock_status_checked)
+ DEBUG((EFI_D_ERROR, "clock operation failed!\n"));
+
+ return EFI_SUCCESS;
+}
+
+VOID PcieSpdSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, UINT8 Spd)
+{
+ UINT32 Value = 0;
+
+ if (0x1610 == soctype)
+ {
+ }
+ else
+ {
+ RegRead(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + 0xa0, Value);
+ Value &= ~(0xf);
+ Value |= Spd;
+ RegWrite(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + 0xa0, Value);
+ return;
+ }
+ return;
+}
+
+VOID PcieSpdControl(UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 Value = 0;;
+
+ /* set link width speed control register */
+ RegRead(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + 0x80c, Value);
+ /*
+ * set the Directed Speed Change field of the Link Width and Speed
+ * Change Control register
+ */
+ Value |= (1 << 17);
+ RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + 0x80c, Value);
+}
+
+VOID PcieSetDb2Enable(UINT32 HostBridgeNum, UINT32 Port, UINT32 enable)
+{
+ UINT32 dbi_ctrl;
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+
+ RegRead(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, dbi_ctrl);
+ if (enable)
+ dbi_ctrl |= BIT0;
+ else
+ dbi_ctrl &= ~BIT0;
+ RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, dbi_ctrl);
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+}
+
+VOID PcieDisabledBar0(UINT32 HostBridgeNum, UINT32 Port)
+{
+ PcieSetDb2Enable(HostBridgeNum, Port, PCIE_DBI_CS2_ENABLE);
+ RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + 0x10,0);
+ PcieSetDb2Enable(HostBridgeNum, Port, PCIE_DBI_CS2_DISABLE);
+}
+
+/* Configure vmid/asid table in PCIe host */
+VOID PcieConfigContextP660(UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 i = 0;
+ UINTN val = 0;;
+
+ /*
+ * enable to clean vmid and asid tables though apb bus
+ * */
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+ RegRead(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val);
+ /* enable ar channel */
+ val |= PCIE_RD_TAB_SEL | PCIE_RD_TAB_EN;
+ RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val);
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SLV_CONTENT_MODE);
+ for (i = 0; i < 0x800; i++)
+ PcieRegWrite(Port, i * 4, 0);
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+ /* enable aw channel */
+ val &= (~PCIE_RD_TAB_SEL);
+ val |= PCIE_RD_TAB_EN;
+ RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val);
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SLV_CONTENT_MODE);
+
+ /*
+ * init vmid and asid tables for all PCIe devices as 0
+ * vmid table: 0 ~ 0x3ff, asid table: 0x400 ~ 0x7ff
+ */
+ for (i = 0; i < 0x800; i++)
+ PcieRegWrite(Port, i * 4, 0);
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+
+ RegRead(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val);
+ /* disable ar channel */
+ val |= PCIE_RD_TAB_SEL;
+ val &= (~PCIE_RD_TAB_EN);
+ RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val);
+ /* disable aw channel */
+ val &= ((~PCIE_RD_TAB_SEL) & (~PCIE_RD_TAB_EN));
+ RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val);
+
+ RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL24_REG, 0xb7010040 & 0xffffffff);
+ RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL28_REG, 0);
+
+ RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL16_REG, (1<<12)|(1<<16));
+ RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL29_REG, (1<<12));
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);;
+}
+
+EFI_STATUS PcieMaskLinkUpInit(UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 Value = 0;
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+ Value = PcieRegRead(Port, 0x1d0);
+ Value |= 1 << 12;
+ PcieRegWrite(Port,0x1d0, Value);
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+ return EFI_SUCCESS;
+}
+
+BOOLEAN PcieIsLinkUp(UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 Value = 0;
+ U_SC_PCIE0_SYS_STATE4 PcieStat;
+
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);
+ Value = PcieStat.UInt32;
+ if ((Value & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE)
+ return TRUE;
+
+ return FALSE;
+}
+
+VOID PcieWriteOwnConfig(UINT32 Port, UINT32 Offset)
+{
+ UINT32 Value = 0;
+ Value = PcieRegRead(Port,Offset & (~0x3));
+ Value &= 0x0000ffff;
+ Value |= 0x06040000;
+ PcieRegWrite(Port, Offset & (~0x3), Value);
+ return;
+}
+
+EFI_STATUS
+EFIAPI
+PciePortInit (
+ IN UINT32 HostBridgeNum,
+ IN PCIE_DRIVER_CFG *PcieCfg
+ )
+{
+ UINT32 Count = 0;
+ UINT32 PortIndex = PcieCfg->PortIndex;
+ UINT32 Value = 0;
+
+
+ if(PortIndex >= PCIE_MAX_PORT_NUM)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if(mPcieIntCfg.PortIsInitilized[PortIndex])
+ {
+ return PCIE_ERR_ALREADY_INIT;
+ }
+
+ mPcieIntCfg.RegResource[PortIndex] = (VOID *)(UINTN)PCIE_REG_BASE(HostBridgeNum, PortIndex);
+
+ /* assert reset signals */
+ (VOID)AssertPcieCoreReset(HostBridgeNum, PortIndex);
+ (VOID)HisiPcieClockCtrl(0x660, HostBridgeNum, PortIndex, 0);
+ (VOID)AssertPciePcsReset(HostBridgeNum, PortIndex);
+
+ /* de-assert phy reset */
+ (VOID)DeassertPciePcsReset(HostBridgeNum, PortIndex);
+
+ /* de-assert core reset */
+ (VOID)DeassertPcieCoreReset(HostBridgeNum, PortIndex);
+ (VOID)HisiPcieClockCtrl(0x660, HostBridgeNum, PortIndex, 1);
+
+ do {
+ RegRead(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(PortIndex * 0x10000) + 0x8108, Value);
+ if (Count == 10) {
+ DEBUG((EFI_D_ERROR, "PCIe Failed! PLL Locked: 0x%x\n\n",Value));
+ return EFI_NOT_READY;
+ }
+ Count++;
+ MicroSecondDelay(100000);
+ } while ((Value & 0x3) == 0);
+ Count = 0;
+
+ /* initialize phy */
+ (VOID)PciePcsInit(HostBridgeNum, PortIndex);
+
+ (VOID)PcieModeSet(HostBridgeNum, PortIndex,PcieCfg->PortInfo.PortType);
+ (VOID)PcieSpdSet(0x660, HostBridgeNum, PortIndex, 3);
+ (VOID)PcieSpdControl(HostBridgeNum, PortIndex);
+ /* setup root complex */
+ (VOID)PcieSetupRC(PortIndex,PcieCfg->PortInfo.PortWidth);
+
+ /* Pcie Equalization*/
+ (VOID)PcieEqualization(PortIndex);
+
+ /* assert LTSSM enable */
+ (VOID)PcieEnableItssm(HostBridgeNum, PortIndex);
+
+ /*
+ * This is a PCS hardware bug, we fix it by resetting
+ * PCS symalign module state machine
+ */
+ (VOID)PcieGen3Config(HostBridgeNum, PortIndex);
+ PcieConfigContextP660(HostBridgeNum, PortIndex);
+ (VOID)PcieDisabledBar0(HostBridgeNum, PortIndex);
+ (VOID)PcieWriteOwnConfig(PortIndex, 0xa);
+ /* check if the link is up or not */
+ while (!PcieIsLinkUp(HostBridgeNum, PortIndex)) {
+ MicroSecondDelay(1000);
+ Count++;
+ if (Count >= 1000) {
+ DEBUG((EFI_D_ERROR, "HostBridge %d, Port %d link up failed\n", HostBridgeNum, PortIndex));
+ return PCIE_ERR_LINK_OVER_TIME;
+ }
+ }
+ DEBUG((EFI_D_ERROR, "HostBridge %d, Port %d Link up ok\n", HostBridgeNum, PortIndex));
+
+ /* dfe enable is just for 660 */
+ (VOID)Gen3DfeEnable(HostBridgeNum, PortIndex);
+
+
+ PcieRegWrite(PortIndex, 0x80c, 0x208FF);
+
+ return EFI_SUCCESS;
+}
+
+
+
+
+EFI_STATUS PcieSetDBICS2Enable(UINT32 HostBridgeNum, UINT32 Port, UINT32 Enable)
+{
+ PCIE_SYS_CTRL20_U dbi_ro_enable;
+
+ if(Port >= PCIE_MAX_PORT_NUM)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+ dbi_ro_enable.UInt32 = PcieRegRead(Port, PCIE_SYS_CTRL20_REG);
+ dbi_ro_enable.Bits.ro_sel = Enable;
+ PcieRegWrite(Port, PCIE_SYS_CTRL20_REG, dbi_ro_enable.UInt32);
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+
+ return EFI_SUCCESS;
+
+}
+
+VOID PcieDelay(UINT32 dCount)
+{
+ volatile UINT32 *uwCnt = &dCount;
+
+ while(*uwCnt > 0)
+ {
+ *uwCnt = *uwCnt - 1;
+ }
+
+}
+
diff --git a/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.h b/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.h new file mode 100644 index 0000000000..00a2b278b9 --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.h @@ -0,0 +1,239 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __PCIE_INIT_LIB_H__
+#define __PCIE_INIT_LIB_H__
+
+#include <Uefi.h>
+#include <Regs/HisiPcieV1RegOffset.h>
+#include "PcieKernelApi.h"
+
+#define PCIE_AXI_SLAVE_BASE (0xb3000000)
+#define PCIE_MAX_AXI_SIZE (0x1000000)
+#define PCIE_AXI_BASE(port) (PCIE_AXI_SLAVE_BASE + port * PCIE_MAX_AXI_SIZE)
+#define PCIE_SMMU_BASE (0xb0040000)
+
+
+#define PCIE_DMA_CHANNEL_NUM (2)
+#define PCIE_DMA_RESOURCE_MODE_SIZE (0x40000)
+#define PCIE_DMA_BURST_SIZE (0x80000000)
+
+#define PCIE_ADDR_BASE_OFFSET 0x46C00000
+#define PCIE_ADDR_BASE_HOST_ADDR (PCIE_ADDR_BASE_OFFSET + NP_DDR_BASE_ADDR_HOST)
+#define NP_DDR_BASE_ADDR_HOST 0x236E00000ULL
+
+
+
+#define PCIE_GIC_MSI_ITS_BASE (0xb7010040)
+#define PCIE_INT_BASE (13824)
+#define PCIE_INT_LIMIT (PCIE_INT_BASE + 64)
+
+#define PCIE_NTB_MEM_SIZE (0x1000000)
+#define PCIE_NTB_BAR01_SIZE (0x10000) // 64K
+#define PCIE_NTB_BAR23_SIZE (0x800000) // 8M
+#define PCIE_NTB_BAR45_SIZE (0x800000)
+
+#define PCIE_IATU_END {PCIE_IATU_OUTBOUND,0,0,0}
+#define PCIE_IATU_INBOUND_MASK (0x80000000)
+#define PCIE_IATU_INDEX_MASK (0x7f)
+#define PCIE_IATU_TYPE_MASK (0x1f)
+#define PCIE_IATU_EN (0x1 << 0)
+#define PCIE_IATU_SHIFT_MODE (0x1 << 1)
+#define PCIE_IATU_BAR_MODE (0x1 << 2)
+#define PCIE_IATU_FUNC_MODE (0x1 << 3)
+#define PCIE_IATU_AT_MODE (0x1 << 4)
+#define PCIE_IATU_ATTR_MODE (0x1 << 5)
+#define PCIE_IATU_TD_MODE (0x1 << 6) //TD
+#define PCIE_IATU_TC_MODE (0x1 << 7) // TC
+#define PCIE_IATU_PREFETCH_MODE (0x1 << 8)
+#define PCIE_IATU_DMA_BY_PASS_MODE (0x1 << 9) //DMA bypass untranslate
+
+#define PCIE_BAR_MASK_SIZE (0x800000)
+#define PCIE_BAR_TYPE_32 (0)
+#define PCIE_BAR_TYPE_64 (2)
+#define PCIE_BAR_PREFETCH_MODE (1)
+
+#define RegWrite(addr,data) (*(volatile UINT32*)(UINTN)(addr) = (data))
+#define RegRead(addr,data) ((data) = *(volatile UINT32*)(UINTN)(addr))
+
+
+typedef struct tagPcieDebugInfo
+{
+ UINT32 pcie_rdma_start_cnt;
+ UINT32 pcie_wdma_start_cnt;
+ UINT64 pcie_wdma_transfer_len;
+ UINT64 pcie_rdma_transfer_len;
+ UINT32 pcie_rdma_fail_cnt;
+ UINT32 pcie_wdma_fail_cnt;
+}pcie_debug_info_s;
+
+
+#define bdf_2_b(bdf) ((bdf >> 8) & 0xFF)
+#define bdf_2_d(bdf) ((bdf >> 3) & 0x1F)
+#define bdf_2_f(bdf) ((bdf >> 0) & 0x7)
+#define b_d_f_2_bdf(b,d,f) (((b & 0xff) << 8 ) | ((d & 0x1f) << 3) | ((f & 0x7) << 0))
+
+
+
+typedef UINT32 (*pcie_dma_func_int)(UINT32 ulErrno, UINT32 ulReserved);
+
+
+typedef struct {
+ UINT32 ViewPort; //iATU Viewport Register
+ UINT32 RegionCtrl1; //Region Control 1 Register
+ UINT32 RegionCtrl2; //Region Control 2 Register
+ UINT32 BaseLow; //Lower Base Address Register
+ UINT32 BaseHigh; //Upper Base Address Register
+ UINT32 Limit; //Limit Address Register
+ UINT32 TargetLow; //Lower Target Address Register
+ UINT32 TargetHigh; //Upper Target Address Register
+} PCIE_IATU_VA;
+
+typedef enum {
+ PCIE_IATU_OUTBOUND = 0x0,
+ PCIE_IATU_INBOUND = 0x1,
+} PCIE_IATU_DIR;
+
+typedef struct {
+ PCIE_IATU_DIR IatuType;
+ UINT64 IatuBase;
+ UINT64 IatuSize;
+ UINT64 IatuTarget;
+} PCIE_IATU;
+
+typedef struct {
+ UINT32 IatuType;
+ UINT64 IatuBase;
+ UINT32 IatuLimit;
+ UINT64 IatuTarget;
+ UINT32 Valid;
+} PCIE_IATU_HW;
+
+typedef struct {
+ UINT32 PortIndex;
+ PCIE_PORT_INFO PortInfo;
+ PCIE_IATU_HW OutBound[PCIE_MAX_OUTBOUND];
+ PCIE_IATU_HW InBound[PCIE_MAX_INBOUND];
+} PCIE_DRIVER_CFG;
+
+typedef enum {
+ PCIE_CONFIG_REG = 0x0,
+ PCIE_SYS_CONTROL = 0x1,
+ PCIE_SLV_CONTENT_MODE = 0x2,
+} PCIE_RW_MODE;
+
+typedef union {
+ PCIE_DRIVER_CFG PcieDevice;
+ PCIE_NTB_CFG NtbDevice;
+} DRIVER_CFG_U;
+
+typedef struct {
+ VOID *MappedOutbound[PCIE_MAX_OUTBOUND];
+ UINT32 OutboundType[PCIE_MAX_OUTBOUND];
+ UINT32 OutboundEn[PCIE_MAX_OUTBOUND];
+} PCIE_MAPPED_IATU_ADDR;
+
+typedef struct {
+ BOOLEAN PortIsInitilized[PCIE_MAX_PORT_NUM];
+ DRIVER_CFG_U Dev[PCIE_MAX_PORT_NUM];
+ VOID *DmaResource[PCIE_MAX_PORT_NUM];
+ UINT32 DmaChannel[PCIE_MAX_PORT_NUM][2];
+ VOID *RegResource[PCIE_MAX_PORT_NUM];
+ VOID *CfgResource[PCIE_MAX_PORT_NUM];
+} PCIE_INIT_CFG;
+
+typedef enum {
+ PCIE_MMIO_IEP_CFG = 0x1000,
+ PCIE_MMIO_IEP_CTRL = 0x0,
+ PCIE_MMIO_EEP_CFG = 0x9000,
+ PCIE_MMIO_EEP_CTRL = 0x8000,
+} NTB_MMIO_MODE;
+
+typedef struct tagPcieDmaDes
+{
+ UINT32 uwChanCtrl;
+ UINT32 uwLen;
+ UINT32 uwLocalLow;
+ UINT32 uwLocalHigh;
+ UINT32 uwTagetLow;
+ UINT32 uwTagetHigh;
+}pcie_dma_des_s,*pcie_dma_des_ps;
+
+typedef enum {
+ PCIE_IATU_MEM,
+ PCIE_IATU_CFG = 0x4,
+ PCIE_IATU_IO
+} PCIE_IATU_OUT_TYPE;
+
+typedef enum {
+ PCIE_PAYLOAD_128B = 0,
+ PCIE_PAYLOAD_256B,
+ PCIE_PAYLOAD_512B,
+ PCIE_PAYLOAD_1024B,
+ PCIE_PAYLOAD_2048B,
+ PCIE_PAYLOAD_4096B,
+ PCIE_RESERVED_PAYLOAD
+} PCIE_PAYLOAD_SIZE;
+
+typedef struct tagPcieDfxInfo
+{
+ PCIE_EP_AER_CAP0_U aer_cap0;
+ PCIE_EP_AER_CAP1_U aer_cap1;
+ PCIE_EP_AER_CAP2_U aer_cap2;
+ PCIE_EP_AER_CAP3_U aer_cap3;
+ PCIE_EP_AER_CAP4_U aer_cap4;
+ PCIE_EP_AER_CAP5_U aer_cap5;
+ PCIE_EP_AER_CAP6_U aer_cap6;
+ UINT32 hdr_log0;
+ UINT32 hdr_log1;
+ UINT32 hdr_log2;
+ UINT32 hdr_log3;
+ PCIE_EP_AER_CAP11_U aer_cap11;
+ PCIE_EP_AER_CAP12_U aer_cap12;
+ PCIE_EP_AER_CAP13_U aer_cap13;
+
+ PCIE_EP_PORTLOGIC62_U port_logic62;
+ PCIE_EP_PORTLOGIC64_U port_logic64;
+ PCIE_EP_PORTLOGIC66_U port_logic66;
+ PCIE_EP_PORTLOGIC67_U port_logic67;
+ PCIE_EP_PORTLOGIC69_U port_logic69;
+ PCIE_EP_PORTLOGIC75_U port_logic75;
+ PCIE_EP_PORTLOGIC76_U port_logic76;
+ PCIE_EP_PORTLOGIC77_U port_logic77;
+ PCIE_EP_PORTLOGIC79_U port_logic79;
+ PCIE_EP_PORTLOGIC80_U port_logic80;
+ PCIE_EP_PORTLOGIC81_U port_logic81;
+ PCIE_EP_PORTLOGIC87_U port_logic87;
+
+ PCIE_CTRL_10_U pcie_ctrl10;
+ UINT32 slve_rerr_addr_low;
+ UINT32 slve_rerr_addr_up;
+ UINT32 slve_werr_addr_low;
+ UINT32 slve_werr_addr_up;
+ UINT32 pcie_state4;
+ UINT32 pcie_state5;
+}PCIE_DFX_INFO_S;
+
+VOID PcieChangeRwMode(UINT32 HostBridgeNum, UINT32 Port, PCIE_RW_MODE Mode);
+
+UINT32 PcieIsLinkDown(UINT32 Port);
+
+BOOLEAN PcieIsLinkUp(UINT32 HostBridgeNum, UINT32 Port);
+
+EFI_STATUS PcieWaitLinkUp(UINT32 Port);
+
+EFI_STATUS PcieSetDBICS2Enable(UINT32 HostBridgeNum, UINT32 Port, UINT32 Enable);
+
+#endif
diff --git a/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieKernelApi.h b/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieKernelApi.h new file mode 100644 index 0000000000..d1ba1c8999 --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieKernelApi.h @@ -0,0 +1,346 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __PCIE_KERNEL_API_H__
+#define __PCIE_KERNEL_API_H__
+
+#define PCIE_HOST_BRIDGE_NUM (1)
+#define PCIE_MAX_PORT_NUM (4)
+#define PCIE_MAX_OUTBOUND (6)
+#define PCIE_MAX_INBOUND (4)
+#define PCIE3_MAX_OUTBOUND (16)
+#define PCIE3_MAX_INBOUND (16)
+
+#define PCIE_LINK_LOOP_CNT (0x1000)
+#define PCIE_IATU_ADDR_MASK (0xFFFFF000)
+#define PCIE_1M_ALIGN_SHIRFT (20)
+#define PCIE_BDF_MASK (0xF0000FFF)
+#define PCIE_BUS_SHIRFT (20)
+#define PCIE_DEV_SHIRFT (15)
+#define PCIE_FUNC_SHIRFT (12)
+
+#define PCIE_DBI_CS2_ENABLE (0x1)
+#define PCIE_DBI_CS2_DISABLE (0x0)
+
+#define PCIE_DMA_CHANLE_READ (0x1)
+#define PCIE_DMA_CHANLE_WRITE (0x0)
+
+
+#define PCIE_ERR_IATU_TABLE_NULL EFIERR (1)
+#define PCIE_ERR_LINK_OVER_TIME EFIERR (2)
+#define PCIE_ERR_UNIMPLEMENT_PCIE_TYPE EFIERR (3)
+#define PCIE_ERR_ALREADY_INIT EFIERR (4)
+#define PCIE_ERR_PARAM_INVALID EFIERR (5)
+#define PCIE_ERR_MEM_OPT_OVER EFIERR (6)
+#define PCIE_ERR_NOT_INIT EFIERR (7)
+#define PCIE_ERR_CFG_OPT_OVER EFIERR (8)
+#define PCIE_ERR_DMA_READ_CHANLE_BUSY EFIERR (9)
+#define PCIE_ERR_DMA_WRITE_CHANLE_BUSY EFIERR (10)
+#define PCIE_ERR_DMAR_NO_RESORCE EFIERR (11)
+#define PCIE_ERR_DMAW_NO_RESORCE EFIERR (12)
+#define PCIE_ERR_DMA_OVER_MAX_RESORCE EFIERR (13)
+#define PCIE_ERR_NO_IATU_WINDOW EFIERR (14)
+#define PCIE_ERR_DMA_TRANSPORT_OVER_TIME EFIERR (15)
+#define PCIE_ERR_DMA_MEM_ALLOC_ERROR EFIERR (16)
+#define PCIE_ERR_DMA_ABORT EFIERR (17)
+#define PCIE_ERR_UNSUPPORT_BAR_TYPE EFIERR (18)
+
+typedef enum {
+ PCIE_ROOT_COMPLEX,
+ PCIE_END_POINT,
+ PCIE_NTB_TO_NTB,
+ PCIE_NTB_TO_RP,
+} PCIE_PORT_TYPE;
+
+typedef enum {
+ PCIE_GEN1_0 = 1, //PCIE 1.0
+ PCIE_GEN2_0 = 2, //PCIE 2.0
+ PCIE_GEN3_0 = 4 //PCIE 3.0
+} PCIE_PORT_GEN;
+
+typedef enum {
+ PCIE_WITDH_X1 = 0x1,
+ PCIE_WITDH_X2 = 0x3,
+ PCIE_WITDH_X4 = 0x7,
+ PCIE_WITDH_X8 = 0xf,
+ PCIE_WITDH_INVALID
+} PCIE_PORT_WIDTH;
+
+
+typedef struct {
+ PCIE_PORT_TYPE PortType;
+ PCIE_PORT_WIDTH PortWidth;
+ PCIE_PORT_GEN PortGen;
+ UINT8 PcieLinkUp;
+} PCIE_PORT_INFO;
+
+typedef struct tagPciecfg_params
+{
+ UINT32 preemphasis;
+ UINT32 deemphasis;
+ UINT32 swing;
+ UINT32 balance;
+}pcie_cfg_params_s;
+
+typedef enum {
+ PCIE_CORRECTABLE_ERROR = 0,
+ PCIE_NON_FATAL_ERROR,
+ PCIE_FATAL_ERROR,
+ PCIE_UNSUPPORTED_REQUEST_ERROR,
+ PCIE_ALL_ERROR
+} PCIE_ERROR_TYPE;
+
+typedef union tagPcieDeviceStatus
+{
+ struct
+ {
+ UINT16 correctable_error : 1;
+ UINT16 non_fatal_error : 1;
+ UINT16 fatal_error : 1;
+ UINT16 unsupported_error : 1;
+ UINT16 aux_power : 1;
+ UINT16 transaction_pending : 1;
+ UINT16 reserved_6_15 : 10;
+ }Bits;
+
+ UINT16 Value;
+}pcie_device_status_u;
+
+
+typedef union tagPcieUcAerStatus
+{
+ struct
+ {
+ UINT32 undefined : 1 ; /* [0] undefined */
+ UINT32 reserved_1_3 : 3 ; /* reserved */
+ UINT32 data_link_proto_error : 1 ; /* Data Link Protocol Error Status */
+ UINT32 reserved_5_11 : 7 ; /* reserved */
+ UINT32 poisoned_tlp_status : 1 ; /* Poisoned TLP Status */
+ UINT32 flow_control_proto_error : 1 ; /* Flow Control Protocol Error Status */
+ UINT32 completion_time_out : 1 ; /* Completion Timeout Status */
+ UINT32 compler_abort_status : 1 ; /* Completer Abort Status */
+ UINT32 unexpect_completion_status : 1 ; /* Unexpected Completion Status */
+ UINT32 receiver_overflow_status : 1 ; /*Receiver Overflow Status */
+ UINT32 malformed_tlp_status : 1 ; /* Malformed TLP Status*/
+ UINT32 ecrc_error_status : 1 ; /* ECRC Error Status */
+ UINT32 unsupport_request_error_status : 1 ; /* Unsupported Request Error Status */
+ UINT32 reserved_21 : 1 ; /* reserved */
+ UINT32 uncorrectable_interal_error : 1 ; /* Uncorrectable Internal Error Status */
+ UINT32 reserved_23 : 1 ; /* reserved*/
+ UINT32 atomicop_egress_blocked_status : 1 ; /* AtomicOp Egress Blocked Status */
+ UINT32 tlp_prefix_blocked_error_status : 1 ; /* TLP Prefix Blocked Error Status */
+ UINT32 reserved_26_31 : 1 ; /* reserved */
+ }Bits;
+
+ UINT32 Value;
+}pcie_uc_aer_status_u;
+
+typedef union tagPcieCoAerStatus
+{
+ struct
+ {
+ UINT32 receiver_error_status : 1 ; /* Receiver Error Status */
+ UINT32 reserved_1_5 : 5 ; /* Reserved */
+ UINT32 bad_tlp_status : 1 ; /* Bad TLP Status */
+ UINT32 bad_dllp_status : 1 ; /* Bad DLLP Status */
+ UINT32 reply_num_rollover_status : 1 ; /* REPLAY_NUM Rollover Status*/
+ UINT32 reserved_9_11 : 3 ; /* Reserved */
+ UINT32 reply_timer_timeout : 1 ; /* Replay Timer Timeout Status */
+ UINT32 advisory_nonfatal_error : 1 ; /* Advisory Non-Fatal Error Status*/
+ UINT32 corrected_internal_error : 1 ; /*Corrected Internal Error Status*/
+ UINT32 reserved_15_31 : 1 ; /* Reserved */
+ }Bits;
+ UINT32 Value;
+}pcie_co_aer_status_u;
+
+typedef struct tagPcieAerStatus
+{
+ pcie_uc_aer_status_u uc_aer_status;
+ pcie_co_aer_status_u co_aer_status;
+}pcie_aer_status_s;
+
+
+
+typedef struct tagPcieLoopTestResult
+{
+ UINT32 tx_pkts_cnt;
+ UINT32 rx_pkts_cnt;
+ UINT32 error_pkts_cnt;
+ UINT32 droped_pkts_cnt;
+ UINT32 push_cnt;
+ pcie_device_status_u device_status;
+ pcie_aer_status_s pcie_aer_status;
+} pcie_loop_test_result_s;
+
+typedef struct tagPcieDmaChannelAttrs {
+ UINT32 dma_chan_en;
+ UINT32 dma_mode;
+ UINT32 channel_status;
+}pcie_dma_channel_attrs_s;
+
+typedef enum tagPcieDmaChannelStatus
+{
+ PCIE_DMA_CS_RESERVED = 0,
+ PCIE_DMA_CS_RUNNING = 1,
+ PCIE_DMA_CS_HALTED = 2,
+ PCIE_DMA_CS_STOPPED = 3
+}pcie_dma_channel_status_e;
+
+typedef enum tagPcieDmaIntType{
+ PCIE_DMA_INT_TYPE_DONE=0,
+ PCIE_DMA_INT_TYPE_ABORT,
+ PCIE_DMA_INT_ALL,
+ PCIE_DMA_INT_NONE
+}pcie_dma_int_type_e;
+
+typedef enum tagPcieMulWinSize
+{
+ WIN_SIZE_4K = 0xc,
+ WIN_SIZE_8K,
+ WIN_SIZE_16K,
+ WIN_SIZE_32K,
+ WIN_SIZE_64K,
+ WIN_SIZE_128K,
+ WIN_SIZE_256K,
+ WIN_SIZE_512K,
+ WIN_SIZE_1M,
+ WIN_SIZE_2M,
+ WIN_SIZE_4M,
+ WIN_SIZE_8M,
+ WIN_SIZE_16M,
+ WIN_SIZE_32M,
+ WIN_SIZE_64M,
+ WIN_SIZE_128M,
+ WIN_SIZE_256M,
+ WIN_SIZE_512M,
+ WIN_SIZE_1G,
+ WIN_SIZE_2G,
+ WIN_SIZE_4G,
+ WIN_SIZE_8G,
+ WIN_SIZE_16G,
+ WIN_SIZE_32G,
+ WIN_SIZE_64G,
+ WIN_SIZE_128G,
+ WIN_SIZE_256G,
+ WIN_SIZE_512G = 0x27,
+}pcie_mul_win_size_e;
+
+typedef struct tagPcieMultiCastCfg
+{
+ UINT64 multicast_base_addr;
+ pcie_mul_win_size_e base_addr_size;
+ UINT64 base_translate_addr;
+}pcie_multicast_cfg_s;
+
+typedef enum tagPcieMode
+{
+ PCIE_EP_DEVICE = 0x0,
+ LEGACY_PCIE_EP_DEVICE = 0x1,
+ RP_OF_PCIE_RC = 0x4,
+ PCIE_INVALID = 0x100
+}pcie_mode_e;
+
+typedef struct{
+ UINT32 PortIndex;
+ PCIE_PORT_INFO PortInfo;
+ UINT64 iep_bar01; /*iep bar 01*/
+ UINT64 iep_bar23;
+ UINT64 iep_bar45;
+ UINT64 iep_bar01_xlat;
+ UINT64 iep_bar23_xlat;
+ UINT64 iep_bar45_xlat;
+ UINT64 iep_bar_lmt23;
+ UINT64 iep_bar_lmt45; /*bar limit*/
+ UINT64 eep_bar01;
+ UINT64 eep_bar23;
+ UINT64 eep_bar45;
+ UINT64 eep_bar23_xlat;
+ UINT64 eep_bar45_xlat;
+ UINT64 eep_bar_lmt23; /*bar limit*/
+ UINT64 eep_bar_lmt45; /*bar limit*/
+} PCIE_NTB_CFG;
+
+extern int pcie_mode_get(UINT32 Port, PCIE_PORT_INFO *port_info);
+
+extern int pcie_port_ctrl(UINT32 Port, UINT32 port_ctrl);
+
+extern int pcie_link_speed_set(UINT32 Port, PCIE_PORT_GEN speed);
+
+extern int pcie_port_cfg_set(UINT32 Port, pcie_cfg_params_s *cfg_params);
+
+extern int pcie_port_cfg_get(UINT32 Port, pcie_cfg_params_s *cfg_params);
+
+
+extern int pcie_dma_chan_ctl(UINT32 Port,UINT32 channel,UINT32 control);
+
+extern int pcie_dma_chan_attribu_set(UINT32 Port,UINT32 channel, pcie_dma_channel_attrs_s *dma_attribute);
+
+extern int pcie_dma_cur_status_get(UINT32 Port, UINT32 channel, pcie_dma_channel_status_e *dma_channel_status);
+
+extern int pcie_dma_int_enable(UINT32 Port, UINT32 channel, pcie_dma_int_type_e int_type);
+
+extern int pcie_dma_int_mask(UINT32 Port, UINT32 channel, pcie_dma_int_type_e int_type);
+
+extern int pcie_dma_tranfer_stop(UINT32 Port, UINT32 channel);
+
+
+extern int pcie_dma_int_status_get(UINT32 Port, UINT32 channel, int *dma_int_status);
+
+extern int pcie_dma_int_clear(UINT32 Port, UINT32 channel, pcie_dma_int_type_e dma_int_type);
+
+
+extern int pcie_dma_read(UINT32 Port,void *source, void *dest,UINT32 transfer_size, UINT32 burst_size);
+
+extern int pcie_dma_write(UINT32 Port,void *source, void *dest,UINT32 transfer_size, UINT32 burst_size);
+
+extern int pcie_multicast_cfg_set(UINT32 Port,pcie_multicast_cfg_s *multicast_cfg,UINT32 win_num);
+
+extern int pcie_setup_ntb(UINT32 Port, PCIE_NTB_CFG *ntb_cfg);
+
+extern int pcie_ntb_doorbell_send(UINT32 Port,UINT32 doorbell);
+
+extern int pcie_loop_test_start(UINT32 Port, UINT32 loop_type);
+
+extern int pcie_loop_test_stop(UINT32 Port, UINT32 loop_type);
+
+extern int pcie_loop_test_get(UINT32 Port, UINT32 loop_type, pcie_loop_test_result_s *test_result);
+extern int pcie_port_reset(UINT32 Port);
+
+extern int pcie_port_error_report_enable(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, PCIE_ERROR_TYPE pcie_error);
+
+extern int pcie_port_error_report_disable(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, PCIE_ERROR_TYPE pcie_error);
+
+extern int pcie_device_error_status_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,UINT32 clear, \
+pcie_device_status_u *pcie_stat);
+extern int pcie_port_aer_cap_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,UINT32 *aer_cap);
+
+extern int pcie_port_aer_status_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,pcie_uc_aer_status_u *pcie_aer_status);
+extern int pcie_port_aer_status_clr(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func);
+
+extern int pcie_port_aer_report_enable(UINT32 Port, PCIE_ERROR_TYPE pcie_aer_type);
+
+
+extern int pcie_port_aer_report_disable(UINT32 Port, PCIE_ERROR_TYPE pcie_aer_type);
+
+
+extern int pcie_cfg_read(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, UINT32 reg_offset, UINT32 * value, UINT32 length);
+
+extern int pcie_cfg_write(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, UINT32 reg_offset, UINT8 * data, UINT32 length);
+
+extern int pcie_mem_read(UINT32 Port,void * local_addr, void *pcie_mem_addr,UINT32 length);
+
+extern int pcie_mem_write(UINT32 Port,void *local_addr , void *pcie_mem_addr,UINT32 length);
+
+#endif
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